Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, a plurality of transition regions, a field oxide layer, and a gate structure. The substrate comprises a laminated substrate and an epitaxial layer. The transition regions are located in the epitaxial layer, and a surface of the transition regions away from the substrate is a first surface. The first surface is a side surface of the epitaxial layer away from the substrate. The field oxide layer is located on the first surface. The field oxide layer comprises a plurality of spaced field oxide portions. The plurality of transition regions in contact with the same field oxide portion are distributed at intervals. The gate structure is located on the first surface between two field oxide portions and on a surface of the partial field oxide layer away from the epitaxial layer. Part of the gate structure is in contact with the transition region. The transition region has a first doping type, the epitaxial layer has a second doping type, and the first doping type and the second doping type are opposite. The application solves the problems of short service life and low reliability of the semiconductor device caused by the overshoot phenomenon in the prior art.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology

[0002] SiC MOSFETs (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors) have shown great application potential in the field of power electronics due to their excellent high-frequency switching characteristics and high-temperature resistance. However, during high-speed switching of SiC MOSFETs, gate voltage overshoot becomes a significant problem. This issue mainly stems from the fact that during the switching instant of a SiC MOSFET, the voltage between the gate and source rises sharply, exceeding the predetermined target voltage. Most of this overshoot voltage ultimately acts on both sides of the gate oxide layer, exacerbating the generation of hot carriers in the gate oxide layer. This accelerates the accumulation of gate oxide layer defects, leading to premature gate oxide layer breakdown, reduced device lifetime, and severely impacting device reliability and performance.

[0003] To suppress gate voltage overshoot in SiC MOSFETs, existing technologies mainly employ three approaches: The first is to reduce switching speed by increasing the gate drive resistor. While this method can alleviate overshoot to some extent, it prolongs switching time, increases switching losses, and sacrifices the high-speed switching advantage of SiC MOSFETs. The second approach involves externally connecting a clamping diode between the gate and source electrodes. Although this method can effectively control overshoot voltage, it may limit the switching frequency and increase switching losses due to the introduction of additional parasitic inductance and capacitance. More importantly, the performance parameters of commercial diodes are often difficult to match with SiC MOSFETs, especially at high temperatures, where diode reliability becomes a significant challenge. The third approach attempts to directly integrate the overvoltage protection structure into the SiC MOSFET. However, this approach increases process complexity, ultimately leading to device performance degradation, and its practical feasibility and potential for improvement are limited.

[0004] In summary, existing semiconductor devices suffer from short lifespans and low reliability due to overshoot. Therefore, there is an urgent need for a power device and its fabrication method that can overcome these problems. Summary of the Invention

[0005] This application provides a semiconductor device and its fabrication method to solve the problems of short device life and low reliability caused by overshoot in related technologies.

[0006] According to one aspect of this application, a semiconductor device is provided, comprising:

[0007] The substrate includes a stacked substrate and an epitaxial layer;

[0008] Multiple transition regions are located in the epitaxial layer, and the surface of the transition region away from the substrate is a portion of a first surface, the first surface being the side surface of the epitaxial layer facing away from the substrate;

[0009] A field oxide layer is located on the first surface, the field oxide layer includes a plurality of spaced field oxide portions, and a plurality of transition regions that are in contact with the same field oxide portion are spaced apart;

[0010] A gate structure is located on a first surface between the two field oxide portions and on a portion of the field oxide layer away from the epitaxial layer, and a portion of the gate structure is in contact with the transition region.

[0011] The transition region has a first doping type, and the epitaxial layer has a second doping type, wherein the first doping type and the second doping type are opposite.

[0012] Optionally, the gate structure includes a gate oxide layer and a gate, the gate oxide layer is located on the first surface and contacts the field oxide layer, the gate covers the gate oxide layer and a portion of the field oxide layer, and the transition region includes: a first transition region that contacts the gate; a second transition region that is spaced apart from the first transition region; the second transition regions and the first transition regions are alternately distributed, and a plurality of second transition regions that contact the same field oxide layer are spaced apart.

[0013] Optionally, the portion of the first surface located between the two field oxide portions and in contact with the gate structure is the first contact portion, and the portion of the first surface in contact with the first transition region is the second contact portion, with the first contact portion located within the second contact portion.

[0014] Optionally, a gate ohmic contact is included, located on the side of the gate structure away from the substrate. The gate ohmic contact contacts a portion of the gate structure. The gate ohmic contact is spaced from a first contact portion in a predetermined direction, the predetermined direction being the arrangement direction of the field oxide portions. The first contact portion is the portion of the first surface located between two of the field oxide portions and in contact with the gate structure.

[0015] Optionally, the second transition region also contacts the gate oxide layer.

[0016] Optionally, the first transition region includes a first portion corresponding to the first contact portion, and the portion remaining after removing the first portion is a second portion. The second portion is in contact with at least two adjacent field oxide portions, and the first contact portion is the portion of the first surface located between two field oxide portions and in contact with the gate structure.

[0017] According to one aspect of this application, a method for fabricating a semiconductor device is provided, the method comprising the following steps:

[0018] A substrate is provided, the substrate comprising a stacked substrate and an epitaxial layer;

[0019] Ion implantation is performed on the first surface of the epitaxial layer to form a transition region. The first surface is the side of the epitaxial layer facing away from the substrate. The transition region has a first doping type, and the epitaxial layer has a second doping type. The first doping type and the second doping type are opposite.

[0020] Multiple spaced field oxide portions are deposited on the first surface, the multiple field oxide portions constitute a field oxide layer, and multiple transition regions in contact with the same field oxide portion are spaced apart.

[0021] A gate structure is formed on the first surface located between the two field oxide portions and on a portion of the field oxide layer away from the epitaxial layer, with a portion of the gate structure in contact with the transition region.

[0022] Optionally, the step of forming the transition region includes: forming a patterned mask layer on the first surface, the area covered by the mask layer being a first region; performing ion implantation on the first region to form the transition region, the transition region including a first transition region and a second transition region, the first transition region being in contact with a gate, the second transition region being spaced apart from the first transition region, the second transition region and the first transition region being alternately distributed, the second transition region being in contact with the field oxide portion, and a plurality of second transition regions in contact with the same field oxide portion being spaced apart.

[0023] Optionally, the steps of forming the field oxide layer and the gate structure include: forming a preliminary field oxide layer on the first surface; etching the preliminary field oxide layer to form a plurality of field oxide portions, wherein the first surface has a first contact portion located between at least two adjacent field oxide portions and exposed, and the plurality of field oxide portions constitute the field oxide layer; forming the gate oxide layer on the first surface, wherein the gate oxide layer and the field oxide layer are in contact; forming the gate on the gate oxide layer, the field oxide layer and the first contact portion, wherein the gate covers the gate oxide layer and a portion of the field oxide layer, a portion of the gate is in contact with the first transition region, wherein the gate oxide layer and the gate constitute the gate structure, and the gate structure is in contact with the first contact portion.

[0024] Optionally, at least two adjacent field oxide portions have a spacing region corresponding to the first contact portion, and the preparation method further includes the following steps: partially filling the spacing region with the isolation dielectric layer, and partially contacting the gate with the isolation dielectric layer.

[0025] Through this application, a transition region is formed inside the epitaxial layer of the semiconductor device. A field oxide layer is located on the first surface, and the field oxide layer includes multiple spaced field oxide portions. Multiple transition regions that contact the same field oxide portion are spaced apart. The gate structure is located on the first surface between any two field oxide portions and on the surface of a portion of the field oxide layer away from the epitaxial layer. A portion of the gate structure contacts the transition region, thereby reducing the parasitic resistance and capacitance between the gate and the source, improving the response speed of voltage control, and achieving fast and efficient overvoltage suppression. The transition region has a first doping type, and the epitaxial layer has a second doping type. The first doping type and the second doping type are opposite. Therefore, the transition region and the epitaxial layer form a back-to-back clamped diode structure, which can effectively absorb or clamp rapidly changing gate-source voltages, prevent overshoot, protect the gate oxide layer from damage, improve device reliability, and extend device life. Furthermore, the transition region is located within the epitaxial layer, i.e., in the non-active region. Therefore, the back-to-back clamped diode formed by the transition region and the epitaxial layer avoids occupying the area of ​​the active region, simplifying the overall structure of the device. It is also highly compatible with existing semiconductor fabrication processes, eliminating the need for new complex process steps or special materials, thus reducing production costs and process complexity. Therefore, the semiconductor device of this application primarily solves the problems of short device lifetime and low reliability caused by overshoot. By forming a back-to-back clamped diode effect between the transition region with different doping types and the epitaxial layer, overvoltage protection capability is improved, thereby enhancing the overall performance and reliability of the device. Attached Figure Description

[0026] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0027] Figure 1 A schematic diagram of a semiconductor device structure according to an embodiment of this application is shown;

[0028] Figure 2 A schematic flowchart of a method for fabricating a semiconductor device structure according to an embodiment of this application is shown;

[0029] Figure 3 A schematic cross-sectional view of a substrate and a buffer layer is shown in a method for fabricating a semiconductor device structure according to an embodiment of this application.

[0030] Figure 4 It shows in Figure 3 A schematic diagram of the cross-sectional structure of the matrix after the formation of a transition region within the epitaxial layer;

[0031] Figure 5 It shows in Figure 4 A schematic diagram of the cross-sectional structure of the substrate after the formation of a field oxide layer on the epitaxial layer;

[0032] Figure 6 It shows in Figure 5 A schematic diagram of the cross-sectional structure of the substrate after the gate structure is formed on the field oxide layer;

[0033] Figure 7 It shows in Figure 6 A schematic diagram of the cross-sectional structure of the substrate after an isolation dielectric layer is formed on the gate structure;

[0034] Figure 8 It shows in Figure 7 A schematic diagram of the cross-sectional structure of the substrate after the gate ohmic contact and source ohmic contact are formed on the isolation dielectric layer.

[0035] 101. Substrate; 102. Epitaxial layer; 10. Base; 20. Buffer layer; 301. First transition region; 302. Second transition region; 30. Transition region; 40. Field oxide; 50. Gate oxide layer; 60. Gate; 70. Gate structure; 80. Gate ohmic contact; 90. Source ohmic contact; 100. Drain ohmic contact; 110. Isolation dielectric layer; 120. Termination region; 130. Active region. Detailed Implementation

[0036] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0037] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0038] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0039] As described in the background section, in the prior art, during high-speed switching of semiconductor devices, the gate voltage may experience overshoot, exceeding the target voltage. Most of the overshoot voltage is ultimately applied to both sides of the gate oxide through the gate. Prolonged overshoot voltage will introduce more hot carriers into the gate oxide, leading to an increase in the defect accumulation rate within the gate oxide thickness range, ultimately causing premature gate oxide breakdown, shortening device lifetime, and significantly reducing device reliability. To solve the above problems, embodiments of this application provide a semiconductor device and its fabrication method.

[0040] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0041] According to embodiments of this application, a semiconductor device is provided, such as... Figure 1 As shown, it includes:

[0042] The substrate 10 includes a stacked substrate 101 and an epitaxial layer 102;

[0043] Multiple transition regions 30 are located in the epitaxial layer 102, and the surface of the transition region 30 away from the substrate 101 is a portion of the first surface, which is the side surface of the epitaxial layer 102 facing away from the substrate 101.

[0044] A field oxide layer is located on the first surface. The field oxide layer includes a plurality of spaced field oxide portions 40 and a plurality of transition regions 30 that are in contact with the same field oxide portion 40 are spaced apart.

[0045] The gate structure 70 is located on the first surface between any two field oxide portions 40 and on the surface of the field oxide layer away from the epitaxial layer 102, and part of the gate structure 70 is in contact with the transition region 30.

[0046] In the semiconductor device provided in the above embodiments, a transition region 30 is formed inside the epitaxial layer 102. The field oxide layer includes multiple spaced field oxide portions 40. Multiple transition regions 30 that are in contact with the same field oxide portion 40 are spaced apart. The gate structure 70 is located on the first surface between any two field oxide portions 40 and on the surface of part of the field oxide layer away from the epitaxial layer 102. Part of the gate structure 70 is in contact with the transition region 30, thereby reducing the parasitic resistance and capacitance between the gate 60 and the source, improving the response speed of voltage control, and realizing fast and efficient overvoltage suppression. The transition region 30 has a first doping type, and the epitaxial layer 102 has a second doping type. The first doping type and the second doping type are opposite. Therefore, the transition region 30 and the epitaxial layer 102 form a back-to-back clamped diode structure, which can effectively absorb or clamp rapidly changing gate-source voltages, prevent overshoot, protect the gate oxide layer 60 from damage, improve device reliability, and extend device life. Furthermore, the transition region is located in the epitaxial layer, i.e., in the non-active region. Therefore, the back-to-back clamped diode structure formed by the transition region and the epitaxial layer avoids occupying the area of ​​the active region, simplifies the overall structure of the device, and is highly compatible with existing semiconductor fabrication processes. It does not require the introduction of new complex process steps or special materials, thus reducing production costs and process difficulty.

[0047] Therefore, the semiconductor device of this application mainly solves the problems of short device life and low reliability caused by overshoot phenomenon. By forming a back-to-back clamping diode effect between the transition region 30 with different doping types and the epitaxial layer 102, the overvoltage protection capability is improved, thereby improving the overall performance and reliability of the device.

[0048] In this embodiment, the substrate 10 can be made of 4H-SiC, which allows the device to have a wide bandgap, high saturation drift velocity, high thermal conductivity, and high breakdown field strength, making it suitable for manufacturing high-performance semiconductor devices that can operate under high temperature, high pressure, and high power environments. Figure 1 As shown, the substrate 10 includes a substrate 101 and an epitaxial layer 102. The doping concentration of the substrate 101 is higher than that of the epitaxial layer 102. The higher doping concentration of the substrate 101 can increase the depth of the depletion layer, thereby increasing the reverse breakdown voltage and reducing the risk of device breakdown. Furthermore, the substrate 101 can absorb carriers from the epitaxial layer 102, further reducing the on-resistance. The lower doping concentration of the epitaxial layer 102 can provide greater carrier mobility when the device is turned on, thereby reducing the on-resistance.

[0049] In this embodiment, multiple regions in the transition region 30 that are in contact with the field oxide layer are spaced apart by the epitaxial layer 102. The transition region 30 and the epitaxial layer 102 have different doping types. The transition region 30 is doped with a P-type dopant, and the epitaxial layer 102 is doped with an N-type dopant. Therefore, the transition region 30 and the epitaxial layer 102 form a back-to-back clamping diode consisting of a p-type transition region-n-type epitaxial layer-p-type transition region-n-type epitaxial layer, etc. The number of these discontinuously distributed p-type transition regions 30 can be freely adjusted, thereby making it easier to increase the number of clamping diodes and making the improvement of overvoltage protection capability more flexible.

[0050] In the above embodiments, the N-type dopant element can be any one of the pentavalent elements, including nitrogen (N), phosphorus (P), arsenic (As) and antimony (Sb), and the P-type dopant element can be any one of the trivalent elements, including boron (B), aluminum (Al) and gallium (Ga). The embodiments of this application do not make specific limitations.

[0051] In some optional embodiments, the gate structure 70 includes a gate oxide layer 50 and a gate 60. The gate oxide layer 50 is located on a first surface and is in contact with the field oxide layer. The gate 60 covers the gate oxide layer 50 and a portion of the field oxide layer. The transition region includes: a first transition region 301, which is in contact with the gate 60; and a second transition region 302, which is spaced apart from the first transition region 301. The second transition region 302 and the first transition region 301 are alternately distributed. The second transition region 302 is in contact with the field oxide portion 40. A plurality of second transition regions 302 that are in contact with the same field oxide portion 40 are distributed at intervals.

[0052] Specifically, the gate 60 can be made of polycrystalline silicon, which is doped with a second type of doping. This polycrystalline silicon gate 60 meets the high electrical performance requirements of high-speed switching scenarios, and it also exhibits good compatibility with SiC materials. The first transition region 301 directly contacts the polycrystalline silicon gate 60, reducing the parasitic resistance and capacitance between the gate 60 and the epitaxial layer 102. This helps improve the switching speed of the device, reduce switching losses, and maintain good electrical characteristics.

[0053] In the above optional embodiments, the polysilicon gate 60 with a first doping type and the first transition region 301 with a second doping type form a PN junction. In the event of voltage overshoot, the PN junction can act as a clamping element. When the voltage exceeds a set threshold, it automatically turns on and "clamps" the voltage to prevent it from rising (or falling), thereby protecting subsequent circuits or devices from overvoltage damage and controlling the voltage within a safe range. Therefore, the gate 60, the first transition region 301, the epitaxial layer 102, and the second transition region 302 ultimately form a back-to-back clamping diode consisting of an n-type polysilicon-p-type transition region-n-type epitaxial layer-p-type transition region-n-type epitaxial layer, etc.

[0054] In some other embodiments of this application, the geometry of the transition region 30 on the cross section along the direction from the field oxide portion 40 to the substrate 10 can be asymmetrical geometric configurations such as sawtooth, bifurcated, annular, honeycomb, and wavy. This allows the transition region 30 to not only perform electrical clamping functions but also participate in functions such as electric field reconstruction, heat flow guidance, and stress dispersion. The sawtooth structure homogenizes the transverse electric field through periodic edge effects, suppressing local breakdown. The bifurcated structure expands the effective contact area with the epitaxial layer, reduces the unit current density, and improves reliability. The annular or semi-annular surrounding structure can surround the gate on the first surface, thereby forming an "electrical shield" that effectively suppresses parasitic capacitance fluctuations and high-frequency oscillations. The honeycomb array realizes a multi-path energy dissipation channel in three-dimensional space, significantly improving heat diffusion efficiency.

[0055] In some alternative embodiments, the portion of the first surface located between the two field oxide portions 40 and in contact with the gate structure 70 is the first contact portion, and the portion of the first surface in contact with the first transition region 301 is the second contact portion, with the first contact portion located within the second contact portion.

[0056] In the above optional embodiments, the first contact portion is located within the second contact portion, ensuring that the polysilicon gate 60 is directly connected to the lower first transition region 301. This allows the transient current to be quickly discharged to the epitaxial layer 102 along the shortest vertical path when overvoltage occurs, forming a low-impedance, low-inductance local clamping circuit. At the same time, it effectively suppresses the risk of electric field concentration and local breakdown caused by positional offset, enhances the current sharing characteristics of the clamping diode, reduces the risk of electrical short circuit, and ensures the safety and reliability of the device under normal operating conditions.

[0057] In some alternative embodiments, a gate ohmic contact 80 is also included, located on the side of the gate structure 70 away from the substrate 101. The gate ohmic contact 80 contacts a portion of the gate structure 70. The gate ohmic contact 80 is spaced from the first contact portion in a predetermined direction, which is the arrangement direction of the field oxide portions 40. The first contact portion is the portion of the first surface located between two field oxide portions 40 and in contact with the gate structure 70.

[0058] In the above optional embodiments, the gate ohmic contact 80 is spaced from the first contact portion in a predetermined direction, that is, the first surface is located away from the gate ohmic contact 80, thereby effectively avoiding unnecessary short circuits between the gate 60 and the source or drain, ensuring normal switching operation of the device. Simultaneously, it allows the polysilicon gate 60 to establish a direct electrical connection with the first transition region 301, thereby introducing an additional electrical path, such as a back-to-back clamped diode structure, to achieve overvoltage protection without interfering with the normal driving function of the gate 60.

[0059] In some alternative implementations, the second transition region 302 also contacts the gate oxide layer 50.

[0060] In the above optional embodiments, a back-to-back clamping diode may also be present at the contact point between the second transition region 302 and the gate oxide layer 50. When an overshoot occurs in the gate 60 voltage, the clamping effect of the diode can more effectively absorb the overvoltage energy, protect the gate oxide layer 50 from damage caused by excessive voltage stress, thereby extending the device life and improving reliability.

[0061] In some alternative embodiments, the first transition region 301 includes a first portion corresponding to the first contact portion, and the portion remaining after removing the first portion is a second portion. The second portion is in contact with at least two adjacent field oxide portions 40, and the first contact portion is the portion of the first surface located between the two field oxide portions 40 and in contact with the gate structure 70.

[0062] In the above optional embodiments, the first transition region 301 is part of the back-to-back diode, and its two ends are in contact with the field oxide section 40. This can ensure that when the gate voltage overshoots, the current can be smoothly injected into the region, forming an effective path from the polysilicon gate 60 to the epitaxial layer 102.

[0063] In the embodiments of this application, such as Figure 1 As shown, the semiconductor device further includes: a buffer layer 20 located between the substrate 101 and the epitaxial layer 102; an isolation dielectric layer 110 covering a portion of the gate structure 70, the field oxide layer, and a portion of the second transition region 302 and having a gate ohmic contact 80; a source ohmic contact 90 located between the isolation dielectric layers 110 and having a contact with the transition region; a drain ohmic contact 100 located on the side surface of the substrate 101 facing away from the epitaxial layer 102; and an active region 130 and a terminal region 120 located at opposite ends of the semiconductor device structure, respectively.

[0064] Specifically, the buffer layer 20 is located between the substrate 101 and the epitaxial layer 102. The material of the buffer layer 20 can be 4H-SiC, and the doping type is the second doping type. During the growth of SiC material, lattice defects are easily generated. The introduction of the buffer layer 20 can effectively prevent the propagation of dislocations, reduce the dislocation density in the epitaxial layer 102, improve the quality of the epitaxial layer 102, and thus improve the performance of the entire SiC MOSFET device. The isolation dielectric layer 110 covers part of the gate structure 70, the field oxide layer, and part of the second transition region 302 and is connected to the gate ohmic contact 80. The isolation dielectric layer 110 isolates the gate structure 70 from other circuit elements to avoid unnecessary electrical short circuits. Covering part of the gate structure 70 and the field oxide layer ensures that there is sufficient insulation distance between the gate 60 and the source, drain, and substrate 101. The source ohmic contact 90 is located between the isolation dielectric layers 110 and contacts the transition region 30. The drain ohmic contact 100 is located on the substrate 101 away from the epitaxial layer. On one side surface of layer 102, the source ohmic contact 90 provides a low-resistance path, facilitating current flow into or out of the device from the source. The drain ohmic contact 100 allows current to efficiently enter or exit the device from the side of substrate 101. Especially in high-power applications, the back contact can provide greater current carrying capacity. The active region 130 and the terminal region 120 are located at the two ends of the semiconductor device structure, respectively. The active region 130 is responsible for the main electrical functions of the device, while the main function of the terminal region 120 is to protect the device from the influence of external electrical and physical environments.

[0065] In the above optional embodiments, the material of the insulating dielectric layer 110 may be selected from silicon oxide film (SIOF), tetraethoxysilane (TEOS), mesoporous silica-based quartz (MSQ), boron phosphosilicate glass (BPSG), or combinations thereof. The metal material forming the source ohmic contact 90 and the drain ohmic contact 100 is selected from one or more of nickel (Ni), titanium (Ti), platinum (Pt), gold (Au), and tungsten (Wu), but is not limited to the above types, and this application does not make specific limitations.

[0066] According to embodiments of this application, a method for fabricating a semiconductor device is provided, used to fabricate the semiconductor device described in the above embodiments, such as... Figure 2 As shown, the preparation method includes:

[0067] Step S1, providing a substrate, the substrate comprising a stacked substrate and an epitaxial layer;

[0068] Step S2: Ion implantation is performed on the first surface of the epitaxial layer to form a transition region. The first surface is the side of the epitaxial layer facing away from the substrate. The transition region has a first doping type, and the epitaxial layer has a second doping type. The first doping type and the second doping type are opposite.

[0069] Step S3: Multiple spaced field oxide portions are deposited on the first surface, the multiple field oxide portions constitute a field oxide layer, and multiple transition regions in contact with the same field oxide portion are distributed at intervals.

[0070] Step S4: A gate structure is formed on the first surface located between the two field oxides and on the surface of the partial field oxide layer away from the epitaxial layer, and the partial gate structure is in contact with the transition region.

[0071] In the fabrication method provided in the above embodiments, a transition region is formed inside the epitaxial layer, and a field oxide layer is located on the first surface. The field oxide layer includes multiple spaced field oxide portions, and multiple transition regions that contact the same field oxide portion are spaced apart. The gate structure is located on the first surface between any two field oxide portions and on the surface of a portion of the field oxide layer away from the epitaxial layer. A portion of the gate structure contacts the transition region, thereby reducing the parasitic resistance and capacitance between the gate and the source, improving the response speed of voltage control, and achieving fast and efficient overvoltage suppression. The transition region has a first doping type, and the epitaxial layer has a second doping type. The first and second doping types are opposite, so the transition region and the epitaxial layer form a back-to-back clamped diode structure, which can effectively absorb or clamp rapidly changing gate-source voltages, prevent overshoot, protect the gate oxide layer from damage, and extend the device's lifespan. Furthermore, this structural design avoids occupying the area of ​​the active region, simplifies the overall device structure, and is highly compatible with existing semiconductor fabrication processes. It does not require the introduction of new complex process steps or special materials, reducing production costs and process difficulty.

[0072] Exemplary embodiments of the method for fabricating a semiconductor device according to embodiments of this application will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0073] First, proceed to step S1: as follows Figure 3 As shown, a substrate 10 is provided, which includes a stacked substrate 101 and an epitaxial layer 102.

[0074] In some optional embodiments, this application further includes the step of forming the substrate 10 described above: providing a substrate 101 made of silicon carbide, and forming an epitaxial layer 102 on the substrate 101 using an epitaxial process. Specifically, the material of the epitaxial layer 102 may include 4H-SiC, and the material of the substrate 101 includes, but is not limited to, semiconductor materials such as silicon, silicon carbide, and gallium nitride, etc., which are not specifically limited in this application.

[0075] In the above optional implementations, such as Figure 3 As shown, the process also includes the steps of forming a buffer layer 20, an active device region 130, and a device termination region 120: A buffer layer 20 is formed on a substrate 101, located between the substrate 101 and the epitaxial layer 102. The active device region 130 and the device termination region 120 are located at opposite ends of the semiconductor device structure. The active device region 130 is responsible for the main electrical functions of the device, while the main function of the device termination region 120 is to protect the device from external electrical and physical environmental influences. Specifically, the material of the buffer layer 20 can be 4H-SiC, with a second doping type. Since SiC material is prone to lattice defects during growth, the introduction of the buffer layer 20 can effectively prevent dislocation propagation, reduce the dislocation density in the epitaxial layer 102, improve the quality of the epitaxial layer 102, and thus enhance the performance of the entire SiC MOSFET device.

[0076] After providing the substrate 10, which includes the substrate 101 and the epitaxial layer 102, step S2 is performed: as follows Figure 4 As shown, ion implantation is performed on the first surface of the epitaxial layer 102 to form a transition region 30. The first surface is the side surface of the epitaxial layer 102 that is away from the substrate 101. The transition region 30 has a first doping type, and the epitaxial layer 102 has a second doping type. The first doping type and the second doping type are opposite.

[0077] In some alternative implementations, the step of forming the transition region 30 includes: as follows Figure 4 As shown, a patterned mask layer is formed on the first surface, and the area covered by the mask layer is the first region. Ion implantation is performed on the first region to form a transition region 30. The transition region 30 includes a first transition region 301 and a second transition region 302. The first transition region 301 is in contact with the gate 60. The first transition region 301 and the second transition region 302 are spaced apart and alternately distributed. The second transition region 302 is in contact with the field oxide portion 40. The second transition regions 302 in contact with the same field oxide portion 40 are spaced apart.

[0078] For example, the carriers injected into the transition region 30 are N-type carriers, and the first doping type is N-type. The carriers injected into the epitaxial layer 102 are P-type carriers, and the second doping type is P-type. This makes the transition region 30 and the epitaxial layer 102 form a back-to-back clamping diode such as p-type transition region-n-type epitaxial layer-p-type transition region-n-type epitaxial layer. The injected N-type carriers are pentavalent elements including any one of phosphorus (P), arsenic (As), and antimony (Sb). The injected P-type carriers are trivalent elements including any one of boron (B), aluminum (Al), and gallium (Ga). At the same time, the injection of N / P type carriers can be done once or in stages. The energy and dose of each injection can be the same or different. This application does not make specific limitations.

[0079] In the above optional embodiments, regardless of whether the gate-source voltage experiences a positive or negative overshoot, there is always one set of PN junctions in the back-to-back clamped diode structure that is forward-conducting, forming a low-resistance path. Furthermore, the number of intermittently distributed p-type transition regions 30 can be freely adjusted, thereby making it easier to increase the number of clamped diodes and making the overvoltage protection capability more flexible. At the same time, this structural design avoids occupying the area of ​​the active region, simplifies the overall structure of the device, and is highly compatible with existing semiconductor fabrication processes. It does not require the introduction of new complex process steps or special materials, thus reducing production costs and process difficulty.

[0080] According to some embodiments of this application, the doping concentration of the transition region 30 increases in a gradient along the direction from the substrate 101 to the epitaxial layer 102. The higher concentration at the surface ensures a low-resistance ohmic contact with the polysilicon and facilitates rapid conduction of the clamping current, while the concentration at deeper layers gradually decreases, which can expand the width of the depletion layer and make the longitudinal electric field distribution more uniform. This effectively suppresses the risk of local electric field spikes and early breakdown caused by high concentration at the interface in traditional uniform doping structures. Furthermore, this gradient structure can significantly reduce the thermal surge trend of reverse leakage current under high-temperature conditions. The deep low-doped region can effectively block hot carrier injection and make the turn-on voltage of the PN junction more linear, avoiding gate oscillation caused by clamping voltage jumps due to abrupt junction characteristics.

[0081] After forming the transition region 30 within the epitaxial layer 102, step S3 is performed: (e.g.) Figure 5 As shown, multiple spaced field oxide portions 40 are deposited on the first surface, the multiple field oxide portions 40 constitute a field oxide layer, and multiple transition regions 30 in contact with the same field oxide portion 40 are distributed at intervals.

[0082] In some alternative embodiments, a preliminary field oxide layer is formed by deposition on the first surface, and the preliminary field oxide layer is etched to form a plurality of field oxide portions 40. The first surface has a first contact portion that is exposed between at least two adjacent field oxide portions 40, and the plurality of field oxide portions 40 constitute the field oxide layer.

[0083] After forming a field oxide layer on the first surface, proceed to step 4: as follows Figure 6 As shown, a gate structure 70 is formed on a first surface located between two field oxide portions 40 and on a surface of a portion of the field oxide layer away from the epitaxial layer 102, and the portion of the gate structure 70 is in contact with the transition region 30.

[0084] In some alternative embodiments, the step of forming the gate structure 70 on the first surface and the field oxide layer includes: as follows Figure 6 As shown, a gate oxide layer 50 is formed on the first surface, and the gate oxide layer 50 is in contact with the field oxide layer; a gate 60 is formed on the gate oxide layer 50 and the field oxide layer, the gate 60 covers the gate oxide layer 50 and part of the field oxide layer, and part of the gate 60 is in contact with the first transition region 301. The gate oxide layer 50 and the gate 60 constitute a gate structure 70, and the gate structure 70 is in contact with the first contact portion.

[0085] Specifically, after the transition region 30 is formed, the field oxide layer and gate structure 70 are fabricated as follows: First, a preliminary field oxide layer is deposited on the surface of the epitaxial layer 102, and an etching process is used to etch the preliminary field oxide layer to form multiple field oxide portions. The first surface has a first contact portion located between at least two adjacent field oxide portions and exposed, thereby exposing part of the first transition region 301. A gate oxide layer 50 is formed on the first surface by dry oxidation growth, and the gate oxide layer 50 is in contact with the field oxide layer. A doped polysilicon layer is deposited on the entire wafer surface, and the polysilicon layer is etched through a photolithography mask to form a gate 60 above the gate oxide layer 50. The gate 60 covers the gate oxide layer 50 and part of the field oxide layer.

[0086] In the above optional embodiments, the gate 60 is made of polysilicon. The first transition region 301 directly contacts the polysilicon gate 60, reducing the parasitic resistance and capacitance between the gate 60 and the epitaxial layer 102. This helps improve the switching speed of the device, reduce switching losses, and maintain good electrical characteristics. Furthermore, during overvoltage, the gate 60 and the transition region 30 form a clamping diode to discharge overshoot energy, thereby improving overvoltage protection capability.

[0087] In some optional embodiments, at least two adjacent field oxide portions 40 have a spacing region corresponding to the first contact portion, and the preparation method further includes the following steps: a portion of the isolation dielectric layer 110 is filled in the spacing region, and a portion of the isolation dielectric layer 110 is in contact with the gate 60.

[0088] In the above optional embodiments, when a gap region corresponding to the first contact portion is formed between at least two adjacent field oxide portions 40, and the gap region is partially filled with an isolation dielectric layer 110 so that it is in direct contact with the gate 60, the local shielding of the gate potential and the active regulation of parasitic capacitance can be effectively achieved, thereby significantly improving the switching stability and anti-interference capability of the device. In addition, the filling structure can also physically isolate the potential leakage path between the source metal and the gate metal, improving the long-term reliability of the device under high temperature, high pressure and high frequency conditions.

[0089] After forming the above-described field oxide layer and gate structure 70, embodiments of this application may further include the following steps: Figure 7 As shown, Figure 8 and Figure 1 As shown, an isolation dielectric layer 110, a source ohmic contact 90, and a drain ohmic contact 100 are formed.

[0090] Specifically, the isolation dielectric layer 110 covers a portion of the gate structure 70, the field oxide layer, and a portion of the second transition region 302 and is connected to the gate ohmic contact 80. The isolation dielectric layer 110 isolates the gate structure 70 from other circuit elements to avoid unnecessary electrical short circuits. Covering a portion of the gate structure 70 and the field oxide layer ensures sufficient insulation distance between the gate 60 and components such as the source, drain, and substrate 101. The source ohmic contact 90 is located between the isolation dielectric layers 110 and contacts the transition region 30. The drain ohmic contact 100 is located on the side of the substrate 101 facing away from the epitaxial layer 102. The source ohmic contact 90 provides a low-resistance path, facilitating current flow into or out of the device from the source. The drain ohmic contact 100 allows current to efficiently enter or exit the device from the side of the substrate 101. Especially in high-power applications, the back contact can provide greater current carrying capacity.

[0091] For example, the isolation dielectric layer 110 is used to isolate the gate 60 and the subsequent metal layer. The material can be selected from silicon oxide film (SIOF), tetraethoxysilane (TEOS), mesoporous silica-based quartz (MSQ), boron phosphorus silicate glass (BPSG) and other materials or combinations thereof. The metal material forming the ohmic contact is selected from one or more of nickel (Ni), titanium (Ti), platinum (Pt), gold (Au) and tungsten (Wu), but is not limited to the above types. This application does not make specific limitations.

[0092] It should be noted that the process steps and sequence in the above method for fabricating a MOSFET power device in the embodiments of this application are not fixed and can be adjusted according to the actual process. The formation of each layer structure requires one or more semiconductor processes such as masking, photolithography, etching, and cleaning, which will not be described in detail in the embodiments of this application.

[0093] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0094] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes a stacked substrate and an epitaxial layer; Multiple transition regions are located in the epitaxial layer, and the surface of the transition region away from the substrate is a portion of a first surface, the first surface being the side surface of the epitaxial layer facing away from the substrate; A field oxide layer is located on the first surface, the field oxide layer includes a plurality of spaced field oxide portions, and a plurality of transition regions that are in contact with the same field oxide portion are spaced apart; A gate structure is located on a first surface between the two field oxide portions and on a portion of the field oxide layer away from the epitaxial layer, and a portion of the gate structure is in contact with the transition region. The transition region has a first doping type, and the epitaxial layer has a second doping type, wherein the first doping type and the second doping type are opposite.

2. The semiconductor device according to claim 1, characterized in that, The gate structure includes a gate oxide layer and a gate, the gate oxide layer is located on the first surface and contacts the field oxide layer, the gate covers the gate oxide layer and a portion of the field oxide layer, and the transition region includes: A first transition region is in contact with the gate. A second transition region is spaced apart from the first transition region. The second transition region and the first transition region are distributed alternately. The second transition region is in contact with the field oxidation part. Multiple second transition regions in contact with the same field oxidation part are distributed at intervals.

3. The semiconductor device according to claim 2, characterized in that, The portion of the first surface located between the two field oxide portions and in contact with the gate structure is the first contact portion, and the portion of the first surface in contact with the first transition region is the second contact portion. The first contact portion is located within the second contact portion.

4. The semiconductor device according to claim 1, characterized in that, It also includes a gate ohmic contact located on the side of the gate structure away from the substrate, the gate ohmic contact contacting a portion of the gate structure, the gate ohmic contact being spaced from a first contact portion in a predetermined direction, the predetermined direction being the arrangement direction of the field oxide portions, and the first contact portion being the portion of the first surface located between two of the field oxide portions and in contact with the gate structure.

5. The semiconductor device according to claim 2, characterized in that, The second transition region is also in contact with the gate oxide layer.

6. The semiconductor device according to claim 2, characterized in that, The first transition region includes a first portion corresponding to the first contact portion, and the portion of the first transition region other than the first portion is a second portion. The second portion is in contact with at least two adjacent field oxide portions, and the first contact portion is the portion of the first surface located between two field oxide portions and in contact with the gate structure.

7. A method for fabricating a semiconductor device, characterized in that, The method for preparing the semiconductor device according to any one of claims 1 to 6 comprises the following steps: A substrate is provided, the substrate comprising a stacked substrate and an epitaxial layer; Ion implantation is performed on the first surface of the epitaxial layer to form a transition region. The first surface is the side of the epitaxial layer facing away from the substrate. The transition region has a first doping type, and the epitaxial layer has a second doping type. The first doping type and the second doping type are opposite. Multiple spaced field oxide portions are deposited on the first surface, the multiple field oxide portions constitute a field oxide layer, and multiple transition regions in contact with the same field oxide portion are spaced apart. A gate structure is formed on the first surface located between the two field oxide portions and on a portion of the field oxide layer away from the epitaxial layer, with a portion of the gate structure in contact with the transition region.

8. The preparation method according to claim 7, characterized in that, The steps for forming the transition region include: A patterned mask layer is formed on the first surface, and the area covered by the mask layer in the epitaxial layer is the first region; Ion implantation is performed on the first region to form the transition region, the transition region including a first transition region and a second transition region, the first transition region being in contact with the gate, the second transition region being spaced apart from the first transition region, the second transition region and the first transition region being alternately distributed, the second transition region being in contact with the field oxide portion, and a plurality of second transition regions in contact with the same field oxide portion being spaced apart.

9. The preparation method according to claim 8, characterized in that, The steps of forming the field oxide layer and the gate structure include: A pre-field oxide layer is formed on the first surface; The pre-formed field oxide layer is etched to form a plurality of field oxide portions. The first surface has a first contact portion that is exposed between at least two adjacent field oxide portions, and the plurality of field oxide portions constitute the field oxide layer. A gate oxide layer is formed on the first surface, wherein the gate oxide layer and the field oxide layer are in contact; The gate is formed on the gate oxide layer, the field oxide layer, and the first contact portion. The gate covers the gate oxide layer and a portion of the field oxide layer. A portion of the gate contacts the first transition region. The gate oxide layer and the gate constitute the gate structure. The gate structure contacts the first contact portion.

10. The preparation method according to claim 9, characterized in that, At least two adjacent field oxidation portions have a spacing region corresponding to the first contact portion, and the preparation method further includes the following steps: A portion of the isolation dielectric layer fills the spacer region, and a portion of the isolation dielectric layer contacts the gate.

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