Method for producing a microelectronic device on an fd-soi substrate, corresponding device and integrated circuit comprising the device

Abstract

The invention relates to a method for producing a microelectronic device on an FD-SOI substrate, wherein the method comprises: forming a first well in a substrate (11) of a first wafer made of insulating material suitable for forming a shallow trench isolation (STI) (14); forming a strained silicon film (23) (sSi) covered with an oxide layer (24) on a second wafer; bonding the second wafer, after a vertical flip, onto the first wafer so that the oxide layer becomes a buried oxide layer (BOX) covered with the sSi film, which thus becomes a strained silicon on insulator film; removing the donor substrate while retaining the BOX layer and the sSi film; and forming a second isolation trench SSTI (34) by local oxidation of the silicon of the sSi film, which is connected to the STI via the BOX, to form a composite isolation structure (STI-BOX-SSTI).

Description

Technical Field

[0001] This invention relates to the microelectronics industry or the semiconductor industry, and specifically to the fabrication of microelectronic structures on SOI (silicon-on-insulator) substrates. The invention also relates to microelectronic structures obtained by this fabrication method.

[0002] This invention is particularly applicable to the manufacture of integrated semiconductor devices, such as microelectromechanical systems (MEMS) or nanoelectromechanical systems (NEMS), or microelectronic or optoelectronic devices such as image sensors (or imagers) in CMOS (complementary metal-oxide-semiconductor) technology, or any other microelectronic devices produced using this technology. Background Technology

[0003] Since the 1950s, the microelectronics industry has been pursuing miniaturization of microelectronic devices. The fundamental component of microelectronic devices is the field-effect transistor, especially the MOS (metal-oxide-semiconductor) transistor, particularly in CMOS (complementary metal-oxide-semiconductor) technology. It is used as a device to switch between two different electrical states corresponding to two opposite logic states (1 or 0 in binary logic). The miniaturization of MOS transistors has led to better control over their electrical characteristics, especially the amount of current flowing through the conductive channels of these transistors per unit time, and their switching speed depends on the amount of this current.

[0004] However, the speed of current depends primarily on the material it passes through. Since microelectronic chip manufacturers are more or less limited to using silicon (Si) substrates, they focus their efforts on increasing switching speed by reducing the size of transistors, such as MOS transistors, especially in CMOS technology.

[0005] In this regard, silicon-on-insulator (SOI) substrates are now widely used to fabricate transistor-based microelectronic devices. However, after decades of advancements in technological methods, the industry has found it increasingly difficult to further reduce the size of transistors.

[0006] For this reason, a technology developed about 20 years ago by the Leti Lab and its partners at the Atomic Energy and Alternative Energy Commission (CEA), called FD-SOI (Fully Depleted Silicon-on-Insulator), proposed a new ultrathin MOS transistor architecture whose channels can therefore be completely depleted (FD), in other words, doped. FD-SOI makes it possible to address the challenges of miniaturization while combining high performance and low power consumption, especially in integrated circuits for millimeter-wave and radio-frequency (RF) analog applications up to 100 GHz (such as for 5G phones). In fact, FD-SOI technology has made it possible to reach technology nodes equal to or below 10 nm, even 7 nm.

[0007] FD-SOI technology differs from thicker conventional SOI structures, such as conventional MOS transistor technology, where the channel is formed in a bulk silicon substrate, and Intel®'s FinFET (Fin Field-Effect Transistor) technology, where the Fin Field-Effect Transistor is a non-planar or 3D transistor built on a bulk substrate, with the gate placed on two, three, or four sides of the channel to form a multi-gate structure. Compared to these technologies, FD-SOI technology enables higher current flow rates because the components are not made of bulk silicon, but rather of an ultrathin silicon layer placed on a thin insulating oxide layer, which itself rests on a silicon substrate that no longer needs to be doped. Therefore, transistors fabricated on SOI substrates (which are planar transistors and thus easier to manufacture than FinFET transistors) are less sensitive to current leakage between the source and their drain, and also less sensitive to current leakage from the silicon carrier substrate. This improves their switching speed without requiring further miniaturization.

[0008] However, the current flow rate is known to also depend on the crystal structure of silicon. This is why SOI substrates currently tend to use strained silicon to fabricate the active regions of microelectronic devices, such as the channels in transistors in CMOS technology. The use of strained silicon, or sSi, is currently one of the most important factors accelerating the development of CMOS technology on silicon. Specifically, the increased charge carrier mobility obtained by applying appropriate stress to the crystal structure enables an increase in the velocity of these charge carriers in the MOS transistor channel, resulting in higher current at a fixed supply voltage and a fixed gate oxide thickness.

[0009] In practice, strained silicon (sSi) is a silicon layer in which silicon atoms are stretched (tensile stress) or compressed (compressive stress) beyond their normal interatomic distance. A strained silicon layer under tensile stress can be obtained by placing a thin silicon layer on a silicon-germanium (SiGe) substrate. When the atoms of the silicon layer align with the atoms of the underlying silicon-germanium layer (which are spaced slightly further apart than the atoms in a bulk silicon crystal), the bonds between the silicon atoms are stretched, creating a deformed silicon atomic lattice. This increases the mobility of these charge carriers, resulting in better chip performance and lower power consumption. Therefore, electrons can move up to 70% faster, meaning that the switching speed of an sSi NMOS transistor can be increased by 35%.

[0010] FD-SOI technology and the use of sSi can be combined to bring together the advantages of these two major technological advancements. This involves bonding a strained silicon (sSi) film on top of a very thin buried oxide (BOX) layer formed on an undoped silicon support. Bonding strained silicon (sSi) films to such substrates is described, for example, in prior art documents EP 1923912 A1 and US 5691231A.

[0011] The thinness of the buried oxide (BOX) layer beneath a strained silicon (sSi) film presents bonding problems when the film is continuous (i.e., unpatterned). This is particularly due to the fact that gaseous hydrogen in the atmosphere in which the bonding operation takes place must be absorbed by the BOX for bonding to occur, and when the BOX is very thin, there is a risk of bonding defects. The solution disclosed in EP 1923912 A1 for bonding a portion of a donor wafer containing the active layer of a microelectronic device to a carrier wafer provides a satisfactory solution to the bonding problem of sSi films on BOX.

[0012] However, it has become apparent that the subsequent etching patterns that form shallow trench isolation (STI) between components fabricated at adjacent locations in the active layer of the microelectronic device have introduced problems. Shallow trench isolation (STI), also known as cell isolation, prevents current leakage between adjacent components of a microelectronic device, provided that the laterally adjacent components are isolated from each other by such isolation trenches, and the microelectronic device is fabricated on the same semiconductor substrate. For many years, STI technology has been widely used in CMOS technologies of 250 nanometers and below.

[0013] However, when seeking to create active regions that are isolated from each other and each comprise a corresponding portion of a strained silicon (sSi) film, it has been found that the stress on the sSi tends to relax, in other words, decreases at the edges of the created active regions (where the sSi film is cut off). This occurs when etching a pattern to fill the insulator to form an isolation trench (STI), because the etching physically damages the sSi film.

[0014] Document US20060071274A1 discloses a method for forming a bonded SOI wafer, comprising a first dielectric layer at a surface and a dielectric-filled trench extending from the surface toward the interior of a semiconductor. The first wafer (after flipping) is bonded to a second wafer to form a bonded wafer, the bonded wafer comprising a body substrate (i.e., the substrate of the second wafer), a buried dielectric layer covering the body, and a semiconductor-on-insulator (SOI) layer covering the buried dielectric layer, the dielectric-filled trench extending upward from the buried dielectric layer into the SOI layer.

[0015] Document FR3051595A1 discloses an improvement to a method for fabricating strained silicon-on-insulator (sSOI) substrates, the method comprising transferring at least a portion of the stress present in a strained silicon-germanium (Si-Ge) layer located on the surface of a receiving substrate to an initially relaxed single-crystal silicon (Si) layer of a donor substrate, the donor substrate being bonded to the receiving substrate via a dielectric layer of a buried insulator layer intended to form an SOI. Summary of the Invention

[0016] The object of the present invention is to overcome at least some of the disadvantages of the prior art, and more specifically, to propose an alternative to the current practice of forming shallow trench isolation (STI), which prevents stress relaxation in the silicon in the discontinuous portions of the continuous strain silicon film due to the formation of the isolation trench that divides the continuous strain silicon film into the discontinuous portions, so as to maintain its good conductivity.

[0017] Therefore, the present invention relates to a method for manufacturing microelectronic devices, the method comprising:

[0018] - Provide a first wafer, which includes a carrier substrate;

[0019] - A first isolation trench is formed on the carrier substrate of the first wafer;

[0020] - Provide a second wafer, which includes a donor substrate;

[0021] - A strained silicon film is formed on the donor substrate of the second wafer;

[0022] - Bond the second wafer to the first wafer such that the strained silicon film is located on the first wafer by means of at least one insulating material layer, the at least one insulating material layer being formed on the first wafer before bonding, after the formation of the first trench, and / or on the second wafer after the formation of the strained silicon film;

[0023] - Remove the donor substrate while retaining the insulating material layer and strained silicon film on the first wafer;

[0024] - A second isolation trench is formed around and / or along a portion of the strained silicon film.

[0025] Therefore, embodiments of the present invention are based on the following combination:

[0026] - On the one hand, a donor wafer, including the strained silicon film to be transferred, is bonded to a carrier wafer having a pattern forming isolation trenches (STI); and,

[0027] - On the other hand, the additional oxidation of the strained silicon film performed after the film is transferred onto the carrier wafer,

[0028] This allows for the creation of additional shallow isolation trenches (STIs) that connect with the insulator already present at deeper levels of the STI trenches, without cutting through the strained silicon film. Advantageously, the strained silicon film is not cut, specifically because it is only locally converted into silicon dioxide. Therefore, in the corresponding portions of the strained silicon film created by forming the isolation trenches, the stress in the silicon does not relax.

[0029] The following section outlines some preferred but non-restrictive aspects.

[0030] In some embodiments, the following can be provided:

[0031] - The first isolation trench formed in the carrier substrate of the first wafer is a trench referred to as a "shallow trench" or STI, and the depth of the first isolation trench is greater than about 5 nm, or from about 5 nm to about 300 nm, preferably from about 50 nm to about 300 nm, and even more preferably from about 70 nm to about 300 nm; and / or

[0032] - The depth of the second isolation trench is equal to or greater than the thickness of the strained silicon film, for example, from about 10 nm to about 20 nm, for example, about 15 nm.

[0033] The insulating material of the first trench, the insulating material of the second trench, and / or the insulating material layer may be silicon dioxide (SiO2).

[0034] In some embodiments, a first trench may be formed in a carrier substrate by etching through a first mask previously produced by photolithography in a hard material layer (e.g., nitride) covering the carrier substrate provided via an associated insulating material layer. After the first trench is formed, any residue of the first mask and the associated insulating material layer is removed from the carrier substrate.

[0035] In some embodiments, the method further includes forming a third isolation trench produced via a second mask previously produced by photolithography in a hard material layer (e.g., a nitride) deposited on top of an associated insulating material layer, which itself is deposited on a strained silicon layer after the donor substrate is removed, and removing any residue of the second mask and the associated insulating material layer after the third trench is formed.

[0036] For example, the second isolation trench is connected to the first trench through an insulating material layer to form an isolation structure surrounding and along the strained silicon film.

[0037] The second trench can be produced by localized oxidation of silicon in a strained silicon film. For example, localized oxidation of silicon in a strained silicon film is thermal oxidation, such as LOCOS-type oxidation.

[0038] In some embodiments, the donor substrate can be removed by polishing, selective removal, or by implantation fracture (e.g., using the Smart-Cut® method).

[0039] The donor substrate of the second wafer may include a silicon-germanium (Si-Ge) layer adapted to stress the silicon in the strained silicon film.

[0040] In some embodiments, at least one opening may be created through the thickness of one of the second trenches and through the insulating material layer to expose the underlying carrier substrate in a region of the carrier substrate where there is no first trench. Furthermore, the silicon (Si) of the carrier substrate is grown upward through epitaxial growth in the opening, reaching at least to and including the level of the insulating material layer.

[0041] In some embodiments, at least some of the second isolation trenches may have the same horizontal dimensions as the associated first trenches and be vertically aligned with the associated first trenches, respectively.

[0042] According to a second aspect of the invention, a microelectronic structure obtained by implementing the manufacturing method according to the first aspect described above is also proposed, the structure comprising unconnected active regions on the surface of the same carrier substrate, the active regions being isolated from each other by deep and shallow isolation trenches, each active region having a corresponding portion of a strained silicon film, and the strained silicon film portions being located on the same insulating layer, the insulating layer itself being located above the carrier substrate.

[0043] Strained silicon can be, for example, silicon-on-insulator of the fully depleted type.

[0044] The insulating material of the first trench, the insulating material of the second trench, and / or the insulating material layer may be silicon dioxide (SiO2).

[0045] The second groove can have non-vertical sides.

[0046] According to a third aspect, an integrated circuit is proposed, which includes a microelectronic structure according to the second aspect above, and further includes at least one MOS-type field-effect transistor produced in the active region of said microstructure, wherein a portion of the strained silicon film serves as a fully depleted silicon-on-insulator (FD-SOI) substrate, and the channel of the MOS transistor is produced in said substrate. Attached Figure Description

[0047] Other aspects, objects, advantages, and features of the invention will become clearer upon reading the following detailed description of preferred embodiments of the invention. This description is provided by way of non-limiting example and references the accompanying drawings, in which:

[0048] - Figures 1A to 1C This is a schematic vertical cross-sectional view of an example of a carrier wafer with shallow isolation trenches (STI) produced prior to bonding the donor wafer to the carrier wafer according to an embodiment of the present invention, during the corresponding steps of its fabrication.

[0049] - Figure 2 This is a schematic vertical cross-sectional view of an example donor wafer including a strained silicon layer intended to be transferred via bonding. Figure 1C The carrier wafer;

[0050] - Figure 3A The diagram schematically depicts bonding the donor wafer and its strained silicon layer together to the carrier wafer after the donor wafer is vertically flipped.

[0051] - Figure 3B Is Figure 3A A schematic vertical cross-sectional view of the new wafer obtained after bonding;

[0052] - Figure 4 yes Figure 3B A schematic vertical cross-sectional view of the wafer after the substrate of the (original) donor wafer has been removed;

[0053] - Figure 5 yes Figure 4 A schematic vertical cross-sectional view of the wafer after the formation of an oxide isolation layer followed by the formation of a nitride protective passivation layer;

[0054] - Figure 6 Showing Figure 5 A vertical cross-sectional view of the wafer after forming a well through oxide and nitride layers to expose the strained silicon layer transferred onto the carrier wafer;

[0055] - Figure 7 It is filled with insulating material Figure 6 The diagram shows a schematic vertical cross-section of a wafer after isolation trenches are formed by localized oxidation of strained silicon. These isolation trenches are connected to trenches located at a deeper level that were already produced in the substrate of the carrier wafer before the strained silicon film was transferred by bonding through the donor wafer.

[0056] - Figure 8 Showing Figure 7 Microstructure after removing the hard mask of dielectric nitride;

[0057] - Figure 9 This is a schematic vertical cross-sectional view of the wafer obtained after removing oxide residues and planarizing.

[0058] - Figure 10 A flowchart illustrating an example of the steps of an embodiment of the method according to the present invention; and,

[0059] - Figure 11 This is a schematic vertical cross-sectional view of an example of an electronic circuit obtained by this method after creating an opening in silicon that allows access to the carrier wafer. Detailed Implementation

[0060] Throughout the accompanying drawings and the remainder of the description, the same reference numerals denote the same or similar elements. Furthermore, for clarity in the drawings, various elements are not shown to scale. Moreover, the various embodiments and variations described are not mutually exclusive and can be combined with each other.

[0061] In the following text, the terms “basically,” “approximately,” and “on the order of magnitude” mean within 10%, preferably within 5%. Furthermore, expressions “to… to…” or equivalent expressions include endpoints, unless otherwise explicitly stated.

[0062] The phrase “based on…” used in relation to materials and elements of interest means that the material is a compound formed from a plurality of elements including at least the element of interest.

[0063] The term "material" that "mainly contains" the element of interest means a material in which at least 50% of its volume is composed of or contains the element of interest.

[0064] The term "wafer" refers to a very thin, single-crystal semiconductor material substrate on which microelectronic devices can be fabricated. Wafers are used in the microelectronics industry as carriers for creating microstructures to fabricate microelectronic devices, which are then integrated into packages to obtain integrated circuits. A wafer comprises a substrate made of doped semiconductor materials such as silicon (Si), gallium arsenide (GaAs), or indium phosphide (InP). This doped semiconductor material serves as the substrate for creating the microstructures that form active microelectronic devices used in the composition of integrated circuits, transistors, power semiconductor products, MEMS, or NEMS, etc. This fabrication uses design techniques such as, but not limited to: photolithography, doping, etching, depositing other materials in layers or by diffusion or any other physical / chemical reaction, polishing, etc. Industrially produced wafers typically range in size from 25.4 mm (1-inch technology) to 300 mm (8-inch technology) and are approximately 0.7 mm thick.

[0065] "Layer" refers to the extent of a crystalline material whose thickness along the Z-axis is less than (for example, ten or even twenty times smaller) its longitudinal dimensions of width and length in the XY plane.

[0066] "Anisotropic etching" means that the etching rate of silicon is not the same in all directions during the etching process. Instead, only the vertical direction of silicon is etched during the etching process, while the lateral direction is not etched. In contrast, in "isotropic etching," there is no preferred etching direction, so all exposed surfaces (regardless of their orientation in space, in other words, whether they are horizontal, vertical, or inclined) are etched simultaneously.

[0067] Chemical mechanical polishing (CMP) is a process that uses the combined action of mechanical abrasion and chemical erosion to smooth a surface. It uses an abrasive polishing suspension or slurry that removes one or more materials from the wafer surface and eliminates any surface morphology, resulting in planarization of the wafer surface exposed to the process. The duration of a CMP process depends on the removal rate and the thickness of material to be removed before reaching the etch stop layer (if any).

[0068] The term "photoresist" refers to a material used for photolithography, more specifically a polymer resin that is photosensitive and used to form patterns on a wafer. This is achieved by using a photomask consisting of opaque and transparent regions that define the pattern to be reproduced on the wafer, through which the photoresist is irradiated. Due to this irradiation, the properties of the photoresist in the transparent regions of the optical filter are altered. Thus, for example, a "positive" photoresist is a photosensitive polymer that, when exposed to ultraviolet (UV) light, transforms into a soluble material: the areas exposed to this irradiation can then be dissolved with a solvent, leaving (what is known to those skilled in the art as development) a layer with a recessed pattern, which can be used as a mask to form a structure through the mask thus formed. For example, this structure can be formed by etching a pre-existing underlying material that is selective to the mask material, or by ion implantation into that underlying material, or by depositing new material in the areas exposed by the mask.

[0069] Finally, a directly orthogonal three-dimensional reference frame (X, Y, Z) is defined here and in the remainder of the specification, wherein the X and Y axes form a plane parallel to the principal plane of the carrier wafer under discussion, and wherein the Z axis is oriented substantially orthogonal to the principal plane of the wafer, the Z axis being oriented along the axis of gravity. In the remainder of the specification, the terms “vertical” and “perpendicularly” are understood to mean an orientation substantially parallel to the Z axis, while the terms “horizontal” and “horizontally” are understood to mean an orientation substantially parallel to the plane (X, Y). Furthermore, the terms “top” and “bottom” and their derivatives (e.g., “above” and “below”, or “on top” and “below”), and the terms “lower” and “upper” used to define elements of the microstructure under discussion, should be understood to relate to an increase in position as the wafer moves upwards (i.e., in the vertical direction + Z) away.

[0070] On the other hand, the terms "back side" and "front side" are used to refer to the side of a wafer through which various processes are performed to produce the microstructures in question. Since these processes are systematically performed from top to bottom when the wafer is placed flat in a housing for performing the processes, the "front side" (by default) is typically the top side of the wafer. However, when a wafer or a die cut from a wafer is flipped vertically, its front side becomes the bottom side, and its back side becomes the top side. The term "back side" for the semiconductor substrate assigned to a single wafer or die is also used with reference to this convention, referring to the portion of the substrate furthest from the wafer or die (the side of the substrate that has been processed), and this portion is always referred to as the back side even when the wafer or die has been flipped vertically.

[0071] In the following description of method embodiments, the microelectronic device of interest is formed on a carrier wafer by a base carrier wafer and a donor wafer. These two wafers are assembled by bonding after the donor wafer is vertically flipped to form a new carrier wafer on which a strained silicon film has been transferred. This wafer is intended for use in manufacturing integrated semiconductor products, such as those in CMOS technology, and the aim of this method is to fabricate shallow isolation trenches (STIs) in a manner compatible with retaining the advantages of FD-SOI technology. The described method embodiments may be adapted to specific aspects of each relevant application without departing from the teachings of the invention.

[0072] like Figure 1A As shown, the carrier wafer 1 is based on a carrier substrate 11, such as a substrate made of single-crystal silicon. The carrier substrate 11 is lightly doped, for example, with p-type doping. This doping can be achieved by introducing electron acceptor atoms (e.g., boron (B) atoms) into the substrate.

[0073] refer to Figure 10 The flowchart steps 101 and 102, step 101 includes depositing a protective layer 12 on a substrate 11, the protective layer 12 being typically based on an oxide (Ox), and then depositing a hard material layer in step 102, the hard material layer being, for example, based on a dielectric nitride (Nx), intended to form a hard mask for subsequent etching operations to form shallow isolation trenches or STI (shallow trench isolation).

[0074] The oxide of layer 12 can be, for example, silicon dioxide (SiO2). SiO2 deposition can include chemical deposition, such as low-pressure chemical vapor deposition (LPCVD) to form high-temperature oxide (HTO). It can also include chemical deposition, such as plasma-enhanced chemical vapor deposition (PECVD), using TEOS (tetraethyl orthosilicate, chemical formula Si(OCH2CH3)4 or more simply Si(OEt)4) as a seed crystal for silicon dioxide (SiO2), followed by simple hydrolysis, which can then form SiO2 by releasing ethanol (CH3CH2OH). Alternatively, deposition can be performed by physical methods, such as cathode sputtering or spin-off deposition.

[0075] The dielectric nitride of layer 13 can be, for example, silicon nitride or Si3N4 (SiN for short). This hard material can be deposited by chemical vapor deposition (CVD), such as low-pressure chemical vapor deposition (LPCVD). This method is performed at relatively high temperatures. Alternatively, silicon nitride layer 13 can be formed by plasma-enhanced chemical vapor deposition (PECVD), which is performed at relatively low temperatures and under vacuum. The resulting SiN layer can have a thickness of, for example, about one hundred nanometers (nm). Other dielectric materials, particularly titanium nitride (TiN) and tungsten nitride (W), as well as various types of oxynitride, can also be used in place of or added to silicon nitride (SiN).

[0076] Now for reference Figure 1B The fabrication of the carrier wafer 1 continues, and isolation trenches 14, i.e., shallow isolation trenches (STI), are produced in the thickness of the substrate 11 of the wafer 1. According to one embodiment, refer to... Figure 10 The flowchart includes a sequence of the following steps:

[0077] - Photolithography step 103, by forming a hard mask for etching, defines the area to be etched in the Si3N4 layer 13 and the protective layer 12 made of SiO2;

[0078] - Step 104, etching layers 13 and 12, made of Si3N4 and SiO2 respectively, through the hard mask formed in step 103, to create wells designed to form isolation trenches (STI) 14 in silicon 11; and,

[0079] - Gap filling step 105: Fill the trench with insulating material to form the STI.

[0080] Step 103 involves isolating the mask required for etching using standard photolithography methods.

[0081] In step 104, the selective etching of the silicon nitride layer 13, followed by the silicon dioxide (SiO2) protective layer 12, can be anisotropic etching, such as reactive ion etching (RIE). This is a variation of plasma etching (dry etching, highly anisotropic) that combines the selectivity of chemical etching with the anisotropy of physical etching. The plasma can be fluorocarbon plasma, based on a gas such as carbon tetrafluoride (CF4), or based on sulfur hexafluoride (SF6), or based on nitrogen trifluoride (NF3), or any combination of these gases. The insulating material layer to be etched is placed in a vacuum chamber, partially protected by an etching mask, for example, formed by a partially opened silicon dioxide layer. The chamber has two horizontal and parallel electrodes, with the lower electrode serving as a receiving plate for the wafer. Once a vacuum is created in the chamber, gas is introduced into it. A strong radio frequency (RF) electric field, for example, about 100 volts per meter or higher, is then applied to the lower electrode. This generates plasma, i.e., partially ionized gas, in the chamber. Specifically, some electrons in the gas molecules are pulled out by an electric field, ionizing the molecules. The top side of the wafer is then bombarded with ions, breaking it apart in the area not protected by a hard mask. Alternatively, the selective etching in step 104 can be chemical etching (or wet etching), for example by a hydrofluoric acid (HF)-based solution, or physical etching (or dry etching), i.e., plasma etching.

[0082] Step 105 is an interstitial filling step, which involves filling the trenches 14 previously formed in step 104 with a thick oxide layer (e.g., silicon dioxide (SiO2)). This step 105 allows insulating material to be deposited from the top surface of the microstructure down to the bottom of the trenches 14. Chemical mechanical polishing (CMP) enables the removal of excess SiO2 deposited on the surface and smoothing of the top surface of the microstructure, such as… Figure 1B As shown, it depicts the microstructure following the sequence of steps 103, 104, and 105. As those skilled in the art will understand, the oxide deposited in trench 14 in step 105 enables the production of isolation trenches (STIs) in the substrate 11 of the carrier wafer 1 even before the strained silicon layer is deposited by transfer from the donor wafer 2.

[0083] In some embodiments, the depth of trench 14 is greater than about 5 nm. It can be from about 5 nm to about 300 nm, preferably from about 50 nm to about 300 nm, and even more preferably from about 70 nm to about 300 nm.

[0084] Alternatively, trench 14 can be filled with silicon nitride (SiN) (e.g., Si3O4) instead of silicon dioxide (SiO2).

[0085] Now for reference Figure 1CThe next step 106 is a chemical mechanical polishing (CMP) step, where etching stops on the silicon of substrate 11. This allows for the simultaneous removal of the nitride hard mask of layer 13 and the silicon dioxide residue of layer 12. Where applicable, this involves lightly oxidizing the silicon of substrate 11 after CMP etching stops to rebuild protection through a thin layer of silicon dioxide (SiO2). Alternatively, CMP etching may stop on the nitride. The nitride is then chemically removed, and the silicon dioxide is removed, for example, by wet chemical removal using a hydrofluoric acid (HF) solution.

[0086] Figure 2 The diagram illustrates a donor wafer 2 comprising a strained silicon (sSi) film. For example, the sSi film is a thin silicon (Si) layer 23 in which silicon atoms are stretched beyond their normal interatomic distances. This can be obtained by depositing the thin silicon layer 23 on a silicon-germanium (SiGe)-based substrate 22, which itself is formed on a base substrate 21 made of silicon, using any suitable silicon deposition method. When the atoms of the thin silicon layer 23 align with the atoms of the underlying silicon-germanium layer 22 (which are spaced slightly further apart than the atoms in the bulk silicon crystal), the bonds between the silicon atoms in layer 23 are stretched, creating a deformed silicon atomic lattice. Spacing these silicon atoms reduces the atomic forces that interfere with the movement of electrons through the channels of the MOS transistors formed in the strained silicon (sSi) layer 23. This improves the mobility of these charge carriers, resulting in better transistor performance and lower power consumption. The donor wafer 2 then includes an oxide layer 24, such as silicon dioxide (SiO2)-based. Alternatively, instead of silicon dioxide (SiO2), layer 24 can be made of another insulating material, particularly another oxide, such as a metal oxide, such as aluminum oxide (Al2O3), germanium oxide (GeO2), tin oxide (SnO2) which is a semiconductor, lead oxide (PbO2), hafnium oxide (HfO2), or tantalum oxide (Ta2O5).

[0087] Notice, Figure 2 The fabrication of donor wafer 2 shown is not described in detail here to avoid unnecessarily lengthening this specification. It does not actually have a significant impact on the implementation of the method of the present invention. If necessary, those skilled in the art can refer to available prior art literature on FD-SOI technology.

[0088] refer to Figure 3A As shown in the schematic diagram, in step 107, the donor wafer 2 is vertically flipped, then aligned and bonded to the carrier wafer 1 to produce... Figure 3B The microstructure 3 shown is sometimes referred to hereinafter as the new carrier wafer 3. Those skilled in the art will understand that, viewed from the top surface of the microstructure 3, the oxide layer 24 of the donor wafer 2 forms a buried oxide (BOX). For simplicity in the illustration, this BOX is... Figure 3AThe diagram shows that the oxide layer is only on donor wafer 2, but carrier wafer 1 can also have an oxide layer deposited after its associated CMP step 106 to promote bonding conditions. Alternatively, it can be specified that only carrier wafer 1 has the oxide layer, while donor wafer 2 does not.

[0089] refer to Figure 4 At this point, the substrates 21 and 22 of the (original) donor wafer 2 were removed, and the substrates were... Figure 10 Step 108 of the flowchart is shown.

[0090] In some embodiments, this can be achieved using the SmartCut® method invented by CEA, according to which a microstructure 3 consisting of a donor wafer 2 bonded to a primary carrier wafer 1 is subjected to a heat treatment that can split the microstructure 3 directly beneath the strained silicon (sSi) layer 23. The wafer 2 is first implanted with hydrogen (H) or helium (He) to create the weakened region.

[0091] Alternatively, the substrates 21 and 22 can be removed from the microstructure 3 by mechanical polishing or by chemical / mechanical polishing (CMP). In some variations, removal can be achieved by chemical wet etching.

[0092] Step 109 then includes Figure 4 An oxide-based (Ox) insulating layer 32 is deposited on the microstructure 3, followed by a nitride (Nx) layer 33 in step 110. This yields... Figure 5 The microstructure 3 is shown. The oxide layer 32 can be silicon dioxide (SiO2). The nitride layer 33 formed on top of layer 32 can be silicon nitride (SiN). Layers 32 and 33 can be respectively connected to the reference above. Figure 1A The same technological processes are used to manufacture layers 12 and 13 of carrier wafer 1. These processes will not be described again here.

[0093] refer to Figure 6 Next are photolithography step 111 and selective etching step 112, used to selectively etch wells 34 through the oxide layer 32 and the nitride layer 33, the bottoms of all these wells being located on the top surface of the strained silicon (sSi) layer 23, so as to form shallow isolation trenches by oxidizing the sSi of the thus exposed layer 23. Again in this case, the photolithography step 111 and selective etching step 112 that enable this result are similar to steps 103 and 104 already described, and therefore will not be described in detail here.

[0094] According to an embodiment of the invention, step 113 includes local oxidation of the strained silicon (sSi) of the layer 23 exposed at the bottom of well 34. Thus, a supplementary isolation trench, denoted as SSTI, is produced, which is based on silicon dioxide (SiO2) obtained through local oxidation of the strained silicon (sSi). In the remaining figures, "SSTI" refers to these thin buried oxide trenches 34. Oxidation can be performed via LOCOS and yields… Figure 7 The structure shown includes an SSTI connected to an STI initially formed in the substrate 11 of the original carrier wafer. Those skilled in the art will understand that, due to the use of the LOCOS method, the sides of the trench 34 are not vertical, but slightly inclined in the vertical direction Z.

[0095] In some embodiments, the depth of the supplementary isolation trench SSTI 34 is equal to or greater than the thickness of the strained silicon film 23, for example, from about 10 nm to about 20 nm, for example, about 15 nm.

[0096] LOCOS (Local Oxidation of Silicon) is a microfabrication method that forms silicon dioxide (SiO2) in a defined region of a silicon wafer, with the Si-SiO2 interface below the surface of the wafer itself. This technique was initially developed (before shallow trench isolation or STI) to isolate MOS field-effect transistors from each other, thereby limiting interference between transistors. A key advantage of this technique is the localized formation of a silicon dioxide structure penetrating below the wafer surface around the MOS transistors, which is not easily achieved through etching. In the context of this embodiment, thermal oxidation of the region of strained silicon (sSi) exposed by the hard mask 33 is also used, at temperatures between 800 and 1200°C, using either water vapor (wet oxidation) or hydrogen peroxide (dry oxidation). In both cases, under thermal action, oxygen (O2) penetrates deep into the wafer, reacts with the strained silicon (sSi) encountered in layer 23, and transforms it into silicon dioxide, forming a structure within the volume of the strained silicon (sSi).

[0097] Advantageously, the use of LOCOS technology under the conditions of this embodiment of the invention enables the formation of discontinuous and isolated regions 100, 200, and 300 of the strained silicon (sSi) film 23 without relaxation of the sSi, in other words, without stress relief in the sSi, because it is never opened. The isolation oxide SSTI thus formed is connected to the deeper isolation oxide STI (i.e., the gap filling of the shallow isolation trench STI produced in the well 14 formed in the silicon substrate of the original carrier wafer 1 before the donor wafer 2 is bonded to transfer the strained silicon (sSi) film 23 onto the carrier wafer 1). This advantageous feature utilized in the embodiments of the present invention is described, for example, in the scientific article: I. De Wolf, J. Vanhellemont, A. Romano‐Rodríguez, H. Norström, HE Maes; “Micro‐Raman study of stress distribution in local isolation structures and correlation with transmission electron microscopy”, Journal of Applied Physics 71 (2), pp. 898--906 (1992); January 15, 1992 (https: / / doi.org / 10.1063 / 1.351311), which may be consulted by those skilled in the art when necessary.

[0098] Next, step 114 may include removing silicon dioxide (SiO2) residue from the hard mask 33 and insulating layer 32 made of silicon nitride (SiN) to obtain Figure 8 The microstructure. For example, the removal of the hard mask made of silicon nitride (Si3N4) can be performed by a first chemical wet etching using a phosphoric acid (H3PO4)-based solution (e.g., diluted to 85%) at a temperature of approximately 180°C. The silicon dioxide (SiO2) of the insulating layer 32 can then be removed by a second wet etching (e.g., based on hydrofluoric acid (HF) acid). Alternatively, the removal of both the hard mask 33 and the silicon dioxide of the insulating layer 32 can be performed in a single etching operation, such as a wet etching based on hydrofluoric acid (HF) acid.

[0099] As those skilled in the art will understand, regions 100, 200, and 300 of this microstructure are discontinuous regions of strained silicon (sSi) on a thin insulating layer, which is the insulator (in this example, SiO2) of the underlying buried oxide (BOX) layer 24. By implementing the proposed method, the stress on the sSi in regions 100, 200, and 300 does not relax, even though regions 100, 200, and 300 are laterally and vertically isolated from each other by supplementary isolation trenches or SSTIs formed in the vertical extensions of isolation trenches (STIs) formed at a deeper level in the bulk substrate 11 of the original carrier wafer prior to bonding step 107. As described in the introduction of this specification, by utilizing the combined advantages of FD-SOI technology and strained silicon substrates, microelectronic devices, such as MOS transistors or more complex devices in CMOS technology, can be fabricated in the active regions corresponding to regions 100, 200, and 300 in this manner.

[0100] in other words, Figure 9 The microelectronic structure 3 depicted in the figure, which is produced according to an embodiment of the manufacturing method of the present invention, includes active regions 100, 200 and 300 that are disconnected (i.e. discontinuous) on the surface of the same carrier substrate 11 and isolated from each other by shallow isolation trenches (STI) 14, the shallow isolation trenches 14 extending vertically through buried oxide (BOX) layer 24 by supplementary isolation trenches (SSTI) 34, each active region having a corresponding portion of strained silicon (sSi) film 23, and the sSi film portion being located on the same insulating layer 24, which itself is located on the carrier substrate 11.

[0101] The integrated circuit may include the aforementioned microelectronic structure, and further include at least one MOS-type field-effect transistor fabricated in the active regions (such as regions 100, 200, and 300) of the microstructure, wherein a portion of the strained silicon film 23 serves as a fully depleted silicon-on-insulator (FD-SOI) substrate in which the channel of the MOS transistor can be fabricated. Therefore, the transistor benefits from the combined advantages of FD-SOI technology and the good conductivity contributed by stress on the silicon.

[0102] As those skilled in the art will understand, the connection between the filling well 34 to form the insulating material (i.e., silicon dioxide (SiO2)) of the supplementary isolation trench (SSTI) and the well 14 of the shallow isolation trench (STI) to form the final isolation structure is created by the buried oxide (BOX) of the silicon dioxide (SiO2) layer 24, and this connection is continuous. This is why it is called an STI-BOX-SSTI composite isolation structure.

[0103] At least some of the supplementary isolation trenches SSTI 34 have the same horizontal dimensions as the associated shallow isolation trenches SSTI 14, and are respectively horizontally aligned with the associated trenches 14. In other words, each of these trenches 34 completely overlaps with the trench 14 in the vertical direction Z, and none of them protrudes beyond the other in the vertical projection in the longitudinal direction X or the lateral direction Y. These trenches 34 and 14 are therefore referred to as vertically aligned. An example of such aligned trenches is shown in Figure 11 The lower right of the schematic diagram of the exemplary structure 3' shown (see below).

[0104] Another advantage of this method is that relatively deep isolation, such as the STI between active regions 100 and 200 with a thickness preferably from about 70 nm to about 300 nm, can be achieved in a single process, while relatively shallow isolation, such as the SSTI between active regions 200 and 300 with a thickness of about 10 nm to about 20 nm, can be achieved. It should be understood that these depths are considered in the vertical Y direction. The MOS transistors on the FD-SOI substrate can be formed in regions 200 and 300, respectively, in corresponding wells in the silicon substrate 11 with the same doping (doping type and doping level). In contrast, another MOS transistor on the FD-SOI substrate can be fabricated in region 100 in a well in the silicon substrate 11 that can have different doping, because the relatively deep isolation STI separates it from the wells in the silicon substrate 11 corresponding to regions 200 or 300.

[0105] According to another advantage, the device fabricated on wafer 2, which is on a silicon-on-insulator (SOI) substrate, can be placed on top of STI, making it very far away from any silicon on carrier wafer 1. Therefore, in operation, it will be very far from the polarization electric field, making it a single structure.

[0106] Finally, the possibility of forming a third isolation trench, different from the second supplementary isolation trench SSTI 34, through etching cannot be ruled out. These third trenches can be produced using a second mask, which is pre-formed using... Figure 5The hard material layer 33 (nitride in this example) is produced by photolithography and deposited on top of an associated insulating material layer 32, which itself is deposited on the strained silicon layer 23 after the donor substrate 22 is removed. After the third trench is formed, the second mask and any residue of the associated insulating material layer are removed. While etching to form the trench with the aid of a mask does result in a loss of stress in the sSi film, this loss is acceptable in some applications where the third isolation trench can be produced in this manner, in addition to forming a second supplementary isolation trench SSTI 34 through oxidation, which allows for the retention of stress in the sSi film 23.

[0107] Finally, refer to Figure 11 Another example of the microelectronic structure 3' shown (by means of...) Figure 9 The structure shown in Figure 3 is obtained using the same method steps, and is derived from... Figure 10 Box 115 in the flowchart indicates that at least one opening can be made through the thickness of one (or more) supplementary trenches (SSTI) 34 and through the buried oxide (BOX) layer 24 to expose the underlying bulk silicon substrate 11, as in regions 400 and 700 in the example. Figure 11 In the diagram, the supplementary isolation trench 34, thus traversed, is shown surrounded by a dashed box. For example, an insulating material (SSTI) layer 34 and an insulating material (BOX) layer 24 can be etched using a hard mask obtained by photolithography to expose the underlying carrier substrate 11 in corresponding areas where there are no shallow isolation trenches 14 (STIs) in the carrier substrate 11, thereby producing openings 400 and 700. Since the etched mask is produced after the trench STIs and SSTIs, it allows for alignment of the patterns of any of these trenches.

[0108] Note that opening 400 divides the supplementary isolation trench SSTI 34 discussed into two such derived SSTI trenches, which have smaller horizontal dimensions and are horizontally adjacent. Figure 11 In the example shown, the derived SSTI trench on the right is vertically aligned with the shallow isolation trench STI 14, which is associated with the shallow isolation trench STI 1 and is continuous with the shallow isolation trench STI 1 material through a portion of the buried oxide BOX layer 24 associated with them. This mutual alignment stems from the alignment of the masks used to form the three elements respectively, and provides a composite isolation structure (STI-BOX-SSTI) in the form of a single isolation trench made of SiO2.

[0109] Once openings 400 and 700 are formed in the SSTI, silicon (Si) of the carrier substrate 11 can be epitaxially grown upwards in the openings 400 and 700, at least reaching and including the insulating material layer 24 (BOX). Thus, access to the silicon (Si) of the carrier substrate 11 is provided without relaxing the active regions 500 and 600 (in... Figure 11 The stress in the strained silicon (sSi) film 23 shown in the figure.

[0110] More generally, if it is necessary to fabricate new trenches on the surface of the microelectronic structure 3' to access the silicon of the carrier substrate 11, considering that this cannot be achieved by directly etching the strained silicon (sSi) layer 23 without causing stress loss in the sSi film, then this can be done in the supplementary isolation trench SSTI 34 produced as described above. In fact, such etching in the SSTI trench does not cause relaxation of the sSi in the film 23, i.e., it does not affect the stress of the sSi film 23.

[0111] This provides, where applicable, the possibility of producing NOSO (Not-On-SOI) type microelectronic devices in (and / or on) a carrier substrate 11, in regions 400 and 700, which is a silicon-doped bulk substrate. Therefore, in addition to components (e.g., transistor 601 shown) produced in active regions 500 and 600 of FD-SOI on a strained silicon film, active components, such as active components in CMOS on a conventional bulk substrate, can be produced in the active regions shown below the surface of the bulk substrate 11, in regions 400 or 700.

[0112] Another possibility provided by regions 400 and 700 for accessing the silicon in substrate 11 is, for example, the ability (through metallization not shown) to polarize wells forming active regions in substrate 11, in which the source and drain of transistor 601 are fabricated. Figure 11 In the diagram, this polarization via region 400 is represented by arrow 401. It can also be achieved via... Figure 11 The well in question is located in the region between the 700 Polarized Shallow Isolation Trench (STI) 14, on the other side of one of these trenches. Figure 11 In the diagram, this polarization via region 700 is represented by arrow 701.

[0113] Specific embodiments have been described. Various alternatives and modifications will be apparent to those skilled in the art. For example, the bulk substrate 11 of the carrier wafer 1 need not necessarily be doped. If it is not necessary to produce components in this substrate, it can be an undoped silicon substrate, unlike the possibilities described above in reference regions 400 and 700.

Claims

1. A method for manufacturing a microelectronic device, the method comprising: - A first wafer (1) is provided, which includes a carrier substrate (11); - A first isolation trench (14) is formed on the carrier substrate (11) of the first wafer (1). - Provide a second wafer (2) which includes a donor substrate (21-22); - A strained silicon film (23) is formed on the donor substrate (21-22) of the second wafer (2); - The second wafer (2) is bonded to the first wafer (1) such that the strained silicon film (23) is located on the first wafer (1) by means of at least one insulating material layer (24), the at least one insulating material layer (24) being formed on the first wafer (1) before bonding, after the formation of the first trench and / or on the second wafer (2) after the formation of the strained silicon film (23); - Remove the donor substrate (21-22) while retaining the insulating material layer (24) and the strained silicon film (23) on the first wafer (1); and, - A second isolation trench (34) is formed around and / or along a portion of the strained silicon film (23).

2. The method according to claim 1, wherein: - The first isolation trench (14) formed in the carrier substrate (11) of the first wafer (1) is a trench referred to as a "shallow trench" or STI, and the depth of the first isolation trench (14) is greater than about 5 nm, or about 5 nm to about 300 nm, preferably about 50 nm to about 300 nm, even more preferably about 70 nm to about 300 nm; and / or - The depth of the second isolation trench (34) is equal to or greater than the thickness of the strained silicon film (23), for example, about 10 nm to about 20 nm, for example, about 15 nm.

3. The method according to claim 1 or claim 2, wherein, The insulating material of the first trench (14), the insulating material of the second trench (34) and / or the insulating material of the insulating material layer (24) is silicon dioxide (SiO2).

4. The method according to any one of claims 1 to 3, wherein, The first trench (14) is formed in the carrier substrate (11) by etching through a first mask, which is produced in advance by photolithography in a hard material layer (13), such as a nitride, which covers the carrier substrate provided via an associated insulating material layer (12). After the first trench (14) is formed, the residue of the first mask (13) and the associated insulating material layer (12) is removed from the carrier substrate (11).

5. The method according to any one of claims 1 to 4, further comprising forming a third isolation trench, the third isolation trench being generated by a second mask previously produced by photolithography in a hard material layer (33), the hard material layer (33) being, for example, a nitride, the hard material layer being deposited on top of an associated insulating material layer (32), the associated insulating material layer (32) being itself deposited on a strained silicon layer (23) after removal of the donor substrate, and removing the second mask (33) and any residue of the associated insulating material layer (32) after forming the third trench.

6. The method according to any one of claims 1 to 5, wherein, The second isolation trench (34) is connected to the first trench (14) via an insulating material layer (24) to form an isolation structure surrounding and along the strained silicon film (23).

7. The method according to any one of claims 1 to 6, wherein, The second trench (34) is produced by local oxidation of silicon in a strained silicon film (23), which is, for example, thermal oxidation, such as LOCOS-type oxidation.

8. The method according to any one of claims 1 to 7, wherein, The donor substrate (21-22) is removed by polishing, selective removal or by implantation fracture, for example using the Smart-Cut® method.

9. The method according to any one of claims 1 to 8, wherein, The donor substrate (21-22) of the second wafer (2) includes a silicon-germanium Si-Ge layer (22) which is adapted to stress the silicon of the strained silicon film (23).

10. The method according to any one of claims 1 to 9, wherein, At least one opening (400) is created through the thickness of one of the second trenches (34) and through the insulating material layer (24) to expose the underlying carrier substrate (11) in a region where there is no first trench (14) in the carrier substrate (11), and wherein, in addition, the silicon (Si) of the carrier substrate (11) is grown upward by epitaxial growth in the opening (400) to at least reach and include the level of the insulating material layer (24).

11. The method according to any one of claims 1 to 10, wherein, At least some of the second isolation trenches (34) have the same horizontal dimensions as the associated first trench (14) and are vertically aligned with the associated first trench (14).

12. A microelectronic structure obtained by implementing the manufacturing method according to any one of claims 1 to 11, the structure comprising unconnected active regions (100, 200, 300) on the surface of the same carrier substrate (11), the active regions being isolated from each other by deep and shallow isolation trenches (14-24-34), each active region having a corresponding portion of a strained silicon film (23), and the strained silicon film portion being located on the same insulating layer (24), the insulating layer (24) itself being located on the carrier substrate (11).

13. The microelectronic structure according to claim 12, wherein, The insulating material of the first trench (14), the insulating material of the second trench (34) and / or the insulating material layer (24) is silicon dioxide (SiO2).

14. The microelectronic structure according to claim 12 or 13, wherein, The second groove (34) has a non-vertical side.

15. An integrated circuit comprising a microelectronic structure according to any one of claims 12 to 14, and further comprising at least one MOS-type field-effect transistor produced in an active region (100, 200, 300) of said microstructure, wherein a portion of a strained silicon film (23) serves as a fully depleted silicon-on-insulator (FD-SOI) substrate in which the channel of the MOS transistor is produced.

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