Field effect transistor and power electronic system

Abstract

The application relates to a field effect transistor and a power electronic system. The field effect transistor comprises a substrate, a channel layer formed on the substrate, a barrier layer formed on the channel layer, a two-dimensional electron gas channel formed between the barrier layer and the channel layer, a source electrode, a gate electrode and a drain electrode formed on the barrier layer and arranged in sequence at intervals along a first direction, a P-type compensation island at least partially higher than the barrier layer and located between the gate electrode and the drain electrode, the P-type compensation island being spaced apart from the drain electrode and the gate electrode, a shielding plate located above the P-type compensation island, a passivation layer arranged between the shielding plate and the P-type compensation island, and the shielding plate being arranged at intervals from the gate electrode and the drain electrode. Through the coupling effect of the P-type compensation island and the shielding plate, the potential distribution between the gate electrode and the drain electrode is more uniform, thereby reducing the peak value of the high field on the drain side, improving the breakdown margin, and effectively reducing the virtual gate effect caused by electron capture after high-voltage turn-off, thereby greatly reducing the increase of the dynamic on-resistance.

Description

Technical Field

[0001] This application belongs to the field of semiconductor devices, specifically relating to a field-effect transistor and a power electronic system. Background Technology

[0002] Thanks to the high-density two-dimensional electron gas at the AlGaN (aluminum gallium nitride) / GaN (gallium nitride) heterojunction interface, GaN field-effect transistors exhibit high electron mobility, fast saturation drift velocity, high breakdown field strength, and excellent high-frequency operating characteristics, making them highly suitable for high-frequency, high-power-density power conversion applications. In current power device applications, silicon-based lateral GaN field-effect transistors are the most common commercial and research structures.

[0003] However, in existing GaN field-effect transistors, local electric field peaks are easily generated between the gate and drain under high-voltage off-state conditions. This high peak electric field not only limits the breakdown voltage of the device but also exacerbates the electron trapping effect at the surface and interface. When the device is turned on again, these trapped electrons trigger additional depletion effects, producing a virtual gate effect. This leads to a decrease in output current when the device is turned on again, resulting in severe current sag and increased dynamic on-resistance. Summary of the Invention

[0004] The purpose of this application is to provide a field-effect transistor and a power electronic system. Through the coupling effect of the P-type compensation island and the shielding plate, the potential distribution between the gate and the drain can be made more uniform, thereby reducing the high field peak on the drain side, increasing the breakdown margin, and effectively weakening the virtual gate effect caused by electron trapping after high voltage turn-off, thereby significantly reducing the increase in dynamic on-resistance.

[0005] To achieve the above objectives, this application provides a field-effect transistor, comprising:

[0006] Base; A channel layer is formed on the substrate; A barrier layer is formed on the channel layer, and a two-dimensional electron gas channel is formed between the barrier layer and the channel layer; The source, gate, and drain are formed on the barrier layer and arranged sequentially at intervals along the first direction; A P-type compensation island, at least partially above the barrier layer, is located between the gate and the drain. The space between the P-type compensation island and the drain is defined as a first isolation region, and the space between the P-type compensation island and the gate is defined as a second isolation region. A shielding plate is located above the P-type compensation island, and a passivation layer is provided between the shielding plate and the P-type compensation island. The orthographic projection of the shielding plate on the substrate and the orthographic projection of the P-type compensation island on the substrate at least partially overlap. The shielding plate is spaced apart from the gate and the drain.

[0007] In some exemplary embodiments of this application, the size of the first isolation region in the first direction is smaller than the size of the second isolation region in the first direction.

[0008] In some exemplary embodiments of this application, an isolation portion is formed in the region of the barrier layer corresponding to the first isolation region, and the isolation portion is configured to electrically isolate the P-type compensation island from the drain.

[0009] In some exemplary embodiments of this application, the region of the barrier layer corresponding to the first isolation region is a trench-type isolation portion, which penetrates the barrier layer and is embedded inside the trench layer; or The barrier layer is an AlGaN barrier layer, and the region of the barrier layer corresponding to the first isolation region is the isolation portion containing He, N, or F ions; or The barrier layer is an AlGaN barrier layer, and the region of the barrier layer corresponding to the first isolation region is the P-type doped isolation portion.

[0010] In some exemplary embodiments of this application, the lower surface of the P-type compensation island is attached to the upper surface of the barrier layer; or A portion of the P-type compensation island penetrates the barrier layer and is embedded within the channel layer, with the portion of the P-type compensation island entering the channel layer not exceeding 10 nm.

[0011] In some exemplary embodiments of this application, the shielding plate is a floating structure, or the shielding plate is electrically connected to the source electrode.

[0012] In some exemplary embodiments of this application, multiple P-shaped compensation islands are provided and arranged at intervals along a second direction, which intersects with the first direction.

[0013] In some exemplary embodiments of this application, multiple shielding plates are provided and arranged at intervals along the second direction.

[0014] In some exemplary embodiments of this application, the channel layer is a GaN channel layer, the barrier layer is an AlGaN barrier layer, and an AlN spacer layer is disposed between the GaN channel layer and the AlGaN barrier layer.

[0015] A second aspect of this application provides a power electronic system comprising a plurality of field-effect transistors as described in any of the preceding claims.

[0016] This application has at least the following beneficial effects: This application adjusts the local potential distribution of the gate-drain access region by setting an electrically isolated P-type compensation island in the region between the gate and drain (i.e., the gate-drain access region), and uses the shielding plate above it to redistribute the lateral and vertical electric fields of the gate-drain access region. This synergistic effect makes the potential distribution between the gate and drain more uniform, effectively reduces and disperses the local high electric field peak of the gate-drain access region, improves the breakdown margin, and can also effectively weaken the virtual gate effect caused by electron trapping after high voltage turn-off, thereby significantly reducing the increase in dynamic on-resistance.

[0017] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0020] Figures 1 to 4 Schematic cross-sectional structures of the field-effect transistors described in different embodiments of this application are shown respectively.

[0021] Figures 5 to 6 The following are schematic top views of the field-effect transistors described in different embodiments of this application.

[0022] Explanation of reference numerals in the attached figures: 10. Substrate; 101. Substrate; 102. Buffer layer; 11. Channel layer; 12. Barrier layer; 13. Source; 14. Gate; 15. Drain; 16. P-type compensation island; 17. Shielding plate; 18. Passivation layer; 19. Two-dimensional electron gas channel; 20. First isolation region; 21. Second isolation region; 22. Isolation section; 23. Cover layer; X, the first direction; Y, the second direction. Detailed Implementation

[0023] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0024] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0025] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0026] To address the drawback of localized electric field peaks between the gate and drain of GaN field-effect transistors during high-voltage turn-off, the following solutions have been proposed in related technologies: Option 1: Extend a metal field plate above the gate or source to effectively lengthen the depletion region and share the potential drop, thereby reducing the electric field peak at the drain-side gate edge and suppressing current collapse while increasing the device breakdown voltage. Furthermore, an optimized gate-source composite field plate structure can achieve a good balance between improving breakdown performance and reducing dynamic on-resistance degradation; however, this structure also introduces additional parasitic capacitance, which can affect the high-frequency characteristics of the device.

[0027] Option 2: Employ a P-type GaN gate or P-type AlGaN gate. This structure is primarily used to implement normally-off devices. The P-type region is typically located below the gate, with the core purpose of depleting the two-dimensional electron gas (2DEG) below the gate and increasing the threshold voltage. However, this increases the channel on-resistance, and the Mg acceptors in the P-type GaN layer introduce additional charge storage effects, leading to increased gate parasitic capacitance. Furthermore, the location of the electric field peak is relatively fixed (always located on the edge of the gate near the drain), making it impossible to flexibly adjust according to actual voltage conditions or device layout.

[0028] Option 3: Employing gate-injected transistors (GITs) and similar structures, this approach introduces a local P-type region to release trapped electrons, effectively mitigating the current collapse effect. However, while improving dynamic characteristics, such structures often come at the cost of sacrificing some leakage current characteristics or increasing on-resistance.

[0029] To address at least one of the aforementioned technical problems, this application proposes a field-effect transistor, which is a GaN field-effect transistor.

[0030] In this embodiment, reference Figure 1 As shown, a field-effect transistor includes at least a substrate 10, a channel layer 11, a barrier layer 12, a source 13, a gate 14, a drain 15, a P-type compensation island 16, and a shielding plate 17.

[0031] Continue to refer to Figure 1 As shown, a channel layer 11 is formed on a substrate 10; a barrier layer 12 is formed on the channel layer 11, and a two-dimensional electron gas channel 19 is formed between the barrier layer 12 and the channel layer 11, which is simply referred to as a 2DEG channel; a source 13, a gate 14, and a drain 15 are formed on the barrier layer 12 and are arranged sequentially at intervals along the first direction X, that is: in the first direction X, the gate 14 is located between the source 13 and the drain 15; at least part of the P-type compensation island 16 The upper surface of the P-type compensation island 16 is higher than the upper surface of the barrier layer 12, and is located between the gate 14 and the drain 15. The shielding plate 17 is located above the P-type compensation island 16, and a passivation layer 18 is provided between the shielding plate 17 and the P-type compensation island 16. The orthographic projection of the shielding plate 17 on the substrate 10 at least partially overlaps with the orthographic projection of the P-type compensation island 16 on the substrate 10. The shielding plate 17 is spaced apart from the gate 14 and the drain 15.

[0032] It should be noted that, in this application, the semiconductor region between the gate 14 and the drain 15 is defined as the gate-drain access region. This region is responsible for the lateral current access and potential drop distribution from the gate-controlled channel to the drain 15, and is a critical region with high drain-side electric field formation and strong trap sensitivity. The current collapse, dynamic on-resistance degradation, and local breakdown risk of GaN field-effect transistors are usually closely related to the electric field and trapping effect in this region.

[0033] Unlike the P-type GaN gate structure in the aforementioned Scheme 2, the P-type compensation island 16 in this application is located in the gate-drain access region and is electrically isolated from the gate 14. Unlike the field plate structure in the aforementioned Scheme 1, this application achieves coordinated control of electric field and charge through coupling between the local P-type compensation island 16 and the local shielding plate 17. That is, by setting the electrically isolated P-type compensation island 16 in the gate-drain access region, the local potential distribution of the gate-drain access region is adjusted, and the shielding plate 17 above it is used to redistribute the lateral and vertical electric fields of the gate-drain access region. This synergistic effect makes the potential distribution between the gate 14 and the drain 15 more uniform, effectively reduces and disperses the local high electric field peak in the gate-drain access region, improves the breakdown margin, and also effectively weakens the virtual gate effect caused by electron trapping after high voltage turn-off, thereby significantly reducing the increase in dynamic on-resistance.

[0034] In addition, it should be noted that the upper surface of a structure mentioned in this application refers to the surface of the structure away from the substrate 10, and the lower surface of a structure mentioned in this application refers to the surface of the structure close to the substrate 10.

[0035] The structure of the field-effect transistor of this application will be described in detail below with reference to the accompanying drawings.

[0036] In some embodiments, combined with Figure 1 and Figure 2 As shown, the substrate 10 includes a substrate 101 and a buffer layer 102 disposed on the substrate 101. The substrate 101 is one of a sapphire substrate, a silicon carbide substrate, or a silicon substrate. The buffer layer 102 is grown between the substrate 101 and the channel layer 11, and is a key transition layer for resolving material lattice mismatch and improving device reliability. The material of the buffer layer 102 is aluminum nitride (AlN) or aluminum gallium nitride (AlGaN).

[0037] In some embodiments, the channel layer 11 is a GaN channel layer, and the barrier layer 12 is an AlGaN barrier layer, with the AlGaN barrier layer formed on the upper surface of the GaN channel layer to form a two-dimensional electron gas channel 19. It should be understood that, with reference to... Figure 1 As shown, at the interface between the barrier layer 12 and the channel layer 11, a thicker dashed line and electron symbols are used ( ) Marks the two-dimensional electronic gas channel 19.

[0038] For example, the lower surface of the AlGaN barrier layer can be in direct contact with the upper surface of the GaN channel layer, but it is not limited to this. An AlN spacer layer (not shown in the figure) can also be provided between the GaN channel layer and the AlGaN barrier layer to improve the heterojunction interface quality and the two-dimensional electron gas conductivity.

[0039] The source 13, gate 14, and drain 15 are disposed on the upper surface of the barrier layer 12 and arranged sequentially at intervals along the first direction X. The source 13 and drain 15 form a low-resistance ohmic contact with the barrier layer 12 to ensure efficient injection and outflow of electrons. The gate 14 is used to control the concentration of the two-dimensional electron gas, thereby controlling the on and off states of the field-effect transistor.

[0040] In some embodiments, the spacer region between the P-type compensation island 16 and the drain 15 is defined as a first isolation region 20. Figure 1 and Figure 5 In the diagram, the first isolation region 20 is marked with a blank dashed box to indicate its spatial extent. The space between the P-type compensation island 16 and the gate 14 is defined as the second isolation region 21. Figure 1 and Figure 5 In the diagram, the spatial extent of the second isolation region 21 is marked by a blank dashed box. Both the first isolation region 20 and the second isolation region 21 are gaps in the first direction X, used to block the electrical connection formed between the P-type compensation island 16 and the drain 15 through a two-dimensional electron gas, and to ensure the physical and electrical independence of the P-type compensation island 16 and the gate 14.

[0041] In this embodiment, the P-type compensation island 16 is disposed in the gate-drain access region, located between the gate 14 and the drain 15, but does not form a direct ohmic contact with the gate 14, the source 13 or the drain 15.

[0042] In some embodiments, combined with Figure 1 and Figure 5 As shown, the size of the first isolation region 20 in the first direction X is smaller than the size of the second isolation region 21 in the first direction X. That is, the P-type compensation island 16 is closer to the drain 15 than the gate 14. This makes the P-type compensation island 16 located in the gate-drain access region near the high electric field sensitive area, which is used to compensate for the local potential distribution and charge distribution.

[0043] For example, the P-type compensation island 16 is formed of a group III nitride material with P-type conductivity, specifically including P-type GaN, P-type AlGaN, a composite layer structure of P-type GaN and P-type AlGaN, or any other group III nitride material with P-type conductivity.

[0044] In some embodiments, the P-type compensation island 16 is formed by selective epitaxial growth, local regrowth, local ion implantation and annealing activation, or local etching followed by backfilling.

[0045] In some embodiments, reference Figure 5 As shown, the P-type compensation islands 16 are continuously arranged along the second direction Y, but are not limited thereto. See reference... Figure 6As shown, the P-type compensation island 16 can also be segmented or discretely distributed along the second direction Y. That is, multiple P-type compensation islands 16 can be set and arranged at intervals along the second direction Y. In other words, the P-type compensation islands 16 can be segmented or discretely distributed to reduce the impact on the channel conduction characteristics while maintaining the electric field control effect.

[0046] It should be noted that the second direction Y intersects with the first direction X; specifically, the first direction X and the second direction Y are perpendicular to each other.

[0047] In some embodiments, reference Figure 3 As shown, a portion of the P-type compensation island 16 penetrates the barrier layer 12 and embeds itself within the channel layer 11 to enhance its local modulation effect on the two-dimensional electron gas channel 19. When the channel layer 11 is a GaN channel layer, the pn junction interface between the P-type compensation island 16 and the channel layer 11 introduces an additional depletion coupling effect. Therefore, the extension depth of the P-type compensation island 16 must be carefully controlled. In this embodiment, the portion of the P-type compensation island 16 that penetrates the channel layer 11 (i.e., the extension depth of the P-type compensation island 16) does not exceed 10 nm to avoid excessively affecting the channel conduction characteristics.

[0048] In some embodiments, reference Figure 1 As shown, the lower surface of the P-type compensation island 16 is attached to the upper surface of the barrier layer 12. That is, the P-type compensation island 16 is disposed on the upper surface of the barrier layer 12 and does not directly contact the channel layer 11. This design not only reduces the processing difficulty, but also allows the P-type compensation island 16 to modulate the potential distribution of the gate-drain access region through its fixed charge and local depletion effect when the field-effect transistor is in the high-voltage off state. This improves the electric field distribution of the gate-drain access region, weakens the trapping effect of surface traps on channel electrons, and reduces the virtual gate effect caused by electron trapping, thereby alleviating the problems of increased dynamic on-resistance and current collapse. Furthermore, since the P-type compensation island 16 is located within the gate-drain access region, it can locally adjust the charge distribution and depletion state of the high electric field sensitive region on the drain side. At the same time, the shielding plate 17 located above the P-type compensation island 16 can further redistribute the lateral and vertical electric fields in the gate-drain access region. The synergistic effect of the two helps to smooth the electric field distribution on the drain side, suppress the electric field peak at the drain edge of the gate 14, thereby reducing the leakage current of the gate 14 and improving the breakdown voltage and long-term operational reliability of the device.

[0049] In some embodiments, to further improve the surface electric field distribution, reduce the influence of surface states, or enhance structural compatibility, a gallium nitride cap layer or a high-resistivity gallium nitride cap layer (not shown in the figure) is provided on the AlGaN barrier layer before forming the source 13, drain 15, gate 14 and P-type compensation island 16.

[0050] In some embodiments, reference Figures 1 to 4As shown, an isolation section 22 is formed in the region of the barrier layer 12 corresponding to the first isolation region 20. The isolation section 22 is configured to electrically isolate the P-type compensation island 16 from the drain 15. Specifically, the isolation section 22 formed in the barrier layer 12 corresponding to the first isolation region 20 is used to deplete the two-dimensional electron gas between the P-type compensation island 16 and the drain 15, thereby blocking the electrical connection formed through the two-dimensional electron gas channel 19.

[0051] In an alternative embodiment, reference Figure 4 As shown, the region corresponding to the barrier layer 12 and the first isolation region 20 is a trench-type isolation section. The isolation section 22 penetrates the barrier layer 12 and is embedded inside the channel layer 11. For example, the trench-type isolation section is etched using a dry etching process. That is, corresponding to the first isolation region 20, the barrier layer 12 and part of the channel layer 11 below it are etched away to form a trench. This trench is the isolation section 22, which physically cuts off the conduction path of the two-dimensional electron gas to achieve electrical isolation between the P-type compensation island 16 and the drain 15.

[0052] It should be understood that this trench is subsequently filled with the material of the passivation layer 18 to ensure the overall stability of the structure.

[0053] In another optional embodiment, the barrier layer 12 is an AlGaN barrier layer, and the region of the barrier layer 12 corresponding to the first isolation region 20 is an isolation portion containing He, N, or F ions. That is, He, N, or F ions are implanted into the region of the barrier layer 12 corresponding to the first isolation region 20 to form a high-resistivity region. This high-resistivity region is the isolation portion 22, which blocks the two-dimensional electron gas and achieves electrical isolation between the P-type compensation island 16 and the drain 15.

[0054] In another optional embodiment, the barrier layer 12 is an AlGaN barrier layer, and the region of the barrier layer 12 corresponding to the first isolation region 20 is a P-type doped isolation portion 22. That is, the region of the barrier layer 12 corresponding to the first isolation region 20 is P-type doped to form a P-type doped region, which is the isolation portion 22. The P-type doped region forms a pn junction with other regions of the barrier layer 12, and the built-in electric field of the pn junction depletes the two-dimensional electron gas below, achieving electrical isolation between the P-type compensation island 16 and the drain 15.

[0055] In some embodiments, the P-type compensation island 16 is disconnected from the gate 14, i.e., a second isolation region 21 is formed between the P-type compensation island 16 and the gate 14, ensuring that the P-type compensation island 16 and the gate 14 are physically and electrically independent. The second isolation region 21 ensures that the two are not directly connected through layout design or process steps.

[0056] For example, the second isolation zone 21 is implemented through one or more of the following processes: The first method is selective epitaxy / growth: the opening region is defined by photolithography, and P-type compensation islands 16 are selectively formed only in the opening region, so that they are naturally separated from the gate 14 in physical space. The second method is etching separation: If the P-type compensation island 16 and the gate 14 are formed from the same material layer (such as the P-type GaN layer), the P-type material between them is removed by etching through a dry etching process. The etching stops at the upper surface of the barrier layer 12 to achieve physical isolation. The third method is layout spacing design: the layout design ensures that the P-type compensation island 16 and the gate 14 maintain a spacing not less than the minimum allowed by the process design rules, so that there is no electrical connection between the two.

[0057] Through the above design, the P-type compensation island 16 of this application embodiment is different from the P-type GaN gate or P-type AlGaN gate mentioned in the aforementioned scheme 2. Instead, it is a local potential modulation structure that participates in the potential shaping of the gate-drain access region when the field-effect transistor is turned off, and does not form a conduction structure that depends on carrier injection.

[0058] It should be understood that this second isolation zone 21 is subsequently filled with the material of the passivation layer 18 to ensure the overall stability of the structure.

[0059] In some embodiments, combined with Figure 1 and Figure 5 As shown, the shielding plate 17 is disposed above the P-type compensation island 16, and the orthographic projection of the shielding plate 17 on the substrate 10 at least partially overlaps with the orthographic projection of the P-type compensation island 16 on the substrate 10. The shielding plate 17 is insulated from the gate 14 and the drain 15.

[0060] In an optional embodiment, the shielding plate 17 and the P-type compensation island 16 overlap in a centrally aligned manner. This design aims to achieve global symmetry and balance in the electric field distribution. The shielding plate 17 and the P-type compensation island 16 are directly opposite the high electric field sensitive area of ​​the gate-drain access region, which can most effectively shield part of the electric field below the gate 14. At the same time, the local potential modulation effect of the P-type compensation island 16 is used to make the electric field distribution in the gate-drain access region smoother and avoid local electric field spikes.

[0061] In another alternative embodiment, the overlap between the shielding plate 17 and the P-type compensation island 16 is biased towards the gate side. This design gives the shielding plate 17 stronger electric field control over the edge of the gate 14 (especially the drain-side edge of the gate 14), greatly smoothing the electric field peak at the edge of the gate 14 and reducing the maximum electric field strength below the gate 14. In addition, this design can significantly reduce the leakage current of the gate 14 and improve the long-term reliability of the gate 14. At the same time, because it is closer to the gate 14, its coverage and compensation effect on channel surface traps is more direct, which helps to further suppress current collapse.

[0062] In another alternative embodiment, the overlap between the shielding plate 17 and the P-type compensation island 16 is biased towards the drain side. This design means that the shielding plate 17 and the P-type compensation island 16 cover more of the drift region or high electric field sensitive region near the drain 15, which can more effectively expand the depletion layer on the drain side, absorb more space charge, and thus maximize the blocking capability of the device. Moreover, in the high-voltage off state, the drain side is the most severely affected area for surface trapping electrons. Biasing towards the drain side can more effectively improve the electric field distribution and trapping effect on the drain side, and better reduce the dynamic on-resistance under high voltage.

[0063] In some embodiments, reference Figure 6 As shown, if multiple P-type compensation islands 16 are provided and arranged at intervals along the second direction Y, multiple shielding plates 17 are also provided and arranged at intervals along the second direction Y. The shielding plates 17 and P-type compensation islands 16 can be arranged in a one-to-one overlapping manner, but this is not limited to this. Alternatively, a continuous shielding plate 17 can cover multiple discrete P-type compensation islands 16, or some shielding plates 17 can cover multiple discrete P-type compensation islands 16, while other shielding plates cover one P-type compensation island 16.

[0064] Since the trapped state distribution on the surface of a field-effect transistor is typically non-uniform, especially in the high-electric-field sensitive region of the gate-drain access region, this embodiment uses a one-to-one overlapping arrangement of the shielding plate 17 and the P-type compensation island 16 to enable each local control unit to coordinately adjust the electric field distribution in its corresponding region. Through the electric field redistribution effect of the shielding plate 17 and the local potential modulation effect of the P-type compensation island 16, the electric field uniformity in the gate-drain access region can be further improved, reducing the trapping effect of surface traps on channel electrons, thereby alleviating the problems of current collapse and dynamic on-resistance degradation.

[0065] Furthermore, by arranging multiple shielding plates 17 at intervals along the second direction Y, a segmented electric field buffer zone is essentially established in the high electric field sensitive region of the gate-drain access area. Combined with the local potential modulation effect of the shielding plates 17 and the P-type compensation island 16, this structure can significantly reduce the peak electric field inside the field-effect transistor, thereby greatly improving the device's breakdown voltage and long-term reliability.

[0066] In this embodiment, multiple P-type compensation islands 16 and multiple shielding plates 17 are staggered on the plane, which is suitable for devices with larger gate widths or scenarios where the local electric field distribution is uneven in the layout.

[0067] It should be noted that the length and width of the shielding plate 17 and its overlap offset with the P-type compensation island 16 are optimized according to the withstand voltage requirements and parasitic capacitance tolerance of the field-effect transistor. By adjusting the degree of overlap between the shielding plate 17 and the P-type compensation island 16 (including the overlap area and relative position), the electric field distribution in the gate-drain access area can be controlled in stages, thereby achieving a better balance between breakdown voltage, dynamic on-resistance and switching speed.

[0068] In some embodiments, the shielding plate 17 is electrically connected to the source 13. By connecting the shielding plate 17 to the source 13, the shielding plate 17 has a more stable potential during the operation of the field-effect transistor, thereby further adjusting the surface potential distribution of the gate-drain access region.

[0069] The shielding plate 17 is not limited to being connected to the source 13; it can also be a floating structure, meaning that the shielding plate 17 is not directly connected to any fixed potential (such as the source 13, drain 15, or gate 14). By using a floating shielding plate 17, it is equivalent to placing a smart electric field regulator in the high electric field sensitive region inside the field-effect transistor. It does not require an external power supply and can automatically adjust the potential solely through the induction of the high voltage at the drain 15, thereby achieving a significant leap in device withstand voltage and long-term reliability at a very low performance cost (the on-resistance remains almost unchanged).

[0070] In some embodiments, since the P-type compensation island 16 does not have direct ohmic contact with the drain 15, gate 14 and source 13, the structure mainly relies on local compensation rather than injection, which is more conducive to balancing low leakage current and high reliability.

[0071] In some embodiments, reference Figure 1 As shown, the field-effect transistor also includes a capping layer 23, which covers the source 13, gate 14, drain 15, P-type compensation island 16, and shielding plate 17.

[0072] In order to ensure that the source 13, gate 14 and drain 15 are connected to other external structures, vias are opened on the cover layer 23 corresponding to the source 13, gate 14 and drain 15.

[0073] This application also provides a power electronic system that includes a plurality of field-effect transistors as described in any of the foregoing embodiments.

[0074] Multiple field-effect transistors are connected by corresponding connecting lines or electronic circuits, depending on the specific situation.

[0075] For example, power electronic systems include on-board chargers, DC / DC (Direct Current to Direct Current) converters, power adapters, server power supplies, photovoltaic energy storage and charging systems, and other structures with high frequency and high power density.

[0076] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0077] In this application, unless otherwise expressly specified and limited, terms such as "connection" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection or an electrical connection; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0078] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0079] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A field-effect transistor, characterized in that, include: Base; A channel layer is formed on the substrate; A barrier layer is formed on the channel layer, and a two-dimensional electron gas channel is formed between the barrier layer and the channel layer; The source, gate, and drain are formed on the barrier layer and arranged sequentially at intervals along the first direction; A P-type compensation island, at least partially above the barrier layer, is located between the gate and the drain. The space between the P-type compensation island and the drain is defined as a first isolation region, and the space between the P-type compensation island and the gate is defined as a second isolation region. A shielding plate is located above the P-type compensation island, and a passivation layer is provided between the shielding plate and the P-type compensation island. The orthographic projection of the shielding plate on the substrate and the orthographic projection of the P-type compensation island on the substrate at least partially overlap. The shielding plate is spaced apart from the gate and the drain.

2. The field-effect transistor according to claim 1, characterized in that, The size of the first isolation zone in the first direction is smaller than the size of the second isolation zone in the first direction.

3. The field-effect transistor according to claim 1, characterized in that, An isolation section is formed in the region of the barrier layer corresponding to the first isolation region, and the isolation section is configured to electrically isolate the P-type compensation island from the drain.

4. The field-effect transistor according to claim 3, characterized in that, The region corresponding to the first isolation region in the barrier layer is a trench-shaped isolation portion, which penetrates the barrier layer and is embedded inside the trench layer; or The barrier layer is an AlGaN barrier layer, and the region of the barrier layer corresponding to the first isolation region is the isolation portion containing He, N, or F ions; or The barrier layer is an AlGaN barrier layer, and the region of the barrier layer corresponding to the first isolation region is the P-type doped isolation portion.

5. The field-effect transistor according to claim 1, characterized in that, The lower surface of the P-type compensation island is in contact with the upper surface of the barrier layer; or A portion of the P-type compensation island penetrates the barrier layer and is embedded within the channel layer, with the portion of the P-type compensation island entering the channel layer not exceeding 10 nm.

6. The field-effect transistor according to claim 1, characterized in that, The shielding plate is a floating structure, or the shielding plate is electrically connected to the source electrode.

7. The field-effect transistor according to claim 1, characterized in that, Multiple P-shaped compensation islands are provided and arranged at intervals along a second direction, which intersects with the first direction.

8. The field-effect transistor according to claim 7, characterized in that, Multiple shielding plates are provided and arranged at intervals along the second direction.

9. The field-effect transistor according to claim 1, characterized in that, The channel layer is a GaN channel layer, the barrier layer is an AlGaN barrier layer, and an AlN spacer layer is disposed between the GaN channel layer and the AlGaN barrier layer.

10. A power electronic system, characterized in that, It includes a plurality of field-effect transistors as described in any one of claims 1 to 9.

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