Optical communication receiving assembly and method of manufacturing the same

Abstract

The application provides an optical communication receiving assembly and a preparation method thereof, and aims to solve the technical problem that the integration density, structural reliability and optical integrity are difficult to be optimized simultaneously in the packaging of an optical receiving module. The scheme realizes high-density vertical interconnection of a photodetector array and a receiving circuit through hybrid bonding, and forms a sealed cavity by coffer bonding a transparent cover plate after the micro-lens array is manufactured, so that the micro-lens array is in a physical isolation state all the time, and damage to the optical structure is effectively avoided. Meanwhile, low parasitic and short-path signal vertical extraction is realized through a first TSV column. Through the collaborative design of hybrid bonding, cavity protection and TSV vertical interconnection, the application improves the integration density, reduces the parasitic parameters, reduces the packaging size, and improves the structural integrity and optical stability in the process, effectively solving the problems of low interconnection density, large packaging size, fragile structure and easy damage to optical performance in the background art.

Description

Technical Field

[0001] This invention belongs to the field of optical interconnect based on Micro-LED, and relates to an optical communication receiving component and its fabrication method. Background Technology

[0002] In the field of optoelectronic integration, high-density, low-loss integration of photodetector units and signal processing units is crucial for achieving high-performance optical receiver modules. Existing technologies using discrete chip flip-chip or micro-bump interconnects suffer from limitations in interconnect density, parasitic parameters affecting signal quality, and difficulties in further reducing package size. To address these issues, three-dimensional stacking integration schemes have been proposed, such as vertical interconnects with circuit units. However, in practical implementation, these schemes still face numerous challenges. For example, in Micro-LED-based optical interconnect architectures, to guide signals from one side of the stacked structure to the other for connection with external circuits, conductive channels are typically fabricated in the substrate, and these processes can negatively impact the overall mechanical stability of the structure. Furthermore, to improve the optical coupling efficiency of the detector unit, specific optical structures are often formed on its light-receiving surface; these structures are prone to performance degradation in subsequent multi-step processes. Currently, there is a lack of a comprehensive system solution that can address all these issues.

[0003] Therefore, how to improve integration density while ensuring structural reliability and the integrity of optical performance has become a pressing technical problem to be solved in this field.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an optical communication receiving component and its fabrication method, so as to solve the problems of low interconnection density, high parasitic parameters, large package size, structural fragility and easy damage to optical performance in optoelectronic integrated structures.

[0006] As described above, the present invention provides a method for fabricating an optical communication receiving component, the method comprising:

[0007] A first wafer is provided, the first wafer including a receiving circuit near the front side of the first wafer; a first wiring layer is disposed on the front side of the first wafer;

[0008] A second wafer is provided, including a photodetector array near the back side of the second wafer; a second wiring layer is disposed on the front side of the second wafer;

[0009] The first wiring layer and the second wiring layer are mixed and bonded to electrically connect the first wafer and the second wafer;

[0010] A microlens array is disposed on the back side of the second wafer, and a transparent cover plate is bonded to the back side of the second wafer using a cofferdam process. A cavity is formed between the transparent cover plate and the second wafer. The transparent cover plate covers and protects the microlens array, and the microlens array is located within the cavity. A first TSV pillar is formed on the back side of the first wafer, penetrating the first wafer to the first wiring layer and electrically connected to the first wiring layer. A third wiring layer is formed on the back side of the first wafer, and the third wiring layer is electrically connected to the first wiring layer through the first TSV pillar.

[0011] The current structure is cut to form multiple receiving elements.

[0012] Optionally, the steps following the mixed bonding of the first wafer and the second wafer specifically include:

[0013] Thin the back side of the second wafer, and then deposit the microlens array on the back side of the second wafer;

[0014] The transparent cover plate is provided and bonded to the surface of the second wafer by a damming process. The cavity is formed between the transparent cover plate and the second wafer. The transparent cover plate covers and protects the microlens array, and the microlens array is located within the cavity.

[0015] The back side of the first wafer is thinned, and a first TSV hole is formed from the back side of the first wafer through the first wafer to the first wiring layer. The hole is filled with conductive material to form the first TSV pillar, and the first TSV pillar is electrically connected to the first wiring layer.

[0016] The third wiring layer is formed on the back side of the first wafer, and the third wiring layer is electrically connected to the first wiring layer through the first TSV pillar;

[0017] The current structure is cut to form multiple receiving elements.

[0018] Optionally, the steps following the mixed bonding of the first wafer and the second wafer specifically include:

[0019] The back side of the first wafer is thinned, and a first TSV hole is formed from the back side of the first wafer through the first wafer to the first wiring layer. The hole is filled with conductive material to form the first TSV pillar, and the first TSV pillar is electrically connected to the first wiring layer.

[0020] The third wiring layer is formed on the back side of the first wafer, and the third wiring layer is electrically connected to the first wiring layer through the first TSV pillar;

[0021] A first temporary substrate is provided, and the first temporary substrate is bonded to the surface of the third wiring layer;

[0022] Thin the back side of the second wafer, and then deposit the microlens array on the back side of the second wafer;

[0023] The transparent cover plate is provided and bonded to the back of the second wafer using a cofferdam process. The cavity is formed between the transparent cover plate and the second wafer. The transparent cover plate covers and protects the microlens array, and the microlens array is located within the cavity.

[0024] Remove the first temporary substrate to expose the third wiring layer;

[0025] The current structure is cut to form multiple receiving elements.

[0026] Optionally, it also includes:

[0027] An intermediate layer is provided, wherein the receiving element is bonded to the intermediate layer via the third wiring layer and the third wiring layer is electrically connected to the intermediate layer, and the intermediate layer has a redistribution layer near the surface;

[0028] A transmitting element is provided, the transmitting element having a fourth wiring layer located on the surface of the transmitting element, and being bonded in parallel to the receiving element to the interposer layer through the fourth wiring layer;

[0029] A molding layer is formed on the surface of the intermediate layer, and the molding layer covers the transmitting element and the receiving element;

[0030] A second TSV post is formed from the side of the interposer away from the molding layer, penetrating the interposer. One end of the second TSV post is electrically connected to the fourth wiring layer and the third wiring layer through the redistribution layer on the interposer, respectively. The other end of the second TSV post is exposed on the side of the interposer away from the receiving element.

[0031] A packaging substrate is provided, wherein a third TSV pillar is disposed therein, and the side of the interlayer opposite to the receiving element is bonded to the packaging substrate, such that one end of the third TSV pillar is electrically connected to the second TSV pillar, and the other end of the third TSV pillar is exposed on the side of the packaging substrate away from the interlayer.

[0032] A metal bump is formed on the side of the packaging substrate away from the interlayer, and the metal bump is electrically connected to the other end of the third TSV pillar.

[0033] Optionally, it further includes: providing at least one SerDes chip, bonding the SerDes chip to the interposer layer, arranging it side-by-side with the receiving element and the transmitting element, and electrically connecting the SerDes chip to the interposer layer.

[0034] Optionally, the cofferdam is formed by the cofferdam process, and the material of the cofferdam includes one of glass frit or polyimide; and / or, the coefficient of thermal expansion of the transparent cover plate is in the range of 3 to 4 ppm / K.

[0035] Optionally, the cavity is further comprising: the cavity being filled with one of nitrogen, helium, or argon.

[0036] This application also provides an optical communication receiving component, the receiving component including a receiving element, the receiving element comprising:

[0037] A first wafer, the first wafer including a receiving circuit near the front side of the first wafer;

[0038] The first wiring layer is located on the front side of the first wafer and is electrically connected to the receiving circuit.

[0039] The second wafer includes a photodetector array near the back side of the second wafer; a second wiring layer is disposed on the front side of the second wafer; the first wiring layer and the second wiring layer are hybrid bonded to electrically connect the first wafer and the second wafer.

[0040] A microlens array is located on the back side of the second wafer;

[0041] A dike is disposed on the back side of the second wafer and surrounds the microlens array;

[0042] A transparent cover plate is bonded to the back side of the second wafer via the dam. The transparent cover plate, the dam, and the second wafer together form a cavity. The transparent cover plate covers and protects the microlens array, and the microlens array is located within the cavity.

[0043] The first TSV pillar extends from the back side of the first wafer through the first wafer to the first wiring layer and is electrically connected to the first wiring layer.

[0044] The third wiring layer is located on the back side of the first wafer and is electrically connected to the first wiring layer through the first TSV pillar.

[0045] Optionally, it further includes: an interposer layer, wherein the third wiring layer is bonded to and electrically connected to the interposer layer, the interposer layer having a redistribution layer near the surface;

[0046] A transmitting element having a fourth wiring layer on the surface of the transmitting element, and being bonded in parallel to the receiving element to the interposer layer via the fourth wiring layer;

[0047] A molding compound is located on the surface of the intermediate layer, and the molding compound covers the transmitting element and the receiving element;

[0048] A packaging substrate is disposed on the side of the interposer layer opposite to the first wafer; a third TSV pillar is disposed within the packaging substrate;

[0049] The second TSV post penetrates the interposer layer. One end of the second TSV post is electrically connected to the fourth routing layer and the third routing layer through the redistribution layer on the interposer layer, respectively. The other end of the second TSV post is electrically connected to the third TSV post.

[0050] A metal bump is located on the side of the packaging substrate away from the interposer and is electrically connected to the third TSV pillar.

[0051] Optionally, the receiving element includes the photodetector and the receiving circuit, the transmitting element includes a Micro-LED array and a corresponding driving circuit, and the transmitting element and the receiving element are spaced apart on the upper intermediate layer.

[0052] Optionally, the transmitting element and the receiving element have the same thickness and are both bonded to the same flat interposer layer.

[0053] Optionally, the cross-section of the first TSV column is stepped or conical.

[0054] Optionally, the cavity is filled with one of nitrogen, helium, or argon.

[0055] In summary, this invention provides an optical communication receiving component and its fabrication method, aiming to solve the technical problem of the difficulty in synergistically optimizing integration density, structural reliability, and optical integrity in optical receiving module packaging. This solution achieves high-density vertical interconnection between the photodetector array and the receiving circuit through hybrid bonding of a first wafer and a second wafer. After the microlens array is fabricated, a transparent cover plate is bonded using a damming process to form a sealed cavity, keeping the microlens array physically isolated. This effectively avoids damage to the optical structure from subsequent processes and ensures the long-term stability of optical coupling efficiency. Simultaneously, a first TSV pillar enables low-parasitic, short-path signal vertical extraction from the back side of the first wafer to the front wiring layer, overcoming the limitations of density and signal quality degradation in traditional interconnection methods. In conclusion, this invention, through the synergistic design of hybrid bonding, cavity protection, and TSV vertical interconnection, effectively reduces parasitic parameters and package size while increasing integration density, and significantly improves structural integrity and optical performance stability during the manufacturing process. This comprehensively solves the problems of low interconnection density, high parasitic parameters, large package size, structural fragility, and susceptibility to optical performance in the prior art. Attached Figure Description

[0056] Figure 1 The diagram shows a process flow chart of the fabrication method of the optical communication receiving component in an embodiment of the present invention.

[0057] Figure 2 The diagram shows a flowchart of the fabrication method of the optical communication receiving component in Embodiment 1 of the present invention.

[0058] Figure 3 The diagram shows the structure after the first wafer is provided and the first wiring layer is formed in Embodiment 1 of the present invention.

[0059] Figure 4 The diagram shows the structure after a second wafer is provided and a second wiring layer is formed in Embodiment 1 of the present invention.

[0060] Figure 5 The diagram shown is a schematic diagram of the structure after the first wiring layer and the second wiring layer are mixed and bonded in Embodiment 1 of the present invention.

[0061] Figure 6 The diagram shows the structure of the second wafer after a microlens array is formed on the back side, as shown in Embodiment 1 of the present invention.

[0062] Figure 7 The diagram shows the structure of the second wafer after a transparent cover plate has been bonded to its surface in Embodiment 1 of the present invention.

[0063] Figure 8 The diagram shows the structure after the first TSV pillar is formed and the third wiring layer is formed after the back side of the first wafer is thinned in Embodiment 1 of the present invention.

[0064] Figure 9 The diagram shows a flowchart of the preparation method of the optical communication receiving component in Embodiment 2 of the present invention.

[0065] Figure 10 This is a schematic diagram of the structure after the first TSV pillar is formed on the back side of the first wafer in Embodiment 2 of the present invention.

[0066] Figure 11 This is a schematic diagram of the structure after the third wiring layer is formed on the back side of the first wafer in Embodiment 2 of the present invention.

[0067] Figure 12 The diagram shows the structure after bonding the first temporary substrate in Embodiment 2 of the present invention.

[0068] Figure 13 The diagram shows the structure after setting a microlens array and bonding a transparent cover plate in Embodiment 2 of the present invention.

[0069] Figure 14 The diagram shown is a schematic representation of the structure after the receiving element is bonded to the intermediary layer in an embodiment of the present invention.

[0070] Figure 15 The diagram shows the structure of the transmitting element and the receiving element after they are bonded side by side to the intermediary layer in an embodiment of the present invention.

[0071] Figure 16 The diagram shows the structure after the intermediate layer is bonded to the packaging substrate in an embodiment of the present invention.

[0072] Figure 17 The diagram shows the structure of the packaging substrate after it has been bonded to the PCB board in an embodiment of the present invention.

[0073] Figure 18 The diagram shown is a structural schematic of the SerDes chip provided in an embodiment of the present invention.

[0074] Figure 19 The diagram shows the structure of the SerDes chip after it has been bonded to the intermediary layer in an embodiment of the present invention.

[0075] Figure 20 The diagram shows the structure after the intermediate layer is bonded to the packaging substrate and then integrated into the PCB board in an embodiment of the present invention.

[0076] Explanation of reference numerals in the attached figures

[0077] 11. Receiving element; 12. Transmitting element; 13. SerDes chip; 100. First wafer; 110. First wiring layer; 120. Cavity; 130. Third wiring layer; 131. First pad; 140. First TSV pillar; 160. Fourth wiring layer; 200. Second wafer; 210. Second wiring layer; 220. Microlens array; 230. Dike; 240. Transparent cover plate; 310. First temporary substrate; 400. SerDes wafer; 410. Fifth wiring layer; 420. Intermediate layer; 500. Packaging substrate; 510. Second TSV pillar; 520. Molding layer; 530. Third TSV pillar; 540. Metal bump; 600. PCB board. Detailed Implementation

[0078] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0079] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0080] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0081] Please see Figures 1-20 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0082] This embodiment provides a method for fabricating an optical communication receiver component. Please refer to [link / reference]. Figure 1 and Figure 8 The diagram shows the fabrication process of an optical communication receiver component, including:

[0083] A first wafer 100 is provided, the first wafer 100 including a receiving circuit near the front side of the first wafer 100; a first wiring layer 110 is disposed on the front side of the first wafer 100.

[0084] A second wafer 200 is provided, including a photodetector array near the back side of the second wafer 200; a second wiring layer 210 is disposed on the front side of the second wafer 200;

[0085] The first wiring layer 110 and the second wiring layer 210 are mixed and bonded to electrically connect the first wafer 100 and the second wafer 200.

[0086] Based on the bonding of the first wafer 100 and the second wafer 200, a structure to be diced is formed, including:

[0087] A microlens array 220 is disposed on the back side of the second wafer 200, and a transparent cover plate 240 is bonded to the back side of the second wafer 200 by a cofferdam process. A cavity 120 is formed between the transparent cover plate 240 and the second wafer 200. The transparent cover plate 240 covers and protects the microlens array 220, and the microlens array 220 is located within the cavity 120. A first TSV pillar 140 is formed on the back side of the first wafer 100, penetrating the first wafer 100 to the first wiring layer 110 and electrically connected to the first wiring layer 110. A third wiring layer 130 is formed on the back side of the first wafer 100, and the third wiring layer 130 is electrically connected to the first wiring layer 110 through the first TSV pillar 140.

[0088] The structure to be cut is cut to form multiple receiving elements.

[0089] The following will describe specific embodiments one and two. The core difference between embodiments one and two is that the steps of forming the microlens array 220 and the transparent cover plate 240 are performed after the formation of the first TSV pillar 140 and the third wiring layer 130 on the back side. Embodiment one completes the fabrication of the microlens array and the sealing of the transparent cover plate before the back side thinning and TSV processes, while embodiment two postpones these two steps to after the back side processes.

[0090] Please refer to the following for details:

[0091] Example 1

[0092] This embodiment provides a method for fabricating an optical communication receiver component. Please refer to [link / reference]. Figure 2 The diagram shows the fabrication process of an optical communication receiver component, including:

[0093] First, refer to Figure 2 and Figure 3 In step S1-1, a first wafer 100 is provided, the first wafer 100 includes a receiving circuit near the front side of the first wafer 100; a first wiring layer 110 is provided on the front side of the first wafer 100.

[0094] Specifically, the first wafer 100 may be a silicon wafer, and the receiving circuit includes, for example, a transimpedance amplifier (TIA), a limiting amplifier, or a clock data recovery circuit. The first wiring layer 110 is formed using conventional processes and is used for hybrid bonding to the second wiring layer 210 of the wafer where the subsequent photodetector array is located, to achieve high-density interconnection.

[0095] Next, refer to Figure 2 and Figure 4 Steps S1-2 are executed to provide a second wafer 200, which includes a photodetector array near the back side of the second wafer 200; the front side of the second wafer 200 is provided with the second wiring layer 210.

[0096] Specifically, the second wafer 200 is used to realize photoelectric conversion, and the photodetector array (e.g., silicon-based PIN photodiode, avalanche photodiode, etc.) is formed in the region near the back side of its interior. The second wiring layer 210 is fabricated on the front side of the second wafer 200 through a metal interconnect process and is electrically connected to the electrodes of the photodetector array to guide the photogenerated current or voltage signal from the inside of the device to the surface of the second wafer 200; the pads on these surfaces are then hybrid-bonded to the first wiring layer 110 so that the photoelectric converted electrical signal can enter the receiving circuit for processing.

[0097] Next, refer to Figure 2 and Figure 5 Then, in steps S1-3, the first wiring layer 110 and the second wiring layer 210 are mixed and bonded to electrically connect the first wafer 100 and the second wafer 200.

[0098] Specifically, at room temperature, the first wiring layer 110 and the second wiring layer 210 are aligned and bonded together, ensuring close contact between the copper pads and dielectric layers on both surfaces. Pre-bonding is achieved using van der Waals forces and hydrogen bonds at the interface. Finally, annealing is performed in an inert atmosphere to form a reliable electrical connection, while covalent bonding occurs between the dielectric layers, thereby forming a stable bonding interface between the first wafer 100 and the second wafer 200.

[0099] Next, refer to Figure 2 and Figure 6 Steps S1-4 are executed to thin the back side of the second wafer 200 and to set a microlens array 220 on the back side of the second wafer 200.

[0100] Specifically, after the hybrid bonding of the first wafer 100 and the second wafer 200 is completed, the back side of the second wafer 200 can be thinned so that light can penetrate the second wafer 200 and reach the photodetector array.

[0101] Furthermore, the microlens array 220 is directly formed using a hot reflow process (e.g., high-temperature melting of spin-coated photosensitive polymers) or micro / nano fabrication processes (including but not limited to nanoimprinting, grayscale lithography, or reactive ion etching). The microlens array 220 corresponds to the pixels of the photodetector array and is used to focus incident light onto the photosensitive area of ​​the photodetector array to improve light collection efficiency and detection sensitivity. Finally, the microlens array 220 is cured.

[0102] Next, refer to Figure 2 and Figure 7 In step S1-5, a transparent cover plate 240 is provided and bonded to the back of the second wafer 200 by a cofferdam process. A cavity 120 is formed between the transparent cover plate 240 and the second wafer 200. The transparent cover plate 240 covers and protects the microlens array 220, and the microlens array 220 is located within the cavity 120.

[0103] Specifically, to prevent the microlens array 220 from being contaminated, scratched, or exposed to moisture, a dam 230 is formed on the outer periphery of the back side of the second wafer 200, and the height of the dam 230 is higher than the apex of the microlens array 220. The transparent cover plate 240 is then aligned and pressed onto the dam 230, and cured to permanently bond the transparent cover plate 240 to the second wafer 200, forming a sealed cavity 120 between them. The microlens array 220 is located within the cavity 120. The cavity 120 avoids changes in optical performance caused by direct contact between the transparent cover plate 240 and the surface of the microlens array 220, while effectively isolating external moisture and particles, thus improving the long-term reliability and optical stability of the receiving element 11.

[0104] Furthermore, the cofferdam 230 forms a supporting gap between the second wafer 200 and the transparent cover plate 240 to enclose the cavity 120 accommodating the microlens array 220, and achieves an airtight seal through bonding with the transparent cover plate 240. Therefore, the material selection of the cofferdam 230 directly affects the heat resistance and reliability of the sealing structure, and the structural integrity and bonding interface stability must be maintained during subsequent high-temperature processes.

[0105] As an example, the material of the cofferdam 230 includes either glass or polyimide.

[0106] Specifically, the cofferdam 230 is made of a high-temperature resistant material, such as glass frit or high-Tg polyimide (Tg>350°C). Glass frit, as a conventional cofferdam 230 material, possesses excellent electrical insulation properties and high-temperature resistance, forming a dense barrier during sintering, and its chemical inertness ensures compatibility with the silicon substrate. The polyimide has a high glass transition temperature (Tg), for example, in one embodiment, the polyimide has a Tg exceeding 350°C, combining flexibility and thermal stability to withstand high-temperature processes such as reflow soldering. In other embodiments, the selection of the cofferdam 230 material also considers its chemical resistance, adhesion, and cost-effectiveness to ensure the durability and functional integrity of the cofferdam process in complex environments.

[0107] In one specific embodiment, a reliable sealing structure is required within the cavity 120. The cofferdam 230 structure adopts a continuous, wide-dimensional design, replacing the traditional dot matrix or narrow line patterns, which can provide a larger bonding area and a more continuous sealing interface. This design can more effectively compensate for the microscopic unevenness of the substrate surface during the bonding process, forming a seamless, fully enclosed airtight barrier that fundamentally blocks external paths.

[0108] As an example, the cavity 120 is filled with one of nitrogen, helium, or argon. In a specific embodiment, the cavity 120 is filled with a high-purity inert gas, the specific gas selection depending on the application requirements. Nitrogen is inexpensive, chemically stable, and has moderate thermal conductivity. Helium has a small molecular weight and high thermal conductivity, which is beneficial for applications requiring efficient heat dissipation. Argon, as an inert gas with a larger molecular weight, can more effectively suppress internal discharge phenomena.

[0109] In another specific embodiment, the internal pressure of the cavity 120 is set to a negative pressure state that is balanced with or slightly lower than the external atmospheric pressure. This pressure setting has several advantages: first, it avoids the package from bulging or cracking at high temperatures due to internal positive pressure; second, the pressure difference between the inside and outside is extremely small, reducing the driving force for gas to permeate and diffuse through microscopic defects; and third, the slightly lower internal pressure can counteract the slight compression effect of the cofferdam 230 material on the internal cavity 120, maintaining structural stability. Through this comprehensive physical isolation and environmental control, the safety and stability of the chip under complex operating conditions are ensured.

[0110] As an example, the CTE of the transparent cover 240 is in the range of 3 to 4 ppm / K, which is close to the 2.6 ppm / K of silicon.

[0111] Specifically, the coefficient of thermal expansion (CTE) of the transparent cover 240 ranges from 3 to 4 ppm / K, a value close to that of silicon (approximately 2.6 ppm / K). This CTE matching is crucial in semiconductor packaging to prevent significant differences in CTE between the transparent cover 240 and the silicon chip when the device experiences temperature variations, which could cause interfacial thermal stress leading to cracking, delamination, or performance degradation. The transparent cover 240 is made of glass or transparent ceramic with specific compositions, effectively reducing thermal stress accumulation and improving packaging reliability and long-term stability, thus simultaneously meeting the requirements of optical transparency, mechanical protection, and environmental sealing.

[0112] Next, refer to Figure 2 and Figure 8 In steps S1-6, the back side of the first wafer 100 is thinned, and a first TSV hole is formed from the back side of the first wafer 100 through the first wafer 100 to the first wiring layer 110. A first TSV pillar 140 is formed by filling it with conductive material. The first TSV pillar 140 is electrically connected to the first wiring layer 110.

[0113] Specifically, after sealing and bonding the cavity 120, the subsequent process proceeds to the wafer-level interconnect stage. First, the back side of the first wafer 100 is thinned using techniques such as mechanical grinding and chemical mechanical polishing. Preferably, CMP is used to reduce the thickness of the first wafer 100 to the target size, creating the necessary conditions for the subsequent formation of through-silicon vias (TSVs). This also facilitates thinner and higher-density three-dimensional integration.

[0114] In one specific embodiment, the transparent cover is preferably a glass cover. During the back-side thinning and CMP processes, the glass cover can provide sufficient rigid support to resist grinding stress and prevent the first wafer 100 from deforming when thinned to the target thickness. At the same time, due to its permanent retention characteristics, it is necessary to maintain thermal matching and interface reliability with the silicon material throughout the entire thinning and subsequent TSV process. Therefore, the glass cover is retained as the optical window or structural layer of the final device, and its supporting role runs through the entire three-dimensional integration process.

[0115] After thinning, starting from the back side of the first wafer 100, advanced processes such as deep reactive ion etching are used to precisely etch a first TSV via penetrating the first wafer 100 all the way to the first wiring layer 110. Then, insulating and barrier layers are formed on the inner walls of the via using methods such as chemical vapor deposition or atomic layer deposition to prevent electrical leakage and block metal diffusion. Next, conductive material (preferably copper) is filled into the first TSV via using processes such as electrochemical copper plating to form a robust first TSV pillar 140 structure that vertically penetrates the first wafer 100. Finally, planarization removes excess metal from the surface, ensuring that the upper end of the first TSV pillar 140 is exposed and forms a flat electrical contact point. This achieves a vertical electrical connection from the back side of the first wafer 100 to the front side of the first wiring layer 110, providing a crucial vertical interconnect path for chip stacking and 3D system integration.

[0116] As an example, see Figure 2 and Figure 8 The cross-section of the first TSV column 140 is stepped or conical.

[0117] Specifically, the stepped cross-section refers to a multi-step change in diameter along the longitudinal direction of the first TSV column 140; in this embodiment, the tapered cross-section refers to a smooth inclined structure in which the diameter of the first TSV column 140 gradually decreases from top to bottom. Both cross-sectional shapes are beneficial for reducing stress concentration, improving the uniformity of membrane coverage, and reducing filling voids.

[0118] Next, refer to Figure 2 and Figure 8 Steps S1-7 are executed to form a third wiring layer 130 on the back side of the first wafer 100. The third wiring layer 130 is electrically connected to the first wiring layer 110 through the first TSV pillar 140.

[0119] Specifically, the first TSV post 140, in conjunction with the third wiring layer 130 on the back side, is used to further route signals and power, enhancing the functionality of the package. The third wiring layer 130 includes a first pad 131 for subsequent bonding, providing the receiving element 11 with back-side fan-out capability, enabling it to be integrated side-by-side with the transmitting element 12, avoiding the space occupied by front-side leads.

[0120] Next, refer to Figure 2 and Figure 8 Execute steps S1-8 to cut the current structure to form multiple receiving elements 11.

[0121] First, the current structure is attached to a scribe line, which provides temporary mechanical support. Then, using blade cutting or laser stealth cutting, the current structure is fully or partially cut along a predetermined cutting line, dividing it into multiple independent receiving elements 11. After cutting, each receiving element 11 is picked up from the scribe line one by one by ultraviolet light irradiation or mechanical pin action. Specifically, the processed structure is divided into multiple independent chip units along the predetermined scribe line. Each chip unit includes the transparent cover plate 240, a TSV interconnect structure, and a wiring layer for subsequent assembly. Through these steps, the goal of three-dimensional integration and miniaturization is achieved while ensuring high packaging reliability.

[0122] As an example, the method for fabricating the optical communication receiving component further includes:

[0123] See Figure 2 and Figure 14 In step S1-9, an intermediary layer 420 is provided. The receiving element 11 is bonded to the intermediary layer 420 through the third wiring layer 130, and the third wiring layer 130 is electrically connected to the intermediary layer 420. The intermediary layer 420 has a rewiring layer near the surface.

[0124] As an example, the interposer 420 may include a silicon interposer, an RDL interposer, or a silicon substrate and a redistribution layer located on the silicon substrate. Optionally, a through-silicon via (TSV) may be formed in the silicon substrate, or the silicon substrate may form a via structure by etching and filling in a subsequent process.

[0125] Specifically, the interposer 420 is preferably a silicon interposer with through-silicon vias (TSVs), with pads (not shown) on its front side that match the third wiring layer 130 of the receiving element 11, and solder balls on its back side for external connections. The receiving element 11, obtained from the aforementioned cutting process, is picked up and flipped (or placed directly) so that the surface of the third wiring layer 130 is aligned with the corresponding pads on the front side of the interposer 420. A flip-chip bonding process, such as thermoforming, reflow soldering, or hybrid bonding, is used to form a robust electrical connection between the metal bumps or planarization pads of the third wiring layer 130 and the pads of the interposer 420. In some embodiments, the gap between the receiving element 11 and the interposer 420 may be filled with an underfill layer (not shown) to buffer thermal stress and improve reliability. The receiving circuit of the receiving element 11 is connected to an external system via the internal wiring of the third wiring layer 130 and the interposer 420, achieving high-density packaging and system integration of the receiving element 11. The intermediary layer 420 can serve as a common platform for multi-chip integration, facilitating subsequent assembly with other chips.

[0126] See Figure 15 In step S1-10, a transmitting element 12 is provided, the transmitting element 12 having a fourth wiring layer 160 located on the surface of the transmitting element 12, and being bonded to the receiving element 11 in parallel to the intermediary layer 420 through the fourth wiring layer 160.

[0127] Specifically, the transmitting element 12 typically includes a light source or signal transmitting element for generating optical or electrical signals. The fourth wiring layer 160 corresponds to the third wiring layer 130 in the receiving element 11, enabling the connection between the internal circuitry of the transmitting element 12 and the external interface, ensuring the efficiency and reliability of signal transmission.

[0128] Furthermore, during bonding, the pads of the fourth wiring layer 160 of the transmitting element 12 are precisely aligned with the corresponding pads on the interposer layer 420. Electrical connection and mechanical fixation are achieved using thermoforming bonding, eutectic bonding, or adhesive bonding. The transmitting element 12 and the receiving element 11 are arranged side-by-side on the interposer layer 420, and they are directly or indirectly interconnected through the interposer layer 420 to form a compact integrated structure. After bonding, the transmitting element 12 and the receiving element 11 are jointly fixed on the interposer layer 420, constituting a fully functional semiconductor device. The interposer layer 420 serves as an intermediate carrier, providing electrical routing and mechanical support, enabling the transmitting element 12 to transmit signals to the receiving element 11. Furthermore, based on the above process, the transmitting element 12 and the receiving element 11 are formed independently on the interposer layer, thereby improving process flexibility and allowing for the selection of processes to form the transmitting element 12 chip and the receiving element 11 chip, respectively.

[0129] In one implementation, the receiving element 11 includes the photodetector and the receiving circuit, the transmitting element 12 includes a Micro-LED array and a corresponding driving circuit, and the transmitting element 12 and the receiving element 11 are spaced apart on the interposer layer 420. The above process can realize the independence of the corresponding chips of the transmitting element 12 and the receiving element 11.

[0130] The steps described above expand the device's integration capabilities, making it suitable for optical communications, sensors, or 3D packaging. Subsequent steps include packaging and integration with other components to achieve the device's intended function.

[0131] See Figure 15 Step S1-11 is performed to form a molding layer 520 on the surface of the intermediate layer 420, the molding layer 520 covering the transmitting element 12 and the receiving element 11.

[0132] Specifically, the molding compound 520 covers the transmitting element 12 and the receiving element 11, providing physical protection and environmental isolation for the heterogeneous integrated structure, preventing damage from moisture, particles, and mechanical forces. Simultaneously, the molding compound 520 can fill gaps between devices and flatten surfaces, facilitating subsequent heat dissipation or the fabrication of electromagnetic shielding layers, thereby improving module reliability.

[0133] See Figure 15 In step S1-12, a second TSV post 510 is formed from the side of the interposer layer 420 away from the molding layer, penetrating the interposer layer 420. One end of the second TSV post 510 is electrically connected to the fourth wiring layer 160 and the third wiring layer 130 respectively through the redistribution layer on the interposer layer 420. The other end of the second TSV post 510 is exposed on the side of the interposer layer 420 away from the transmitting element 12, so as to realize the vertical lead-out of the signal to the external substrate.

[0134] Specifically, the structure of the second TSV pillar 510 allows the high-density interconnect signals between the transmitting element 12 and the receiving element 11 to be fanned downwards, facilitating the direct integration of the bottom of the interposer layer 420 onto the surface of the subsequent packaging substrate 500 to form a complete three-dimensional packaging module. The electrical connection between the second TSV pillar 510 and the third and fourth wiring layers is achieved through a rewiring layer on the surface of the interposer layer.

[0135] See Figure 16In steps S1-13, a packaging substrate 500 is provided, wherein a third TSV pillar 530 is disposed within the packaging substrate 500. The side of the interposer 420 facing away from the receiving element 11 is bonded to the packaging substrate 500, and one end of the third TSV pillar 530 is electrically connected to the second TSV pillar 510, while the other end of the third TSV pillar 530 is exposed on the side of the packaging substrate 500 away from the interposer 420. Specifically, by bonding the second TSV pillar 510 on the bottom surface of the interposer 420 to the packaging substrate 500 through the above bonding, vertical electrical connection between the transmitting element 12 and the receiving element 11 and the external system is achieved. The packaging substrate 500 provides mechanical support and signal fan-out for the interposer 420, thereby completing three-dimensional system integration from the chip level to the board level.

[0136] See Figure 16 In step S1-14, a metal bump 540 is formed on the side of the packaging substrate 500 away from the interposer layer 420, and the metal bump 540 is electrically connected to the other end of the third TSV pillar 530.

[0137] Specifically, the metal bump 540 is electrically connected to the wiring layer and pads inside the packaging substrate 500, serving as an interface for electrical interconnection of the package to the outside world, and is used for subsequent flip-chip soldering with printed circuit boards or other external circuit boards.

[0138] The packaging substrate 500 is provided with a third TSV pillar 530, one end of which is electrically connected to the internal circuitry of the packaging substrate 500. (See reference...) Figure 17 Subsequently, a PCB board 600 or other circuit board is provided, and the packaging substrate 500 is bonded to the PCB board 600 or other circuit board through the metal bumps 540, thereby realizing the final fan-out and interconnection of the signals of the transmitting element 12 and the receiving element 11 to external systems (such as motherboard, power supply, data interface).

[0139] As a specific embodiment, the receiving circuit integrates a deserializer circuit.

[0140] Specifically, the deserializer circuit is integrated inside the receiving circuit, which can deserialize the received serial data into parallel data. This integration method eliminates the need for an external independent SerDes chip 13 (serializer / deserializer), reduces the package area, and lowers signal transmission delay and power consumption.

[0141] As another specific embodiment, see Figures 18-20When the receiving circuit does not integrate a deserializer circuit and the transmitting element 12 does not integrate a serializer circuit, the method further includes: providing at least one SerDes chip 13, and bonding the SerDes chip 13 to the interposer layer 420, which is arranged side by side with the receiving element 11 and the transmitting element 12, and the SerDes chip 13 is electrically connected to the interposer layer 420.

[0142] Specifically, see Figure 18 The SerDes chip 13 includes a SerDes wafer 400 and a fifth wiring layer 410 formed on the surface of the SerDes wafer 400. The fifth wiring layer 410 is electrically connected to corresponding functional components through the second TSV pillars 510 in the interposer layer 420, providing them with serialization / deserialization functions. This solution can flexibly adapt to the high-speed data interface requirements of different application scenarios without changing the existing receiver circuit design, reducing process flow and cost.

[0143] As can be seen from the above, the fabrication method of the optical communication receiving component provided in this embodiment advances the microlens array fabrication and transparent cover sealing steps before the fabrication of the first TSV pillar, placing the microlenses within a cavity for protection. This achieves simultaneous physical isolation and protection of the optical structure throughout the entire process without requiring an additional temporary substrate support step. This process sequence effectively avoids damage to the microlens surface caused by particulate matter, chemical atmospheres, and mechanical contact during subsequent TSV etching, metal filling, and cleaning steps, ensuring the long-term stability of optical coupling efficiency. Although the high temperature during the subsequent TSV process will be conducted to the transparent cover 240 through silicon, stress is suppressed due to CTE matching and the material selection of the cofferdam 230, and the cavity itself also provides thermal isolation. Furthermore, the permanently bonded glass cover provides continuous rigid support during the thinning and TSV processes, eliminating the cumbersome temporary bonding / debonding steps and further improving process yield and manufacturing efficiency. In addition, the vertical interconnect channel provided by the first TSV pillar has a shorter signal transmission path and lower parasitic parameters compared to traditional wire bonding, which simplifies the process flow, reduces manufacturing costs, and simultaneously achieves high-density integration and excellent high-frequency electrical performance.

[0144] It should be noted that the specific structural dimensions, materials, and number of layers described in this embodiment are merely examples and not intended to limit the invention. Those skilled in the art can reasonably adjust the above parameters without departing from the core structural features of this invention, and these adjusted solutions still fall within the protection scope of this invention.

[0145] Example 2

[0146] This embodiment provides a method for fabricating an optical communication receiving component. Unlike Embodiment 1, the steps of forming the microlens array 220 and the transparent cover plate 240 are performed after forming the first TSV pillar 140 on the back side and the third wiring layer 130. Please refer to... Figure 9 The diagram shows a schematic of the semiconductor structure fabrication process, including:

[0147] First, refer to Figure 9 and Figure 2 In step S2-1, a first wafer 100 is provided, the first wafer 100 includes a receiving circuit near the front side of the first wafer 100; a first wiring layer 110 is provided on the front side of the first wafer 100.

[0148] Next, refer to Figure 9 and Figure 4 Step S2-2 is executed to provide a second wafer 200, including a photodetector array near the back side of the second wafer 200; a second wiring layer 210 is provided on the front side of the second wafer 200.

[0149] Next, refer to Figure 9 and Figure 5 Then, in step S2-3, the first wiring layer 110 and the second wiring layer 210 are mixed and bonded to electrically connect the first wafer 100 and the second wafer 200.

[0150] The process of steps S2-1 to S2-3 is the same as that in Example 1. The specific process can be referred to in Example 1, and will not be repeated here.

[0151] Next, refer to Figure 9 and Figure 10 In step S2-4, the back side of the first wafer 100 is thinned, and a first TSV hole is formed from the back side of the first wafer 100 through the first wafer 100 to the first wiring layer 110. A first TSV pillar 140 is formed by filling it with conductive material. The first TSV pillar 140 is electrically connected to the first wiring layer 110.

[0152] Specifically, the first wafer 100 is first thinned on its back side using techniques such as mechanical grinding and chemical mechanical polishing, preferably CMP, to reduce the thickness of the first wafer 100 to the target size. This creates the necessary conditions for subsequent formation of through-silicon vias (TSVs) and facilitates thinner, higher-density 3D integration. After thinning, starting from the back side of the first wafer 100, advanced processes such as deep reactive ion etching are used to precisely etch the first TSV via through the first wafer 100 up to the first wiring layer 110. Then, insulating and barrier layers are formed on the inner walls of the via using methods such as chemical vapor deposition or atomic layer deposition to prevent electrical leakage and block metal diffusion. Next, conductive material, typically copper, is filled into the first TSV via using processes such as electrochemical copper plating to form a robust first TSV pillar 140 structure that vertically penetrates the first wafer 100. Finally, excess metal on the surface is removed by planarization to ensure that the upper end of the first TSV pillar 140 is exposed and forms a flat electrical contact point; thereby realizing a vertical electrical connection from the back side of the first wafer 100 to the front side of the first wiring layer 110, providing a crucial vertical interconnect path for chip stacking and three-dimensional system integration.

[0153] As an example, see Figure 9 and Figure 10 The cross-section of the first TSV column 140 is stepped or conical. See Embodiment 1 for details.

[0154] Next, refer to Figure 9 and Figure 11 In step S2-5, a third wiring layer 130 is formed on the back side of the first wafer 100. The third wiring layer 130 is electrically connected to the first wiring layer 110 through the first TSV pillar 140.

[0155] Specifically, the first TSV post 140 cooperates with the third wiring layer 130 on the back side, the third wiring layer 130 including a first pad 131 for subsequent bonding, providing the receiving element 11 with back fan-out capability, enabling it to be integrated side-by-side with the transmitting element 12, avoiding the space occupied by front leads.

[0156] Next, refer to Figure 9 and Figure 12 In step S2-6, a first temporary substrate 310 is provided, and the first temporary substrate 310 is bonded to the surface of the third wiring layer 130, thereby giving the structure rigid support for subsequent processes.

[0157] Next, refer to Figure 9 and Figure 13Steps S2-7 are executed to thin the back side of the second wafer 200 and to set a microlens array 220 on the back side of the second wafer 200.

[0158] Specifically, in one embodiment, the second wafer 200 is thinned using techniques such as mechanical grinding and chemical mechanical polishing, preferably CMP. The microlens array 220 is formed using processes such as thermal reflow. The microlens array 220 corresponds to the pixels of the photodetector array and is used to focus incident light onto the photosensitive area of ​​the photodetector array to improve light collection efficiency and detection sensitivity. Finally, the microlens array 220 is cured.

[0159] Next, refer to Figure 9 and Figure 13 In step S2-8, a transparent cover plate 240 is provided and bonded to the back of the second wafer 200 using a cofferdam process. A cavity 120 is formed between the transparent cover plate 240 and the second wafer 200. The transparent cover plate 240 covers and protects the microlens array 220, and the microlens array 220 is located within the cavity 120.

[0160] Specifically, a dam 230 higher than the microlens array 220 is formed around the second wafer 200, and the transparent cover plate 240 is pressed and solidified to form a sealed cavity 120. This physically isolates the lenses from contamination, scratches, and moisture erosion, ensuring optical stability. In some embodiments, the dam 230 adopts a continuous wide-dimensional design and is made of high-temperature resistant materials such as glass or high-Tg (>350°C) polyimide to achieve airtight sealing and withstand subsequent high-temperature processes. Other implementations can also employ existing processes and materials. In other embodiments, the cavity 120 can be filled with inert gases such as nitrogen, helium, or argon, and set to a pressure balanced with or slightly negative of the external environment to prevent high-temperature expansion and reduce gas permeation. In other embodiments, the coefficient of thermal expansion (CTE) of the transparent cover plate 240 is designed to be 3~4 ppm / K to match the CTE of silicon (approximately 2.6 ppm / K), avoiding thermal stress caused by temperature changes that could lead to cracking or delamination. Other implementations can also utilize existing processes and materials. In this embodiment, by first fabricating the first TSV pillar 140 and the third wiring layer 130, and then fabricating the microlens array 220 and protecting it with the transparent cover plate 240, particles and chemicals from the first TSV pillar process can be blocked from contaminating the lens. Furthermore, due to the CTE matching and the material selection of the cofferdam 230, the stress caused by the high temperature of the TSV is controllable. For specific materials and processes, please refer to Embodiment 1.

[0161] Next, refer to Figure 9Then, perform step S2-9 to remove the first temporary substrate 310 and expose the third wiring layer 130.

[0162] Specifically, the structure after this step can be found in the following reference. Figure 8 Specifically, the first temporary substrate 310 can be removed by methods such as thermal sliding, chemical dissolution or mechanical peeling to ensure that no damage is caused to the structure.

[0163] Next, refer to Figure 9 Then, proceed with step S2-10 to cut the current structure into multiple receiving elements 11. The cut structure can be referenced. Figure 8 .

[0164] The specific process steps of steps S2-9 to S2-10 can be found in Example 1, and will not be described in detail here.

[0165] As an example, the method for fabricating the semiconductor structure further includes:

[0166] See Figure 14 In step S2-11, an intermediary layer 420 is provided. The receiving element 11 is bonded to the intermediary layer 420 through the third wiring layer 130, and the third wiring layer 130 is electrically connected to the intermediary layer 420. The intermediary layer 420 has a rewiring layer near the surface.

[0167] See Figure 15 Step S2-12 is performed to provide a transmitting element 12, the transmitting element 12 having a fourth wiring layer 160 located on the surface of the transmitting element 12, and being bonded to the receiving element 11 in parallel to the intermediate layer 420 through the fourth wiring layer 160.

[0168] See Figure 15 Step S2-13 is executed to form a molding layer 520 on the surface of the intermediate layer 420, the molding layer 520 covering the transmitting element 12 and the receiving element 11.

[0169] See Figure 15 In step S2-14, a second TSV post 510 is formed from the side of the interposer layer 420 away from the molding layer, penetrating the interposer layer 420. One end of the second TSV post 510 is electrically connected to the fourth wiring layer 160 and the third wiring layer 130 respectively through the redistribution layer on the interposer layer 420. The other end of the second TSV post 510 is exposed on the side of the interposer layer 420 away from the transmitting element 12, so as to realize the vertical lead-out of the signal to the external substrate.

[0170] See Figure 16In step S2-15, a packaging substrate 500 is provided, wherein a third TSV pillar 530 is disposed therein; the side of the interposer layer 420 facing away from the receiving element 11 is bonded to the packaging substrate 500, such that one end of the third TSV pillar 530 is electrically connected to the second TSV pillar 510, and the other end of the third TSV pillar 530 is exposed on the side of the packaging substrate 500 away from the interposer layer 420.

[0171] See Figure 16 In step S2-16, a metal bump 540 is formed on the side of the packaging substrate 500 away from the interposer layer 420. The metal bump 540 is electrically connected to the other end of the third TSV pillar 530. (See also...) Figure 17 Subsequently, a PCB board 600 or other circuit board is provided, and the packaging substrate 500 is bonded to the PCB board 600 through the metal bumps 540, thereby realizing the final fan-out and interconnection of the signals of the transmitting element 12 and the receiving element 11 to the external system. For a detailed description of the materials and processes of the above steps, please refer to Embodiment 1.

[0172] This embodiment effectively addresses the technical challenge of simultaneously achieving high integration density, structural reliability, and optical integrity by adjusting the relationship between the design process timing and the structure. Specifically, by separating the TSV high-temperature process from the microlens fabrication and combining it with transparent cover plate 240 packaging, the damage path to the optical structure from subsequent processes is eliminated at the source. Simultaneously, the introduction of the first temporary substrate provides end-to-end mechanical support for the thin wafer, overcoming the structural instability risk caused by thinning. Furthermore, the vertical interconnection of the first TSV pillars 140 further shortens the signal transmission distance. Thus, this solution achieves three-dimensional high-density integration while simultaneously improving device reliability, optical efficiency, and high-frequency electrical performance, constituting a systematic solution to the technical challenges at each stage.

[0173] Example 3

[0174] See Figure 8 This embodiment provides an optical communication receiving component, which can be fabricated using the preparation method described in Embodiment 1 or 2, or a similar method. The optical communication receiving component includes a receiving element 11, which comprises:

[0175] A first wafer 100 includes a receiving circuit located near the front side of the first wafer 100.

[0176] The first wiring layer 110 is located on the front side of the first wafer 100.

[0177] Specifically, the first wafer 100 serves as the substrate of the receiving element 11 in this embodiment, and its internal receiving circuit (e.g., a transimpedance amplifier) ​​is used to convert the weak photocurrent generated by the photodetector array into a voltage signal and amplify it. In addition, the first wiring layer 110 is fabricated on the front side of the first wafer 100 and includes multiple layers of metal interconnects and bonding pads for leading out the input / output signals of the aforementioned receiving circuit.

[0178] The second wafer 200 includes a photodetector array near the back side of the second wafer 200; a second wiring layer 210 is disposed on the front side of the second wafer 200; the first wiring layer 110 and the second wiring layer 210 are mixed-bonded to electrically connect the first wafer 100 and the second wafer 200.

[0179] Specifically, the aforementioned photodetector array includes a PIN or APD for converting incident light signals into electrical signals. The second wiring layer 210 is electrically connected to the anode / cathode of the photodetector array, for collecting photogenerated carriers and forming a photocurrent, and for providing a metal interface for hybrid bonding with the first wiring layer 110.

[0180] The microlens array 220 is located on the back side of the second wafer 200 and is aligned with the pixels of the photodetector array to focus incident light and improve light collection efficiency.

[0181] A dike 230 is disposed on the back side of the second wafer 200 and surrounds the microlens array 220;

[0182] A transparent cover plate 240 is bonded to the back side of the second wafer 200 via the cofferdam 230. The transparent cover plate 240, the cofferdam 230, and the second wafer 200 together form a cavity 120. The transparent cover plate 240 covers and protects the microlens array 220, and the microlens array 220 is located within the cavity 120, thereby preventing it from getting damp or scratched.

[0183] Specifically, a cofferdam 230 can be formed through a cofferdam process. The cavity 120 is limited by the height of the cofferdam 230 and is filled with air or inert gas to prevent the transparent cover plate 240 from directly contacting the surface of the microlens array 220, thereby maintaining the designed optical focal length.

[0184] The first TSV pillar 140 extends from the back of the first wafer 100 through the first wafer 100 to the first wiring layer 110 and is electrically connected to the first wiring layer 110, thereby realizing low-impedance transmission of the receiving circuit signal from the front to the bottom.

[0185] The third wiring layer 130 is located on the back side of the first wafer 100 and is electrically connected to the first wiring layer 110 through the first TSV pillar 140, thereby fanning out the received signal into a high-density bonding structure.

[0186] As an example, see Figures 14-17 The optical communication receiving component further includes:

[0187] Intermediate layer 420, the third wiring layer 130 is bonded to the intermediate layer 420 and electrically connected to the intermediate layer 420, so that the receiving element 11 is bonded to the intermediate layer 420 side by side, thereby realizing the external output of the received signal and coplanar integration with the transmitting element 12.

[0188] In this embodiment, the emitting element 12 and the receiving element 11 are designed to have the same thickness and are both bonded to the same flat interposer layer 420. Therefore, their upper surfaces are naturally coplanar, achieving passive optical alignment without the need for active dimming. It should be noted that having the same thickness can be understood as the height of the emitting surface of the Micro-LED of the emitting element 12 relative to the interposer layer 420 and the height of the light-receiving surface of the photodetector of the receiving element 11 relative to the interposer layer 420 being the same. This sameness is within the error range of the process implementation in this field. The above arrangement can also mitigate crosstalk between emitted and received light based on the process described in this application.

[0189] The transmitting element 12 has a fourth wiring layer 160 located on the surface of the transmitting element 12, and is bonded to the receiving element 11 in parallel to the intermediate layer 420 through the fourth wiring layer 160.

[0190] A molding compound 520 is located on the surface of the interposer 420, and the molding compound 520 covers the transmitting element 12 and the receiving element 11; in some embodiments, the semiconductor structure further includes a SerDes chip 13 for providing serialization and / or deserialization functions for the semiconductor structure.

[0191] The packaging substrate 500 is disposed on the side of the interposer 420 opposite to the first wafer 100, providing mechanical support and external electrical interface for the entire semiconductor structure. A third TSV pillar 530 is disposed in the packaging substrate 500. The packaging substrate 500 is usually an organic substrate or a ceramic substrate, and its surface is provided with bonding pads corresponding to the second TSV pillar 510.

[0192] The second TSV pillar 510 penetrates the interposer layer 420. One end of the second TSV pillar 510 is electrically connected to the fourth wiring layer 160 and / or the third wiring layer 130, and the other end of the second TSV pillar 510 is electrically connected to the third TSV pillar 530, so as to realize the vertical fan-out of chip signals to the board-level system.

[0193] Metal bump 540, the metal bump 540 is located on the side of the packaging substrate 500 away from the interposer layer 420, and is electrically connected to the third TSV pillar 530.

[0194] As an example, the cross-section of the first TSV column 140 is stepped or conical.

[0195] Specifically, the stepped cross-section refers to a multi-step change in diameter along the longitudinal direction of the first TSV column 140; in this embodiment, the tapered cross-section refers to a smooth inclined structure in which the diameter of the first TSV column 140 gradually decreases from top to bottom. Both cross-sectional shapes are beneficial for reducing stress concentration, improving the uniformity of membrane coverage, and reducing filling voids.

[0196] As an example, the cavity 120 is filled with one of nitrogen, helium or argon.

[0197] As an example, see Figure 19 and Figure 20 The semiconductor structure further includes at least one SerDes chip 13, which is bonded to the interposer layer 420, arranged side-by-side with the receiving element 11, and is electrically connected to the interposer layer 420.

[0198] As an example, the cofferdam 230 is formed by the cofferdam process, and the material of the cofferdam 230 structure includes either glass or polyimide.

[0199] In one example, a reliable sealing structure is required within the cavity 120. The cofferdam 230 structure adopts a continuous, wide-dimensional design, replacing the traditional dot matrix or narrow line pattern, which can provide a larger bonding area and a more continuous sealing interface.

[0200] Unless otherwise specified, the materials, structures and preparation methods of each component in this embodiment are the same as those in Embodiment 1, and will not be described again here.

[0201] In summary, this invention provides an optical communication receiving component and its fabrication method, aiming to solve the technical problem of the difficulty in synergistically optimizing integration density, structural reliability, and optical integrity in optical receiving module packaging. High-density vertical interconnection between the photodetector array and the receiving circuit is achieved through hybrid bonding of a first wafer and a second wafer. After the microlens array is fabricated, a transparent cover plate is bonded using a damming process to form a sealed cavity, ensuring the microlens array is physically isolated. This effectively avoids damage to the optical structure from particles, chemicals, and mechanical contact in subsequent processes, ensuring the long-term stability of optical coupling efficiency. Simultaneously, a first TSV pillar enables low-parasitic, short-path signal vertical extraction from the back side of the first wafer to the front wiring layer, overcoming the limitations of density and signal quality degradation in traditional interconnection methods. Through the synergistic design of hybrid bonding, cavity protection, and TSV vertical interconnection, this invention effectively reduces parasitic parameters and package size while increasing integration density, and significantly improves structural integrity and optical performance stability during the manufacturing process. This comprehensively solves the problems of low interconnection density, high parasitic parameters, large package size, structural fragility, and susceptibility to optical performance in the prior art. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0202] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an optical communication receiving component, characterized in that, include: A first wafer is provided, the first wafer including a receiving circuit near the front side of the first wafer; a first wiring layer is disposed on the front side of the first wafer; A second wafer is provided, including a photodetector array near the back side of the second wafer; a second wiring layer is disposed on the front side of the second wafer; The first wiring layer and the second wiring layer are mixed and bonded to electrically connect the first wafer and the second wafer; Based on the bonding of the first wafer and the second wafer, a structure to be diced is formed, including: A microlens array is disposed on the back side of the second wafer, and a transparent cover plate is bonded to the back side of the second wafer using a cofferdam process. A cavity is formed between the transparent cover plate and the second wafer. The transparent cover plate covers and protects the microlens array, and the microlens array is located within the cavity. A first TSV pillar is formed on the back side of the first wafer, penetrating the first wafer to the first wiring layer and electrically connected to the first wiring layer. A third wiring layer is formed on the back side of the first wafer, and the third wiring layer is electrically connected to the first wiring layer through the first TSV pillar. The structure to be cut is cut to form multiple receiving elements.

2. The method for fabricating an optical communication receiving component according to claim 1, characterized in that, The specific steps following the co-bonding of the first wafer and the second wafer include: Thin the back side of the second wafer, and then deposit the microlens array on the back side of the second wafer; The transparent cover plate is provided and bonded to the surface of the second wafer by a damming process. The cavity is formed between the transparent cover plate and the second wafer. The transparent cover plate covers and protects the microlens array, and the microlens array is located within the cavity. The back side of the first wafer is thinned, and a first TSV hole is formed from the back side of the first wafer through the first wafer to the first wiring layer. The hole is filled with conductive material to form the first TSV pillar, and the first TSV pillar is electrically connected to the first wiring layer. The third wiring layer is formed on the back side of the first wafer, and the third wiring layer is electrically connected to the first wiring layer through the first TSV pillar to obtain the structure to be cut. The structure to be cut is cut to form a plurality of receiving elements.

3. The method for fabricating an optical communication receiving component according to claim 1, characterized in that, The specific steps following the co-bonding of the first wafer and the second wafer include: The back side of the first wafer is thinned, and a first TSV hole is formed from the back side of the first wafer through the first wafer to the first wiring layer. The hole is filled with conductive material to form the first TSV pillar, and the first TSV pillar is electrically connected to the first wiring layer. The third wiring layer is formed on the back side of the first wafer, and the third wiring layer is electrically connected to the first wiring layer through the first TSV pillar; A first temporary substrate is provided, and the first temporary substrate is bonded to the surface of the third wiring layer; Thin the back side of the second wafer, and then deposit the microlens array on the back side of the second wafer; The transparent cover plate is provided and bonded to the back of the second wafer using a cofferdam process. The cavity is formed between the transparent cover plate and the second wafer. The transparent cover plate covers and protects the microlens array, and the microlens array is located within the cavity. Remove the first temporary substrate to expose the third wiring layer, thereby obtaining the structure to be cut; The structure to be cut is cut to form a plurality of receiving elements.

4. The method for fabricating an optical communication receiving component according to claim 1, characterized in that, Also includes: An intermediate layer is provided, wherein the receiving element is bonded to the intermediate layer via the third wiring layer and the third wiring layer is electrically connected to the intermediate layer, and the intermediate layer has a redistribution layer near the surface; A transmitting element is provided, the transmitting element having a fourth wiring layer located on the surface of the transmitting element, and being bonded in parallel to the receiving element to the interposer layer through the fourth wiring layer; A molding layer is formed on the surface of the intermediate layer, and the molding layer covers the transmitting element and the receiving element; A second TSV post is formed from the side of the interposer away from the molding layer, penetrating the interposer. One end of the second TSV post is electrically connected to the fourth wiring layer and the third wiring layer through the redistribution layer on the interposer, respectively. The other end of the second TSV post is exposed on the side of the interposer away from the receiving element. A packaging substrate is provided, wherein a third TSV pillar is disposed therein, and the side of the interlayer opposite to the receiving element is bonded to the packaging substrate, such that one end of the third TSV pillar is electrically connected to the second TSV pillar, and the other end of the third TSV pillar is exposed on the side of the packaging substrate away from the interlayer. A metal bump is formed on the side of the packaging substrate away from the interlayer, and the metal bump is electrically connected to the other end of the third TSV pillar.

5. The method for fabricating an optical communication receiving component according to claim 4, characterized in that, Also includes: At least one SerDes chip is provided and bonded to the interposer layer, arranged side by side with the receiving element and the transmitting element, and the SerDes chip is electrically connected to the interposer layer.

6. The method for preparing the optical communication receiving component according to claim 4, characterized in that, The receiving element includes the photodetector and the receiving circuit, and the transmitting element includes a Micro-LED array and a corresponding driving circuit. The transmitting element and the receiving element are disposed at intervals on the interposer layer.

7. The method for fabricating an optical communication receiving component according to claim 1, characterized in that: The material of the cofferdam includes either glass or polyimide; and / or, the coefficient of thermal expansion of the transparent cover plate is in the range of 3 to 4 ppm / K.

8. The method for fabricating an optical communication receiving component according to claim 1, characterized in that, Also includes: The cavity is filled with one of nitrogen, helium, or argon.

9. An optical communication receiving component, characterized in that, The optical communication receiving component includes a receiving element, which includes: A first wafer, the first wafer including a receiving circuit near the front side of the first wafer; The first wiring layer is located on the front side of the first wafer and is electrically connected to the receiving circuit. The second wafer includes a photodetector array near the back side of the second wafer; a second wiring layer is disposed on the front side of the second wafer; the first wiring layer and the second wiring layer are hybrid bonded to electrically connect the first wafer and the second wafer. A microlens array is located on the back side of the second wafer; A dike is disposed on the back side of the second wafer and surrounds the microlens array; A transparent cover plate is bonded to the back side of the second wafer via the dam. The transparent cover plate, the dam, and the second wafer together form a cavity. The transparent cover plate covers and protects the microlens array, and the microlens array is located within the cavity. The first TSV pillar extends from the back side of the first wafer through the first wafer to the first wiring layer and is electrically connected to the first wiring layer. The third wiring layer is located on the back side of the first wafer and is electrically connected to the first wiring layer through the first TSV pillar.

10. The optical communication receiving component according to claim 9, characterized in that, Also includes: An interposer layer, wherein the third wiring layer is bonded to and electrically connected to the interposer layer, the interposer layer having a redistribution layer near the surface; A transmitting element having a fourth wiring layer on the surface of the transmitting element, and being bonded in parallel to the receiving element to the interposer layer via the fourth wiring layer; A molding compound is located on the surface of the intermediate layer, and the molding compound covers the transmitting element and the receiving element; A packaging substrate is disposed on the side of the interposer layer opposite to the first wafer; a third TSV pillar is disposed within the packaging substrate; The second TSV post penetrates the interposer layer. One end of the second TSV post is electrically connected to the fourth routing layer and the third routing layer through the redistribution layer on the interposer layer, respectively. The other end of the second TSV post is electrically connected to the third TSV post. A metal bump is located on the side of the packaging substrate away from the interposer and is electrically connected to the third TSV pillar.

11. The optical communication receiving component according to claim 10, characterized in that, It also includes at least one SerDes chip, which is bonded to the interposer layer, arranged side by side with the receiving element and the transmitting element, and the SerDes chip is electrically connected to the interposer layer.

12. The optical communication receiving component according to claim 10, characterized in that, The receiving element includes the photodetector and the receiving circuit, and the transmitting element includes a Micro-LED array and a corresponding driving circuit. The transmitting element and the receiving element are disposed at intervals on the interposer layer.

13. The optical communication receiving component according to claim 10, characterized in that, The transmitting element and the receiving element have the same thickness and are both bonded to the same interposer layer.

14. The optical communication receiving component according to claim 9, characterized in that: The first TSV column has a stepped or conical cross-section.

15. The optical communication receiving component according to claim 9, characterized in that: The cavity is filled with one of nitrogen, helium, or argon.

Images