A method for bit synchronization performance enhancement for a non-continuous wave communication reception link

Abstract

The application relates to a bit synchronization performance enhancement method for a non-continuous wave communication receiving link, which comprises the following steps: performing frame synchronization on a receiving signal frame to determine the starting position of a frame header sample point; performing frequency offset estimation based on the frame header sample point, and performing frequency offset compensation on the receiving signal frame according to the estimation result; embedding a set number of redundant sample points before the starting position of the frame header sample point of the receiving signal frame after the frequency offset compensation, and performing bit synchronization on the generated signal frame to obtain a processing signal frame; and removing the bit-synchronized redundant sample points from the processing signal frame to obtain a bit-synchronized receiving signal frame. The application can effectively solve the performance loss problem caused by the bit synchronization convergence process in the non-continuous wave scene, and greatly reduces the complexity of high-throughput satellite communication receiving.

Description

Technical Field

[0001] This invention relates to the field of discontinuous wave communication technology, and in particular to a method for enhancing bit synchronization performance in discontinuous wave communication receiving links. Background Technology

[0002] In satellite communication, the differences in frequency and phase between the sampling clocks of the transmitter and receiver, coupled with inherent signal delays during transmission and processing, often cause the receiver's sampling time to deviate from the optimal sampling time. This introduces inter-symbol interference (ISI), increasing the bit error rate and degrading reception performance. Therefore, timing synchronization is essential in the signal processing of satellite communication receivers to minimize sampling time deviations, i.e., timing errors. This timing synchronization is also called bit synchronization.

[0003] There are various bit synchronization algorithms, among which Gardner timing synchronization in feedback timing synchronization only requires a sampling rate of 2x to work. For high-bandwidth, high-throughput satellite communication, a sampling rate of 2x can greatly reduce receiver complexity. However, Gardner bit synchronization has a convergence time, and timing synchronization is inaccurate in the first few thousand sampling points. In discontinuous wave scenarios, this bit synchronization convergence process will cause inaccurate timing synchronization of the frame header. Since channel estimation (LMS, RLS, etc.) is performed after the frame header, the timing error at the frame header will greatly reduce the accuracy of channel estimation, resulting in degraded performance after equalization, and further affecting demodulation performance. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for enhancing the bit synchronization performance of a discontinuous wave communication receiving link, which can effectively solve the performance loss problem caused by the bit synchronization convergence process in discontinuous wave scenarios and greatly reduce the complexity of high-throughput satellite communication reception.

[0005] The technical solution adopted by this invention to solve its technical problem is: to provide a method for enhancing bit synchronization performance in discontinuous wave communication receiving links, comprising: Perform frame synchronization on the received signal frames to determine the starting position of the frame header samples; Frequency offset estimation is performed based on frame header samples, and frequency offset compensation is performed on the received signal frame based on the estimation results. A set number of redundant samples are embedded before the start position of the header sample of the received signal frame after frequency offset compensation, and bit synchronization is performed on the generated signal frame to obtain the processed signal frame. The redundant samples after bit synchronization are removed from the processed signal frame to obtain the bit-synchronized received signal frame.

[0006] Furthermore, the number of redundant samples is set based on the convergence time when performing bit synchronization on the received signal frame after frequency offset compensation.

[0007] Furthermore, bit synchronization is Gardner bit synchronization.

[0008] Furthermore, when Gardner bit synchronization uses first-order loop filtering, the number of redundant samples is 2000.

[0009] Furthermore, redundant samples are obtained by copying a set number of frequency offset compensated frame header samples.

[0010] Furthermore, if the number of frame header samples is equal to the number of redundant samples, the received signal frame after frequency offset compensation is serially read twice for the frame header samples and then read for the non-frame header samples. The read samples are then bit synchronized to obtain the processed signal frame.

[0011] Furthermore, the frequency offset estimation is a coarse frequency offset estimation.

[0012] Furthermore, the received signal frames after bit synchronization are sequentially subjected to fine frequency offset synchronization, equalization processing, phase offset synchronization, symbol demapping, and decoding.

[0013] Beneficial effects By adopting the above-mentioned technical solution, the present invention has the following advantages and positive effects compared with the prior art: This invention transfers the entire convergence process of the loop to subsequent, removable redundant samples by locally splicing redundant frame header samples that match the loop convergence time. This ensures that the frame header samples of valid frames are high-precision timing samples output after the loop enters steady state, thus avoiding the negative impact of the convergence process on channel estimation and equalization from the root. It completely solves the inherent performance loss of existing links, enabling a 2x speed bit synchronization receiver to achieve performance comparable to a 4x speed feedforward bit synchronization receiver, and greatly reducing the complexity of high-throughput satellite communication receivers. This invention does not rely on the physical layer parameters of a specific communication scenario. For all discontinuous wave communication systems that adopt a link architecture of first frame synchronization and then position synchronization, the length of redundant samples only needs to be adjusted according to the convergence time of the Gardner loop used to improve the timing accuracy of the frame header, thereby improving the channel estimation and equalization performance, and ultimately improving the demodulation performance of the entire system, without the need for customized modifications for different scenarios. Attached Figure Description

[0014] Figure 1 This is a flowchart of an embodiment of the present invention; Figure 2 This is a schematic diagram of the Gardner bit synchronization process according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the satellite communication receiving link processing flow according to an embodiment of the present invention; Figure 4This is a schematic diagram of Gardner bit synchronization convergence according to an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the channel estimation effect of an embodiment of the present invention; Figure 6 This is a flowchart illustrating a preferred embodiment of the present invention. Figure 7 This is a flowchart illustrating a preferred embodiment of the present invention, specifically a second embodiment. Detailed Implementation

[0015] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0016] Embodiments of the present invention relate to a method for enhancing bit synchronization performance in discontinuous wave communication receiver links, such as... Figure 1 As shown, it includes: Perform frame synchronization on the received signal frames to determine the starting position of the frame header samples; Frequency offset estimation is performed based on frame header samples, and frequency offset compensation is performed on the received signal frame based on the estimation results. A set number of redundant samples are embedded before the start position of the header sample of the received signal frame after frequency offset compensation, and bit synchronization is performed on the generated signal frame to obtain the processed signal frame. The redundant samples after bit synchronization are removed from the processed signal frame to obtain the bit-synchronized received signal frame.

[0017] By synchronizing the received signal frames, the valid start point of the current transmission frame can be located, the range of the entire frame can be determined, and the position of the frame header sample points that need to be copied later can be determined.

[0018] Then, coarse frequency offset estimation is performed using the frame header, and frequency offset compensation is applied to the entire frame. This step is to ensure that the bit synchronization convergence time is controllable. Bit synchronization has an upper limit to its tolerance for frequency offset; a large frequency offset will cause the timing error detection results to deviate, resulting in slower convergence or even divergence. By first performing coarse frequency offset compensation to bring the frequency offset within the working range of bit synchronization, it is possible to ensure that the loop convergence time is stable at around the preset number of samples, avoiding insufficient redundancy length or wasted processing resources in the future.

[0019] For example Figure 2Taking Gardner bit synchronization as an example, the convergence time of a first-order loop filter is approximately 2000 samples. The 2000 frame header samples are repeated once, inserted before the valid start point of the frame header, and then bit synchronization is performed on the transmitted frame after the insertion of redundant samples. The loop iteratively adjusts during the processing of these 2000 redundant samples. By the time these redundant samples are processed, the loop has entered a steady state, and the timing error is stable within acceptable limits.

[0020] Directly copying existing frame header samples eliminates the need to generate new sequences. Furthermore, the copied samples undergo coarse frequency offset compensation, ensuring complete consistency in symbol characteristics, modulation format, and subsequent useful data. This avoids post-convergence offset issues caused by mismatches between training sequences and data characteristics, resulting in extremely low implementation costs. If the frame header length itself is insufficient to meet the quantity requirements, the frame header samples can be repeated multiple times to reach the required convergence length, making the solution highly adaptable.

[0021] Finally, the 2000 duplicate samples in the bit synchronization output are removed, and the remaining samples are used for subsequent receiver processing (i.e., Figure 3 (This refers to the processing after bit synchronization in the satellite communication receiver's processing flow). At this point, the remaining samples constitute the original complete transmission frame. Furthermore, when the original frame header enters the bit synchronization module, the loop is already in a steady state. Therefore, the timing accuracy of the frame header is completely unaffected by the convergence process. The accuracy of channel estimation using this frame header is greatly improved, and the subsequent equalization and demodulation performance is naturally guaranteed.

[0022] Specifically, such as Figure 4 As shown in the figure, the convergence time of Gardner bit synchronization is approximately 2000 samples. Figure 5 As shown, it is easy to see that after skipping the bit synchronization convergence time, the constellation diagram becomes clearer, thus greatly improving demodulation performance. Simulation results show that for a 32APSK 8 / 9 bit rate, the method of this invention can produce a 2dB performance gain in demodulation.

[0023] like Figure 6 The image shown is a preferred embodiment of this implementation.

[0024] The frame structure of the input bit synchronization module consists of four parts: Redundant samples (repeated parts of the frame header): The length matches the convergence time of the Gardner loop (2000 samples), and is a redundant area specifically for warming up the loop for convergence. Frame header sample: The actual frame header of the original transmitted frame, which is a reference for subsequent channel estimation; Payload samples: valid business data; Post-samples: Training sequences at the end of frames, used to assist in synchronization and equalization operations.

[0025] First, frame synchronization is used to find the starting position of the frame header samples. Then, approximately 2000 samples from the frame header are repeated before being inserted into the frame header, and bit synchronization is performed again. Finally, the approximately 2000 repeated samples from the bit synchronization output are deleted, and the remaining samples are used for subsequent receiver processing.

[0026] like Figure 7 The image shown is a preferred embodiment of this implementation.

[0027] The frame structure of the input to the bit synchronization module consists of three parts: frame header, payload, and post-caption. Before sending data into the bit synchronization module, the receiver serially reads the frame header sample points located in the buffer twice: the frame header sample points read the first time are used as redundant sample points, and the frame header sample points read the second time are the original valid frame header. The original payload and post-caption are then concatenated to generate a transmission frame with redundancy.

[0028] If the frame header itself is less than 2000 samples long, the required 2000 samples can be obtained by repeatedly reading the frame header samples in a loop, adapting to different frame structure designs. The copied samples have completely consistent modulation characteristics and frequency offset compensation characteristics with the entire frame, avoiding the problem of mismatch between the loop and the actual data after convergence using an unfamiliar sequence. Moreover, only a small amount of buffer reading logic needs to be added, without the need for additional sequence generation circuitry, resulting in extremely low hardware implementation costs.

[0029] The specific steps are as follows: Use frame synchronization to find the starting position of the frame header sample; The 2000 samples in the frame header were serially read twice using a bit-synchronized hardware accelerator. For the output frame of the bit sync accelerator, 2000 duplicate samples are removed, and the remaining samples are used for subsequent receiver processing.

[0030] In this implementation, the intermediate synchronization convergence time of 2000 points is a configurable value, and different values ​​can be configured according to different scenarios.

Claims

1. A method for enhancing bit synchronization performance in discontinuous wave communication receiving links, characterized in that, include: Perform frame synchronization on the received signal frames to determine the starting position of the frame header samples; Frequency offset estimation is performed based on frame header samples, and frequency offset compensation is performed on the received signal frame based on the estimation results. A set number of redundant samples are embedded before the start position of the header sample of the received signal frame after frequency offset compensation, and bit synchronization is performed on the generated signal frame to obtain the processed signal frame. The redundant samples after bit synchronization are removed from the processed signal frame to obtain the bit-synchronized received signal frame.

2. The bit synchronization performance enhancement method according to claim 1, characterized in that, The number of redundant samples is set based on the convergence time when performing bit synchronization on the received signal frame after frequency offset compensation.

3. The bit synchronization performance enhancement method according to claim 2, characterized in that, Bit synchronization is Gardner bit synchronization.

4. The bit synchronization performance enhancement method according to claim 3, characterized in that, When Gardner bit synchronization uses a first-order loop filter, the number of redundant samples is 2000.

5. The bit synchronization performance enhancement method according to claim 1, characterized in that, Redundant samples are obtained by copying a set number of frequency offset compensated frame header samples.

6. The bit synchronization performance enhancement method according to claim 5, characterized in that, If the number of frame header samples is equal to the number of redundant samples, then the received signal frame after frequency offset compensation is serially read twice for the frame header samples and then read for the non-frame header samples. The read samples are then bit synchronized to obtain the processed signal frame.

7. The bit synchronization performance enhancement method according to claim 1, characterized in that, The frequency offset estimation is a coarse frequency offset estimation.

8. The bit synchronization performance enhancement method according to claim 1, characterized in that, After the received signal frame is synchronized, fine frequency offset synchronization, equalization processing, phase offset synchronization, symbol demapping and decoding are performed sequentially.

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