A miniaturized satellite navigation receiver

Abstract

The application relates to a miniaturized satellite navigation receiver, which receives three constellation navigation satellite signals of GPS, GLONASS and BD second-generation B1 through a first electric connector, receives a BD second-generation B3 constellation navigation satellite signal through a second electric connector, and respectively carries out filtering, frequency mixing and down conversion to a baseband, and through an A / D analog-digital converter, the down-converted analog-digital conversion is sent to an FPGA; the FPGA realizes capturing and tracking of the above three navigation signals, and after frequency domain narrowband interference resistance processing of another frequency point navigation signal, the FPGA realizes capturing and tracking again, the FPGA sends demodulated original data to a DSP, the DSP carries out navigation calculation, and a data stream is transmitted through an interface circuit, the receiver realizes reduction of the volume of the satellite navigation receiver, realizes miniaturized design, has strong anti-interference capability, the FPGA has large design resources, and the performance of the satellite navigation receiver is greatly improved.

Description

Technical Field

[0001] This invention belongs to the field of satellite positioning, navigation and control technology, and relates to a miniaturized satellite navigation receiver. Background Technology

[0002] The common design approach for satellite navigation receivers involves combining multiple independent functional chips to perform functions such as amplification, mixing, automatic gain control, and down-conversion of GPS, GLONASS, and BD2 single-constellation satellite signals. This is typically accomplished using independent amplifiers, frequency synthesizers, and quadrature demodulators. The down-converted satellite signal to baseband is acquired, tracked, and demodulated by an FPGA, while positioning is calculated by a DSP.

[0003] The miniaturization of satellite navigation receivers has been greatly improved. However, the current satellite navigation and security control systems, while maintaining the same external dimensions and interfaces as the original satellite navigation and security control instruments, receive and process signals from three satellite systems at three frequencies: GPS, GLONASS, and BeiDou-1. The satellite navigation receivers can only receive and process signals from GPS, GLONASS, and BeiDou-1 satellites and lack anti-interference capabilities. Summary of the Invention

[0004] The purpose of this invention is to overcome the above-mentioned shortcomings of the prior art and provide a miniaturized satellite navigation receiver. This receiver reduces the size of the satellite navigation receiver, achieves a miniaturized design, and simultaneously has navigation and positioning capabilities for four frequency points of three systems: GPS, GLONASS, BDII-B1, and BDII-B3. It also has strong anti-interference capabilities, large FPGA design resources, and greatly improves the performance of the satellite navigation receiver.

[0005] The above-mentioned objectives of the present invention are mainly achieved through the following technical solutions:

[0006] A miniaturized satellite navigation receiver includes a first filter, a second filter, a first mixer, a second mixer, a first A / D analog-to-digital converter, a second A / D analog-to-digital converter, a DSP, an FPGA, a first crystal oscillator, a second crystal oscillator, an amplifier, a clock generator, a FLASH memory, a watchdog timer, an interface circuit, a first electrical connector, a second electrical connector, and a third electrical connector, wherein:

[0007] The first electrical connector transmits satellite signals from three constellations—GPS, GLONASS, and BD2B1—received from the outside to the first filter.

[0008] First filter: Bandpass-filters the satellite signal received from the first electrical connector and sends it to the first mixer;

[0009] First mixer: Receives the satellite signal from the first filter, amplifies, performs automatic gain control, mixes and down-converts the satellite signal, and outputs it to the first A / D analog-to-digital converter;

[0010] The first A / D converter converts the analog intermediate frequency satellite signal received from the first mixer into a digital signal y(n1) and outputs it to the FPGA.

[0011] Second electrical connector: transmits satellite signals received from the external BD2 B3 constellation to the second filter;

[0012] Second filter: Bandpass-filters the satellite signal received from the second electrical connector and sends it to the second mixer;

[0013] Second mixer: Receives satellite signals from the second filter, amplifies, performs automatic gain control, mixes and down-converts the satellite signals, and outputs them to the second A / D analog-to-digital converter;

[0014] The second A / D converter converts the analog intermediate frequency satellite signal received from the second mixer into a digital signal y(n2) and outputs it to the FPGA.

[0015] The FPGA receives digital signals y(n1) from three constellations (GPS, GLONASS, and BD2B1) output from the first A / D converter, and performs correlation processing with the local GPS, GLONASS, and BD2B1 signals to obtain the GPS digital signal g(n1), the GLONASS digital signal s(n1), and the BD2B1 digital signal b(n1). It also receives the BD2B3 digital signal y(n2) output from the second A / D converter, performs frequency domain anti-interference processing on y(n2) to obtain the interference-free BD2B3 signal z(n2). Subsequently, it performs code acquisition and tracking, carrier acquisition and tracking, bit synchronization, frame synchronization, data acquisition, and message demodulation on signals g(n1), s(n1), b(n1), and z(n2) to obtain raw observation data, which is then output to the DSP. Simultaneously, it receives positioning data output from the DSP, performs timing conversion on the positioning data, and outputs it to the third electrical connector via an interface circuit.

[0016] The DSP includes a system control unit, a navigation processing unit, and a channel processing unit. The channel processing unit controls the FPGA's acquisition and tracking, outputs acquisition and tracking status information to the system control unit, and reads raw observation data from the FPGA, sending it to the navigation processing unit. The navigation processing unit performs positioning calculations on the raw observation data to generate receiver position information, velocity information, pseudorange, pseudorange rate, satellite almanac, and time information, and outputs these information to the system control unit. The system control unit outputs the receiver position information, velocity information, pseudorange, pseudorange rate, and time information to the FPGA, stores the satellite almanac, receiver position information, and time information in FLASH memory, and initializes the first mixer, second mixer, DSP, FPGA, first A / D converter, second A / D converter, and interface circuits upon power-up. It also receives control information from external matching devices through the FPGA.

[0017] First crystal oscillator: generates clock and outputs it to amplifier and clock generator;

[0018] Amplifier: Receives the clock generated by the first crystal oscillator and outputs the amplified clock 1 to the first mixer and the second mixer;

[0019] Clock generator: Receives the clock generated by the first crystal oscillator, and sends the clock 2 obtained after frequency conversion to the FPGA, the first A / D analog-to-digital converter and the second A / D analog-to-digital converter respectively;

[0020] Second crystal oscillator: generates clock 3 and sends it to the DSP;

[0021] FLASH: Stores the DSP program and FPGA program, and also saves the satellite almanac, receiver position information and time information stored in the DSP;

[0022] Watchdog: Monitors program execution and provides a reset function for the DSP to prevent program crashes due to unexpected reasons;

[0023] Interface circuit: Receives information from the third electrical connector and outputs it to the FPGA. At the same time, it receives receiver position information, speed information, pseudorange, pseudorange rate and time information from the FPGA and sends them to the third electrical connector.

[0024] The third electrical connector outputs control information sent by the external matching device to the interface circuit, and sends the receiver position information, speed information, pseudorange, pseudorange rate and time information output by the interface circuit to the external matching device.

[0025] In the aforementioned miniaturized satellite navigation receiver, the FPGA includes a frequency domain anti-narrowband interference processing unit, an acquisition and tracking unit, and a serial port core, wherein:

[0026] Frequency domain anti-narrowband interference processing unit: Receives digital signals y(n1) from three constellations (GPS, GLONASS, and BD2B1) output from the first A / D converter, and performs correlation processing with the local GPS, GLONASS, and BD2B1 signals respectively to obtain the GPS digital signal g(n1), the GLONASS digital signal s(n1), and the BD2B1 digital signal b(n1); Receives the BD2B3 digital signal y(n2) output from the second A / D converter, and performs frequency domain anti-interference processing on the digital signal y(n2) to obtain the interference-free BD2B3 signal z(n2);

[0027] Acquisition and tracking unit: performs code acquisition and tracking, carrier acquisition and tracking, bit synchronization, frame synchronization, data acquisition and message demodulation on signals g(n1), s(n1), b(n1), and z(n2) respectively to obtain raw observation data, and sends the raw observation data to the DSP; at the same time, it receives the positioning data output by the DSP, and outputs the positioning data to the third electrical connector through the interface circuit after timing conversion.

[0028] Serial port kernel: Generates a second pulse and sends it to the interface circuit. It performs timing processing on the serial port data received and sent through the interface circuit to obtain serial data.

[0029] The miniaturized satellite navigation receiver described above also includes a power chip, which provides the necessary power to each component of the satellite navigation receiver and sends the input power of the external matching device to the power chip through a third electrical connector.

[0030] In the aforementioned miniaturized satellite navigation receiver, both the first mixer and the second mixer use the MAX2112 chip.

[0031] The miniaturized satellite navigation receivers described above are suitable for single GPS, single GLONASS, single BDII-B1, GPS+GLONASS combination, GPS+BDII-B1 combination, and GLONASS+BDII-B1 combination.

[0032] In the aforementioned miniaturized satellite navigation receiver, the first and second A / D converters are AD9218BST-65, each supporting two analog inputs and 10-bit quantization output.

[0033] In the aforementioned miniaturized satellite navigation receiver, the FPGA is a multi-channel FPGA.

[0034] In the aforementioned miniaturized satellite navigation receiver, the FLASH storage space is divided into L segments, which are used to store DSP and FPGA programs. The segmented address space is controlled by the DSP's general-purpose I / O, where L is a positive integer greater than or equal to 2.

[0035] In the aforementioned miniaturized satellite navigation receiver, the interface circuit includes four 5VTTL signal interfaces and one RS232 signal interface.

[0036] Compared with the prior art, the present invention has the following advantages:

[0037] (1) The satellite navigation receiver of the present invention adopts a highly integrated design method. It uses a single large-scale integrated circuit to realize the functions of GPS, GLONASS, and BDII-B1 multi-constellation combined satellite signal amplification, automatic gain control, mixing, and down-conversion. After A / D conversion, the FPGA performs broadband sampling and captures and demodulates GPS, GLONASS, and BDII-B1 multi-constellation satellite signals by mixing with local satellite signals. This large-scale integrated circuit replaces the independent amplifier, frequency synthesizer, quadrature demodulator, and three channels with a total of nine chips in the commonly used design method of satellite navigation receivers. It realizes the miniaturization design of satellite navigation receivers and has navigation and positioning capabilities of four frequency points of three systems: GPS, GLONASS, BDII-B1, and BDII-B3. The BDII-B3 signal has strong anti-interference capability and the FPGA design resources are large, which greatly improves the performance of satellite navigation receivers.

[0038] (2) The satellite navigation receiver of the present invention is suitable for the miniaturization design requirements of satellite receivers with single GPS, single GLONASS, single BDII-B1, GPS+GLONASS combination, GPS+BDII-B1 combination, GLONASS+BDII-B1 combination, and BDII-B3, and has a wide range of applications.

[0039] (3) The satellite navigation receiver of the present invention uses a highly integrated mixer chip MAX2112, which includes powerful functions such as amplification, automatic gain control, local oscillator, mixing, and A / D analog-to-digital conversion. Multiple functions can be completed with just a single chip. At the same time, the small chip size can improve the hardware density of the receiving device and realize the miniaturization of the satellite navigation receiver.

[0040] (4) The highly integrated mixer chip MAX2112 of this invention outputs analog signals, which are used in conjunction with the high-precision A / D analog-to-digital converter AD9218BST-65 for the transformation and processing of anti-interference satellite signals, thereby improving the hardware density of the anti-interference link.

[0041] (5) The FPGA of the satellite navigation receiver of the present invention can be implemented by multiple FPGAs as needed, realizing resource expansion. At the same time, multiple FPGAs can be designed as different processing algorithms as needed, which greatly enhances the processing capability of the device.

[0042] (6) The satellite navigation receiver of the present invention has a modular design for the DSP. The DSP includes a system control unit, a navigation processing unit and a channel processing unit. The three units work together to achieve the characteristics of tracking a large number of satellites, fast positioning speed, multiple positioning modes and high positioning accuracy. It can also perform hardware fault detection with a high detection rate.

[0043] (7) The power supply chip models used in the satellite navigation receiver of the present invention are MAX1951ESA, LTC3633 and LT1763, which improves the reliability of the device.

[0044] (8) The satellite navigation receiver of the present invention can resist 1 to 3 interferences within the BDII-B3 signal bandwidth, and the sum of the interference bandwidths is <10% of the navigation signal bandwidth of the narrowband interference, with an interference-to-signal ratio of 55dB.

[0045] (9) The interface circuit of the satellite navigation receiver of the present invention adopts the method of FPGA internal serial port protocol IP core plus interface circuit to realize RS422 and RS232 interfaces;

[0046] (10) The satellite navigation receiver of this invention simultaneously uses a 20MHz temperature-compensated crystal oscillator, CFPT-9007-EX-1B, as the system clock. A highly integrated temperature-compensated crystal oscillator is used as the system clock reference. An amplifier AD8061AR generates a low-jitter 20MHz system clock, one path of which is amplified to provide clock for two mixers, and another path to the clock generator AD9522 to provide a highly stable clock for the FPGA and A / D converter. The second crystal oscillator is model GZPB-26-40M-3.3V / -50, providing a 40MHz clock for the DSP. The DSP uses a 12x frequency multiplication, resulting in a main frequency of 480MHz, which improves the overall processing performance. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the satellite navigation receiver structure of the present invention;

[0048] Figure 2 This is a functional block diagram of the DSP in the satellite navigation receiver of the present invention;

[0049] Figure 3 This is a flowchart of the DSP implementation in the satellite navigation receiver of the present invention. Detailed Implementation

[0050] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0051] like Figure 1 The diagram shows the structural composition of the satellite navigation receiver of the present invention. The satellite navigation receiver of the present invention replaces the nine chips in the three channels of the commonly used satellite navigation receiver design, including the independent amplifier, frequency synthesizer, and quadrature demodulator, with a single large-scale integrated circuit. It realizes functions such as amplification, automatic gain control, mixing, and down-conversion of satellite signals from three constellations: GPS, GLONASS, and BD2 B1.

[0052] As shown in the figure, the satellite navigation receiver of the present invention includes a first filter, a second filter, a first mixer, a second mixer, a first A / D analog-to-digital converter, a second A / D analog-to-digital converter, a DSP, an FPGA, a first crystal oscillator, a second crystal oscillator, an amplifier, a clock generator, a FLASH, a watchdog timer, a DC / DC converter, an interface circuit, a first electrical connector, a second electrical connector, a third electrical connector, and a power supply chip.

[0053] The first electrical connector transmits satellite signals from three constellations—GPS, GLONASS, and BD2B1—received from the outside to the first filter; in this embodiment, the model is MCX-KHD1.

[0054] First filter: The satellite signal received from the first electrical connector is bandpass filtered and then sent to the first mixer. In this embodiment, the model is 1343A.

[0055] The first mixer receives the satellite signal from the first filter, amplifies, performs automatic gain control, mixes, and down-converts the satellite signal before outputting it to the first A / D converter. The first mixer performs a single-conversion to baseband for GPS, GLONASS, and BDII-B1 satellite signals. Compared to a two-conversion scheme, the three-conversion scheme has advantages such as fewer external components, higher integration, smaller size, and lower power consumption. In this embodiment, the model is MAX2112.

[0056] The first A / D converter: samples the analog intermediate frequency satellite signal received from the first mixer at clock 2 and converts it into a digital signal y(n1), and outputs it to the FPGA; in this embodiment, the model is AD9218BST-65.

[0057] The second electrical connector transmits the satellite signals received from the external BD2 B3 constellation to the second filter; in this embodiment, the model is MCX-KHD1.

[0058] The second filter: after bandpass filtering the satellite signal received from the second electrical connector, it is sent to the second mixer. In this embodiment, the model is TA0862A.

[0059] The second mixer receives the satellite signal from the second filter, amplifies, performs automatic gain control, mixes, and down-converts the satellite signal before outputting it to the second A / D converter. The second mixer performs a single-conversion to baseband on the BDII-B3 satellite signal. Compared to a two-conversion scheme, the three-conversion scheme has advantages such as fewer external components, higher integration, smaller size, and lower power consumption. In this embodiment, the model is MAX2112.

[0060] The second A / D converter: It samples the analog intermediate frequency satellite signal received from the second mixer at clock 2 and converts it into a digital signal y(n2), and outputs it to the FPGA; in this embodiment, the second A / D converter is model AD9218BST-65.

[0061] FPGA: Model EP4CGX150DF27I7N. The FPGA includes a frequency domain narrowband interference suppression unit, a capture and tracking unit, and a serial port core, among which:

[0062] Frequency domain anti-narrowband interference processing unit: Receives digital signals y(n1) from three constellations (GPS, GLONASS, and BD2B1) output from the first A / D converter, and performs correlation processing with the local GPS, GLONASS, and BD2B1 signals respectively to obtain the GPS digital signal g(n1), the GLONASS digital signal s(n1), and the BD2B1 digital signal b(n1); Receives the BD2B3 digital signal y(n2) output from the second A / D converter, and performs frequency domain anti-interference processing on the digital signal y(n2). Spectral leakage is improved by windowing the digital signal y(n2). The windowed signal is then transformed to the frequency domain via FFT processing. Interference is removed in the frequency domain by detecting the signal spectral intensity and setting a reasonable threshold to eliminate narrowband interference spectrum. Finally, the useful, interference-free BD2B3 signal z(n2) is recovered through IFFT transformation.

[0063] Acquisition and tracking unit: performs code acquisition and tracking on signals g(n1), s(n1), b(n1), and z(n2), respectively; implements carrier acquisition and tracking using a carrier-locked loop; performs bit synchronization, frame synchronization, data acquisition, and message demodulation to obtain raw observation data; and sends the raw observation data to the DSP for positioning calculation; at the same time, it receives the positioning data output by the DSP, performs timing conversion on the positioning data, and outputs it to the third electrical connector through the interface circuit.

[0064] Serial port kernel: Generates a second pulse and sends it to the interface circuit. It performs timing processing on the serial port data received and sent through the interface circuit to obtain serial data.

[0065] The specific working process of an FPGA is as follows:

[0066] (1) Add window

[0067] In practical applications, FFT processing of digital signals y(n2) can only be performed on a finite number of points, which will cause spectral leakage and reduce the signal-to-noise ratio. Windowing can effectively reduce spectral leakage. Commonly used window functions include Hamming window, Hanning window, and Blackman window. The Blackman window has the best suppression of spectral leakage and less data attenuation. Therefore, the Blackman window is used for windowing in this invention.

[0068] (2) FFT processing

[0069] FFT, or Fast Fourier Transform, transforms a signal from the time domain to the frequency domain. Considering both processing accuracy and hardware resources, this invention uses a 512-point FFT.

[0070] (3) Interference removal

[0071] By estimating the power of the input signal, an appropriate threshold is set. When the spectral line intensity is higher than the threshold, the spectral line is set to zero; conversely, when the spectral line intensity is lower than the threshold, the spectral line remains unchanged, thus eliminating interference and retaining the useful signal.

[0072] (4) IFFT processing

[0073] IFFT processing, or Inverse Fast Fourier Transform, transforms a signal from the frequency domain to the time domain. This invention uses a 512-point IFFT processing method.

[0074] (5) Code capture

[0075] The main search is conducted within two uncertain ranges: the code phase of the satellite pseudocode and the carrier Doppler. The system detects whether the signal energy exceeds the detection threshold. Once a signal is detected, the system locks on and enters the tracking state.

[0076] (6) Code tracking

[0077] A code delay-locked loop is used to track satellite pseudocode, and pseudorange observations are obtained by measuring the phase difference between the local pseudocode and the input pseudocode.

[0078] (7) Carrier acquisition

[0079] After the code acquisition system acquires the pseudo code and carrier component, the local carrier has not yet accurately tracked the carrier component of the satellite signal, resulting in a large Doppler frequency error, generally above several hundred hertz. In order to accurately acquire the carrier Doppler, AFC (Automatic Frequency Locking) and COSTAS combined loop processing are used, which not only reduces the frequency locking time but also reduces the phase locking time.

[0080] (8) Carrier tracking

[0081] The carrier Doppler error is already very small after being processed by the carrier acquisition module. To obtain higher accuracy, it then enters the carrier tracking module, which uses a narrowband digital phase-locked loop (DPLL).

[0082] (9) Bit synchronization

[0083] The initial phase of the satellite pseudocode is synchronized with the data conversion point. Taking GPS as an example, the bit synchronization process is to correctly determine which of the 20 C / A code initial phases coincides with a data bit at 50Hz. The energy of each of the 20 C / A code initial phases is determined by integrating and summing them, and the maximum energy is found to achieve bit synchronization.

[0084] (10) Frame synchronization

[0085] A sequence word with a distinctive identifier is identified from the satellite's navigation data stream to achieve subframe synchronization. Taking GPS as an example, this identifier is located in the first 8 bits of the telemetry word in the message subframe and is repeated every 6 seconds.

[0086] (11) Data Acquisition

[0087] This module reads pseudorange and pseudorange change rate information and outputs it to the navigation processing module.

[0088] (12) Message demodulation

[0089] The satellite signal data is demodulated and transmitted to the navigation processing module for processing parameters such as ephemeris and almanac.

[0090] In this embodiment of the invention, the FPGA uses an EP4CGX150DF27I7N, which provides loop design resources for 8 PLLs, 150,000 logic units, and 360 18-bit multipliers.

[0091] like Figure 2 The diagram shown is a functional block diagram of the DSP in the baseband processing device of this invention. This invention uses the DSP chip TMS32C6414EZLZA6E3 as the main program processor. The DSP includes a system control unit, a navigation processing unit, and a channel processing unit. The DSP uses a second crystal oscillator to output 40MHz at 12 times the frequency, and operates at 480MHz, enabling the DSP to run at high speed and improve the processing speed of the satellite navigation receiver.

[0092] The channel processing unit controls the FPGA's acquisition and tracking, outputting acquisition and tracking status information to the system control unit. Simultaneously, it reads raw observation data from the FPGA and sends it to the navigation processing unit. The navigation processing unit performs positioning calculations on the raw observation data to generate receiver position information, velocity information, pseudorange, pseudorange rate, satellite almanac, and time information, and outputs these information to the system control unit. The system control unit outputs the receiver position information, velocity information, pseudorange, pseudorange rate, and time information to the FPGA, and stores the satellite almanac, receiver position information, and time information in FLASH memory. Upon power-up, it initializes the first mixer, second mixer, DSP, FPGA, first A / D converter, second A / D converter, and interface circuitry; and receives control information from external matching devices through the FPGA.

[0093] The system control unit is the management center of the baseband processing device. It is responsible for the organic coordination and mutual invocation of various subtasks, connecting the various dispersed modules to jointly complete the system's various tasks. The system control unit consists of the following functional modules: main program module, initialization module, FLASH data read / write module, channel allocation module, and external interface module.

[0094] The initialization module includes the initialization of both hardware and software, enabling them to begin working together. Hardware initialization includes enabling the hardware interrupt timer, toggling the watchdog timer, initializing the FPGA, initializing the two mixers, and initializing the interface circuitry. Software initialization includes initializing global variables, the time system, the positioning mode and state, and the navigation model.

[0095] The FLASH data read / write module is responsible for writing the received satellite almanac, current receiver position information, and time information into the FLASH memory. When the baseband processing device resets or powers on again, it uses the saved, more accurate time, receiver position information, and satellite almanac to predict satellites, thereby accelerating the baseband processing device's satellite search and acquisition and shortening the user terminal's initial positioning time. It also includes upgrade functions for the DSP and FPGA programs.

[0096] The channel allocation module allocates satellites to parallel satellite tracking channels. This module performs the following functions: pre-setting satellite channels and setting the search frequency until a satellite is tracked; re-acquiring a satellite after it has lost lock; resetting idle channels to acquire satellites; and forcibly dropping certain satellites.

[0097] The main program module completes the organic coordination and mutual calling of each sub-module.

[0098] The external interface module outputs position information, velocity information, pseudorange, pseudorange rate, and time information to the FPGA, and receives matching device control information from the FPGA.

[0099] The navigation processing unit performs positioning calculations on the raw observation data to generate receiver position information, velocity information, pseudorange, pseudorange rate, satellite almanac, and time information, and outputs these information to the system control unit. The navigation processing unit consists of the following functional modules: message processing module, satellite prediction module, navigation calculation module, and RAIM monitoring module.

[0100] The main function of the message processing module is to demodulate information such as ephemeris and almanac from the original satellite navigation messages obtained from the FPGA for navigation calculations, and to save the almanac data to FLASH.

[0101] The satellite prediction module's functions include almanac prediction and ephemeris calculation. For navigation satellites, the message consists of two parts: ephemeris and almanac. Ephemeris contains precise satellite clock and orbital information, used for positioning calculations. Almanac is a collection of reduced-precision ephemeris data from all satellites, primarily used for satellite acquisition. Almanac prediction uses satellite ephemeris parameters to predict the satellite's position, velocity, elevation, azimuth, and Doppler parameters at a specific time, used for satellite acquisition. Ephemeris calculation uses satellite ephemeris parameters to calculate the satellite's position, velocity, time delay, clock error, and other information at a specific time, used for navigation calculations.

[0102] The navigation solution module is the main task of the DSP. It uses the satellite prediction module to obtain information such as the satellite's position, velocity, clock error, ionospheric and tropospheric corrections, pseudorange, and pseudorange change rate at the positioning time. It then establishes navigation solution equations and matrices and iteratively calculates navigation information such as the user's position, velocity, and time using the least squares method.

[0103] The RAIM monitoring module primarily detects faulty satellites and identifies which satellite is faulty. It employs the least squares method, using pseudorange residual vectors as the monitoring quantity to detect and determine the presence of faulty satellites. Its key features are: it's based on the assumption of a single satellite malfunctioning; that is, at the same sampling time, when one satellite malfunctions, there's a way to determine which satellite is faulty; however, when more than one satellite malfunctions simultaneously, it only provides the information that a faulty satellite is present, without specifying which satellites are faulty. The algorithm only uses current measurement data for detection and judgment, independent of historical data. The RAIM algorithm operates conditionally: for a single constellation, at least 5 satellites are required for RAIM monitoring to detect errors, and at least 6 satellites are required to remove a faulty satellite. For a dual-constellation RAIM monitoring system, at least 6 satellites are required for error detection, and at least 7 satellites are required to remove a faulty satellite.

[0104] The channel processing unit is driven by an interrupt handler, and its functions are implemented by the channel processing module. The channel processing module controls the FPGA to perform code acquisition and tracking, carrier acquisition and tracking, bit synchronization, frame synchronization, data acquisition, and message demodulation. It outputs pseudorange, pseudorange change rate, and raw message data to the navigation processing unit and outputs tracking status information to the system control unit. The module reads raw observation data from the FPGA for digital signal processing, including the highest priority task at 1kHz (carrier lock decision and carrier tracking); the second-highest priority task at 10Hz (measurement data reading module); and the lowest priority task at 1kHz (switching task), which performs code acquisition, code tracking, carrier lockout decision, carrier acquisition decision, bit synchronization, and data demodulation.

[0105] like Figure 3 The diagram shows the DSP implementation flowchart of the navigation receiver device of this invention. The software of this invention is embedded and runs in the DSP, coordinating with the hardware to receive and process radio frequency navigation satellite signals. After running, it first executes an initialization module, and then cycles through the message processing module, satellite prediction module, navigation calculation module, RAIM monitoring module, FLASH data read / write module, channel allocation module, external interface module, and channel processing module. These modules are called in the main program module, performing different processing for different needs and times. The internal time cycle control of the program uses the count value of the 100ms period sampling time generated by the FPGA. The receiver device continuously sends the current position, pseudorange, pseudorange rate, velocity, and time information to the matching device through the interface circuit.

[0106] The first crystal oscillator generates a high-stability clock and outputs it to the amplifier and clock generator; the second crystal oscillator generates clock 3 and sends it to the DSP. The first crystal oscillator is a temperature-compensated crystal oscillator, model 20MHz CFPT-9007-EX-1B, which generates a 20MHz clock for the system. One output is amplified by an AD8061AR amplifier to provide clock 1 for the two mixers, and the other output is generated by an AD9255 clock generator to provide clock 2 for the FPGA and A / D converter. The second crystal oscillator is model GZPB-26-40M-3.3V-50, which provides a 40MHz clock 3 for the DSP.

[0107] Amplifier: Receives the clock generated by the first crystal oscillator and outputs the amplified clock 1 to the first mixer and the second mixer;

[0108] Clock generator: Receives the clock generated by the first crystal oscillator, and sends the clock 2 obtained after frequency conversion to the FPGA, the first A / D analog-to-digital converter and the second A / D analog-to-digital converter respectively. The clock jitter generated by this clock generator is extremely small, which can improve the anti-interference capability of BDII B3.

[0109] FLASH: Stores the DSP and FPGA programs, as well as the satellite almanac, receiver position information, and time information stored in the DSP. This embodiment uses the 64Mbits storage space of the SST39VF6401B-70-4I-EKE, divided into four 16Mbit segments. The segmented address space is controlled by the DSP's general-purpose I / O, storing the DSP and FPGA programs in segments, and simultaneously storing the satellite almanac, position information, and time information stored in the DSP.

[0110] The watchdog timer, model MAX824SEUK+T, monitors program execution and provides a reset function for the DSP to prevent program crashes due to unforeseen circumstances.

[0111] Interface circuit: Receives information from the third electrical connector and outputs it to the FPGA. Simultaneously, it receives receiver position information, speed information, pseudorange, pseudorange rate, and time information from the FPGA and sends them to the third electrical connector. In this embodiment, the interface circuit includes four 5VTTL signal interface circuits and one RS232 signal interface circuit. The four 5VTTL signals include interface circuits for inertial navigation, integrated control unit, security control, and second pulse.

[0112] The third electrical connector is a rectangular interface connector. It outputs control information sent by the external matching device to the interface circuit, and sends the receiver position information, speed information, pseudorange, pseudorange rate, and time information output by the interface circuit to the external matching device. The rectangular interface connector communicates with the matching device, obtains +5V power from the matching device and supplies power to the power chip. The communication port sends the positioning results to the matching device via serial port; it receives instructions from the matching device and transmits them to the FPGA and DSP for control, and the communication port is also used for FPGA and DSP program upgrades.

[0113] The power supply chips used are MAX1951ESA, LTC36333, and LT1763, providing the necessary power to the various components of the satellite navigation receiver. Upon power-up, a +5V primary bus power supply is obtained via the third electrical connector. Four voltage converters (DC / DC converters) are used to generate the required secondary power supplies of +1.2V, +1.4V, +1.8V, +2.5V, and +3.3V to power the various devices. The DC / DC converters perform voltage conversion.

[0114] The navigation receiver of this invention uses surface acoustic wave (SAW) filters TA1343A and TA0862A, which are small in size and improve the hardware density of the receiver.

[0115] This invention realizes a miniaturized design method for satellite navigation receivers. It employs the high-density integrated mixer MAX2112, improving the hardware density of the receiver and reducing its size, thus achieving miniaturization. The receiver has the capability to simultaneously receive satellite signals from three systems (GPS, GLONASS, BDII-B1, and BDII-B3) at four frequencies for positioning and navigation. It utilizes frequency domain anti-narrowband interference processing technology to achieve anti-interference capability within the BDII-B3 frequency band, achieving an anti-interference signal-to-interference ratio of 55dB, demonstrating superior performance.

[0116] Of course, this miniaturized design method for the satellite navigation receiver is based on the first electrical connector inputting GPS+GLONASS+BDII B1 satellite signals and the second electrical connector inputting BDII B3 satellite signals. If the user requires that the satellite signals input to the electrical connector be one of the following: single GPS, single GLONASS, single BDII-B1, GPS+GLONASS combination, GPS+BDII-B1 combination, GLONASS+BDII-B1 combination, or BDII-B3, simply select the appropriate filter according to the frequency of the satellite signal. For example, the BDII B3 frequency point filter can use the SAW filter SBP5295, the GPS frequency point filter can use the SAW filter SBP5296, the GLONASS frequency point filter can use the SAW filter SBP5297, and the BDII B1 frequency point filter can use the SAW filter SBP5477.

[0117] The FPGA internally selects and processes the local signal corresponding to the satellite signal. This method of miniaturizing a satellite navigation receiver also falls within the scope of this invention.

[0118] The above description is only the best specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the protection scope of the present invention.

[0119] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A miniaturized satellite navigation receiver, characterized in that: Includes a first filter, a second filter, a first mixer, a second mixer, a first A / D converter, a second A / D converter, a DSP, an FPGA, a first crystal oscillator, a second crystal oscillator, an amplifier, a clock generator, a FLASH memory, a watchdog timer, interface circuitry, a first electrical connector, a second electrical connector, and a third electrical connector, wherein: The first electrical connector transmits satellite signals from three constellations—GPS, GLONASS, and BD2B1—received from the outside to the first filter. First filter: Bandpass-filters the satellite signal received from the first electrical connector and sends it to the first mixer; First mixer: Receives the satellite signal from the first filter, amplifies, performs automatic gain control, mixes and down-converts the satellite signal, and outputs it to the first A / D analog-to-digital converter; The first A / D converter converts the analog intermediate frequency satellite signal received from the first mixer into a digital signal y(n1) and outputs it to the FPGA. Second electrical connector: transmits satellite signals received from the external BD2 B3 constellation to the second filter; Second filter: Bandpass-filters the satellite signal received from the second electrical connector and sends it to the second mixer; Second mixer: Receives the satellite signal from the second filter, amplifies, performs automatic gain control, mixes and down-converts the satellite signal, and outputs it to the second A / D analog-to-digital converter; The second A / D converter converts the analog intermediate frequency satellite signal received from the second mixer into a digital signal y(n2) and outputs it to the FPGA. The FPGA receives digital signals y(n1) from three constellations (GPS, GLONASS, and BD2B1) output from the first A / D converter, and performs correlation processing with the local GPS, GLONASS, and BD2B1 signals to obtain the GPS digital signal g(n1), the GLONASS digital signal s(n1), and the BD2B1 digital signal b(n1). It also receives the BD2B3 digital signal y(n2) output from the second A / D converter, performs frequency domain anti-narrowband interference processing on y(n2) to obtain the interference-free BD2B3 signal z(n2). Subsequently, it performs code acquisition and tracking, carrier acquisition and tracking, bit synchronization, frame synchronization, data acquisition, and message demodulation on signals g(n1), s(n1), b(n1), and z(n2) to obtain raw observation data, which is then output to the DSP. Simultaneously, it receives positioning data output from the DSP, performs timing conversion on the positioning data, and outputs it to the third electrical connector via an interface circuit. The DSP includes a system control unit, a navigation processing unit, and a channel processing unit. The channel processing unit controls the FPGA's acquisition and tracking, outputs acquisition and tracking status information to the system control unit, and reads raw observation data from the FPGA, sending it to the navigation processing unit. The navigation processing unit performs positioning calculations on the raw observation data to generate receiver position information, velocity information, pseudorange, pseudorange rate, satellite almanac, and time information, and outputs these information to the system control unit. The system control unit outputs the receiver position information, velocity information, pseudorange, pseudorange rate, and time information to the FPGA, stores the satellite almanac, receiver position information, and time information in FLASH memory, and initializes the first mixer, second mixer, DSP, FPGA, first A / D converter, second A / D converter, and interface circuits upon power-up. It also receives control information from external matching devices through the FPGA. First crystal oscillator: generates clock and outputs it to amplifier and clock generator; Amplifier: Receives the clock generated by the first crystal oscillator and outputs the amplified clock 1 to the first mixer and the second mixer; Clock generator: Receives the clock generated by the first crystal oscillator, and sends the clock 2 obtained after frequency conversion to the FPGA, the first A / D analog-to-digital converter and the second A / D analog-to-digital converter respectively; Second crystal oscillator: generates clock 3 and sends it to the DSP; FLASH: Stores the DSP program and FPGA program, and also saves the satellite almanac, receiver position information and time information stored in the DSP; Watchdog: Monitors program execution and provides a reset function for the DSP to prevent program crashes due to unexpected reasons; Interface circuit: Receives information from the third electrical connector and outputs it to the FPGA. At the same time, it receives receiver position information, speed information, pseudorange, pseudorange rate and time information from the FPGA and sends them to the third electrical connector. The third electrical connector outputs control information sent by the external matching device to the interface circuit, and sends the receiver position information, speed information, pseudorange, pseudorange rate and time information output by the interface circuit to the external matching device.

2. A miniaturized satellite navigation receiver according to claim 1, characterized in that: The FPGA includes a frequency domain anti-narrowband interference processing unit, a capture and tracking unit, and a serial port core, wherein: Frequency domain anti-narrowband interference processing unit: Receives digital signals y(n1) from three constellations (GPS, GLONASS, and BD2B1) output from the first A / D converter, and performs correlation processing with the local GPS, GLONASS, and BD2B1 signals respectively to obtain the GPS digital signal g(n1), the GLONASS digital signal s(n1), and the BD2B1 digital signal b(n1); Receives the BD2B3 digital signal y(n2) output from the second A / D converter, and performs frequency domain anti-narrowband interference processing on the digital signal y(n2) to obtain the interference-free BD2B3 signal z(n2); Acquisition and tracking unit: performs code acquisition and tracking, carrier acquisition and tracking, bit synchronization, frame synchronization, data acquisition and message demodulation on signals g(n1), s(n1), b(n1), and z(n2) respectively to obtain raw observation data, and sends the raw observation data to the DSP; at the same time, it receives the positioning data output by the DSP, and outputs the positioning data to the third electrical connector through the interface circuit after timing conversion. Serial port kernel: Generates a second pulse and sends it to the interface circuit. It performs timing processing on the serial port data received and sent through the interface circuit to obtain serial data.

3. A miniaturized satellite navigation receiver according to claim 1, characterized in that: It also includes a power chip, which provides the necessary power to the various components of the satellite navigation receiver and sends the input power of the external matching device to the power chip through a third electrical connector.

4. A miniaturized satellite navigation receiver according to claim 1, characterized in that: The first mixer and the second mixer both use the MAX2112 chip.

5. A miniaturized satellite navigation receiver according to claim 1, characterized in that: It is applicable to single GPS, single GLONASS, single BDII-B1, GPS+GLONASS combination, GPS+BDII-B1 combination, and GLONASS+BDII-B1 combination.

6. A miniaturized satellite navigation receiver according to claim 1, characterized in that: The first and second A / D converters are AD9218BST-65, each supporting 2 analog inputs and 10-bit quantization output.

7. A miniaturized satellite navigation receiver according to claim 1, characterized in that: The FPGA is a multi-channel FPGA.

8. A miniaturized satellite navigation receiver according to claim 1, characterized in that: The FLASH storage space is divided into L segments, which are used to store DSP and FPGA programs. The segmented address space is controlled by the DSP general-purpose I / O, where L is a positive integer greater than or equal to 2.

9. A miniaturized satellite navigation receiver according to claim 1, characterized in that: The interface circuit includes four 5V TTL signal interfaces and one RS232 signal interface.

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