interposer

Abstract

The invention solves the problem of improving the joining reliability. The interposer (1) comprises a dielectric substrate (2), a feedthrough conductor (3), a pad electrode (4), and a protective layer (5). The feedthrough conductor (3) penetrates the dielectric substrate (2). The pad electrode (4) is arranged across a first main face (21) of the dielectric substrate (2) and the feedthrough conductor (3). The pad electrode (4) is connected to the feedthrough conductor (3). The protective layer (5) is provided on the first main face (21) of the dielectric substrate (2). The pad electrode (4) comprises a first portion (41) provided in contact with the first main face (21) of the dielectric substrate (2) and a second portion (42) superposed on the first portion (41). An outer edge of the first portion (41) of the pad electrode (4) is located inside an outer edge of the second portion (42) of the pad electrode (4). A portion of the protective layer (5) is interposed between the first main face (21) of the dielectric substrate (2) and the second portion (42) of the pad electrode (4).

Description

Technical Field

[0001] This disclosure generally relates to interposers, and more particularly to interposers comprising dielectric substrates. Background Technology

[0002] In related technologies, wiring boards to which electronic components such as semiconductor chips are bonded are known to be interposers (e.g., see Patent Document 1).

[0003] Sometimes an intermediary layer is needed to improve the reliability of the connection. Existing technical documents Patent documents

[0004] Patent Document 1: Japanese Patent Application Publication No. 2012-94734 Summary of the Invention

[0005] The purpose of this disclosure is to provide an intermediary layer that can help improve the reliability of its own bonding.

[0006] An interposer according to one aspect of this disclosure includes a dielectric substrate, a feed conductor, a pad electrode, and a protective layer. The dielectric substrate has a first main surface and a second main surface opposite to the first main surface. The feed conductor extends through the dielectric substrate. The pad electrode is arranged across the first main surface of the dielectric substrate and the feed conductor. The pad electrode is connected to the feed conductor. The protective layer is disposed on the first main surface of the dielectric substrate. The pad electrode includes: a first portion disposed in contact with the first main surface of the dielectric substrate; and a second portion stacked on the first portion. The outer edge of the first portion of the pad electrode is located inside the outer edge of the second portion of the pad electrode. A portion of the protective layer is located between the first main surface of the dielectric substrate and the second portion of the pad electrode. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view of the interposer layer according to the first embodiment; Figure 2 A and Figure 2 B is a cross-sectional view illustrating the various steps in a method for manufacturing an intermediate layer; Figure 3 A and Figure 3 B is a cross-sectional view illustrating the various steps in a method for manufacturing an intermediate layer; Figure 4 A and Figure 4 B is a cross-sectional view illustrating the various steps in a method for manufacturing an intermediate layer; Figure 5 A and Figure 5B is a cross-sectional view illustrating the various steps in a method for manufacturing an intermediate layer; Figure 6 A and Figure 6 B is a cross-sectional view illustrating the various steps in a method for manufacturing an intermediate layer; Figure 7 A and Figure 7 B is a cross-sectional view illustrating the various steps in a method for manufacturing an intermediate layer; Figure 8 A and Figure 8 B is a cross-sectional view illustrating the various steps in a method for manufacturing an intermediate layer; Figure 9 A and Figure 9 B is a cross-sectional view illustrating the various steps in a method for manufacturing an intermediate layer; Figure 10 This is a cross-sectional view of the interposer layer according to the second embodiment; Figure 11 This is a cross-sectional view of the interposer layer according to the third embodiment; Figure 12 It is a cross-sectional view of an electronic component module according to a fourth embodiment, including an intermediary layer according to a first embodiment; and Figure 13 A and Figure 13 B is a cross-sectional view illustrating the various steps in a method for manufacturing an electronic component module. Detailed Implementation

[0008] The first to fourth embodiments and their variations will be described with reference to the accompanying drawings. Note that all the drawings to be referenced in the following description of the first to fourth embodiments and their variations are schematic diagrams. Therefore, the ratios of the dimensions (including thickness) of the various constituent elements illustrated in the drawings, as well as the ratios of the dimensions (including thickness) between these constituent elements, do not always reflect their actual size ratios.

[0009] (First Embodiment) (1) Intermediary layer like Figure 1As shown, the interposer 1 according to the first embodiment includes a dielectric substrate 2, a plurality of feed conductors 3, a plurality of pad electrodes 4, and a protective layer 5. The dielectric substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. The plurality of feed conductors 3 penetrate the dielectric substrate 2. The plurality of pad electrodes 4 are arranged across the first main surface 21 of the dielectric substrate 2 and the feed conductors 3. The plurality of pad electrodes 4 are respectively connected to the plurality of feed conductors 3. The protective layer 5 is disposed on the first main surface 21 of the dielectric substrate 2. Each of the plurality of pad electrodes 4 includes: a first portion 41 which is disposed in contact with the first main surface 21 of the dielectric substrate 2; and a second portion 42 which is stacked on the first portion 41. When viewed in a plan view relative to the thickness direction D1 defined by the dielectric substrate 2, the outer edge of the first portion 41 of each of the plurality of pad electrodes 4 is located inside the outer edge of the second portion 42 of the pad electrode 4. In the interposer 1, a portion of the protective layer 5 is located between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of each of the plurality of pad electrodes 4.

[0010] The intermediary layer 1 according to the first embodiment can help improve the reliability of the bonding.

[0011] Furthermore, the interposer layer 1 according to the first embodiment also includes a plurality of wiring conductors 6 and a plurality of second pad electrodes 7 disposed separately from the plurality of pad electrodes 4 (hereinafter referred to as "first pad electrodes 4"). The plurality of second pad electrodes 7 are disposed one-to-one with the plurality of feed conductors 3 and one-to-one with the plurality of first pad electrodes 4. Each of the plurality of second pad electrodes 7 is connected to a corresponding feed conductor among the plurality of feed conductors 3. In addition, each of the plurality of second pad electrodes 7 is also connected to a corresponding first pad electrode among the plurality of first pad electrodes 4 via its corresponding feed conductor 3.

[0012] According to the first embodiment, the interposer 1 is, for example, located between a semiconductor chip and a system-in-package (SiP) board. Examples of semiconductor chips include processors, logic integrated circuits (ICs), and memories (such as high-bandwidth memory (HBM)).

[0013] (2) The constituent elements of the intermediate layer Next, we will refer to Figure 1 The constituent elements of the intermediary layer 1 according to the first embodiment are described.

[0014] The dielectric substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. When viewed in a plan view relative to the thickness direction D1 defined by the dielectric substrate 2, the outer edge of the dielectric substrate 2 forms a rectangular shape. However, this is merely an example and should not be construed as limiting. Alternatively, the outer edge of the dielectric substrate 2 may also form a non-rectangular shape.

[0015] The dielectric substrate 2 includes a first dielectric layer 201 and a second dielectric layer 202. The first dielectric layer 201 is stacked on the second dielectric layer 202. The first dielectric layer 201 has a first main surface 211 and a second main surface 212 opposite to the first main surface 211. The second dielectric layer 202 has a first main surface 221 and a second main surface 222 opposite to the first main surface 221. In the dielectric substrate 2, the second main surface 212 of the first dielectric layer 201 is in contact with the first main surface 221 of the second dielectric layer 202. The first main surface 21 of the dielectric substrate 2 is defined by the first main surface 211 of the first dielectric layer 201. The second main surface 22 of the dielectric substrate 2 is defined by the second main surface 222 of the second dielectric layer 202.

[0016] The first main surface 21 of the dielectric substrate 2 has an uneven shape on its entire first main surface 21. In other words, the first main surface 21 of the dielectric substrate 2 is a rough surface.

[0017] The material used for the first dielectric layer 201 includes organic materials. More specifically, the material used for the first dielectric layer 201 includes imide resins (such as polyimide or bismaleimide) or fluoropolymers (such as polytetrafluoroethylene) as its main components. From the viewpoint of improving the radio frequency characteristics of the interposer 1, the material used for the first dielectric layer 201 preferably has a low dielectric constant and a low dielectric loss tangent. As used herein, "improving radio frequency characteristics" means reducing the transmission loss of the signal being transmitted through the feed conductor 3.

[0018] The material used for the second dielectric layer 202 includes organic materials. More specifically, the material used for the second dielectric layer 202 includes imide resins (such as polyimide or bismaleimide), fluoropolymers (such as polytetrafluoroethylene), or epoxy resins as their main components. The material used for the second dielectric layer 202 may be the same as or different from the material used for the first dielectric layer 201, either way is appropriate.

[0019] Each of the plurality of feed conductors 3 includes, for example, a first pass conductor 31, a connecting electrode 32, and a second pass conductor 33. The first pass conductor 31 includes a first portion 311 seamlessly connected to a first portion 41 of the first pad electrode 4, and a second portion 312 seamlessly connected to a second portion 42 of the first pad electrode 4. In each feed conductor 3, the first pass conductor 31, the connecting electrode 32, and the second pass conductor 33 are sequentially arranged from the first main surface 21 of the dielectric substrate 2. In each feed conductor 3, the first pass conductor 31 and the connecting electrode 32 are directly connected to each other, the connecting electrode 32 and the second pass conductor 33 are directly connected to each other, and the first pass conductor 31, the connecting electrode 32, and the second pass conductor 33 are electrically connected to each other. In each feed conductor 3, the first pass conductor 31 penetrates the first dielectric layer 201. Furthermore, in each feed conductor 3, the connecting electrode 32 and the second pass conductor 33 are embedded in the second dielectric layer 202. The plurality of connecting electrodes 32 are embedded in the second dielectric layer 202 and exposed from the first main surface 221 of the second dielectric layer 202. Each of the multiple connecting electrodes 32 has its main surface 321 covered by a portion of the first dielectric layer 201 and the first pass conductor 31.

[0020] When viewed in a plan view along the thickness direction D1 defined relative to the dielectric substrate 2, each of the plurality of first path conductors 31 has a circular outer edge shape. Each of the plurality of first path conductors 31 also has a frustum-shaped cone. The outer diameter of each of the plurality of first path conductors 31 gradually decreases from the first pad electrode 4 toward the connecting electrode 32 along the thickness direction D1 defined relative to the dielectric substrate 2. At the interface between the first path conductors 31 and the connecting electrode 32, the outer diameter of the first path conductors 31 is smaller than the outer diameter of the connecting electrode 32.

[0021] When viewed in a plan view relative to the thickness direction D1 defined relative to the dielectric substrate 2, each of the plurality of connecting electrodes 32 has a circular outer edge shape. Each of the plurality of connecting electrodes 32 has a frustum-shaped cone. The outer diameter of each of the plurality of connecting electrodes 32 gradually decreases from the first pass conductor 31 in the thickness direction D1 defined relative to the dielectric substrate 2.

[0022] When viewed in a plan view relative to the thickness direction D1 defined relative to the dielectric substrate 2, each of the plurality of second-path conductors 33 has a circular outer edge shape. Each of the plurality of second-path conductors 33 also has a frustum-shaped cone. The outer diameter of each of the plurality of second-path conductors 33 gradually decreases from the second pad electrode 7 toward the connecting electrode 32 along the thickness direction D1 defined relative to the dielectric substrate 2. At the interface between the second-path conductors 33 and the connecting electrode 32, the outer diameter of the second-path conductors 33 is smaller than the outer diameter of the connecting electrode 32.

[0023] The materials used for each of the multiple feed conductors 3 include, for example, copper. The materials used for each of the multiple feed conductors 3 need not be copper, but may be, for example, copper alloys, aluminum or titanium.

[0024] Each of the plurality of first pad electrodes 4 is arranged to span a corresponding feed conductor in the plurality of feed conductors 3 and a first main surface 21 of the dielectric substrate 2. More specifically, each of the plurality of first pad electrodes 4 is configured to cover a portion of a first pass conductor 31 of a corresponding feed conductor in the plurality of feed conductors 3 and a portion of the first main surface 21 of the dielectric substrate 2.

[0025] When viewed in a plan view along the thickness direction D1 defined relative to the dielectric substrate 2, each of the plurality of first pad electrodes 4 has a circular shape. When viewed in a plan view along the thickness direction D1 defined relative to the dielectric substrate 2, each of the plurality of first pad electrodes 4 is larger than either the feed conductor 3 or the second pad electrode 7. When viewed in a plan view along the thickness direction D1 defined relative to the dielectric substrate 2, the outer edge 402 of each of the plurality of first pad electrodes 4 surrounds the outer edge of the first pass conductor 31 connected to the first pad electrode 4. Furthermore, when viewed in a plan view along the thickness direction D1 defined relative to the dielectric substrate 2, the outer edge 402 of each of the plurality of first pad electrodes 4 surrounds the outer edge 322 of the connecting electrode 32 overlapping with the first pad electrode 4. Furthermore, when viewed in a plan view along the thickness direction D1 defined relative to the dielectric substrate 2, the outer edge 402 of each of the plurality of first pad electrodes 4 surrounds the outer edge 702 of the second pad electrode 7 overlapping with the first pad electrode 4. The plurality of first pad electrodes 4 protrude from the first main surface 21 of the dielectric substrate 2. Each of the plurality of first pad electrodes 4 has a main surface 401 facing away from the dielectric substrate 2. In each of the plurality of first pad electrodes 4, the second portion 42 has an outer peripheral surface 421 connected to the main surface 401 of the first pad electrode 4.

[0026] The materials used for each of the plurality of first pad electrodes 4 include, for example, copper. The materials used for each of the plurality of first pad electrodes 4 need not be copper, but may be, for example, copper alloys, aluminum or titanium.

[0027] Each of the plurality of first pad electrodes 4 may, for example, but need not have, a thickness of 10 μm. In this case, the thickness of each of the plurality of first pad electrodes 4 is the thickness of the portion of the portion that contacts the first main surface 21 of the dielectric substrate 2.

[0028] Each of the plurality of first pad electrodes 4 includes: a first portion 41 that contacts a first main surface 21 of the dielectric substrate 2; and a second portion 42 that is stacked on the first portion 41. When viewed in a plan view relative to the thickness direction D1 defined relative to the dielectric substrate 2, the first portion 41 of each of the plurality of first pad electrodes 4 has a circular shape, and the second portion 42 of each of the plurality of first pad electrodes 4 also has a circular shape. In each of the plurality of first pad electrodes 4, when viewed in a plane relative to the thickness direction D1 defined relative to the dielectric substrate 2, the outer edge of the first portion 41 is located inside the outer edge of the second portion 42. In each of the plurality of first pad electrodes 4, a step exists between the outer peripheral surface 411 of the first portion 41 and the outer peripheral surface 421 of the second portion 42.

[0029] Each of the plurality of second pad electrodes 7 is arranged to span a corresponding feed conductor in one of the plurality of feed conductors 3 and a second main surface 22 of the dielectric substrate 2. More specifically, each of the plurality of second pad electrodes 7 is configured to cover a second path conductor 33 of a corresponding feed conductor in one of the plurality of feed conductors 3 and a portion of the second main surface 22 of the dielectric substrate 2.

[0030] When viewed in a plan view along the thickness direction D1 defined relative to the dielectric substrate 2, each of the plurality of second pad electrodes 7 has a circular shape. When viewed in a plan view along the thickness direction D1 defined relative to the dielectric substrate 2, each of the plurality of second pad electrodes 7 is smaller than any of the first pad electrodes 4. When viewed in a plan view along the thickness direction D1 defined relative to the dielectric substrate 2, the outer edge 702 of each of the plurality of second pad electrodes 7 surrounds the outer edge of the second via conductor 33 connected to the second pad electrode 7. When viewed in a plan view along the thickness direction D1 defined relative to the dielectric substrate 2, the outer edge 702 of each of the plurality of second pad electrodes 7 is surrounded within the outer edge 322 of the connecting electrode 32 connected to the second pad electrode 7. Furthermore, when viewed in a plan view along the thickness direction D1 defined relative to the dielectric substrate 2, the outer edge 702 of each of the plurality of second pad electrodes 7 is surrounded within the outer edge 402 of the first pad electrode 4 connected to the second pad electrode 7. The plurality of second pad electrodes 7 protrude from the second main surface 22 of the dielectric substrate 2. Each of the plurality of second pad electrodes 7 has a main surface 701 facing away from the dielectric substrate 2.

[0031] The materials used for each of the plurality of second pad electrodes 7 include, for example, copper. The materials used for each of the plurality of second pad electrodes 7 need not be copper, but may be, for example, copper alloys, aluminum or titanium.

[0032] Each of the plurality of second pad electrodes 7 may, for example, but need not have, a thickness of 5 μm. In this case, the thickness of each of the plurality of second pad electrodes 7 is the thickness of the portion of the portion that contacts the second main surface 22 of the dielectric substrate 2.

[0033] The protective layer 5 is directly stacked on and covers the first main surface 21 of the dielectric substrate 2. The protective layer 5 is a passivation layer. The protective layer 5 includes: a first portion 501 that does not overlap with any of the plurality of pad electrodes 4; and a plurality of second portions 502 that are located between the first main surface 21 of the dielectric substrate 2 and the respective second portions 42 of the plurality of pad electrodes 4.

[0034] The materials used for the protective layer 5 include organic materials. More specifically, the materials used for the protective layer 5 include, for example, imide resins (such as polyimide or bismaleimide) or fluoropolymers (such as polytetrafluoroethylene) as their main components. From the viewpoint of improving the radio frequency characteristics of the interposer 1, the materials used for the protective layer 5 preferably have a low dielectric constant and a low dielectric loss tangent.

[0035] The thickness of the protective layer 5 is greater than the distance between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of each of the plurality of first pad electrodes 4, and less than the thickness of the first pad electrodes 4. The protective layer 5 partially covers the outer peripheral surface 421 of the second portion 42 of the first pad electrodes 4, but does not reach the main surface 401 of the first pad electrodes 4. In this embodiment, the distance between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of each of the plurality of first pad electrodes 4 is, for example, 100 nm, and the thickness of the pad electrodes 4 is, for example, 10 μm. In this case, the thickness of the protective layer 5 is preferably equal to or greater than 100 nm and less than 10 μm.

[0036] In this embodiment, the surface roughness of the main surface 51 of the protective layer 5 is less than the surface roughness of the first main surface 21 of the dielectric substrate 2. The surface roughness of the main surface 51 of the protective layer 5 is the surface roughness of the first portion 501 of the protective layer 5. As used herein, "surface roughness" refers to the arithmetic mean roughness Ra. The arithmetic mean roughness Ra is defined, for example, by JIS B 0601-2001 (ISO 4287-1997). As used herein, the arithmetic mean roughness Ra is a value measured based on a cross-sectional scanning electron microscope (SEM) image.

[0037] From the viewpoint that the surface roughness of the main surface 51 of the protective layer 5 is less than the surface roughness of the first main surface 21 of the dielectric substrate 2, the thickness of the protective layer 5 is more preferably equal to or greater than 500 nm and less than 10 μm. Furthermore, from the viewpoint that the protective layer 5 does not reach the main surface 401 of any of the plurality of first pad electrodes 4, the thickness of the protective layer 5 is more preferably equal to or less than 8 μm (i.e., equal to or less than 80% of the thickness of the first pad electrode 4).

[0038] Multiple wiring conductors 6 are embedded in the dielectric substrate 2. More specifically, the multiple wiring conductors 6 are embedded in the second dielectric layer 202, exposed from the first main surface 221 of the second dielectric layer 202, and covered by the first dielectric layer 201. The multiple wiring conductors 6 are connected to at least one of the multiple connection electrodes 32. Each of the multiple wiring conductors 6 is the same thickness as any of the multiple connection electrodes 32.

[0039] (3) Methods for manufacturing intermediate layers Reference Figure 2 A to Figure 9 B describes a method for manufacturing an intermediary layer 1 according to the first embodiment.

[0040] According to the method used to manufacture intermediate layer 1, in such Figure 2 As shown in Figure A, after the multilayer stack 10 with the second dielectric layer 202 stacked on the first carrier substrate 9 has been provided, the first process to the fifteenth process are performed sequentially.

[0041] In the first carrier substrate 9, a metal substrate 91, a metal foil 92 (hereinafter referred to as "first metal foil 92"), a peelable layer 93, and a second metal foil 94 are stacked sequentially, one on top of the other. The material used for the metal substrate 91 is stainless steel in this embodiment, but it can also be a material other than stainless steel. Furthermore, in this embodiment, the first metal foil 92 is a copper foil. The material used for the first metal foil 92 is copper in this embodiment, but it does not have to be copper. The material used for the second metal foil 94 is copper in this embodiment, but it does not have to be copper. The material used for the peelable layer 93 is acrylic resin in this embodiment, but it does not have to be acrylic resin, and it can also be silicone resin. The thickness of the second metal foil 94 is less than the thickness of the first metal foil 92. Alternatively, the first carrier substrate 9 may include an organic substrate, a silicon substrate, or a glass substrate instead of the metal substrate 91. Examples of organic substrates include liquid crystal polymer (LCP) substrates, polyethylene terephthalate (PET) substrates, and polytetrafluoroethylene (PTFE) substrates.

[0042] like Figure 2 As shown in B, the first process includes forming a plurality of connection electrodes 32 and a plurality of wiring conductors 6 in the second dielectric layer 202 of the multilayer stack 10.

[0043] like Figure 3As shown in Figure A, the second step includes forming a first dielectric layer 201 that covers a first main surface 221 of the second dielectric layer 202, a plurality of connection electrodes 32, and a plurality of wiring conductors 6. In the second step, the first dielectric layer 201 is formed by applying a solution containing an organic material for the first dielectric layer 201 onto the multilayer stack 10 using a coating machine (such as a spin coater) or a dispensing machine, followed by pre-baking the assembly. Alternatively, the second step may further include forming the first dielectric layer 201 by laminating a resin film to be used as the first dielectric layer 201 onto the multilayer stack 10.

[0044] like Figure 3 As shown in B, the third step includes: forming a plurality of first via holes 213 through the first dielectric layer 201 using laser processing and performing a decontamination treatment to make the first main surface 21 of the dielectric substrate 2 uneven, in which resin residue generated by laser processing is removed. In the third step, the plurality of first via holes 213 are formed in various regions of the dielectric substrate 2 where a plurality of first via conductors 31 are to be formed. The plurality of first via holes 213 are provided one-to-one for the plurality of first via conductors 31.

[0045] The method for manufacturing an interposer 1 according to this embodiment includes: forming a plurality of first via conductors 31 by performing a fourth to a sixth process, and forming a plurality of first pad electrodes 4 by performing a fourth to a seventh process.

[0046] like Figure 4 As shown in Figure A, the fourth step includes forming a seed layer 11 by, for example, electroless plating, to cover the first main surface 21 of the dielectric substrate 2, the inner peripheral surfaces of the plurality of first via holes 213, and the exposed portions of the main surfaces 321 of the plurality of connecting electrodes 32. The material used for the seed layer 11 is the same as the material used for the first portion 41 of each first pad electrode 4. The material used for the seed layer 11 can be copper but does not have to be copper, and can also be a copper alloy. The method of forming the seed layer 11 does not have to be electroless plating, but can also be sputtering.

[0047] like Figure 4 As shown in B, the fifth step includes forming a resist layer 13 with a predetermined pattern on the seed layer 11. The predetermined pattern of the resist layer 13 is a pattern that exposes the respective areas of the seed layer 11 where the plurality of first through conductors 31 and the plurality of first pad electrodes 4 will be formed.

[0048] like Figure 5As shown in A, the sixth step includes forming a plurality of first conductive paths 31 and a plurality of first pad electrodes 4. In the sixth step, the plurality of first conductive paths 31 and the plurality of first pad electrodes 4 are formed, for example, by electroplating, and then the resist layer 13 is stripped. In the sixth step, the material used for the plurality of plating layers 12 grown on the seed layer 11 is the same as the material used for the second portion 42 of the first pad electrodes 4. The material used for the plating layers 12 can be copper but does not have to be copper, and can also be a copper alloy.

[0049] like Figure 5 As shown in Figure B, the seventh step includes exposing the first main surface 21 of the dielectric substrate 2 by partially removing the seed layer 11. In the seventh step, the seed layer 11 is removed by wet etching. Figure 5 The portion exposed in state A. In the seventh step, a portion of the seed layer 11, which forms a portion of each of the plurality of first pad electrodes 4, is laterally etched, thereby forming a first portion 41 with a smaller outer diameter than the second portion 42 in each of the plurality of first pad electrodes 4. Therefore, in the seventh step, a gap 14 is left between the second portion 42 of each of the plurality of first pad electrodes 4 and the first main surface 21 of the dielectric substrate 2. In this embodiment, the material used for the plurality of plating layers 12 is the same as the material used for the seed layer 11. However, each plating layer 12 has been formed by electroplating, while the seed layer 11 has been formed by electroless plating. Therefore, the film quality of each plating layer 12 is different from the film quality of the seed layer 11. Therefore, when using an etchant for etching copper, the etching rate of the plating layer 12 is lower than the etching rate of the seed layer 11, thereby allowing selective etching of the seed layer 11 in a maskless state (i.e., in). Figure 5 The exposed portion (as shown in state A).

[0050] like Figure 6 As shown in A, the eighth step includes forming a protective layer 5 covering the first main surface 21 of the dielectric substrate 2. In the eighth step, the protective layer 5 is formed by applying a solution comprising an organic material for the protective layer 5 using a coating machine (such as a spin coater) and baking the assembly. From the viewpoint of forming the protective layer 5 to eliminate the gap 14 between the second portion 42 of the first pad electrode 4 and the first main surface 21 of the dielectric substrate 2, the solution comprising the organic material for the protective layer 5 preferably has a viscosity of less than 50 mPa·s.

[0051] like Figure 6 As shown in B, the ninth step includes forming a temporary adhesive layer 15 covering a plurality of first pad electrodes 4 and a protective layer 5. In the ninth step, a varnish comprising an organic material (such as acrylic resin) for the temporary adhesive layer 15 is applied and dried, thereby forming the temporary adhesive layer 15. The temporary adhesive layer 15 has, for example, a thickness of 20 μm. The thickness of the temporary adhesive layer 15 is the thickness of the portion in contact with the protective layer 5.

[0052] like Figure 7 As shown in A, the tenth step includes bonding a second carrier substrate 16 to a temporary adhesive layer 15. The second carrier substrate 16 includes, for example, a glass substrate 161 and a peelable layer 162 stacked on the glass substrate 161. In the tenth step, the peelable layer 162 of the second carrier substrate 16 is bonded to the temporary adhesive layer 15.

[0053] like Figure 7 As shown in B, the eleventh step includes removing the first carrier substrate 9 from the dielectric substrate 2. In the eleventh step, the structure of the first carrier substrate 9, including the metal substrate 91, the first metal foil 92 and the peelable layer 93, is peeled off from the second metal foil 94, and then the second metal foil 94 is etched away.

[0054] like Figure 8 As shown in A, the twelfth step includes forming a plurality of second vias 223 through the dielectric substrate 2. In the twelfth step, the plurality of second vias 223 are formed in various regions of the dielectric substrate 2 where a plurality of second via conductors 33 will be formed.

[0055] like Figure 8 As shown in B, the thirteenth step includes: forming a plurality of second path conductors 33 and a plurality of second pad electrodes 7.

[0056] like Figure 9 As shown in A, the fourteenth step includes: peeling the second carrier substrate 16 from the temporary adhesive layer 15.

[0057] like Figure 9 As shown in B, the fifteenth step includes obtaining the intermediate layer 1 by mechanically peeling off the temporary adhesive layer 15. Alternatively, in the fifteenth step, the temporary adhesive layer 15 can also be dry etched away instead of being mechanically peeled off.

[0058] In the method for manufacturing intermediate layer 1 according to the first embodiment, intermediate layer 1 is formed by performing the first step to the fifteenth step.

[0059] (4) Advantages In the interposer 1 according to the first embodiment, the pad electrode 4 includes: a first portion 41 disposed in contact with a first main surface 21 of the dielectric substrate 2; and a second portion 42 stacked on the first portion 41. The outer edge of the first portion 41 of the pad electrode 4 is located inside the outer edge of the second portion 42 of the pad electrode 4. In the interposer 1, a portion of the protective layer 5 is located between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of the pad electrode 4.

[0060] This configuration helps improve bonding reliability. More specifically, according to this configuration, a portion of the protective layer 5 is located between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of the pad electrode 4, thereby increasing impact resistance compared to the case where a gap 14 is left between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of the pad electrode 4. Therefore, this allows for bonding of the interposer 1 to a circuit board (such as a printed circuit board) including the pad electrode 4 connected to the land electrode with higher reliability.

[0061] Furthermore, in the interposer 1 according to the first embodiment, the thickness of the protective layer 5 is greater than the distance between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of the pad electrode 4, and less than the thickness of the pad electrode 4. The protective layer 5 partially covers the outer peripheral surface 421 of the second portion 42 of the pad electrode 4, but does not reach the main surface 401 of the pad electrode 4.

[0062] This configuration can further increase impact resistance and further improve joint reliability.

[0063] Furthermore, in the intermediate layer 1 according to the first embodiment, the material used for the protective layer 5 is an organic material.

[0064] This configuration, compared to the case where the material of the protective layer 5 is inorganic, results in a reduction in the dielectric constant and dielectric loss tangent of the protective layer 5. This allows for improved radio frequency characteristics of the interposer 1.

[0065] Furthermore, in the interposer 1 according to the first embodiment, the first main surface 21 of the dielectric substrate 2 has an uneven shape over the entire first main surface 21.

[0066] This configuration allows the protective layer 5 to adhere more tightly to the first main surface 21 of the dielectric substrate 2.

[0067] Furthermore, in the interposer 1 according to the first embodiment, the surface roughness of the main surface 51 of the protective layer 5 that is away from the first main surface 21 of the dielectric substrate 2 is less than the surface roughness of the first main surface 21 of the dielectric substrate 2.

[0068] This configuration makes it easier to remove the temporary adhesive layer 15 from the protective layer 5, for example, when using a manufacturing method that includes bonding the second carrier substrate 16 to the protective layer 5 via the temporary adhesive layer 15 as a method for manufacturing the intermediate layer 1.

[0069] (Second Embodiment) Reference Figure 10 The following description describes an intermediary layer 1A according to a second embodiment. In the following description, the intermediary layer 1A according to the second embodiment has the same characteristics as the intermediary layer 1 (refer to) according to the first embodiment. Figure 1Any constituent element having the same function as the corresponding part of the drawing will be designated by the same reference numerals as the corresponding part, and its description will be omitted herein.

[0070] (1) Configuration In the intermediate layer 1A according to the second embodiment, the plurality of feed conductors 3 of the intermediate layer 1 according to the first embodiment are each composed only of a first pass conductor 31, and the plurality of connecting electrodes 32 are used as a plurality of second pad electrodes 7A, which is different from the intermediate layer 1 according to the first embodiment.

[0071] In the intermediate layer 1A according to the second embodiment, a plurality of second pad electrodes 7A are connected one-to-one to a plurality of first pad electrodes 4.

[0072] (2) Methods for manufacturing intermediate layers Regarding the method for manufacturing intermediate layer 1A according to the second embodiment, descriptions of the same steps as those in the method for manufacturing intermediate layer 1 according to the first embodiment will be appropriately omitted herein.

[0073] In the method for manufacturing intermediate layer 1A according to the second embodiment, the intermediate layer 1A is obtained by performing the first to eleventh steps of the method for manufacturing intermediate layer 1 according to the first embodiment. Figure 7 The structure shown in B is then subjected to a chemical mechanical polishing (CMP) process on the second dielectric layer 202, thereby exposing multiple second pad electrodes 7A and multiple wiring conductors 6.

[0074] Subsequently, as in the fourteenth step of the method for manufacturing intermediate layer 1 according to the first embodiment, the second carrier substrate 16 is peeled off from the temporary adhesive layer 15, and then the temporary adhesive layer 15 is mechanically peeled off as in the fifteenth step of the method, thereby completing the intermediate layer 1A.

[0075] (3) Advantages Intermediate layer 1A according to the second embodiment, like intermediate layer 1 according to the first embodiment, can help improve bonding reliability.

[0076] (Third Embodiment) Reference Figure 11 The following description describes an intermediary layer 1B according to a third embodiment. In the following description, the intermediary layer 1B according to the third embodiment has the same characteristics as the intermediary layer 1 according to the first embodiment (refer to...). Figure 1 Any constituent element having the same function as the corresponding part of the drawing will be designated by the same reference numerals as the corresponding part, and its description will be omitted herein.

[0077] (1) Configuration The intermediate layer 1B according to the third embodiment includes a protective layer 5B instead of the protective layer 5 of the intermediate layer 1 according to the first embodiment, which is different from the intermediate layer 1 according to the first embodiment.

[0078] The protective layer 5B covers the first main surface 21 of the dielectric substrate 2, just like the protective layer 5. In the interposer 1B, a portion of the protective layer 5B is located between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of each pad electrode 4.

[0079] Additionally, in the interposer 1B, the protective layer 5B is arranged to span a first main surface 21 of the dielectric substrate 2, the outer peripheral surface 421 of the second portion 42 of each of the plurality of first pad electrodes 4, and a portion of the main surface 401 of each of the plurality of first pad electrodes 4. The protective layer 5B is a solder resist layer, but also functions as a passivation layer. The protective layer 5B includes: a first portion 511 that does not overlap with any of the plurality of pad electrodes 4; and a plurality of second portions 512 that are located between the first main surface 21 of the dielectric substrate 2 and the second portion 42 of each of the plurality of pad electrodes 4. The protective layer 5B has a plurality of openings 53B that each of the plurality of openings 53B partially exposes the main surface 401 of the corresponding first pad electrode among the plurality of first pad electrodes 4.

[0080] The opening width of each opening 53B of the protective layer 5B increases with the increase of the distance relative to the main surface 401 of the first pad electrode 4.

[0081] The surface roughness of the main surface 51B of the protective layer 5B that is away from the first main surface 21 of the dielectric substrate 2 is less than the surface roughness of the first main surface 21 of the dielectric substrate 2.

[0082] (2) Methods for manufacturing intermediate layers The method for manufacturing the intermediate layer 1B according to the third embodiment is substantially the same as the method for manufacturing the intermediate layer 1 according to the first embodiment, but includes forming a protective layer 5B instead of the protective layer 5, which is different from the method for manufacturing the intermediate layer 1 according to the first embodiment. In the following description of the method for manufacturing the intermediate layer 1B according to the third embodiment, descriptions of any steps corresponding to the corresponding parts of the method for manufacturing the intermediate layer 1 according to the first embodiment will be appropriately omitted herein.

[0083] The method for manufacturing intermediate layer 1B differs from the method for manufacturing intermediate layer 1 only in the eighth step out of the first to fifteenth steps.

[0084] In the method for manufacturing intermediate layer 1B, the intermediate layer 1B is obtained by performing the first to seventh steps of the method for manufacturing intermediate layer 1B. Figure 5The structure shown in B is then used to form a protective layer 5B in an eighth step. The eighth step includes forming multiple openings 53B through the protective layer 5B using photolithography. Specifically, in the eighth step, a solution containing an organic material for the protective layer 5B is applied using a coating machine (such as a spin coater) and pre-baked, and then the protective layer 5B with multiple openings 53B is formed using photolithography. A positive photoresist material is used as the organic material for the protective layer 5B.

[0085] According to the method for manufacturing intermediate layer 1B, after the eighth step has been performed, the same steps as the ninth to fifteenth steps of the method for manufacturing intermediate layer 1 are performed, thereby completing intermediate layer 1B according to the third embodiment.

[0086] (3) Advantages Intermediate layer 1B according to the third embodiment, like intermediate layer 1 according to the first embodiment, can also help improve bonding reliability.

[0087] (Fourth Embodiment) Reference Figure 12 The electronic component module 100 according to the fourth embodiment is described below. The electronic component module 100 according to the fourth embodiment includes an intermediary layer 1 according to the first embodiment (refer to...). Figure 1 ).

[0088] (1) Configuration The electronic component module 100 according to the fourth embodiment includes an intermediary layer 1, an IC chip 19 as an electronic component, and a resin layer 20.

[0089] IC chip 19 is bonded to interposer 1. More specifically, IC chip 19 is bonded to interposer 1 in a flip-chip manner. IC chip 19 includes a plurality of external connection electrodes (not shown), which are connected to a plurality of second pad electrodes 7 of interposer 1 via solder bumps 18.

[0090] A resin layer 20 is disposed on the second main surface 22 of the dielectric substrate 2 of the interposer 1 to cover the IC chip 19. The resin layer 20 may include, for example, a resin (such as epoxy resin). Optionally, the resin layer 20 may also include a filler.

[0091] (2) Methods for manufacturing electronic component modules The method for manufacturing electronic component module 100 is substantially the same as the method for manufacturing intermediate layer 1 according to the first embodiment, except that a component bonding step and a molding step are included between the thirteenth and fourteenth steps of the method for manufacturing intermediate layer 1 according to the first embodiment, which is different from the method for manufacturing intermediate layer 1 according to the first embodiment.

[0092] By performing the first to thirteenth steps of the method for manufacturing intermediate layer 1 according to the first embodiment, a result is obtained that... Figure 8 The structure shown in B is the same as the structure shown therein. Subsequently, as... Figure 13 As shown in Figure A, the component bonding process includes bonding the IC chip 19 as an electronic component to the interposer layer 1. In this embodiment, solder bumps 18 are formed on each of the plurality of second pad electrodes 7 via the barrier layer 17 prior to the component bonding process. However, it should be noted that forming the barrier layer 17 and the solder bumps 18 are not essential steps.

[0093] like Figure 13 As shown in Figure A, the molding process includes: forming a resin layer 20 on the second main surface 22 of the dielectric substrate 2 of the interposer 1 to cover the IC chip 19. As... Figure 13 As shown in B, the fourteenth step includes: peeling the second carrier substrate 16 from the temporary adhesive layer 15.

[0094] The fifteenth step includes removing the temporary adhesive layer 15, thereby completing the electronic component module 100 including the intermediary layer 1.

[0095] (3) Advantages The electronic component module 100 according to the fourth embodiment includes an intermediary layer 1, which effectively helps to improve the reliability of the connection.

[0096] (appendix) In the interposers 1, 1A and 1B, the organic material used as the material for the first dielectric layer 201 and the second dielectric layer 202 is an electrical insulator, and the first dielectric layer 201, the second dielectric layer 202 and the dielectric substrate 2 are respectively the first insulating layer, the second insulating layer and the insulating substrate.

[0097] (Modified Example) Note that the first to fourth embodiments and their variations described above are merely exemplary embodiments of various embodiments and variations of this disclosure and should not be construed as restrictive. Rather, the first to fourth embodiments and their variations can be readily modified in various ways, depending on design choices or any other factors, without departing from the scope of this disclosure.

[0098] For example, in the interposers 1, 1A, and 1B, the materials used for the first dielectric layer 201 and the second dielectric layer 202 do not necessarily have to be organic materials, but can be, for example, inorganic materials (such as ceramics). In the interposers 1, 1A, and 1B, if the materials used for the first dielectric layer 201 and the second dielectric layer 202 are inorganic materials, then the inorganic materials are electrical insulators, and the first dielectric layer 201, the second dielectric layer 202, and the dielectric substrate 2 are respectively the first insulating layer, the second insulating layer, and the insulating substrate.

[0099] Optionally, in the interposers 1, 1A and 1B, the dielectric substrate 2 may include one or more additional dielectric layers in addition to the first dielectric layer 201 and the second dielectric layer 202.

[0100] Furthermore, in intermediate layers 1 and 1A, the material used for protective layer 5 does not have to be an organic material, but can be, for example, an inorganic material.

[0101] Furthermore, although each of the interposers 1, 1A and 1B includes multiple feed conductors 3 and multiple pad electrodes 4, each of the interposers 1, 1A and 1B may have only one feed conductor 3 and only one pad electrode 4.

[0102] (in all aspects) The foregoing description provides specific implementations of the following aspects of this disclosure.

[0103] According to the first aspect, the interposer (1; 1A; 1B) includes a dielectric substrate (2), a feed conductor (3), a pad electrode (4), and a protective layer (5; 5B). The dielectric substrate (2) has a first main surface (21) and a second main surface (22) opposite to the first main surface (21). The feed conductor (3) penetrates the dielectric substrate (2). The pad electrode (4) is arranged across the first main surface (21) of the dielectric substrate (2) and the feed conductor (3). The pad electrode (4) is connected to the feed conductor (3). The protective layer (5; 5B) is disposed on the first main surface (21) of the dielectric substrate (2). The pad electrode (4) includes: a first portion (41) disposed in contact with the first main surface (21) of the dielectric substrate (2); and a second portion (42) superimposed on the first portion (41). The outer edge of the first portion (41) of the pad electrode (4) is located inside the outer edge of the second portion (42) of the pad electrode (4). A portion of the protective layer (5; 5B) is located between the first main surface (21) of the dielectric substrate (2) and the second portion (42) of the pad electrode (4).

[0104] This aspect can help improve the reliability of the joint.

[0105] In the interposer layer (1; 1A) according to the second aspect, which can be implemented in conjunction with the first aspect, the thickness of the protective layer (5; 5B) is greater than the distance between the first main surface (21) of the dielectric substrate (2) and the second portion (42) of the pad electrode (4) and less than the thickness of the pad electrode (4). The protective layer (5; 5B) partially covers the outer peripheral surface (421) of the second portion (42) of the pad electrode (4), but does not reach the main surface (401) of the pad electrode (4).

[0106] This aspect can further increase impact resistance and further improve joint reliability.

[0107] In the intermediate layer (1; 1A) according to the third aspect, which can be implemented in conjunction with the first aspect or the second aspect, the material used for the protective layer (5) is an organic material.

[0108] This aspect can help improve radio frequency characteristics.

[0109] In the interlayer (1; 1A) according to the fourth aspect, which can be implemented in combination with any of the first to third aspects, the first main surface (21) of the dielectric substrate (2) has an uneven shape over the entire first main surface (21).

[0110] This aspect enables the protective layer (5) to adhere more tightly to the first main surface (21) of the dielectric substrate (2).

[0111] In the interposer layer (1; 1A) according to the fifth aspect, which can be implemented in conjunction with the fourth aspect, the surface roughness of the main surface (51) of the protective layer (5) facing away from the first main surface (21) of the dielectric substrate (2) is less than the surface roughness of the first main surface (21) of the dielectric substrate (2).

[0112] This aspect makes it easier to remove the temporary adhesive layer (15) from the protective layer (5) when using a manufacturing process that includes bonding the second carrier substrate (16) to the protective layer (5) via a temporary adhesive layer (15).

[0113] In the interposer (1B) according to the sixth aspect, which can be implemented in conjunction with the first aspect, the protective layer (5B) is arranged across the first main surface (21) of the dielectric substrate (2), the outer peripheral surface (421) of the second portion (42) of the pad electrode (4), and the main surface (401) of the pad electrode (4). The protective layer (5B) has an opening (53B) that partially exposes the main surface (401) of the pad electrode (4).

[0114] This aspect can further increase impact resistance and further improve joint reliability.

[0115] In the intermediate layer (1B) according to the seventh aspect, which can be implemented in conjunction with the sixth aspect, the opening width of the opening (53B) of the protective layer (5B) increases with the increase of the distance relative to the main surface (401) of the pad electrode (4).

[0116] This aspect makes it easier to remove the temporary adhesive layer (15) from the protective layer (5) when using a manufacturing process that includes bonding the second carrier substrate (16) to the protective layer (5) via a temporary adhesive layer (15).

[0117] In the intermediate layer (1B) according to the eighth aspect, which can be implemented in conjunction with the sixth or seventh aspect, the protective layer (5B) is a solder resist layer.

[0118] This aspect allows for improved positioning accuracy during the bonding process.

[0119] In the interlayer (1; 1A; 1B) according to the ninth aspect, which can be implemented in conjunction with any of the first to eighth aspects, the material used for the dielectric substrate (2) includes organic materials.

[0120] This aspect can help improve radio frequency characteristics.

[0121] In the interlayer (1; 1A; 1B) according to the tenth aspect, which can be implemented in conjunction with any of the first to ninth aspects, the material for the first portion (41) of the pad electrode (4) includes Cu, and the material for the second portion (42) of the pad electrode (4) includes Cu. Explanation of reference numerals in the attached figures

[0122] 1. Intermediate Layers 1A and 1B 2 Dielectric substrates 21 First Main Page 22 Second Main Face 3 feed conductors 4 pad electrodes (first pad electrode) 41 Part 1 42 Part Two 421 outer periphery 401 main surface 5. 5B protective layer 51, 51B Main Face 53B opening 6 wiring conductors 7.7A Second Pad Electrode 19IC chip 20 resin layers 100 Electronic Component Module D1 Thickness Direction

Claims

1. An intermediary layer, comprising: A dielectric substrate having a first main surface and a second main surface opposite to the first main surface; A feed conductor that penetrates the dielectric substrate; A pad electrode is arranged across the first main surface of the dielectric substrate and the feed conductor, and the pad electrode is connected to the feed conductor; as well as A protective layer is disposed on the first main surface of the dielectric substrate. The pad electrode includes: The first portion is configured to contact the first main surface of the dielectric substrate; and The second part is stacked on top of the first part. The outer edge of the first portion of the pad electrode is located inside the outer edge of the second portion of the pad electrode, and A portion of the protective layer is located between the first main surface of the dielectric substrate and the second portion of the pad electrode.

2. The intermediary layer according to claim 1, wherein, The thickness of the protective layer is greater than the distance between the first main surface of the dielectric substrate and the second portion of the pad electrode, and less than the thickness of the pad electrode. The protective layer partially covers the outer peripheral surface of the second portion of the pad electrode, but does not reach the main surface of the pad electrode.

3. The intermediary layer according to claim 1 or 2, wherein, The material used for the protective layer is an organic material.

4. The intermediary layer according to claim 1 or 2, wherein, The first main surface of the dielectric substrate has an uneven shape on the entire first main surface.

5. The intermediary layer according to claim 4, wherein, The surface roughness of the main surface of the protective layer that is opposite to the first main surface of the dielectric substrate is less than the surface roughness of the first main surface of the dielectric substrate.

6. The intermediary layer according to claim 1, wherein, The protective layer is arranged across the first main surface of the dielectric substrate, the outer peripheral surface of the second portion of the pad electrode, and the main surface of the pad electrode. The protective layer has an opening that partially exposes the main surface of the pad electrode.

7. The intermediary layer according to claim 6, wherein, The opening width of the opening in the protective layer increases with the increase of the distance relative to the main surface of the pad electrode.

8. The intermediary layer according to claim 6 or 7, wherein, The protective layer is a solder resist layer.

9. The intermediary layer according to claim 1 or 2, wherein, The materials used for the dielectric substrate include organic materials.

10. The intermediary layer according to claim 1 or 2, wherein, The material used for the first portion of the pad electrode includes Cu, and The material used for the second part of the pad electrode includes Cu.

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