A method and system for generating integrated circuit layout design for manufacturing rule violation patterns

Abstract

The application discloses an integrated circuit layout manufacturability design violation pattern generation method and system, and belongs to the technical field of DFM. The method trains a violation pattern generation model by using a generative adversarial network or a diffusion model, automatically synthesizes simulation violation patterns, and verifies and filters compliance by using a DRC tool. The application can automatically generate a large number of effective DFM violation samples, solves the problems of insufficient training data and insufficient coverage, and improves verification completeness and AI model performance.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design for manufacturability (DFM), and particularly relates to a method and system for generating non-compliant patterns in integrated circuit layout design for manufacturability, which is applicable to integrated circuit physical verification, design optimization and manufacturing yield improvement. Background Technology

[0002] As semiconductor process nodes continue to evolve, the complexity of integrated circuit design has increased significantly, leading to a continuous expansion of the DFM rule base. While traditional rule-based DRC tools can detect known violation patterns, their detection capabilities are limited by the completeness of the rule base. Currently, DFM validation and model training face the following prominent challenges: Insufficient sample coverage: The non-compliant patterns that appear in actual manufacturing are diverse and complex, and the existing sample library is difficult to fully cover, especially the rare non-compliant patterns under process boundary conditions. Training data shortage: Machine learning-based DFM classifiers require a large amount of labeled data, but manual collection and labeling are costly, which limits the model's generalization ability. Lagging rule updates: New violation patterns introduced by new processes are difficult to incorporate into the verification system in a timely manner, relying on the accumulation of manual experience, resulting in long response cycles.

[0003] Current research has attempted to classify DFM patterns using convolutional neural networks (CNNs), but there is a lack of systematic methods to actively generate illegal patterns, making it impossible to automatically expand the dataset and actively detect rule loopholes. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method and system for generating irregular patterns in the design for manufacturability of integrated circuit layouts.

[0005] The present invention is implemented as follows: In a first aspect, the present invention provides a method for generating patterns that violate design for manufacturability in integrated circuit layouts, the method comprising: Extract multiple layout clips from the integrated circuit layout database and label them with conditional tags indicating the type of violation; The labeled data is trained using a Generative Adversarial Network (GAN) or a diffusion model to obtain a violation pattern generation model. The aforementioned violation pattern generation model is used to generate simulated violation patterns; A rule-based physical design verification system (DRC tool) is used to verify the compliance of the generated patterns and filter out invalid samples.

[0006] Preferably, during training, the generative adversarial network includes a generator and a discriminator; The generator input includes a random noise vector sampled from a Gaussian distribution and a conditional label for the violation type, and the output is a simulated violation pattern; The discriminator is used to distinguish between real and fake input samples. Its input is a real violation pattern from the database or a simulated violation pattern generated by the generator. The output is a confidence value between 0 and 1, which represents the probability that the input belongs to a real sample.

[0007] More preferably, the generator maps low-dimensional random noise vectors into high-dimensional two-dimensional image representations through multi-layer deconvolution or upsampling structures, and integrates conditional label information during the generation process so that the output simulated violation pattern conforms to the specified violation type in terms of geometric shape and topological features.

[0008] More preferably, the discriminator extracts pattern features from the input samples using a convolutional neural network structure.

[0009] Preferably, during training, the diffusion model learns the structural distribution characteristics of normal map images through a generation mechanism of progressively adding and removing noise, and introduces manufacturability rules to constrain the generation process in order to obtain irregular patterns with higher physical consistency and controllability.

[0010] More preferably, the diffusion model generates the pattern through two stages: forward diffusion and reverse denoising. In the forward diffusion stage, starting from a cropped fragment of the map as the real map image, noise is gradually added to the image, causing it to gradually degenerate into a near-randomly distributed noisy image. In the reverse denoising stage, random noise is used as input, and noise is gradually removed through multiple reverse iterations to recover the structured pattern layer by layer, ultimately generating a violation pattern that is similar to the real map image in terms of geometric, topological, and hierarchical features. At the same time, a manufacturability rule judgment signal is embedded in each denoising iteration, automatically biasing towards structural regions that may trigger violations during generation.

[0011] Preferably, the compliance verification step further includes a physical consistency check on the generated pattern to ensure that it conforms to actual manufacturing constraints.

[0012] Preferably, the method further includes using the generated violation pattern to construct a high-risk test scenario or to train a classifier.

[0013] Secondly, the present invention provides a system for generating patterns that violate design for manufacturability of integrated circuit layouts, comprising: The layout slicing module is used to extract multiple layout clipping segments from the integrated circuit layout database and mark whether they violate manufacturability design rules; The generative model training module is used to train the labeled data using a generative adversarial network (GAN) or a diffusion model to obtain a violation pattern generation model. The compliance judgment module is used to generate simulated violation patterns using the violation pattern generation model, and to perform compliance verification on the generated patterns using a rule-based physical design verification system, filtering out invalid samples.

[0014] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method described thereon.

[0015] Fourthly, the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to implement the method described thereon.

[0016] This invention introduces Generative Adversarial Networks (GANs) or diffusion models to learn and internalize the deep structure and distribution patterns of DFM violations from limited raw data. Once the model is trained, simulated violation patterns can be continuously and batch-generated based on random noise or conditional labels without human intervention. This fundamentally changes the data acquisition model, transforming the sample source from "manual collection" to "automatic synthesis," providing near-unlimited data expansion capabilities for AI-based DFM verification.

[0017] The generative model of this invention, through exploration and creation in a high-dimensional design space, can generate a wide variety of violation pattern variants that far exceed the scope of the original training set. In particular, by introducing conditional labels, specific types of violations can be generated in a targeted manner, effectively compensating for potential loopholes in the rule base, conducting more rigorous "stress tests" on the design, and exposing potential problems that may arise during mass production in advance.

[0018] This invention uses the DRC tool to automatically perform compliance verification and physical consistency checks on each batch of generated patterns, ensuring that the final output samples are real DFM violations that may occur in actual manufacturing, rather than mathematical artifacts. This allows all generated samples to be directly used in subsequent classifier training or verification processes, guaranteeing the practical value of the entire technical solution.

[0019] This invention enables the system to quickly start and generate a large amount of relevant simulated violation data based on a small number of initial violation samples under a new process (and even conditional guidance using rule descriptions), which greatly shortens the time lag between DFM verification capabilities and the introduction of new processes, and provides an agile and efficient DFM support tool for rapidly iterating integrated circuit manufacturing processes. Attached Figure Description

[0020] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of the DFM violation pattern generation method provided in the embodiments of the present invention.

[0022] Figure 2 This is a schematic diagram of the generation process of the illegal pattern generation model provided in the embodiment of the present invention.

[0023] Figure 3 This is a diagram showing the result of generating a DFM violation pattern according to the present invention.

[0024] Terminology definition: DFM (Design for Manufacturability): Design for manufacturability is used to optimize IC layout to improve mass production yield.

[0025] Violation Pattern: DFM violation pattern, which is a local structure in the layout that violates the manufacturability rule.

[0026] GAN (Generative Adversarial Network): A network used to generate data such as images.

[0027] Layout Clip: An image clipped from the IC layout.

[0028] Rule-based DRC: A rule-based physical design verification system. Detailed Implementation

[0029] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0030] like Figure 1 As shown in the figure, the present invention provides a method for generating DFM violation patterns. This method automatically synthesizes DFM violation patterns that conform to physical constraints using generative AI technologies such as Generative Adversarial Networks (GANs) or diffusion models, thereby expanding the training dataset, enhancing validation coverage, and assisting in rule refinement. Specifically: Layout clips are extracted from IC design databases obtained through legal and compliant means, and normal / non-compliant segments are marked based on existing DFM rules to construct an initial training set; Using a GAN or diffusion model structure, a generator capable of generating violation patterns is trained based on labeled data. Conditional input is supported to enable targeted generation for different violation types; see appendix. Figure 2 ; The DRC tool is called to verify the generated patterns, filter out samples that are genuinely non-compliant and physically feasible, and exclude invalid patterns that are logically contradictory or cannot be manufactured. Valid violation patterns can be used to train DFM classification models, build high-risk test cases, or serve as input data for rule vulnerability analysis.

[0031] Example 1: Generation of Illegal Patterns Based on GAN like Figure 2 As shown, this embodiment provides a method for generating violation patterns based on Conditional Generative Adversarial Networks (cGANs). By introducing an adversarial training mechanism, the generator can learn the potential distribution of real violation patterns, thereby automatically generating diverse and highly realistic DFM violation patterns during the design phase. Specifically: Extract layout clips from the existing DFM violation database, scale them to a fixed resolution, and label them with violation categories; A conditional generative adversarial network is constructed, in which the generator receives random noise and violation category labels, and outputs a synthetic pattern. The generated patterns are batch-validated using a pre-trained DRC tool, retaining only the samples deemed to be in violation.

[0032] For example, the conditional generative adversarial network in this embodiment includes two main sub-networks: a generator and a discriminator.

[0033] The generator is used to generate simulated violation patterns based on a random noise vector and conditional labels. Its input includes a random noise vector sampled from a Gaussian distribution and conditional labels for the violation type, such as "too narrow linewidth," "insufficient metal spacing," and "via enclosure deviation." The generator maps low-dimensional noise to a high-dimensional two-dimensional image representation using multi-layer deconvolution or upsampling structures, and integrates conditional label information during the generation process, ensuring the output image conforms to the specified violation type in terms of geometry and topological features. The generator's goal is to generate violation patterns that are as realistic as possible, closely resembling real-world samples in appearance.

[0034] The discriminator is used to distinguish between genuine and fake input pattern samples. The input can be a fake pattern from a real database or a simulated sample generated by a generator. The discriminator extracts pattern features using a convolutional neural network structure and outputs a confidence value between 0 and 1, representing the probability that the input pattern belongs to a real sample. The goal of the discriminator is to maximize the distinguishability between real and generated samples in the feature space, thereby improving recognition capability.

[0035] During training, the generator and discriminator optimize simultaneously in an adversarial manner. The discriminator continuously learns how to more accurately distinguish between real and generated samples, while the generator continuously adjusts its parameters to make its output gradually approximate the distribution characteristics of real violation patterns. As training continues, the quality of the patterns generated by the generator gradually improves, while the discriminator's ability to distinguish them gradually decreases, eventually reaching an equilibrium state where the generator can generate violation patterns that are visually and structurally highly similar to real data.

[0036] Through this adversarial training mechanism, the generative model in this embodiment can automatically learn the statistical relationships and potential patterns between complex violation structures, thereby generating a large number of highly realistic violation pattern samples under limited sample conditions. Compared with traditional data augmentation or random perturbation methods, this method can autonomously explore new violation patterns in a high-dimensional feature space, making the generated results not only conform to manufacturing physical constraints, but also have rich geometric variations and morphological differences, thus significantly improving sample diversity.

[0037] After being filtered by the pre-trained DRC tool, the retained generated violation patterns can be directly used in the following scenarios: as training samples for the DFM classifier to improve the model's recognition ability; to construct high-risk test patterns to verify the coverage of design rules; and to assess potential violation risks under new process nodes and identify rule loopholes in advance. Through the above method, this embodiment achieves a closed-loop process from violation pattern generation, verification to filtering, enabling the batch generation of high-quality violation pattern datasets without manual intervention, providing important support for the improvement and intelligent verification of manufacturability design rules.

[0038] Example 2: Generation of Illegal Patterns Based on a Diffusion Model This embodiment provides a method for generating irregular patterns based on a diffusion model. Unlike the generative adversarial network in Embodiment 1, this method learns the structural distribution characteristics of normal layout images through a progressive noise addition and denoising mechanism. Furthermore, it introduces manufacturability rules to constrain the generation process, thereby obtaining irregular patterns with higher physical consistency and controllability. Specifically: Extract layout clips from the existing DFM violation database, scale them to a fixed resolution, and label them with violation categories; A diffusion model is constructed, and the structural distribution characteristics of the normal layout image are learned from the generation mechanism of progressive noise addition and denoising. Manufacturability rules are introduced during the generation process to obtain irregular patterns with higher physical consistency and controllability. The generated patterns are batch-validated using a pre-trained DRC tool, retaining only the samples deemed to be in violation.

[0039] For example, the core idea of ​​the diffusion model in this embodiment is to generate a pattern through two stages: "forward diffusion" and "reverse denoising." In the forward diffusion stage, the system starts with real training samples (e.g., real DFM violation image segments or normal map samples) and gradually adds noise to the image, causing it to degenerate into a near-randomly distributed noisy image. Through this process, the model learns the structural changes of the image at different noise levels. In the reverse denoising stage, the model takes random noise as input and gradually removes the noise through multiple reverse iterations, recovering the structured pattern layer by layer, ultimately generating a violation pattern similar to the real map in terms of geometry, topology, and hierarchical features. This denoising process is implemented by a deep neural network, preferably using a U-Net structure to capture multi-scale spatial features and local connectivity relationships in the pattern.

[0040] To improve the physical plausibility of the generated patterns, this embodiment introduces a rule constraint mechanism during the reverse generation process. Specifically, a manufacturability rule judgment signal is embedded in each denoising iteration, causing the model to automatically favor structural regions that may trigger violations during generation. By introducing rule consistency constraints into the network training objective, the model can be guided to generate pattern samples that more closely resemble the distribution of real manufacturing violations, rather than simply generating geometrically similar noise.

[0041] Finally, the DRC verification engine performs physical consistency and manufacturability checks on the generated patterns obtained by the diffusion model. It automatically filters out samples that do not conform to physical rules or geometric logic, retaining only high-quality samples that genuinely pose manufacturing risks and meet violation characteristics. The filtered pattern samples can be used to: construct extreme verification scenarios to simulate high-risk structures under process boundary conditions; serve as training data for DFM classification models to improve the model's ability to identify rare violation patterns; and support the verification and improvement of rule effectiveness under new process nodes. Compared with GAN-based generation methods, the diffusion model in this embodiment has higher stability and generation controllability, and can generate high-fidelity violation samples through a continuous denoising process without relying on discriminator training. This method is particularly suitable for DFM violation pattern generation tasks that require high physical consistency and structural constraints.

[0042] In summary, this embodiment utilizes the stepwise generation characteristics and rule constraint mechanism of the diffusion model to achieve controllable synthesis of real manufacturing non-compliant structures, which can significantly expand the coverage of the non-compliant sample dataset and enhance the learning ability and process adaptability of the AI ​​model.

[0043] See appendix Figure 3 This invention illustrates the relationship and verification process between real DFM violations and violations generated by the model of this invention. As shown in the figure, the left side represents real DFM violation samples extracted from an integrated circuit layout database. These samples were detected using existing physical verification systems (e.g., DRC tools) and contain known and confirmed manufacturability violation patterns. These patterns are used as training samples input into the violation pattern generation model of this invention. The right side represents simulated DFM violations automatically generated by the generation model of this invention (e.g., generative adversarial network or diffusion model) based on the distribution patterns of the aforementioned real samples. These samples structurally continue the geometric features and topological relationships of the real violation patterns, but the specific graphic combinations differ, representing potential novel violation structures autonomously generated by the model based on the learned pattern features. The two are connected through pattern comparison and feature mapping. The generation model uses real violation samples as a reference, learns their geometric features and violation distribution patterns, and then forms new violation samples with similar but not completely identical structures during the generation stage. A DRC check and verification module is located in the middle of the figure to verify the rule consistency and physical realizability of the generated violation samples. Only samples deemed "genuinely illegal and manufacturable" by this module are retained for subsequent training or rule testing, thus forming a data augmentation and rule-based closed-loop mechanism. Therefore, attached... Figure 3 This invention intuitively demonstrates that through a closed-loop process of "real violation data → model generation → DRC verification → effective sample screening," it achieves an automated DFM violation pattern generation and verification mechanism, significantly improving the efficiency and quality of violation sample generation.

[0044] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for generating irregular patterns in the design for manufacturability of integrated circuit layouts, characterized in that, The method includes: Extract multiple layout clippings from the integrated circuit layout database and label them with conditional tags indicating the type of violation; Generative adversarial networks or diffusion models are used to train labeled data to obtain illegal pattern generation models; The aforementioned violation pattern generation model is used to generate simulated violation patterns; A rule-based physical design verification system is used to verify the compliance of the generated patterns and filter out invalid samples.

2. The method according to claim 1, characterized in that, During training, a generative adversarial network consists of a generator and a discriminator; The generator input includes a random noise vector sampled from a Gaussian distribution and a conditional label for the violation type, and the output is a simulated violation pattern; The discriminator is used to distinguish between real and fake input samples. Its input is a real violation pattern from the database or a simulated violation pattern generated by the generator. The output is a confidence value between 0 and 1, which represents the probability that the input belongs to a real sample.

3. The method according to claim 2, characterized in that, The generator maps low-dimensional random noise vectors into high-dimensional two-dimensional image representations through multi-layer deconvolution or upsampling structures, and integrates conditional label information during the generation process so that the output simulated violation pattern conforms to the specified violation type in terms of geometric shape and topological features.

4. The method according to claim 2, characterized in that, The discriminator extracts pattern features from the input samples using a convolutional neural network structure.

5. The method according to claim 1, characterized in that, During training, the diffusion model learns the structural distribution characteristics from normal map images through a generation mechanism that involves progressively adding and removing noise. Furthermore, manufacturability rules are introduced during the generation process to obtain non-compliant patterns with higher physical consistency and controllability.

6. The method according to claim 5, characterized in that, The diffusion model generates the pattern through two stages: forward diffusion and reverse denoising. In the forward diffusion stage, starting from a cropped fragment of the map as the real map image, noise is gradually added to the image, causing it to gradually degenerate into a noise image that is close to random distribution. In the reverse denoising stage, random noise is used as input, and noise is gradually removed through multiple reverse iterations to recover the structured pattern layer by layer, ultimately generating a violation pattern that is similar to the real map image in terms of geometric, topological, and hierarchical features. At the same time, a manufacturability rule judgment signal is embedded in each denoising iteration, which automatically biases the structural regions that may trigger violations during generation.

7. The method according to claim 1, characterized in that, The compliance verification step also includes a physical consistency check on the generated pattern to ensure that it conforms to actual manufacturing constraints.

8. A system for generating irregular patterns in the design for manufacturability of integrated circuit layouts, characterized in that, include: The layout slicing module is used to extract multiple layout clipping segments from the integrated circuit layout database and label them with conditional tags indicating the type of violation. The generative model training module is used to train the labeled data using a generative adversarial network (GAN) or a diffusion model to obtain a violation pattern generation model. The compliance judgment module is used to generate simulated violation patterns using the violation pattern generation model, and to perform compliance verification on the generated patterns using a rule-based physical design verification system, filtering out invalid samples.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1 to 7.

10. An electronic device, characterized in that, It includes a memory and a processor, the memory storing a computer program, and the processor executing the program to implement the method as described in any one of claims 1 to 7.

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