Apparatus for manufacturing display device

Abstract

The utility model relates to an apparatus for manufacturing a display device. The apparatus for manufacturing a display device includes: a mask assembly disposed in a chamber and facing a display substrate; a magnetic portion disposed in the chamber and applying a magnetic force to the mask assembly; and a deposition source. The mask assembly includes: a first mask layer having a first mask opening formed therein; and a second mask layer disposed on the first mask layer. The second mask layer includes: a metal layer having a metal opening formed therein; and an inorganic layer disposed on the metal layer and having an inorganic opening overlapping the first mask opening in a plan view. The metal opening overlaps the inorganic opening in a plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0039061 filed in the Korean Intellectual Property Office (KIPO) on March 24, 2023 and Korean Patent Application No. 10-2023-0080675 filed in the Korean Intellectual Property Office (KIPO) on June 22, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to an apparatus and method for manufacturing a display device. Background Art

[0004] Display devices are used to visually display data. Display devices can provide images by using light emitting diodes. Display devices are used for various purposes. Therefore, various designs have been tried to improve the quality of display devices. Utility Model Content

[0005] Embodiments include an apparatus for manufacturing a display device, the apparatus including a mask assembly having magnetism, wherein a manufacturing process of the mask assembly is simplified.

[0006] However, such an object is an example, and the object to be solved by the present disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the embodiments of the disclosure.

[0008] According to an embodiment, an apparatus for manufacturing a display device may include: a chamber; a mask assembly arranged in the chamber and facing a display substrate; a magnetic force portion arranged in the chamber and applying a magnetic force to the mask assembly; and a deposition source arranged in the chamber, facing the mask assembly, and supplying a deposition material that passes through the mask assembly to be deposited on the display substrate. The mask assembly may include: a first mask layer having a first mask opening formed therein; and a second mask layer disposed on the first mask layer. The second mask layer may include: a metal layer having a metal opening formed therein; and an inorganic layer disposed on the metal layer and having an inorganic opening that overlaps the first mask opening in a plan view. The metal opening may overlap the inorganic opening in a plan view.

[0009] In an embodiment, the metal layer may surround the inorganic opening in a plan view.

[0010] In an embodiment, at least a portion of the inorganic layer may be disposed within the metal opening.

[0011] In an implementation, the metal layer may include a plurality of metal layers.

[0012] In an implementation, a plurality of metal layers may be spaced apart from each other by a certain distance in a plan view.

[0013] In an embodiment, in a cross-sectional view, at least a portion of the inorganic layer may be disposed between the plurality of metal layers.

[0014] In an embodiment, a lower surface of the metal layer may be exposed from the inorganic layer.

[0015] In an embodiment, an inorganic layer may cover an upper surface of the metal layer.

[0016] According to an embodiment, a method for manufacturing a display device may include: arranging a display substrate in a chamber; arranging a mask assembly in the chamber; applying a magnetic force to the mask assembly through a magnetic force portion; and providing a deposition material toward the mask assembly through a deposition source. Arranging the mask assembly may include: disposing a metal layer on a first mask layer; forming a metal opening in the metal layer; disposing an inorganic layer on the metal layer; forming a first mask opening in the first mask layer; and forming an inorganic opening in the inorganic layer that overlaps the metal opening in a plan view.

[0017] In an implementation, forming the inorganic opening in the inorganic layer may include etching the inorganic layer in a direction where the first mask layer faces the metal layer.

[0018] In an embodiment, according to etching of the inorganic layer, a lower portion of the metal layer may be exposed from the inorganic layer.

[0019] In an embodiment, according to forming the inorganic opening in the inorganic layer, the metal layer may surround the inorganic opening.

[0020] In an embodiment, according to the arrangement of the inorganic layer, at least a portion of the inorganic layer may be arranged within the metal opening.

[0021] In an implementation, the metal layer may include a plurality of metal layers.

[0022] In an implementation, a plurality of metal layers may be spaced apart from each other by a certain distance in a plan view.

[0023] In an embodiment, in a cross-sectional view, at least a portion of the inorganic layer may be disposed between the plurality of metal layers.

[0024] In an embodiment, according to the arrangement of the inorganic layer, the inorganic layer may cover the upper surface of the metal layer.

[0025]

[0011] Other aspects, features, and advantages in addition to those described above will become apparent from the accompanying drawings, claims, and detailed description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a schematic cross-sectional view of an apparatus for manufacturing a display device according to an embodiment;

[0028] Figure 2 is a schematic cross-sectional view of a mask assembly according to an embodiment;

[0029] Figure 3 is a schematic plan view of a portion of a second mask layer according to an embodiment;

[0030] Figures 4 to 11 is a schematic cross-sectional view of a mask assembly according to an embodiment, illustrating a method of manufacturing the mask assembly;

[0031] Fig.12 is a schematic perspective view of a display device according to an embodiment;

[0032] Fig.13 is a schematic cross-sectional view of a display device according to an embodiment;

[0033] Fig.14 is a schematic plan view of a display panel according to an embodiment;

[0034] Fig.15 is a schematic diagram of an equivalent circuit of a pixel included in a display device according to an embodiment; and

[0035] Fig.16 is a schematic cross-sectional view of a display device according to an embodiment. DETAILED DESCRIPTION

[0036] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals represent the same elements throughout. In this regard, embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, embodiments are described below only by reference to the accompanying drawings to explain the aspects of the description. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0037] Various modifications may be applied to the embodiments, and specific embodiments will be shown in the drawings and described in the detailed description section. The effects and features of the embodiments and methods for implementing the same will become more apparent with reference to the following detailed description in conjunction with the drawings. However, the embodiments may be implemented in various forms and are not limited to the embodiments presented below.

[0038] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings, and in the description with reference to the accompanying drawings, the same or corresponding components are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0039] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0040] The terms used herein are used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprises", "comprising", "includes" and / or "including" specify the existence of stated features, integral bodies, steps, operations, elements, components and / or groups thereof, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as degree terms, and therefore, are used to allow for the inherent deviations in the measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0041] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly" "on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements. In addition, when an element is referred to as being "in contact" or "contacted" with another element, etc., the element may be "electrically in contact" or "physically in contact" with the other element, or "indirectly in contact" or "directly in contact" with the other element.

[0042] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiments may be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence.

[0043] For descriptive purposes, spatially relative terms such as "below," "below," "under," "down," "above," "on," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein, and thereby describe the relationship of one element to another element (or elements) as shown in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both above and below orientations. Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0044] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0045] When a specific embodiment can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously, or in the reverse order of the described order.

[0046] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in this specification.

[0047] Figure 1is a schematic cross-sectional view of an apparatus 1 for manufacturing a display device according to an embodiment.

[0048] The apparatus 1 for manufacturing a display device may include a chamber CH, a first supporting part SP1, a second supporting part SP2, a mask assembly MA, a deposition source SC, a magnetic part MG, a visual part VS, and a pressure control part PSC.

[0049] The chamber CH may have a space formed therein, and the display substrate DS and the mask assembly MA may be accommodated in the chamber CH. An opening portion may be formed in a portion of the chamber CH, a gate valve GB may be installed on the opening portion of the chamber CH, and the opening portion of the chamber CH may be opened or closed according to the operation of the gate valve GB.

[0050] The display substrate DS may be a substrate 100 (see FIG. 1 ) described below in which at least one of an organic layer, an inorganic layer, and a metal layer is deposited during the process of manufacturing a display device. Fig.14 In another embodiment, the display substrate DS may be a display substrate in which any one of the organic layer, the inorganic layer, and the metal layer has not been deposited.

[0051] The first supporting portion SP1 may support the display substrate DS. The first supporting portion SP1 may be in the form of a plate fixed in the chamber CH. In another embodiment, the first supporting portion SP1 may be in the form of a shuttle equipped with the display substrate DS and capable of linear movement within the chamber CH. In another embodiment, the first supporting portion SP1 may include an electrostatic chuck or an adhesive chuck arranged in the chamber CH and fixed to the chamber CH or movable within the chamber CH.

[0052] The second supporting portion SP2 may support the mask assembly MA. The second supporting portion SP2 may be disposed within the chamber CH. The second supporting portion SP2 may finely control the position of the mask assembly MA. The second supporting portion SP2 may include a separate driving portion, an alignment unit, etc. to move the mask assembly MA in one direction.

[0053] In another embodiment, the second supporting portion SP2 may be in the form of a shuttle, and the mask assembly MA may be placed on the second supporting portion SP2, and thus, the second supporting portion SP2 may transfer the mask assembly MA. For example, the second supporting portion SP2 may be moved to the outside of the chamber CH, and after the mask assembly MA is placed on the second supporting portion SP2, the second supporting portion SP2 may enter the chamber CH from the outside of the chamber CH.

[0054] In the above embodiment, the first supporting portion SP1 and the second supporting portion SP2 may be formed integrally with each other, and the first supporting portion SP1 and the second supporting portion SP2 may include a movable shuttle. The first supporting portion SP1 and the second supporting portion SP2 may have a structure for fixing the mask assembly MA and the display substrate DS while the display substrate DS is placed on the mask assembly MA, and may linearly move the display substrate DS and the mask assembly MA at the same time.

[0055] However, in the following description, for convenience of explanation, an embodiment in which the first supporting portion SP1 and the second supporting portion SP2 are respectively formed and located at different positions and the first supporting portion SP1 and the second supporting portion SP2 are arranged within the chamber CH is described in detail.

[0056] The mask assembly MA may be disposed within the chamber CH and face the display substrate DS. The deposition material M may pass through the mask assembly MA to be deposited on the display substrate DS.

[0057] The deposition source SC may be arranged to face the mask assembly MA, and the deposition material M may be provided to be deposited on the display substrate DS by passing through the mask assembly MA. The deposition source SC may evaporate or sublime the deposition material M by applying heat to the deposition material M. The deposition source SC may be arranged to be fixed inside the chamber CH, or arranged inside the chamber CH to be able to move linearly in one direction.

[0058] The magnetic portion MG may be disposed within the chamber CH and face the display substrate DS and / or the mask assembly MA. The magnetic portion MG may apply a magnetic force to the mask assembly MA toward the display substrate DS.

[0059] The vision part VS may be arranged in the chamber CH, and may detect the positions of the display substrate DS and the mask assembly MA. The vision part VS may include a camera for detecting the positions of the display substrate DS and the mask assembly MA. The positions of the display substrate DS and the mask assembly MA may be identified based on an image taken by the vision part VS, and misalignment of the mask assembly MA may be checked. In addition, based on the image, the first supporting part SP1 may finely adjust the position of the display substrate DS, or the second supporting part SP2 may finely adjust the position of the mask assembly MA. However, in the following description, an embodiment in which the second supporting part SP2 finely adjusts the position of the mask assembly MA to align the positions of the display substrate DS and the mask assembly MA is described in detail.

[0060] The pressure control section PSC may be connected to the chamber CH and may control the pressure in the chamber CH. For example, the pressure control section PSC may control the pressure in the chamber CH to be the same as or similar to the atmospheric pressure. For example, the pressure control section PSC may control the pressure in the chamber CH to be the same as or similar to a vacuum state.

[0061] The pressure control portion PSC may include a connection pipe 81 connected to the chamber CH and a pump 82 mounted on the connection pipe 81. According to the operation of the pump 82, external air may be introduced through the connection pipe 81, or gas in the chamber CH may be discharged to the outside through the connection pipe 81.

[0062] In a method of manufacturing a display device (not shown) by using the apparatus 1 for manufacturing a display device, first, a display substrate DS may be prepared.

[0063] The pressure control portion PSC may maintain the interior of the chamber CH in a state that is the same as or similar to the atmospheric pressure, and an opening portion of the chamber CH may be opened by operating the gate valve GB.

[0064] The display substrate DS can be loaded into the chamber CH from the outside. The display substrate DS can be loaded into the chamber CH in various ways. For example, the display substrate DS can be loaded into the chamber CH from the outside by a robot arm or the like arranged outside the chamber CH. In another embodiment, in the case where the first supporting portion SP1 is in the form of a shuttle, the first supporting portion SP1 can be moved from the inside of the chamber CH to the outside of the chamber CH, the display substrate DS can be placed on the first supporting portion SP1 by a separate robot arm or the like arranged outside the chamber CH, and the first supporting portion SP1 can be loaded into the chamber CH from the outside of the chamber CH.

[0065] As described above, the mask assembly MA may be disposed within the chamber CH. In another embodiment, the mask assembly MA may be loaded into the chamber CH from outside the chamber CH in the same or similar manner as the display substrate DS.

[0066] In the case where the display substrate DS is loaded into the chamber CH, the display substrate DS may be placed on the first support portion SP1. The vision portion VS may photograph the positions of the display substrate DS and the mask assembly MA. The positions of the display substrate DS and the mask assembly MA may be identified based on the image photographed by the vision portion VS. The apparatus 1 for manufacturing a display device may be provided with a separate controller (not shown) to identify the positions of the display substrate DS and the mask assembly MA.

[0067] After completing the recognition of the positions of the display substrate DS and the mask assembly MA, the second supporting portion SP2 may finely adjust the position of the mask assembly MA.

[0068] The deposition source SC may be operated to provide the deposition material M toward the mask assembly MA, and the deposition material M having passed through the mask assembly MA may be deposited on the display substrate DS. The deposition source SC may be moved in parallel to the display substrate DS and the mask assembly MA, or the display substrate DS and the mask assembly MA may be moved in parallel to the deposition source SC. For example, the deposition source SC may be moved relative to the display substrate DS and the mask assembly MA, and the pump 82 may suck the gas in the chamber CH and discharge the gas to the outside, so that the pressure in the chamber CH may be maintained in a state identical to or similar to a vacuum.

[0069] As described above, the deposition material M provided from the deposition source SC may pass through the mask assembly MA and be deposited on the display substrate DS. Thus, at least one of a plurality of layers (eg, organic layers, inorganic layers, and metal layers) to be stacked in a display device described below may be formed.

[0070] Figure 2 is a schematic cross-sectional view of a mask assembly MA according to an embodiment, and Figure 3 is a schematic plan view of a portion of a second mask layer according to an embodiment. For example, Figure 3 The plan view shows Figure 2 Area A.

[0071] refer to Figure 2 and Figure 3 , the mask assembly MA may include a first mask layer 41 and a second mask layer 42 .

[0072] The first mask opening OP41 may be disposed in the first mask layer 41, and the material M may be deposited (see Figure 1 ) may pass through the first mask opening OP41. An inner circumferential surface may be formed on the first mask layer 41 through the first mask opening OP41. The first mask opening OP41 may be arranged at a central portion of the first mask layer 41. A central portion of the second mask layer 42 may be exposed through the first mask opening OP41 of the first mask layer 41. Although Figure 2 It is illustrated that the inner circumferential surface of the first mask layer 41 is inclined with respect to the second mask layer 42 , but the present disclosure is not limited thereto, and the inner circumferential surface of the first mask layer 41 may be perpendicular to the second mask layer 42 .

[0073] The first mask layer 41 may include a silicon material. For example, the first mask layer 41 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiO x N y ) at least one of.

[0074] The second mask layer 42 may be disposed on the first mask layer 41. The second mask layer 42 may be formed on the first mask layer 41. The second mask layer 42 may include a metal layer 421 and an inorganic layer 422.

[0075] The metal layer 421 may be disposed on the first mask layer 41. The metal layer 421 may be magnetic. For example, the metal layer 421 may include at least one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo).

[0076] The metal layer 421 may be supported on the first mask layer 41 through the inorganic layer 422. The metal opening OP421 may be arranged in the metal layer 421. In a plan view, the metal opening OP421 may overlap with the first mask opening OP41. The metal layer 421 may include a plurality of metal layers 421. Figure 3 As shown in FIG. 4 , in a plan view, the metal layers 421 may be arranged to be spaced apart from each other by a first distance D421. Figure 3 As shown in , the metal openings OP421 may be arranged in a first direction (eg, a y-axis direction) and a second direction (eg, an x-axis direction).

[0077] The inorganic layer 422 may be disposed on the first mask layer 41 and the metal layer 421. The inorganic layer 422 may be supported on the first mask layer 41. The inorganic layer 422 may include SiO x 、SiN x and SiO x N y At least one of .

[0078] The inorganic opening OP422 overlapping the first mask opening OP41 and the metal opening OP421 in a plan view may be arranged in the inorganic layer 422. In a plan view, the inorganic opening OP422 may overlap the first mask opening OP41. The inorganic opening OP422 may include a plurality of inorganic openings OP422. For example, Figure 3 As shown in , the inorganic openings OP422 may be arranged in a first direction (eg, a y-axis direction) and a second direction (eg, an x-axis direction).

[0079] The position of the inorganic opening OP422 may correspond to the position of the metal opening OP421. Figure 3 As shown in FIG. 4 , in a plan view, the width of the metal opening OP421 may be greater than the width of the inorganic opening OP422. In this structure, at least a portion of the inorganic layer 422 may be arranged in the metal opening OP421. Figure 3 As shown in FIG. 4 , in a plan view, the width of the metal opening OP421 may be greater than the width of the inorganic opening OP422. In other words, in a plan view, the metal layer 421 may surround the inorganic opening OP422.

[0080] The inorganic layer 422 may cover the metal layer 421. For example, the inorganic layer 422 may cover the upper surface 421US of the metal layer 421. In the case where the metal layer 421 includes a plurality of metal layers 421, at least a portion of the inorganic layer 422 may be disposed on the metal layer 421. A portion of the metal layer 421 may be exposed from the inorganic layer 422. For example, the lower surface 421DS of the metal layer 421 may be exposed from the inorganic layer 422.

[0081] Due to the arrangement of the metal layer 421 having magnetism, the magnetic part MG may apply magnetic force to the mask assembly MA. In other words, there may be an attractive force between the mask assembly MA and the magnetic part MG. Therefore, the mask assembly MA and the display substrate DS may be in close contact with each other. Therefore, an error occurring in the process of depositing the display substrate DS may be reduced.

[0082] Figures 4 to 11 is a schematic cross-sectional view of a mask assembly MA according to an embodiment, which illustrates a method of manufacturing the mask assembly MA.

[0083] exist Figures 4 to 11 middle, Figures 1 to 3 The same elements in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0084] refer to Figures 4 to 11 , the method of manufacturing a display device may include arranging a mask assembly MA in a chamber CH (see Figure 1 ).

[0085] Arranging the mask assembly MA may include disposing a metal layer 421 on the first mask layer 41 , forming a metal opening OP421 in the metal layer 421 , disposing an inorganic layer 422 on the metal layer 421 , forming a first mask opening OP41 in the first mask layer 41 , and forming an inorganic opening OP422 in the inorganic layer 422 .

[0086] refer to Figures 4 to 8 , it can be described that a metal layer 421 is disposed on the first mask layer 41 and a metal opening OP421 is formed in the metal layer 421 .

[0087] First, refer to Figure 4 , a metal layer 421 may be disposed on the first mask layer 41, and a first photoresist material PRM1 may be disposed on the metal layer 421. The first photoresist material PRM1 may include a photosensitive material.

[0088] refer to Figure 5, a first photomask PMA1 in which a first photomask opening OPPMA1 is arranged may be provided above the first photoresist material PRM1. The first photoresist material PRM1 may be exposed to light LT through the first photomask opening OPPMA1. The light LT may pass through the first photomask opening OPPMA1 to be incident on the first photoresist material PRM1. For example, the light LT may be ultraviolet light. In this process, the solubility of the first photoresist material PRM1 overlapping with the first photomask opening OPPMA1 in a plan view may be reduced. In addition, the solubility of the first photoresist material PRM1 that does not overlap with the first photomask opening OPPMA1 in a plan view may be increased.

[0089] refer to Figure 6 , the first photoresist material PRM1 may be developed into a first photoresist layer PRL1. For example, a portion of the first photoresist material PRM1 may be removed by using an alkaline developer. Figure 5 The first photoresist material PRM1 in the optical fiber not contacting the light LT. The first photoresist layer PRL1 may have a first light opening OPPRL1.

[0090] refer to Figure 7 , a portion of the metal layer 421 overlapping with the first optical opening OPPRL1 in a plan view may be etched. The metal layer 421 may be etched in a direction (e.g., a -z axis direction) in which the metal layer 421 faces the first mask layer 41. A portion of the metal layer 421 overlapping with the first photoresist layer PRL1 in a plan view may be retained, and a portion of the metal layer 421 overlapping with the first optical opening OPPRL1 in a plan view may be removed. When the metal layer 421 is etched, a metal opening OP421 may be formed in the metal layer 421.

[0091] Since the first optical opening OPPRL1 includes a plurality of first optical openings OPPRL1, the metal layer 421 may also include a plurality of metal layers 421. The metal layers 421 may be spaced apart from each other by a first distance D421. When the metal layer 421 is etched, the first mask layer 41 may be exposed from the metal layer 421 through the metal opening OP421. For example, the metal layer 421 may be etched by dry etching using an etching gas.

[0092] refer to Figure 8 , the first photoresist layer PRL1 can be removed (see Figure 7 ). When the first photoresist layer PRL1 is removed, the upper surface of the metal layer 421 may be exposed.

[0093] refer to Fig. 9, describes that an inorganic layer 422 is provided on a metal layer 421. At least a portion of the inorganic layer 422 may be arranged in the metal opening OP421 and contact the first mask layer 41. A portion of the inorganic layer 422 may be accommodated between the metal layers 421 and contact the first mask layer 41. The inorganic layer 422 may cover an upper surface 421US of the metal layer 421, and a lower surface 421DS of the metal layer 421 may contact the first mask layer 41. The metal layer 421 may be sealed by the first mask layer 41 and the inorganic layer 422. A first groove GR421 may be formed in the inorganic layer 422 corresponding to the shape of the metal layer 421.

[0094] refer to Fig.10 , describes forming a first mask opening OP41 in the first mask layer 41. The first mask opening OP41 may be formed by a photolithography process. Figures 4 to 8 The photolithography process is described, and thus a detailed description thereof is omitted When the first mask opening OP41 is formed, lower surfaces of the metal layer 421 and the inorganic layer 422 may be exposed from the first mask layer 41 through the first mask opening OP41 .

[0095] refer to Fig.11 , describes forming an inorganic opening OP422 in an inorganic layer 422. Forming the inorganic opening OP422 in the inorganic layer 422 may include etching the inorganic layer 422 in a direction (e.g., +z-axis direction) in which the first mask layer 41 faces the metal layer 421. When etching a lower portion of the inorganic layer 422, the inorganic opening OP422 may be formed in the inorganic layer 422. In addition, a lower portion of the metal layer 421 may be exposed from the inorganic layer 422. When forming the inorganic opening OP422 in the inorganic layer 422, the metal layer 421 may surround the inorganic opening OP422.

[0096] In the process, the inorganic opening OP422 can be formed without using a photolithography process. In other words, the inorganic opening OP422 can be formed without a separate photoresist material and a photomask. Therefore, the manufacturing process of the mask assembly MA can be simplified. For example, the inorganic layer 422 can be etched by dry etching using an etching gas.

[0097] Fig.12 is a schematic perspective view of a display device 2 according to the embodiment.

[0098] refer to Fig.12 , the display device 2 may include a display area DA and a peripheral area PA adjacent to (eg, surrounding) the display area DA. The display device 2 may provide an image by using light emitted from a plurality of pixels arranged in the display area DA.

[0099] In a plan view, the peripheral area PA may completely surround the display area DA. The peripheral area PA may be a non-display area in which pixels are not arranged, and a driver or wiring for supplying electrical signals or power to the pixels may be arranged in the peripheral area PA.

[0100] like Fig.12 As shown in , the display device 2 may have a rectangular shape in which the horizontal length is greater than the vertical length in a plan view, but the present disclosure is not limited thereto. The display device 2 may have various shapes, such as other polygonal shapes, a circular shape, or an elliptical shape.

[0101] In the following description, although an organic light emitting display device is described as an embodiment of the display device 2, the display device is not limited thereto. In another embodiment, a different type of display device may be used for this purpose, such as a quantum dot light emitting display device.

[0102] Fig.13 is a schematic cross-sectional view of a display device 2 according to an embodiment. Fig.13 Can correspond to Fig.12 The line A-A'.

[0103] refer to Fig.13 The display device 2 may include a display panel 10, an input sensing layer 40 disposed on the display panel 10, and an optical functional layer 50 covered by a window 60. The display device 2 may be various types of electronic devices, such as a mobile phone, a notebook computer, a smart watch, and the like.

[0104] The display panel 10 may display an image. The display panel 10 may include pixels arranged in a display area DA. The pixels may include a display element and a pixel circuit connected to the display element. The display element may include an organic light emitting diode, a quantum dot organic light emitting diode, etc.

[0105] The input sensing layer 40 may obtain coordinate information according to an external input (e.g., a touch event). The input sensing layer 40 may include a sensing electrode (or a touch electrode) and a trace connected to the sensing electrode. The input sensing layer 40 may be disposed on the display panel 10. The input sensing layer 40 may sense an external input by a mutual capacitance method or / and a self-capacitance method.

[0106] The input sensing layer 40 may be formed (e.g., directly formed) on the display panel 10, or may be formed separately and coupled by an adhesive layer such as an optically transparent adhesive. For example, the input sensing layer 40 may be formed continuously after the process of forming the display panel 10, and the input sensing layer 40 may be a part of the display panel 10, and an adhesive layer may not be provided between the input sensing layer 40 and the display panel 10. Although Fig.13It is illustrated that the input sensing layer 40 is disposed between the display panel 10 and the optical function layer 50 , but the present disclosure is not limited thereto, and in another embodiment, the input sensing layer 40 may be disposed on the optical function layer 50 .

[0107] The optical function layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) input from the outside to the display panel 10 through the window 60. In an embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged according to the color of light emitted from each of the pixels of the display panel 10.

[0108] In another embodiment, the anti-reflection layer may include a retarder and a polarizer. The retarder may be a film type or a liquid crystal coating type, or may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type polarizer may include a stretchable synthetic resin film, and the liquid crystal coating type polarizer may include liquid crystals arranged in an array. The retarder and the polarizer may also include a protective film. The retarder and the polarizer themselves or the protective film may be defined as the base layer of the anti-reflection layer.

[0109] In another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light respectively reflected from the first reflective layer and the second reflective layer may destructively interfere with each other, thereby reducing the reflectivity of the external light.

[0110] In an embodiment, the optical function layer 50 may be continuously formed after a process of forming the display panel 10 and / or the input sensing layer 40 , and an adhesive layer may not be provided between the optical function layer 50 , the display panel 10 , and / or the input sensing layer 40 .

[0111] Although not in Fig.13 , but a layer including an optically transparent adhesive, an optically transparent resin, etc. may be located between the window 60 and the optically functional layer 50 .

[0112] Fig.14 is a schematic plan view of a display panel 10 according to an embodiment. Fig.13 As described, the display device 2 according to the embodiment may include the display panel 10 . Fig.14 The shape may correspond to that of the substrate 100 of the display panel 10 .

[0113] refer to Fig.14, the display panel 10 may include a display area DA and a peripheral area PA adjacent to the display area DA. The display area DA may be a portion for displaying an image, and a plurality of pixels P may be arranged in the display area DA. The display area DA may have various shapes in a plan view, such as a circular shape, an elliptical shape, a polygonal shape, a specific graphic shape, etc. Fig.14 It is illustrated that the display area DA has a rectangular shape with approximately rounded corners, but the present disclosure is not limited thereto.

[0114] Each of the pixels P may be a sub-pixel and may include, for example, an organic light emitting diode OLED (see Fig.15 ) display element. The pixel P can emit, for example, red light, green light, blue light or white light.

[0115] The peripheral area PA may be arranged adjacent to the display area DA. External circuits for driving the pixels P may be arranged in the peripheral area PA. The first scan drive circuit 11, the second scan drive circuit 12, the emission control drive circuit 13, the terminal 14, the drive power wiring 15, and the common power wiring 16 may be arranged in the peripheral area PA.

[0116] The first scan driving circuit 11 may provide a scan signal to the pixel P through the scan line SL. The second scan driving circuit 12 may be arranged in parallel with the first scan driving circuit 11, and the display area DA is between the first scan driving circuit 11 and the second scan driving circuit 12. Some of the pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit 11, and other some of the pixels P may be electrically connected to the second scan driving circuit 12. In another embodiment, the second scan driving circuit 12 may be omitted, and all of the pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit 11.

[0117] The emission control driving circuit 13 may be disposed adjacent to the first scanning driving circuit 11 and may provide an emission control signal to the pixel P through the emission control line EL. Fig.12 It is shown that the emission control driving circuit 13 is arranged at only one side of the display area DA, but the present disclosure is not limited thereto, and like the first scan driving circuit 11 and the second scan driving circuit 12, the emission control driving circuit 13 may be arranged at both sides of the display area DA.

[0118] In an embodiment, the peripheral area PA may include a curved area extending from one side (-y direction) of the display area DA. The curved area may be curved toward the rear surface of the display area DA, thereby reducing the area of ​​the non-display area perceived from the front surface of the display device 2.

[0119] The driving chip 20 may be disposed in the peripheral area PA. The driving chip 20 may include an integrated circuit for driving the display panel 10. The integrated circuit may include a data driving integrated circuit for generating a data signal, but the present disclosure is not limited thereto.

[0120] The terminal 14 may be disposed in the peripheral area PA. The terminal 14 may be exposed without being covered by the insulating layer, and may be electrically connected to the printed circuit board 30. The terminal 34 of the printed circuit board 30 may be electrically connected to the terminal 14 of the display panel 10.

[0121] The printed circuit board 30 may transmit a signal or power of a controller (not shown) to the display panel 10. A control signal generated by the controller may be transmitted to the driving circuit through the printed circuit board 30. In addition, the controller may transmit a driving voltage ELVDD (see FIG. 1 ) to the driving power wiring 15. Fig.15 ), and transmits the common voltage ELVSS to the common power wiring 16 (see Fig.15 ). The driving voltage ELVDD may be transmitted to each pixel P through the driving voltage line PL connected to the driving power wiring 15, and the common voltage ELVSS may be transmitted to the opposite electrode of the pixel P connected to the common power wiring 16. In a plan view, the driving power wiring 15 may have a shape extending in one direction (x-axis direction) below the display area DA. The common power wiring 16 may have a ring shape with an open side, and may have a shape partially surrounding the display area DA in a plan view.

[0122] The controller may generate a data signal, and the generated data signal may be transmitted to the input line IL through the driving chip 20 and transmitted to the pixel P through the data line DL connected to the input line IL. For example, the “line” may be a “wiring”. The same applies to the embodiments described below.

[0123] Fig.15 is a schematic diagram of an equivalent circuit of a pixel P included in a display device according to an embodiment.

[0124] refer to Fig.15 , one pixel P may be a display element including a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red light, green light, or blue light through the organic light emitting diode OLED, or emit red light, green light, blue light, or white light.

[0125] The second thin film transistor T2 as a switching thin film transistor may be connected to the scan line SL and the data line DL, and may transmit a data voltage input through the data line DL to the first thin film transistor T1 based on a switching voltage input through the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage received from the second thin film transistor T2 and a driving voltage ELVDD provided through the driving voltage line PL.

[0126] The first thin film transistor T1 as a driving thin film transistor can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL into the organic light emitting diode OLED in response to the value of the voltage stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a brightness corresponding to the driving current. The opposite electrode (e.g., cathode) of the organic light emitting diode OLED can receive the common voltage ELVSS.

[0127] although Fig.15 The pixel circuit PC is shown to include two thin film transistors and one storage capacitor, but the present disclosure is not limited thereto. The number of thin film transistors and the number of storage capacitors may vary according to the design of the pixel circuit PC. For example, in addition to the two thin film transistors described above, the pixel circuit PC may also include four or more thin film transistors.

[0128] Fig.16 is a schematic cross-sectional view of a display device 2 according to an embodiment.

[0129] refer to Fig.16 , the display panel 10 may include a substrate 100 .

[0130] The substrate 100 may include a glass material or a polymer resin. In an implementation, the substrate 100 may have a multi-layer structure in which a base layer including a polymer resin and a barrier layer for preventing penetration of external foreign materials are alternately stacked on each other.

[0131] The base layer may include a polymer resin, including polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP), etc.

[0132] The barrier layer may include an inorganic material such as silicon nitride (SiN x ), silicon oxide (SiO x )wait.

[0133] A first pixel P1 for emitting light of a first color, a second pixel P2 for emitting light of a second color, and a third pixel P3 for emitting light of a third color may be arranged in the display area DA of the substrate 100. The first color, the second color, and the third color may each be one of red, blue, green, and white.

[0134] The first pixel P1 may include a first pixel circuit PC1 and a first organic light emitting diode OLED1 as a display element electrically connected to the first pixel circuit PC1. The second pixel P2 may include a second pixel circuit PC2 and a second organic light emitting diode OLED2 electrically connected to the second pixel circuit PC2. The third pixel P3 may include a third pixel circuit PC3 and a third organic light emitting diode OLED3 electrically connected to the third pixel circuit PC3.

[0135] A buffer layer 201 for preventing impurities from penetrating into the semiconductor layer Act of the thin film transistor TFT of the first pixel circuit PC1 may be disposed on the substrate 100. The buffer layer 201 may include an inorganic insulating material such as SiN x , SiON and SiO x and may be a single layer or multiple layers including the above-mentioned inorganic insulating material.

[0136] The first pixel circuit PC1, the second pixel circuit PC2 and the third pixel circuit PC3 may be disposed on the buffer layer 201. The first pixel circuit PC1 may include a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE and a drain electrode DE. Fig.16 The thin film transistor TFT shown in FIG. 1 may correspond to the reference Fig.15 The first thin film transistor T1 described. Fig.16 , but the data line DL may be electrically connected to the second thin film transistor included in the first pixel circuit PC1. Although in this embodiment, a top gate type in which the gate electrode GE is disposed on the semiconductor layer Act and the gate insulating layer 203 is between the gate electrode GE and the semiconductor layer Act is described, the present disclosure is not limited thereto, and according to another embodiment, the thin film transistor TFT may be a bottom gate type. The second pixel circuit PC2, the third pixel circuit PC3, and the first pixel circuit PC1 may have the same or similar structures. The respective constituent elements of the first pixel circuit PC1 are described.

[0137] The semiconductor layer Act may include polycrystalline silicon. In another embodiment, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, an organic semiconductor, etc. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material such as Mo, Al, Cu, Ti, etc., and may be formed as a multilayer or single layer including the above materials.

[0138] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as SiO x 、SiN x , SiON, Alumina (Al 2 O 3 ), titanium oxide (TiO x ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) etc. The gate insulating layer 203 may be a single layer or multiple layers including the above materials.

[0139] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 overlapping each other in a plan view with a first interlayer insulating layer 205 therebetween. In a plan view, the storage capacitor Cst may overlap the thin film transistor TFT. Fig.16 It is shown that the gate electrode GE of the thin film transistor TFT is the lower electrode CE1 of the storage capacitor Cst, but the present disclosure is not limited thereto. In another embodiment, in a plan view, the storage capacitor Cst may not overlap with the thin film transistor TFT. The storage capacitor Cst may be covered by the second interlayer insulating layer 207. The upper electrode CE2 of the storage capacitor Cst may include a conductive material such as Mo, Al, Cu, Ti, etc., and may be formed as a multilayer or single layer including the above materials.

[0140] The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may each include an inorganic insulating material such as SiO x 、SiN x 、SiON、Al 2 O 3 、TiO x 、 2 O 5 , HfO 2 The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may each be a single layer or a multilayer including the above-mentioned materials.

[0141] The source electrode SE, the drain electrode DE, and the data line DL may be located on the same layer and may include the same material. For example, the source electrode SE, the drain electrode DE, and the data line DL may be located on the second interlayer insulating layer 207. The source electrode SE, the drain electrode DE, and the data line DL may include a material having excellent conductivity. The source electrode SE and the drain electrode DE may each include a conductive material such as Mo, Al, Cu, Ti, etc., and may be formed as a multilayer or a single layer including the above materials. In an embodiment, the source electrode SE, the drain electrode DE, and the data line DL may be formed as a multilayer of Ti / Al / Ti.

[0142] The first, second, and third pixel circuits PC1, PC2, and PC3, each including a thin film transistor TFT and a storage capacitor Cst, may be covered by a first organic insulating layer 209. The first organic insulating layer 209 may include an upper surface having an approximately flat surface.

[0143] A first organic light emitting diode OLED1 electrically connected to the first pixel circuit PC1 , a second organic light emitting diode OLED2 electrically connected to the second pixel circuit PC2 , and a third organic light emitting diode OLED3 electrically connected to the third pixel circuit PC3 may be located over the first organic insulating layer 209 .

[0144] The first pixel circuit PC1 may be electrically connected to the first pixel electrode 221r ​​of the first organic light emitting diode OLED1. Fig.16 As shown in , the contact metal layer CM may be disposed between the thin film transistor TFT and the first pixel electrode 221r. The contact metal layer CM may be connected to the thin film transistor TFT through a contact hole passing through the first organic insulating layer 209. The first pixel electrode 221r ​​may be connected to the contact metal layer CM through a contact hole passing through the second organic insulating layer 211 on the contact metal layer CM. The contact metal layer CM may include a conductive material such as Mo, Al, Cu, Ti, etc., and may be formed as a multilayer or a single layer including the above materials. In an embodiment, the contact metal layer CM may be formed as a multilayer of Ti / Al / Ti.

[0145] The first organic insulating layer 209 and the second organic insulating layer 211 may each include a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, or a blend thereof. In an embodiment, the first organic insulating layer 209 and the second organic insulating layer 211 may include polyimide.

[0146] According to another embodiment, one of the first organic insulating layer 209 and the second organic insulating layer 211 may be omitted, and the contact metal layer CM may be omitted.

[0147] The first organic light emitting diode OLED1 may include a first pixel electrode 221r, a first emission layer 222r, and a first opposing electrode 223r. The second organic light emitting diode OLED2 may include a second pixel electrode 221g, a second emission layer 222g, and a second opposing electrode 223g. The third organic light emitting diode OLED3 may include a third pixel electrode 221b, a third emission layer 222b, and a third opposing electrode 223b. The second organic light emitting diode OLED2, the third organic light emitting diode OLED3, and the first organic light emitting diode OLED1 may have the same or similar structure.

[0148] The first pixel electrode 221r ​​may be disposed on the second organic insulating layer 211. The first pixel electrode 221r ​​may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). In another embodiment, the first pixel electrode 221r ​​may include a reflective film, and the reflective film includes silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. In another embodiment, the first pixel electrode 221r ​​may also include ITO, IZO, ZnO or In above / below the above-mentioned reflective film. 2 O 3 The film formed.

[0149] The pixel defining layer 213 and the bank layer 215 may be disposed on the first pixel electrode 221r. The pixel defining layer 213 may overlap an edge of the first pixel electrode 221r ​​in a direction substantially perpendicular to the substrate 100 (z-axis direction). The pixel defining layer 213 may include an inorganic insulating material such as SiN x , SiON or SiO x .

[0150] The first remaining sacrificial layer 212R may be located between the first pixel electrode 221r ​​and the pixel defining layer 213. The first remaining sacrificial layer 212R may be a portion remaining after removing the sacrificial layer for protecting the upper surface of the first pixel electrode 221r. The first remaining sacrificial layer 212R may be located in a region where the pixel defining layer 213 and the first pixel electrode 221r ​​overlap each other in a direction (z-axis direction) substantially perpendicular to the substrate 100. For example, the first remaining sacrificial layer 212R may be located along an edge of the first pixel electrode 221r ​​to expose a central portion of the first pixel electrode 221r.

[0151] The first remaining sacrificial layer 212R may be formed continuously with the first pixel electrode 221r ​​and may include a selectively etchable material that does not damage the first pixel electrode 221r. For example, the first remaining sacrificial layer 212R may include indium gallium zinc oxide (IGZO) and / or indium zinc oxide (IZO).

[0152] The first remaining sacrificial layer 212R and the pixel defining layer 213 overlapping the edge of the first pixel electrode 221r ​​can increase the distance between the first pixel electrode 221r ​​and the first opposing electrode 223r and the bank layer 215, thereby preventing arcing, etc. from being generated therebetween. In an embodiment, when the sacrificial layer is completely removed, the first remaining sacrificial layer 212R may not exist. The recess generated between the first pixel electrode 221r ​​and the pixel defining layer 213 by removing the sacrificial layer may be empty or filled with the first emission layer 222r described below.

[0153] The bank layer 215 may be disposed on the pixel defining layer 213. The bank layer 215 may include a conductive material. For example, the bank layer 215 may include a conductive material such as Mo, Al, Cu, Ti, etc., and may be formed as a multilayer or single layer including the above materials. For example, the bank layer 215 may have a double layer of Al / Ti or a triple layer of Ti / Al / Ti.

[0154] The pixel defining layer 213 and the bank layer 215 may extend from the display area DA of the substrate 100 to the peripheral area PA (see FIG. Fig.14 ), and the bank layer 215 can directly contact the peripheral area PA (see Fig.14 ) in the common power supply wiring 16 (see Fig.14 ). Therefore, the bank layer 215 may function as a connection electrode or an auxiliary wiring for transmitting the common voltage ELVSS to a first opposing electrode 223r, a second opposing electrode 223g, and a third opposing electrode 223b described below.

[0155] The first conductive layer 217 may be disposed on the bank layer 215. The first conductive layer 217 may have a tip 217T protruding outward relative to the center of the first pixel electrode 221r. In a plan view (in a direction perpendicular to the upper surface of the substrate 100 (z-axis direction)), the tip 217T of the first conductive layer 217 may have a ring shape completely surrounding the first pixel electrode 221r.

[0156] The first opening OP1 may expose the upper surface of the central portion of the first pixel electrode 221r ​​through the pixel defining layer 213, the bank layer 215, and the first conductive layer 217, and the first emission layer 222r described below may overlap and contact the first pixel electrode 221r ​​through the first opening OP1. Therefore, the first opening OP1 may define a first emission area EA1. The outside of the first emission area EA1 may be defined as a non-emission area NEA. Similarly, the second opening OP2 may define a second emission area EA2, and the third opening OP3 may define a third emission area EA3.

[0157] A portion of the first conductive layer 217 may form a tip 217T, which is spaced apart from the bank layer 215 in a direction perpendicular to the substrate 100 (z-axis direction) and protrudes outward relative to the center of the first pixel electrode 221r. When the tip 217T of the first conductive layer 217 is formed as a portion of the sacrificial layer disposed between the first conductive layer 217 and the bank layer 215 is removed, the first conductive layer 217 may have an undercut structure. Therefore, the tip 217T of the first conductive layer 217 may form an eaves structure in which its lower surface is exposed. The protruding length of the tip 217T of the first conductive layer 217 may be greater than or equal to about 0.5 μm. In an embodiment, the protruding length of the tip 217T of the first conductive layer 217 may be in the range of about 0.3 μm to about 1 μm. In an embodiment, the protruding length of the tip 217T of the first conductive layer 217 may be in the range of about 0.3 μm to about 0.7 μm.

[0158] The first conductive layer 217 may include a conductive material. For example, the first conductive layer 217 may include a conductive material such as Mo, Al, Cu, Ti, etc., and may be formed as a multilayer or single layer including the above materials. For example, the first conductive layer 217 may have a double layer of Al / Ti or a triple layer of Ti / Al / Ti.

[0159] In an embodiment, a low-reflective layer (not shown) may be provided on the first conductive layer 217. The low-reflective layer may be a layer having a surface reflectivity lower than that of the first conductive layer 217. The low-reflective layer may prevent light (external light) input toward the display device 2 from being reflected by the surface of the first conductive layer 217 and being perceived by a user of the display device 2.

[0160] In an embodiment, the low reflection layer may include a low reflection material. The low reflection material may include a metal oxide having a high light absorbance (eg, a high extinction coefficient k). For example, the low reflection layer may include copper oxide (CuO), calcium oxide (CaO), molybdenum oxide (MoO x In an embodiment, the low reflection layer may include a material in which CuO and CaO are mixed.

[0161] The second remaining sacrificial layer 214R may be disposed between the first conductive layer 217 and the bank layer 215. The second remaining sacrificial layer 214R may be a remaining portion of the sacrificial layer that is removed to form the tip 217T of the first conductive layer 217. The second remaining sacrificial layer 214R may be spaced a certain distance from the first pixel electrode 221r ​​in a plan view (in a direction (z-axis direction) substantially perpendicular to the substrate 100), and may have a ring shape that completely surrounds the first pixel electrode 221r. Due to the second remaining sacrificial layer 214R, the first conductive layer 217 may have an undercut structure.

[0162] The second remaining sacrificial layer 214R may determine a protruding length of a tip 217T of the first conductive layer 217. For example, the second remaining sacrificial layer 214R may be located inside an end of a tip 217T of the first conductive layer 217, and the protruding length of the tip 217T may be a length from a sidewall of the second remaining sacrificial layer 214R to an end of the tip 217T.

[0163] The second remaining sacrificial layer 214R may include a selectively etchable material that does not damage the first pixel electrode 221r, the bank layer 215, and the first conductive layer 217. For example, the second remaining sacrificial layer 214R and the first remaining sacrificial layer 212R may include the same material. The second remaining sacrificial layer 214R may include IGZO and / or IZO.

[0164] The first emission layer 222r may be arranged on the first pixel electrode 221r ​​and the first conductive layer 217. For example, the first emission layer 222r may be arranged to contact the first pixel electrode 221r ​​through the first opening OP1. The first pixel electrode 221r ​​may include a polymer or a low molecular weight organic material that emits light of a first color (e.g., red). In another embodiment, the first emission layer 222r may include an inorganic material or a quantum dot.

[0165] The first emission layer 222r may include a first functional layer (not shown) and a second functional layer (not shown) above and / or below the first functional layer. The first functional layer may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0166] although Fig.16 A single stacked structure including a single emission layer is shown, but the present disclosure is not limited thereto, and in another embodiment, the display device 2 may have a column structure as a plurality of stacked structures including a plurality of emission layers. In the column structure, the charge generation layer may be arranged between the plurality of stacks.

[0167] The first emission layer 222r may be separated from the dummy portion 222rp by the tip 217T of the first conductive layer 217. The first emission layer 222r and the dummy portion 222rp may include sublayers (eg, first functional layer, second functional layer, etc.) having the same material and / or the same number.

[0168] The first emission layer 222 r may have at least one first hole 222 rh exposing a portion of the upper surface of the first conductive layer 217 .

[0169] The second emission layer 222g may include a polymer or a low molecular weight organic material that emits light of a second color (eg, green), and the third emission layer 222b may include a polymer or a low molecular weight organic material that emits light of a third color (eg, blue).

[0170] The first opposing electrode 223r may be separated from the dummy portion 223rp by a tip 217T of the first conductive layer 217. The first opposing electrode 223r and the dummy portion 223rp may include the same material.

[0171] The first opposing electrode 223r may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), alloys thereof, etc. In an embodiment, the first opposing electrode 223r may further include a (semi) transparent layer including ITO, IZO, ZnO or In 2 O 3 layer.

[0172] The first inorganic encapsulation layer 311 may be disposed on the first relative electrode 223r. Since the first inorganic encapsulation layer 311 has relatively excellent step coverage, the first inorganic encapsulation layer 311 may cover at least a portion of the exposed lower surface of the tip 217T of the first conductive layer 217. For example, the first inorganic encapsulation layer 311 may be continuously formed to cover the upper and side surfaces of the first relative electrode 223r, the side surface of the first emission layer 222r, the side surface and lower surface of the tip 217T of the first conductive layer 217, the side surface of the second remaining sacrificial layer 214R, and the upper surface of the bank layer 215.

[0173] The first inorganic encapsulation layer 311 may include an inorganic insulating material such as SiN x , SiON and SiOx The first inorganic encapsulation layer 311 may directly contact the metal surface in the side surface and the lower surface of the tip 217T of the first conductive layer 217, thereby forming an inorganic contact region ICR. Therefore, the inorganic contact region ICR may form a closed ring completely surrounding the first organic light emitting diode OLED1, thereby reducing or preventing a path along which impurities such as moisture and / or air penetrate.

[0174] like Fig.16 As shown in FIG. 1 , the second inorganic encapsulation layer 312 may seal the second organic light emitting diode OLED2, and the third inorganic encapsulation layer 313 may seal the third organic light emitting diode OLED3. When the first inorganic encapsulation layer 311, the second inorganic encapsulation layer 312, and the third inorganic encapsulation layer 313 form the inorganic contact region ICR in the display area DA, the peripheral area PA (see FIG. 1 ) necessary for reducing the delamination defect caused by the emission layer may be reduced. Fig.14 ) In addition, since the organic light emitting diode is sealed in units of pixels, even if a path along which impurities such as moisture and / or air penetrate occurs at the boundary of one pixel or the substrate 100, defects can be prevented from being transferred to adjacent pixels.

[0175] The organic planarization layer 410 may be arranged to cover the first inorganic encapsulation layer 311, the second inorganic encapsulation layer 312, and the third inorganic encapsulation layer 313. The organic planarization layer 410 may cover the unevenness caused by the pixel defining layer 213, the bank layer 215, and the first conductive layer 217, thereby providing a flat base surface for the constituent elements arranged above the organic planarization layer 410. The organic planarization layer 410 may include a polymer-based material. For example, the organic planarization layer 410 may include an acrylic resin, an epoxy resin, a polyimide, polyethylene, etc.

[0176] In an embodiment, the refractive index of the organic planarization layer 410 may be greater than the refractive index of the first inorganic encapsulation layer 311, the second inorganic encapsulation layer 312, and the third inorganic encapsulation layer 313. For example, the refractive index of the organic planarization layer 410 may be greater than or equal to about 1.6. The refractive index of the organic planarization layer 410 may be in the range of about 1.6 to about 1.9. The organic planarization layer 410 may also include dispersed particles for high refraction. For example, metal oxide particles (such as zinc oxide (ZnO x ), titanium oxide (TiO 2 )、ZrO 2 ), barium titanate (BaTiO 3 ) etc.) may be dispersed in the organic planarization layer 410 .

[0177] The protective layer 420 may be disposed on the organic planarization layer 410. The protective layer 420 may include an inorganic insulating material such as SiNx , SiON and SiO x In an implementation, the refractive index of the protection layer 420 may be lower than the refractive index of the organic planarization layer 410 .

[0178] The anti-reflection layer 500 including the first color filter 510, the second color filter 520, the third color filter 530, the light shielding layer 540 and the overcoat layer 550 may be disposed on the protective layer 420. The anti-reflection layer 500 may reduce reflectivity of light (external light) incident on the display device 2 from the outside.

[0179] The light shielding layer 540 may overlap with the bank layer 215 and the first conductive layer 217 in a plan view, and therefore, the light shielding layer 540 at least partially absorbs light reflected by the bank layer 215 and the first conductive layer 217 in the non-emission area NEA. The non-emission area NEA may be an area that does not overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3. The light shielding layer 540 may include a black pigment. The light shielding layer 540 may be a black matrix. The light shielding layer 540 may have a first filter opening 540OP1 corresponding to the first emission area EA1, a second filter opening 540OP2 corresponding to the second emission area EA2, and a third filter opening 540OP3 corresponding to the third emission area EA3.

[0180] The first color filter 510 may be located within the first filter opening 540OP1 to correspond to the first emission layer 222r disposed below the first color filter 510. The first color filter 510 may selectively transmit light emitted from the first emission layer 222r. Fig.16 The first color filter 510 shown in FIG. 5 may be a red color filter that transmits red light.

[0181] Likewise, the second color filter 520 may be located within the second filter opening 540OP2 to correspond to the second emission layer 222g. The second color filter 520 may selectively transmit light emitted from the second emission layer 222g. The third color filter 530 may be located within the third filter opening 540OP3 to correspond to the third emission layer 222b. The third color filter 530 may selectively transmit light emitted from the third emission layer 222b. For example, Fig.16 The second color filter 520 shown in FIG. 5 may be a green color filter that transmits green light, and the third color filter 530 may be a blue color filter that transmits blue light.

[0182] An overcoat layer 550 may be disposed on the first color filter 510, the second color filter 520, and the third color filter 530. The overcoat layer 550, which is a light-transmitting layer, may cover unevenness caused by the first color filter 510, the second color filter 520, and the third color filter 530 and the light-shielding layer 540, thereby providing a flat upper surface. The overcoat layer 550 may include a colorless light-transmitting organic material, such as an acrylic-based resin.

[0183] According to an embodiment, in an apparatus for manufacturing a display device, manufacturing speed and manufacturing quality may be improved.

[0184] The effects of the present disclosure are not limited to the above-mentioned effects, and other various effects not described in the present specification can be clearly understood from the following description by those skilled in the art to which the present disclosure belongs.

[0185] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure belongs will be able to make various modifications and changes.Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0186] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the attached claims, and it should be understood that all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. An apparatus for manufacturing a display device, characterized in that The device comprises: room; a mask assembly disposed in the chamber and facing the display substrate; a magnetic force portion disposed in the chamber and applying a magnetic force to the mask assembly; and a deposition source disposed in the chamber, facing the mask assembly, and supplying a deposition material that passes through the mask assembly to be deposited on the display substrate, wherein The mask assembly comprises: a first mask layer having a first mask opening formed therein; and a second mask layer, disposed on the first mask layer, The second mask layer comprises: a metal layer having a metal opening formed therein; and an inorganic layer disposed on the metal layer and having an inorganic opening overlapping the first mask opening in a plan view, and The metal opening overlaps the inorganic opening in a plan view.

2. The device for manufacturing a display device according to claim 1, characterized in that: In a plan view, the metal layer surrounds the inorganic opening.

3. The device for manufacturing a display device according to claim 1, characterized in that: At least a portion of the inorganic layer is disposed within the metal opening.

4. The apparatus for manufacturing a display device according to claim 1, characterized in that: The metal layer includes a plurality of metal layers.

5. The device for manufacturing a display device according to claim 4, characterized in that: In a plan view, the plurality of metal layers are spaced apart from each other by a certain distance.

6. The apparatus for manufacturing a display device according to claim 4, characterized in that: In a cross-sectional view, at least a portion of the inorganic layer is disposed between the plurality of metal layers.

7. The apparatus for manufacturing a display device according to claim 1, characterized in that: A lower surface of the metal layer is exposed from the inorganic layer.

8. The apparatus for manufacturing a display device according to claim 1, characterized in that: The inorganic layer covers an upper surface of the metal layer.

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