Low-dropout linear voltage stabilizing circuit

Abstract

The utility model relates to a low-dropout linear voltage stabilizing circuit. The low-dropout linear voltage stabilizing circuit comprises a front-stage low-dropout linear voltage stabilizing module and one or more rear-stage low-dropout linear voltage stabilizing modules in cascade connection with the front-stage low-dropout linear voltage stabilizing module. The preceding-stage low-dropout linear voltage stabilization module is configured to generate a stable first output voltage which serves as a power supply voltage to be provided for the backward-stage low-dropout linear voltage stabilization module. The rear-stage low-dropout linear voltage stabilization module is configured to generate stable output voltage under the power supply of the first output voltage; wherein the front-stage low-dropout linear voltage stabilization module adopts a current mode buffer compensation structure so as to improve the frequency stability; the rear-stage low-dropout linear voltage stabilization module is provided with an inverted source follower, and the output of the inverted source follower is connected to the control end of the second power adjustment tube so as to improve the circuit bandwidth. According to the low-dropout linear voltage stabilizing circuit, the frequency stability, the output voltage stability and the circuit bandwidth of the low-dropout linear voltage stabilizing circuit are improved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a low voltage difference linear voltage stabilization circuit. Background Art

[0002] At present, low dropout linear regulator (LDO) adopts low dropout linear voltage regulation structure, has high stability, fast dynamic response and high efficiency power supply characteristics, which makes it widely used. For example, it can be used in battery-powered products such as portable devices (such as smart phones, tablet computers, notebook computers, etc.) for effective power management.

[0003] Therefore, designing a low-dropout linear regulator with high frequency stability is critical to the overall performance of the device. Utility Model Content

[0004] In view of this, an embodiment of the present application provides a low voltage difference linear voltage regulator circuit to solve at least one problem existing in the background technology.

[0005] The embodiment of the present application provides a low voltage difference linear voltage regulator circuit, the low voltage difference linear voltage regulator circuit comprising a front-stage low voltage difference linear voltage regulator module and one or more rear-stage low voltage difference linear voltage regulator modules cascaded with the front-stage low voltage difference linear voltage regulator module;

[0006] The front-stage low voltage difference linear voltage regulator module is configured to generate a stable first output voltage to be provided to the rear-stage low voltage difference linear voltage regulator module as a power supply voltage;

[0007] The post-stage low voltage difference linear voltage regulator module is configured to generate a stable output voltage under the power supply of the first output voltage;

[0008] Among them, the front-stage low-voltage difference linear voltage regulator module adopts a current-mode buffer compensation structure to improve frequency stability; the rear-stage low-voltage difference linear voltage regulator module is provided with an inverted source follower, and the output of the inverted source follower is connected to the control end of the second power adjustment tube to improve the circuit bandwidth.

[0009] In an optional implementation, the front-stage low voltage drop linear voltage regulator module includes:

[0010] A first error amplification module is configured to use the first reference signal and the first feedback signal as inputs of the first error amplification module to obtain a first control signal;

[0011] A first power adjustment tube is configured to determine a turn-on or turn-off state according to the first control signal to control the output of a first output voltage; and

[0012] The resistor feedback network is configured to generate the first feedback signal according to the first output voltage division.

[0013] In an optional implementation, the first error amplification module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth NMOS transistor and a ninth NMOS transistor; the first power adjustment tube includes a tenth PMOS transistor; the resistor feedback network includes a first resistor and a second resistor;

[0014] The gate of the first NMOS transistor is configured to input a first feedback signal, and the gate of the second NMOS transistor is configured to input a first reference signal; the source of the first NMOS transistor and the source of the second NMOS transistor are respectively connected to the drain of the third NMOS transistor, and the gate of the third NMOS transistor is configured to input a start control signal; the drain of the first NMOS transistor is respectively connected to the drain of the fourth PMOS transistor and the source of the sixth PMOS transistor, and the drain of the second NMOS transistor is respectively connected to the drain of the fifth PMOS transistor and the source of the seventh PMOS transistor; the gate of the fourth PMOS transistor and the gate of the fifth PMOS transistor are respectively connected to the drain of the fourth PMOS transistor and the source of the sixth PMOS transistor. The first bias signal is input, and the gate of the sixth PMOS transistor and the gate of the seventh PMOS transistor are respectively configured to input the second bias signal; the drain of the sixth PMOS transistor is respectively connected to the drain of the eighth NMOS transistor, the gate of the eighth NMOS transistor and the gate of the ninth NMOS transistor, and the drain of the seventh PMOS transistor is connected to the drain of the ninth NMOS transistor and is configured to output the first control signal; the source of the fourth PMOS transistor and the source of the fifth PMOS transistor are respectively connected to the circuit power supply terminal, and the source of the third NMOS transistor, the source of the eighth NMOS transistor and the source of the ninth NMOS transistor are respectively connected to the circuit ground terminal;

[0015] The gate of the tenth PMOS transistor is configured to input the first control signal, the source of the tenth PMOS transistor is connected to the circuit power supply terminal, and the drain of the tenth PMOS transistor is configured to output the first output voltage;

[0016] The first end of the first resistor is configured to input the first output voltage, the second end of the first resistor is connected to the first end of the second resistor and configured to output the first feedback signal, and the second end of the second resistor is connected to the circuit ground.

[0017] In an optional implementation manner, the front-stage low voltage difference linear voltage regulator module further includes a first Miller compensation capacitor;

[0018] A first end of the first Miller compensation capacitor is connected to the drain of the fifth PMOS transistor, and a second end of the first Miller compensation capacitor is connected to the drain of the tenth PMOS transistor.

[0019] In an optional implementation, the post-stage low voltage dropout linear voltage regulator module includes:

[0020] A second error amplification module is configured to use the second reference signal and the second feedback signal as inputs of the second error amplification module respectively to obtain a second control signal;

[0021] A second power adjustment tube is configured to determine a conduction or cutoff state according to the second control signal to control the output of the output voltage;

[0022] a current source feedback network configured to generate the second feedback signal according to the output voltage under the control of a current source; and

[0023] The buffer module is configured to control the voltage at the control end of the second power adjustment tube to change with the change of the second control signal to stabilize the output voltage.

[0024] In an optional implementation, the buffer module includes a twentieth PMOS transistor, a twenty-first PMOS transistor and a first current source;

[0025] The gate of the twenty-first PMOS transistor is configured to input the second control signal, the drain of the twenty-first PMOS transistor is respectively connected to the gate of the twentieth PMOS transistor and the first end of the first current source, the second end of the first current source is connected to the circuit ground, the source of the twenty-first PMOS transistor is connected to the drain of the twentieth PMOS transistor and is configured to output the third control signal, and the source of the twentieth PMOS transistor is configured to input the internal power supply voltage determined according to the first output voltage.

[0026] In an optional implementation, the second error amplification module includes an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth NMOS transistor and a nineteenth NMOS transistor; the second power adjustment tube includes a twenty-second PMOS transistor; the current source feedback network includes a second current source;

[0027] The gate of the eleventh NMOS transistor is configured to input the second feedback signal, and the gate of the twelfth NMOS transistor is configured to input the second reference signal; the source of the eleventh NMOS transistor and the source of the twelfth NMOS transistor are respectively connected to the drain of the thirteenth NMOS transistor, and the gate of the thirteenth NMOS transistor is configured to input the start control signal; the drain of the eleventh NMOS transistor is respectively connected to the drain of the fourteenth PMOS transistor and the source of the sixteenth PMOS transistor, and the drain of the twelfth NMOS transistor is respectively connected to the drain of the fifteenth PMOS transistor and the source of the seventeenth PMOS transistor; the gate of the fourteenth PMOS transistor and the gate of the fifteenth PMOS transistor are respectively configured to input the first bias signal, the gate of the sixteenth PMOS transistor and the gate of the seventeenth PMOS transistor are respectively configured to input the second bias signal; the drain of the sixteenth PMOS transistor is respectively connected to the drain of the eighteenth NMOS transistor, the gate of the eighteenth NMOS transistor and the gate of the nineteenth NMOS transistor, the drain of the seventeenth PMOS transistor is connected to the drain of the nineteenth NMOS transistor and is configured to output the second control signal; the source of the fourteenth PMOS transistor and the source of the fifteenth PMOS transistor are respectively configured to input the internal power supply voltage determined according to the first output voltage, the source of the thirteenth NMOS transistor, the source of the eighteenth NMOS transistor and the source of the nineteenth NMOS transistor are respectively connected to the circuit ground;

[0028] The gate of the twenty-second PMOS transistor is configured to input the third control signal, the source of the twenty-second PMOS transistor is configured to input the internal power supply voltage determined according to the first output voltage, and the drain of the twenty-second PMOS transistor is configured to output the second output voltage;

[0029] A first end of the second current source is connected to the drain of the twenty-second PMOS transistor and the gate of the eleventh NMOS transistor respectively, and a second end of the second current source is connected to the circuit ground.

[0030] In an optional implementation manner, the post-stage low voltage difference linear voltage regulator module further includes a second Miller compensation capacitor;

[0031] A first end of the second Miller compensation capacitor is connected to the drain of the fifteenth PMOS transistor, and a second end of the second Miller compensation capacitor is connected to the drain of the twenty-second PMOS transistor.

[0032] In an optional implementation, the low voltage difference linear voltage stabilization circuit further includes a low pass filter;

[0033] The low-pass filter is configured to perform low-pass filtering on the first output voltage and then provide the first output voltage to the subsequent low-voltage difference linear voltage regulator module.

[0034] In an optional implementation, the low-pass filter includes a filter resistor and a filter capacitor;

[0035] The first end of the filter resistor is configured to input the first output voltage, the second end of the filter resistor is connected to the first end of the filter capacitor and is configured to output the internal power supply voltage, and the second end of the filter capacitor is connected to the circuit ground.

[0036] The beneficial effects brought by the technical solution provided by the embodiment of the present application include: providing power supply voltage to the rear-stage low-voltage difference linear voltage regulator module through the front-stage low-voltage difference linear voltage regulator module to form a cascade, thereby improving the output voltage stability of the entire low-voltage difference linear voltage regulator circuit. In addition, the front-stage low-voltage difference linear voltage regulator module adopts a current mode buffer compensation structure to achieve compensation for the pole frequency and improve the frequency stability, such as being able to obtain frequency stability under the full range, and also improves the power supply rejection ratio, reduces the output voltage ripple and improves the output voltage stability, thereby also improving the output voltage stability of the entire low-voltage difference linear voltage regulator circuit. In addition, the rear-stage low-voltage difference linear voltage regulator module is provided with an inverted source follower, which improves the circuit bandwidth, thereby improving the transient response of the circuit.

[0037] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below and in part will become apparent from the description below or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application for those skilled in the art by referring to specific embodiments. In the drawings:

[0039] Figure 1 is a schematic diagram of a specific example of a low dropout linear regulator;

[0040] Figure 2 A principle block diagram of a specific example of a low voltage difference linear voltage regulator circuit in an embodiment of the present application;

[0041] Figure 3 A circuit diagram of a specific example of a front-stage low voltage difference linear voltage regulator module in an embodiment of the present application;

[0042] Figure 4A circuit diagram of a specific example of a low voltage difference linear voltage regulator circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the technical solutions and beneficial effects of the embodiments of the present application more obvious and easy to understand, the following is a detailed description by listing specific embodiments. Among them, the drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meaning as those in the technical field to which the embodiments of the present application belong.

[0044] It should be noted that the terms "first", "second", etc. can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. When describing "first", it does not mean that "second" necessarily exists; and when discussing "second", it does not mean that "first" necessarily exists in this application. The singular forms of "one", "one" and "said / the" may also be intended to include plural forms unless the context clearly indicates another way. The term "includes" is to determine the existence of the included features, but does not exclude the existence or addition of one or more other features. The term "and / or" includes any and all combinations of the relevant listed items. The term "multiple" means two or more. The term "connection" means that there is a transmission of electrical signals or data between the connected end and the connected end, which can be understood as "electrical connection", "communication connection", etc.

[0045] like Figure 1 As shown, the low voltage drop linear regulator mainly includes an error amplifier EA, a transistor M0, a first feedback resistor R f1 and the second feedback resistor R f2 Etc. The transistor M0 may include a P-type MOS transistor (metal oxide semiconductor field effect transistor), an N-type MOS transistor or a BJT transistor, etc., which has a control terminal, a first terminal and a second terminal. Its working principle is that under the control of the control signal input at the control terminal, the path between the first terminal and the second terminal is turned on or off to connect or block the signal transmission between the first terminal and the second terminal. For example, the first terminal may be a source or an emitter, and correspondingly, the second terminal may be a drain or a collector; or conversely, the first terminal may be a drain or a collector, and correspondingly, the second terminal may be a source or an emitter. The positive input terminal of the error amplifier EA is configured to input a reference voltage V ref The output end of the error amplifier EA is connected to the gate (or base) of the transistor M0, and the first end of the transistor M0 is connected to the first feedback resistor R f1 The first end of the first feedback resistor R is connected and configured to output a regulated voltage signal LDO. f1The second end of the second feedback resistor R f2 The first end is connected to the negative input terminal of the error amplifier EA, and the second feedback resistor R f2 The second end of transistor M0 is connected to the circuit ground, the second end of transistor M0 is connected to the power supply, and the load capacitor C L Across the first feedback resistor R f1 between the first end and the circuit ground.

[0046] The response process of the low-dropout linear regulator is as follows: when the load increases (from light load to heavy load), the load current I load For load capacitance C L The unloading will cause the voltage of the LDO output regulated voltage signal LDO to drop. At this time, the first feedback resistor R f1 , the second feedback resistor R f2 The negative feedback network composed of the error amplifier EA and the transistor M0 will increase the gate (or base) voltage of the transistor M0, thereby increasing the effect of the transistor M0 on the load capacitance C. L The charging current makes the output of the low-dropout linear regulator return to its normal value. Conversely, when the load decreases (from heavy load to light load), the negative feedback network will also reduce the load capacitance C of transistor M0. L The charging current flows through the first resistor R f1 and the second resistor R f2 The path to ground releases the load capacitance C L The charge on the LDO restores the output of the LDO to its normal value.

[0047] However, in a general low voltage drop linear regulator, the size of the transistor M0 is relatively large, and it has a relatively large parasitic capacitance, which easily forms a relatively high pole frequency, reduces the frequency stability, and leads to a relatively poor output voltage stability.

[0048] To this end, the present application provides a low voltage drop linear voltage regulator circuit that can improve frequency stability and output voltage stability, for example, can obtain frequency stability in the full range, and can be applied to battery-powered products such as portable devices. Figures 2 to 4 As shown, the low voltage difference linear voltage regulator circuit 01 includes a front-stage low voltage difference linear voltage regulator module 10 and one or more rear-stage low voltage difference linear voltage regulator modules 20 cascaded with the front-stage low voltage difference linear voltage regulator module 10;

[0049] The front-stage low voltage difference linear voltage regulator module 10 is configured to generate a stable first output voltage v1 to be provided as a power supply voltage to the rear-stage low voltage difference linear voltage regulator module 20;

[0050] The post-stage low voltage difference linear voltage regulator module 20 is configured to generate a stable output voltage under the power supply of the first output voltage v1;

[0051] Among them, the front-stage low-voltage difference linear voltage regulator module 10 adopts a current-mode buffer compensation structure to improve frequency stability; the rear-stage low-voltage difference linear voltage regulator module 20 is provided with an inverted source follower (FVF), and the output of the inverted source follower (FVF) is connected to the control end of the second power adjustment tube 22 to improve the circuit bandwidth.

[0052] The embodiment of the present application forms a cascade type LDO, and the front-stage low-voltage difference linear voltage regulator module 10 and the rear-stage low-voltage difference linear voltage regulator module 20 can both adopt a low-voltage difference linear voltage regulator structure. Since the rear-stage low-voltage difference linear voltage regulator module 20 utilizes the stable first output voltage output by the front-stage low-voltage difference linear voltage regulator module 10, the stability of the output voltage of the entire low-voltage difference linear voltage regulator circuit 01 is improved. The stable output voltage generated by each rear-stage low-voltage difference linear voltage regulator module 20 can be used as a low-ripple, clean stable voltage that can be provided by the low-voltage difference linear voltage regulator circuit 01, so that the low-voltage difference linear voltage regulator circuit 01 can provide one or more stable output voltages, such as the second output voltage vout,..., the third output voltage vout'. The load resistor RL and the load capacitor CL can be the load of the entire low-voltage difference linear voltage regulator circuit 01.

[0053] In the case where a front-stage low-voltage difference linear voltage regulator module 10 is cascaded with a rear-stage low-voltage difference linear voltage regulator module 20, the front-stage low-voltage difference linear voltage regulator module 10 can be the first stage, and the rear-stage low-voltage difference linear voltage regulator module 20 can be the second stage. The first stage can output a stable first output voltage to the second stage to be used as a power supply voltage. For example, the circuit power supply terminal vdda of the entire low-voltage difference linear voltage regulator circuit 01 can provide a power supply voltage of 1.65V-1.95V, and the first stage can obtain a power supply voltage of 1.65V-1.95V from the circuit power supply terminal vdda. The first stage can output a stable first output voltage v1 of 1.5V. After passing through the first stage, the first output voltage v1 can be provided to the second stage as a power supply voltage. The second stage can output a stable second output voltage vout of 1.2V. Finally, the second output voltage vout can be used as the output voltage of the low-voltage difference linear voltage regulator circuit 01.

[0054] The front-stage low-voltage difference linear voltage regulator module 10 and the rear-stage low-voltage difference linear voltage regulator module 20 can respectively adopt a current-mode buffer compensation structure, which can overcome the defect of easily forming a higher pole frequency due to the large size of the power adjustment tube, and can reduce the pole frequency, thereby improving the frequency stability. In addition to using the first output voltage v1 of the front-stage low-voltage difference linear voltage regulator module 10 as the power supply voltage, the other circuit structures of the rear-stage low-voltage difference linear voltage regulator module 20 can be the same. The current-mode buffer compensation structure can be set according to actual needs to obtain a specified, preset desired frequency stability (such as frequency stability under the full range). For example, the differential operational amplifier in the low-voltage difference linear voltage regulator structure can be used to construct a current-mode buffer compensation structure. And based on the output of the current-mode buffer compensation structure, the compensation of the power adjustment tube control end (such as the gate of the MOS tube) is formed, and the power supply rejection ratio is also improved, and a low-ripple, clean output voltage can be provided, which further improves the stability of the output voltage.

[0055] The post-stage low voltage drop linear regulator module 20 is provided with an inverted source follower (FVF). The FVF structure has a very small output impedance, so it will generate a high-frequency pole at the control end of the second power adjustment tube 22, so that the circuit has a large bandwidth, thereby improving the transient response of the circuit.

[0056] The embodiment of the present application provides power supply voltage to the subsequent low-voltage difference linear voltage regulator module through the previous low-voltage difference linear voltage regulator module to form a cascade, thereby improving the output voltage stability of the entire low-voltage difference linear voltage regulator circuit. In addition, the previous low-voltage difference linear voltage regulator module adopts a current mode buffer compensation structure to achieve compensation for the pole frequency and improve frequency stability, such as obtaining frequency stability under the full range, and also improves the power supply rejection ratio, reduces the output voltage ripple and improves the output voltage stability, thereby also improving the output voltage stability of the entire low-voltage difference linear voltage regulator circuit. In addition, the subsequent low-voltage difference linear voltage regulator module is provided with an inverted source follower, which improves the circuit bandwidth, thereby improving the transient response of the circuit.

[0057] In an alternative embodiment, if Figure 3 As shown, the front-stage low voltage difference linear voltage regulator module 10 includes:

[0058] The first error amplification module 11 is configured to use the first reference signal vref1 and the first feedback signal as inputs of the first error amplification module 11 to obtain a first control signal k1;

[0059] A first power adjustment tube 12 is configured to determine a turn-on or turn-off state according to a first control signal k1 to control the output of a first output voltage v1; and

[0060] The resistor feedback network 13 is configured to generate a first feedback signal according to a voltage division of the first output voltage v1.

[0061] In the embodiment of the present application, the first error amplification module 11 can use the differential operational amplifier in the low voltage difference linear voltage stabilization structure as the differential operational amplifier of the current mode buffer compensation structure, input the first reference signal vref1 and the first feedback signal into the current mode buffer compensation structure, and connect the output end of the current mode buffer compensation structure to the control end of the first power adjustment tube 12, so that the first power adjustment tube 12 can be controlled by the output of the current mode buffer compensation structure (i.e., the first control signal k1) to turn on or off, thereby controlling the output of the first output voltage v1. The resistor feedback network 13 can be set according to actual needs. The error amplifier is formed by the current mode buffer compensation structure, which simplifies the circuit structure, saves costs, and improves frequency stability, power supply rejection ratio and output voltage stability.

[0062] The first power adjustment tube 12 may include a PMOS transistor (P-type metal oxide semiconductor field effect transistor), an NMOS transistor or a BJT transistor, etc., which has a control terminal, a first terminal and a second terminal. Its working principle is that under the control of the control signal input to the control terminal, the path between the first terminal and the second terminal is turned on or off to connect or block the signal transmission between the first terminal and the second terminal. For example, the first terminal may be a source or an emitter, and correspondingly, the second terminal may be a drain or a collector; or conversely, the first terminal may be a drain or a collector, and correspondingly, the second terminal may be a source or an emitter. The first power adjustment tube 12 may also adopt a power transistor combination circuit including at least one of an NMOS transistor, a PMOS transistor and other transistors. The power transistor combination circuit may include a control terminal, a first signal terminal and a second signal terminal. Its working principle is that under the control of the control signal input to the control terminal, the path between the first signal terminal and the second signal terminal is turned on or off to connect or block the signal transmission between the first signal terminal and the second signal terminal.

[0063] The first reference signal vref1 may come from outside the low voltage drop linear voltage regulator circuit, for example, it may be provided by a reference voltage generator. The voltage of the first reference signal vref1 may be a zero-temperature reference voltage to improve stability.

[0064] In an alternative embodiment, if Figure 3 As shown, the first error amplification module 11 includes a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth PMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth NMOS transistor M8 and a ninth NMOS transistor M9; the first power adjustment tube 12 includes a tenth PMOS transistor mpass1; the resistor feedback network 13 includes a first resistor R1 and a second resistor R2;

[0065] The gate of the first NMOS transistor M1 is configured to input the first feedback signal, and the gate of the second NMOS transistor M2 is configured to input the first reference signal vref1; the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2 are respectively connected to the drain of the third NMOS transistor M3, and the gate of the third NMOS transistor M3 is configured to input the start control signal vb1; the drain of the first NMOS transistor M1 is respectively connected to the drain of the fourth PMOS transistor M4 and the source of the sixth PMOS transistor M6, and the drain of the second NMOS transistor M2 is respectively connected to the drain of the fifth PMOS transistor M5 and the source of the seventh PMOS transistor M7; the gate of the fourth PMOS transistor M4 and the gate of the fifth PMOS transistor M5 are respectively configured to input The first bias signal vbp1 is input, the gate of the sixth PMOS transistor M6 and the gate of the seventh PMOS transistor M7 are respectively configured to input the second bias signal vbp2; the drain of the sixth PMOS transistor M6 is respectively connected to the drain of the eighth NMOS transistor M8, the gate of the eighth NMOS transistor M8 and the gate of the ninth NMOS transistor M9, the drain of the seventh PMOS transistor M7 is connected to the drain of the ninth NMOS transistor M9 and is configured to output the first control signal k1; the source of the fourth PMOS transistor M4 and the source of the fifth PMOS transistor M5 are respectively connected to the circuit power supply terminal vdda, the source of the third NMOS transistor M3, the source of the eighth NMOS transistor M8 and the source of the ninth NMOS transistor M9 are respectively connected to the circuit ground terminal vsa;

[0066] The gate of the tenth PMOS transistor mpass1 is configured to input the first control signal k1, the source of the tenth PMOS transistor mpass1 is connected to the circuit power supply terminal vdda, and the drain of the tenth PMOS transistor mpass1 is configured to output the first output voltage v1;

[0067] The first end of the first resistor R1 is configured to input the first output voltage v1, the second end of the first resistor R1 is connected to the first end of the second resistor R2 and configured to output a first feedback signal, and the second end of the second resistor R2 is connected to the circuit ground vsa.

[0068] In the embodiment of the present application, the voltage value of the first reference signal vref1 may not be too high in actual engineering practice, for example, 1.2V, so by using NMOS transistors (first NMOS transistor M1 and second NMOS transistor M2) as input pairs, the upper limit of the voltage margin can be avoided to be insufficient. The fourth PMOS transistor M4, the fifth PMOS transistor M5, the sixth PMOS transistor M6, the seventh PMOS transistor M7, the eighth NMOS transistor M8 and the ninth NMOS transistor M9 form a single-stage folded common source and common gate structure, and the first NMOS transistor M1 and the second NMOS transistor M2 are combined to form an error amplifier EA, whose load is a diode structure. Compared with the cascode load, its output impedance is relatively low, which will cause a higher pole frequency to be generated at its output end, and its input common mode range upper limit is high. To this end, the above-mentioned defects can also be overcome by the current mode buffer compensation structure, so as to improve the frequency stability when the NMOS transistor is used as the input pair and the diode load.

[0069] The bias voltage is provided to the fourth PMOS transistor M4 and the fifth PMOS transistor M5 through the first bias signal vbp1, and the bias voltage is provided to the sixth PMOS transistor M6 and the seventh PMOS transistor M7 through the second bias signal vbp2. The third NMOS transistor M3 can be turned on or off by the start control signal vb1, so as to realize the start and stop control of the front-stage low-voltage difference linear voltage regulator module 10, thereby realizing the start and stop control of the entire low-voltage difference linear voltage regulator circuit 01. The start control signal vb1, the first bias signal vbp1 and the second bias signal vbp2 can be provided by the inside of the low-voltage difference linear voltage regulator circuit 01, or by a control device outside the low-voltage difference linear voltage regulator circuit 01. The control device can be programmable.

[0070] The tenth PMOS transistor mpass1 is a PMOS transistor and can be regarded as a second-stage amplifier, and the first-stage amplifier is an error amplifier formed by the first error amplifier module 11. The second-stage amplifier can be used as a common-source amplifier to improve the output voltage stability.

[0071] The first resistor R1 and the second resistor R2 in the resistor feedback network can be a single resistor or a plurality of resistors connected in series or in parallel, and can be set according to actual needs. The first output voltage v1 is Wherein, R1 represents the resistance value of the first resistor R1, R2 represents the resistance value of the second resistor R2, V ref1It indicates the voltage value of the first reference signal vref1. It can be seen that the multiple relationship between the first output voltage v1 and the first reference signal vref1 can be configured through the resistor feedback network. For example, a first output voltage v1 of 1.5V can be obtained under a first reference signal vref1 of 1.2V.

[0072] In an optional implementation, the front-stage low voltage difference linear voltage regulator module 10 further includes a first Miller compensation capacitor 14;

[0073] The first end of the first Miller compensation capacitor 14 is connected to the drain of the fifth PMOS transistor M5, and the second end of the first Miller compensation capacitor 14 is connected to the drain of the tenth PMOS transistor mpass1. By setting the first Miller compensation capacitor 14, the stability of the first output voltage v1 is improved. It should be understood by those skilled in the art that the first Miller compensation capacitor 14 can be a single capacitor Cc1, or a series-parallel circuit of multiple capacitors, or other circuits having the same function as a capacitor.

[0074] In an alternative embodiment, if Figure 4 As shown, the post-stage low voltage drop linear voltage regulator module 20 includes:

[0075] The second error amplification module 21 is configured to use the second reference signal vref2 and the second feedback signal as inputs of the second error amplification module 21 to obtain a second control signal k2;

[0076] The second power adjustment tube 22 is configured to determine the on or off state according to the second control signal k2 to control the output of the output voltage;

[0077] a current source feedback network 25 configured to generate a second feedback signal according to the output voltage under the control of the current source; and

[0078] The buffer module 23 is configured to control the voltage at the control end of the second power adjustment tube 22 to change with the change of the second control signal k2, so as to stabilize the output voltage.

[0079] In the embodiment of the present application, the second error amplification module 21 can use the differential operational amplifier in the low voltage difference linear voltage stabilization structure as the differential operational amplifier of the current mode buffer compensation structure, input the second reference signal vref2 and the second feedback signal into the current mode buffer compensation structure, and connect the output end of the current mode buffer compensation structure to the input end of the buffer module 23, and the output end of the buffer module 23 is connected to the control end of the second power adjustment tube 22, so that the second power adjustment tube 22 can be controlled by the output of the current mode buffer compensation structure (i.e., the second control signal k2) to turn on or off, thereby controlling the output of the output voltage. The current source feedback network 25 can be set according to actual needs to provide a second feedback signal by setting a current source in the feedback network. The current source can be set according to actual needs, for example, a current source load at the output end of the second power adjustment tube 22 can be set, and the current source load can be a PMOS constant current source, etc. The embodiment of the present application forms the error amplifier EA through the current mode buffer compensation structure, simplifies the circuit structure, saves costs, and improves frequency stability, power supply rejection ratio and output voltage stability.

[0080] The second error amplification module 21 and the first error amplification module 11 can be configured to have the same structure or different structures according to actual needs. If the structures of the two are the same, the first reference signal vref1 and the second reference signal vref2 can be configured to be the same, for example, they can be two identical reference voltages provided by the reference voltage generator, both of which are 1.2V. Similarly, if the structures of the two are different, the first reference signal vref1 and the second reference signal vref2 can be configured to be different.

[0081] The second power adjustment tube 22 may include a PMOS transistor (P-type metal oxide semiconductor field effect transistor), an NMOS transistor or a BJT transistor, etc., which has a control end, a first end and a second end. Its working principle is that under the control of the control signal input to the control end, the path between the first end and the second end is turned on or off to connect or block the signal transmission between the first end and the second end. For example, the first end may be a source or an emitter, and correspondingly, the second end may be a drain or a collector; or conversely, the first end may be a drain or a collector, and correspondingly, the second end may be a source or an emitter. The second power adjustment tube 22 may also adopt a power transistor combination circuit including at least one of an NMOS transistor, a PMOS transistor and other transistors.

[0082] In an alternative embodiment, if Figure 4 As shown, the buffer module 23 includes a twentieth PMOS transistor M20, a twenty-first PMOS transistor M21 and a first current source I1;

[0083] The gate of the twenty-first PMOS transistor M21 is configured to input the second control signal k2, the drain of the twenty-first PMOS transistor M21 is respectively connected to the gate of the twentieth PMOS transistor M20 and the first end of the first current source I1, the second end of the first current source I1 is connected to the circuit ground terminal vssa, the source of the twenty-first PMOS transistor M21 is connected to the drain of the twentieth PMOS transistor M20 and is configured to output the third control signal, and the source of the twentieth PMOS transistor M20 is configured to input the internal power supply voltage determined according to the first output voltage v1;

[0084] In the embodiment of the present application, the first current source I1 can be set according to actual needs, for example, a PMOS constant current source can be used. The twentieth PMOS transistor M20 and the twenty-first PMOS transistor M21 can also adopt a high-side power transistor combination circuit, which can be set according to actual needs. The high-side power transistor combination circuit can be a power transistor combination circuit in which a power transistor is combined between the positive pole of the power supply and the high voltage end of the load.

[0085] In an optional implementation, the second error amplification module 21 includes an eleventh NMOS transistor M11, a twelfth NMOS transistor M12, a thirteenth NMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth PMOS transistor M15, a sixteenth PMOS transistor M16, a seventeenth PMOS transistor M17, an eighteenth NMOS transistor M18 and a nineteenth NMOS transistor M19; the second power adjustment tube 22 includes a twenty-second PMOS transistor mpass2; the current source feedback network 25 includes a second current source I2;

[0086] The gate of the eleventh NMOS transistor M11 is configured to input the second feedback signal, and the gate of the twelfth NMOS transistor M12 is configured to input the second reference signal vref2; the source of the eleventh NMOS transistor M11 and the source of the twelfth NMOS transistor M12 are respectively connected to the drain of the thirteenth NMOS transistor M13, and the gate of the thirteenth NMOS transistor M13 is configured to input the start control signal vb1; the drain of the eleventh NMOS transistor M11 is respectively connected to the drain of the fourteenth PMOS transistor M14 and the source of the sixteenth PMOS transistor M16, and the drain of the twelfth NMOS transistor M12 is respectively connected to the drain of the fifteenth PMOS transistor M15 and the source of the seventeenth PMOS transistor M17; the gate of the fourteenth PMOS transistor M14 and the gate of the fifteenth PMOS transistor M15 are respectively configured to input the first bias signal signal vbp1, the gate of the sixteenth PMOS transistor M16 and the gate of the seventeenth PMOS transistor M17 are respectively configured to input the second bias signal vbp2; the drain of the sixteenth PMOS transistor M16 is respectively connected to the drain of the eighteenth NMOS transistor M18, the gate of the eighteenth NMOS transistor M18 and the gate of the nineteenth NMOS transistor M19, the drain of the seventeenth PMOS transistor M17 is connected to the drain of the nineteenth NMOS transistor M19 and is configured to output the second control signal k2; the source of the fourteenth PMOS transistor M14 and the source of the fifteenth PMOS transistor M15 are respectively configured to input the internal power supply voltage determined according to the first output voltage v1, the source of the thirteenth NMOS transistor M13, the source of the eighteenth NMOS transistor M18 and the source of the nineteenth NMOS transistor M19 are respectively connected to the circuit ground terminal vsa;

[0087] The gate of the twenty-second PMOS transistor mpass2 is configured to input the third control signal, the source of the twenty-second PMOS transistor mpass2 is configured to input the internal power supply voltage determined according to the first output voltage v1, and the drain mpass2 of the twenty-second PMOS transistor is configured to output the second output voltage vout;

[0088] A first end of the second current source I2 is respectively connected to the drain of the twenty-second PMOS transistor mpass2 and the gate of the eleventh NMOS transistor M11 , and a second end of the second current source I2 is connected to the circuit ground terminal vsa.

[0089] In the embodiment of the present application, the second error amplification module 21 has the same structure as the first error amplification module 11, so by the same token, by using NMOS transistors (the eleventh NMOS transistor M11 and the twelfth NMOS transistor M12) as input pairs, the upper limit of the voltage margin can be avoided to be insufficient. The fourteenth PMOS transistor M14, the fifteenth PMOS transistor M15, the sixteenth PMOS transistor M16, the seventeenth PMOS transistor M17, the eighteenth NMOS transistor M18 and the nineteenth NMOS transistor M19 form a single-stage folded common source and common gate structure, and the eleventh NMOS transistor M11 and the twelfth NMOS transistor M12 are combined to form an error amplifier EA, whose output impedance is relatively low, so through the current mode buffer compensation structure, the defects of high pole frequency and high upper limit of input common mode range can also be overcome, thereby improving frequency stability.

[0090] The bias voltage is provided to the fourteenth PMOS transistor M14 and the fifteenth PMOS transistor M15 through the first bias signal vbp1, and the bias voltage is provided to the sixteenth PMOS transistor M16 and the seventeenth PMOS transistor M17 through the second bias signal vbp2. The thirteenth NMOS transistor M13 can be turned on or off by the start control signal vb1, thereby realizing the start and stop control of the subsequent low voltage difference linear voltage regulator module 20, thereby also realizing the start and stop control of the entire low voltage difference linear voltage regulator circuit 01.

[0091] The second output voltage vout is fed back to the gate of the eleventh NMOS transistor as a second feedback signal. The twenty-second PMOS transistor mpass2 uses a PMOS transistor, thereby obtaining a cascaded dual PMOS transistor low voltage dropout linear regulator (2-PT LDO), which can provide a higher power supply rejection ratio (PSR). Figure 4Compared with the front-stage low-voltage difference linear voltage regulator module 10, the rear-stage low-voltage difference linear voltage regulator module 20 has an additional buffer in structure, including an inverted source follower (FVF) composed of the twentieth PMOS transistor M20 and the twenty-first PMOS transistor M21. The FVF structure has a very small output impedance, so it will generate a high-frequency pole at the gate end of the twenty-second PMOS transistor mpass2, so that the circuit has a large bandwidth, thereby improving the transient response of the circuit. When the load increases (from light load to heavy load), the second output voltage vout drops, and the current source feedback network plays a role at this time, which will increase the gate voltage of the twenty-first PMOS transistor M21, accelerate the release of the charge of the gate capacitance of the twenty-second PMOS transistor mpass2, and restore the second output voltage vout to a normal value; conversely, when the load decreases (from heavy load to light load), the twentieth PMOS transistor M20 is used for current compensation, so that the second output voltage vout is restored to a normal value, thereby improving the stability of the output voltage.

[0092] Since the output load of the 22nd PMOS transistor mpass2 of the post-stage low voltage difference linear regulator module 20 is a current source (such as 1μA-3μA), the output is equal to the input, so the second output voltage vout is equal to the voltage of the second reference signal vref2. For example, a second output voltage vout of 1.2V can also be obtained under a second reference signal vref2 of 1.2V.

[0093] In an optional implementation, the post-stage low voltage difference linear voltage regulator module 20 further includes a second Miller compensation capacitor 24;

[0094] The first end of the second Miller compensation capacitor 24 is connected to the drain of the fifteenth PMOS transistor M15, and the second end of the second Miller compensation capacitor 24 is connected to the drain of the twenty-second PMOS transistor mpass2. By setting the second Miller compensation capacitor 24, the stability of the second output voltage vout is improved. It should be understood by those skilled in the art that the second Miller compensation capacitor 24 can be a single capacitor Cc2, or a series-parallel circuit of multiple capacitors, or other circuits having the same function as a capacitor.

[0095] In an alternative embodiment, if Figure 4 As shown, the low voltage difference linear voltage regulator circuit 01 further includes a low pass filter 30;

[0096] The low-pass filter 30 is configured to perform low-pass filtering on the first output voltage v1 and then provide the first output voltage v1 to the subsequent low voltage difference linear voltage regulator module 20 .

[0097] In the embodiment of the present application, a low-pass filter is provided between the front and rear low-voltage difference linear voltage regulator modules to filter out high-frequency noise, thereby achieving better PSR performance.

[0098] In an optional embodiment, the low-pass filter 30 includes a filter resistor R and a filter capacitor C;

[0099] The first end of the filter resistor R is configured to input the first output voltage v1, the second end of the filter resistor R is connected to the first end of the filter capacitor C and is configured to output the internal power supply voltage, and the second end of the filter capacitor C is connected to the circuit ground terminal vssa.

[0100] In the embodiment of the present application, the low-pass filter 30 may be an RC low-pass filter, or may be other low-pass filters such as an RLC low-pass filter.

[0101] In the embodiment of the present application, the third NMOS transistor M3 and the thirteenth NMOS transistor M13, which can have a switch function, can also use other controllable semiconductor switch devices, which can be set according to actual needs. For example, the controllable semiconductor switch device can include at least one of BJT (bipolar junction transistor), SCR (silicon controlled rectifier), GTO (gate turn-off thyristor), MOSFET (metal oxide semiconductor field effect transistor, MOS tube for short), IGBT (insulated gate bipolar transistor), MCT (MOS controlled thyristor) and SIT (static induction transistor).

[0102] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes may be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A low voltage drop linear voltage regulator circuit, characterized in that: The low voltage difference linear voltage regulator circuit comprises a front-stage low voltage difference linear voltage regulator module and one or more rear-stage low voltage difference linear voltage regulator modules cascaded with the front-stage low voltage difference linear voltage regulator module; The front-stage low voltage difference linear voltage regulator module is configured to generate a stable first output voltage to be provided to the rear-stage low voltage difference linear voltage regulator module as a power supply voltage; The post-stage low voltage difference linear voltage regulator module is configured to generate a stable output voltage under the power supply of the first output voltage; Among them, the front-stage low-voltage difference linear voltage regulator module adopts a current-mode buffer compensation structure to improve frequency stability; the rear-stage low-voltage difference linear voltage regulator module is provided with an inverted source follower, and the output of the inverted source follower is connected to the control end of the second power adjustment tube to improve the circuit bandwidth.

2. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The front-stage low voltage difference linear voltage regulator module comprises: A first error amplification module is configured to use the first reference signal and the first feedback signal as inputs of the first error amplification module to obtain a first control signal; A first power adjustment tube is configured to determine a turn-on or turn-off state according to the first control signal to control the output of a first output voltage; and The resistor feedback network is configured to generate the first feedback signal according to the first output voltage division.

3. The low voltage difference linear voltage regulator circuit according to claim 2, characterized in that: The first error amplification module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth NMOS transistor and a ninth NMOS transistor; the first power adjustment tube includes a tenth PMOS transistor; the resistor feedback network includes a first resistor and a second resistor; The gate of the first NMOS transistor is configured to input a first feedback signal, and the gate of the second NMOS transistor is configured to input a first reference signal; the source of the first NMOS transistor and the source of the second NMOS transistor are respectively connected to the drain of the third NMOS transistor, and the gate of the third NMOS transistor is configured to input a start control signal; the drain of the first NMOS transistor is respectively connected to the drain of the fourth PMOS transistor and the source of the sixth PMOS transistor, and the drain of the second NMOS transistor is respectively connected to the drain of the fifth PMOS transistor and the source of the seventh PMOS transistor; the gate of the fourth PMOS transistor and the gate of the fifth PMOS transistor are respectively connected to the drain of the fourth PMOS transistor and the source of the sixth PMOS transistor. The first bias signal is input, and the gate of the sixth PMOS transistor and the gate of the seventh PMOS transistor are respectively configured to input the second bias signal; the drain of the sixth PMOS transistor is respectively connected to the drain of the eighth NMOS transistor, the gate of the eighth NMOS transistor and the gate of the ninth NMOS transistor, and the drain of the seventh PMOS transistor is connected to the drain of the ninth NMOS transistor and is configured to output the first control signal; the source of the fourth PMOS transistor and the source of the fifth PMOS transistor are respectively connected to the circuit power supply terminal, and the source of the third NMOS transistor, the source of the eighth NMOS transistor and the source of the ninth NMOS transistor are respectively connected to the circuit ground terminal; The gate of the tenth PMOS transistor is configured to input the first control signal, the source of the tenth PMOS transistor is connected to the circuit power supply terminal, and the drain of the tenth PMOS transistor is configured to output the first output voltage; The first end of the first resistor is configured to input the first output voltage, the second end of the first resistor is connected to the first end of the second resistor and configured to output the first feedback signal, and the second end of the second resistor is connected to the circuit ground.

4. The low voltage difference linear voltage regulator circuit according to claim 3, characterized in that: The front-stage low voltage difference linear voltage stabilization module also includes a first Miller compensation capacitor; A first end of the first Miller compensation capacitor is connected to the drain of the fifth PMOS transistor, and a second end of the first Miller compensation capacitor is connected to the drain of the tenth PMOS transistor.

5. The low voltage difference linear voltage regulator circuit according to any one of claims 1 to 4, characterized in that: The post-stage low voltage difference linear voltage regulator module comprises: A second error amplification module is configured to use the second reference signal and the second feedback signal as inputs of the second error amplification module respectively to obtain a second control signal; A second power adjustment tube is configured to determine a conduction or cutoff state according to the second control signal to control the output of the output voltage; a current source feedback network configured to generate the second feedback signal according to the output voltage under the control of a current source; and The buffer module is configured to control the voltage at the control end of the second power adjustment tube to change with the change of the second control signal to stabilize the output voltage.

6. The low voltage difference linear voltage regulator circuit according to claim 5, characterized in that: The buffer module includes a 20th PMOS transistor, a 21st PMOS transistor and a first current source; The gate of the twenty-first PMOS transistor is configured to input the second control signal, the drain of the twenty-first PMOS transistor is respectively connected to the gate of the twentieth PMOS transistor and the first end of the first current source, the second end of the first current source is connected to the circuit ground, the source of the twenty-first PMOS transistor is connected to the drain of the twentieth PMOS transistor and is configured to output the third control signal, and the source of the twentieth PMOS transistor is configured to input the internal power supply voltage determined according to the first output voltage.

7. The low voltage difference linear voltage regulator circuit according to claim 6, characterized in that: The second error amplification module includes an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth NMOS transistor and a nineteenth NMOS transistor; the second power adjustment tube includes a twenty-second PMOS transistor; the current source feedback network includes a second current source; The gate of the eleventh NMOS transistor is configured to input the second feedback signal, and the gate of the twelfth NMOS transistor is configured to input the second reference signal; the source of the eleventh NMOS transistor and the source of the twelfth NMOS transistor are respectively connected to the drain of the thirteenth NMOS transistor, and the gate of the thirteenth NMOS transistor is configured to input the start control signal; the drain of the eleventh NMOS transistor is respectively connected to the drain of the fourteenth PMOS transistor and the source of the sixteenth PMOS transistor, and the drain of the twelfth NMOS transistor is respectively connected to the drain of the fifteenth PMOS transistor and the source of the seventeenth PMOS transistor; the gate of the fourteenth PMOS transistor and the gate of the fifteenth PMOS transistor are respectively configured to input the first bias signal, the gate of the sixteenth PMOS transistor and the gate of the seventeenth PMOS transistor are respectively configured to input the second bias signal; the drain of the sixteenth PMOS transistor is respectively connected to the drain of the eighteenth NMOS transistor, the gate of the eighteenth NMOS transistor and the gate of the nineteenth NMOS transistor, the drain of the seventeenth PMOS transistor is connected to the drain of the nineteenth NMOS transistor and is configured to output the second control signal; the source of the fourteenth PMOS transistor and the source of the fifteenth PMOS transistor are respectively configured to input the internal power supply voltage determined according to the first output voltage, the source of the thirteenth NMOS transistor, the source of the eighteenth NMOS transistor and the source of the nineteenth NMOS transistor are respectively connected to the circuit ground; The gate of the twenty-second PMOS transistor is configured to input the third control signal, the source of the twenty-second PMOS transistor is configured to input the internal power supply voltage determined according to the first output voltage, and the drain of the twenty-second PMOS transistor is configured to output the second output voltage; A first end of the second current source is connected to the drain of the twenty-second PMOS transistor and the gate of the eleventh NMOS transistor respectively, and a second end of the second current source is connected to the circuit ground.

8. The low voltage difference linear voltage regulator circuit according to claim 7, characterized in that: The post-stage low voltage difference linear voltage stabilization module also includes a second Miller compensation capacitor; A first end of the second Miller compensation capacitor is connected to the drain of the fifteenth PMOS transistor, and a second end of the second Miller compensation capacitor is connected to the drain of the twenty-second PMOS transistor.

9. The low voltage difference linear voltage regulator circuit according to claim 8, characterized in that: The low voltage difference linear voltage stabilization circuit also includes a low pass filter; The low-pass filter is configured to perform low-pass filtering on the first output voltage and then provide the first output voltage to the subsequent low-voltage difference linear voltage regulator module.

10. The low voltage difference linear voltage regulator circuit according to claim 9, characterized in that: The low-pass filter includes a filter resistor and a filter capacitor; The first end of the filter resistor is configured to input the first output voltage, the second end of the filter resistor is connected to the first end of the filter capacitor and is configured to output the internal power supply voltage, and the second end of the filter capacitor is connected to the circuit ground.

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