Insulated gate bipolar transistor capable of reducing turn-off loss
By introducing a P-type carrier storage layer into an insulated gate bipolar transistor, the problem of the pull-tail current increase in traditional devices when shutdown is solved, and the effect of reducing shutdown loss and improving Eoff characteristics is achieved.
Patent Information
- Application Number
- CN202421668494.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-15
- Publication Date
- 2025-05-27
- Estimated Expiration
- 2034-07-15
AI Technical Summary
When the traditional insulated gate bipolar transistor is turned off, the tailing current increases due to the suppression effect of the carrier storage layer, which in turn increases the shutdown loss, affecting the Eoff characteristics of the device.
A P-type carrier storage layer is introduced into an insulated gate bipolar transistor. By realizing carrier accumulation of P-inverted to N-type layer when the gate +15V is turned on, the on-saturation voltage is reduced; when the gate is turned off, the carrier extraction is enhanced, the accumulation is reduced, and the shutdown loss is reduced.
It effectively reduces the shutdown loss, improves the Eoff characteristics of the device, and enhances the conductance modulation effect and improves the on-saturation voltage.
Smart Images
Figure CN222916502U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of semiconductor power devices, and particularly relates to an insulated gate bipolar transistor for reducing turn-off loss. Background Art
[0002] A large number of power rectifiers are used in switching power supplies. The performance of power rectifiers has an important impact on the overall performance of switching power supplies. Insulated gate bipolar transistors are new composite devices that integrate power field-effect transistors and triodes on a single chip. Power field-effect transistors are voltage-driven unipolar devices, which have the advantages of easy driving, high speed, high input impedance, and good thermal stability, but they have a large on-resistance and low current capacity; while triodes are current-driven bipolar devices, which have the characteristics of high blocking voltage and strong current-carrying ability, but they have a slow working speed, large drive current, and a relatively complex control circuit. Insulated gate bipolar transistors combine the advantages of both, having both the speed advantages of field-effect transistors and the current-carrying ability of triodes, with better performance.
[0003] In order to reduce Eoff through surface design in the active region of traditional insulated gate bipolar transistor chips, it is necessary to reduce the hole accumulation on the surface. Usually, a carrier storage layer is used, and the potential difference between the carrier storage layer N and the drift region N- is used to enhance the hole accumulation, thereby enhancing the conductance modulation effect for reducing Vce(sat). However, during turn-off, the carrier storage layer N will inhibit the hole extraction, resulting in the problem of tail current increasing Eoff.
[0004] Therefore, in order to ensure a low on-state voltage, the turn-off loss has to be increased, resulting in a low turn-off Eoff characteristic. Summary of the Utility Model
[0005] This application provides an insulated gate bipolar transistor for reducing turn-off loss, which solves the problem of the trade-off between forward on-state Vce(sat) and turn-off loss Eoff.
[0006] An insulated gate bipolar transistor for reducing turn-off loss includes a zone-melted single crystal layer. In addition to an N-type carrier storage layer provided on the top of the zone-melted single crystal layer, a P-type carrier storage layer with switch adaptability is also provided in the middle of the cell.
[0007] First trenches, second trenches, and third trenches are provided on the N-type carrier storage layer and the P-type carrier storage layer; the first trenches, second trenches, and third trenches are independent of each other and do not communicate to form a grid-like trench; oxide layers are sequentially grown in the first trenches, second trenches, and third trenches, and after depositing polysilicon, polycrystalline back etching is performed to keep it flush with the silicon plane.
[0008] A Pbody layer is provided on the top of the zone-melted single-crystal layer; N+ layers are provided on the Pbody layers on both sides of the first trench; the Pbody layer is connected to the P-type carrier storage layer, and the N+ layer is connected to the interlayer dielectric layer;
[0009] An interlayer dielectric layer is provided on the zone-melted single-crystal layer, and a number of through holes extending downward are provided on the interlayer dielectric layer;
[0010] The through holes between the first trench and the second trench sequentially pass through the interlayer dielectric layer and the N+ layer and contact the Pbody layer;
[0011] The through holes between the second trench and the third trench pass through the interlayer dielectric layer and are connected to the Pbody layer;
[0012] The through holes in the second trench pass through the interlayer dielectric layer and are connected to the polysilicon in the second trench; the two polysilicons in the second trench are connected to the emitter through through holes to form an emitter trench structure;
[0013] The front metal layer fills a number of through holes respectively.
[0014] Specifically, polysilicon in the first trench is filled on the oxide layer in the first trench;
[0015] Polysilicon in the second trench is filled on the oxide layer in the second trench;
[0016] Polysilicon in the third trench is filled on the oxide layer in the third trench.
[0017] Specifically, an electric field cutoff layer and a collector are sequentially provided on the bottom surface of the zone-melted single-crystal layer.
[0018] Specifically, the first trench, the second trench and the third trench have equal cross-sectional areas, and the first trench, the second trench and the third trench have equal depths.
[0019] Specifically, the depths of the first trench, the second trench and the third trench are respectively 5000 - 5500 nm.
[0020] Specifically, the top surfaces of the polysilicon in the first trench, the top surface of the polysilicon layer in the second trench and the top surface of the polysilicon layer in the third trench are respectively on the same horizontal plane.
[0021] Specifically, the thickness of the oxide layer is 120 - 200 nm.
[0022] Specifically, the thickness of the interlayer dielectric layer is 1000 - 1100 nm.
[0023] The thickness (or the so-called lateral cross-sectional width) of the oxide layer is less than the lateral cross-sectional width of the polysilicon in the third trench.
[0024] Specifically, the height of the P-type carrier storage layer ( Figure 1 distance in the up and down direction) is less than the height of the third trench polysilicon ( Figure 1 distance in the up and down direction).
[0025] The above solution of the present application has the following beneficial effects:
[0026] The present application provides a switch-adaptive insulated gate bipolar transistor structure and a manufacturing method thereof. Compared with the traditional device cell structure, a P-type injection layer (10 P-type carrier storage layer in the figure) is introduced to replace part of the N-type layer to form a new carrier storage layer, effectively providing a new design method for the structural adjustment of the on-state saturation voltage and the turn-off loss. When the insulated gate bipolar transistor is turned on with a gate voltage of +15V, the newly introduced P-type carrier storage layer is inverted from P-type to N-type to accumulate carriers (holes), thereby enhancing the conductivity modulation effect and reducing the on-state saturation voltage. When the insulated gate bipolar transistor is turned off with a gate voltage of -5V / -8V, the newly introduced P-type carrier storage layer can change from P-type to P-type, enhancing the extraction of carriers (holes) during turn-off, reducing the accumulation of carriers (holes), and reducing the turn-off time and tail current, thereby achieving a reduction in turn-off loss. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0028] Figure 1 Schematic cross-section of the insulated gate bipolar transistor prepared according to the present application Figure 1 ;
[0029] Figure 2 Schematic cross-section of the insulated gate bipolar transistor prepared according to the present application Figure 2 ;
[0030] Figure 3 Schematic cross-section of the insulated gate bipolar transistor prepared according to the present application Figure 3 ;
[0031] Figure 4 Schematic cross-section of the insulated gate bipolar transistor prepared according to the present application Figure 4 ;
[0032] Figure 5 Schematic cross-section of the insulated gate bipolar transistor prepared according to the present application Figure 5 ;
[0033] Figure 6 The cross-sectional schematic of manufacturing an insulated gate bipolar transistor provided by this application Figure 6 ;
[0034] Figure 7 The cross-sectional schematic of manufacturing an insulated gate bipolar transistor provided by this application Figure 7 ;
[0035] Figure 8 The cross-sectional schematic of manufacturing an insulated gate bipolar transistor provided by this application Figure 8 ;
[0036] Figure 9 The cross-sectional schematic of manufacturing an insulated gate bipolar transistor provided by this application Figure 9 ;
[0037] Figure 10 The cross-sectional schematic of manufacturing an insulated gate bipolar transistor provided by this application Figure 10 ;
[0038] 1 - Front metal layer, 17 - Mask layer photoresist, 13 - Interlayer dielectric layer, 21 - First trench, 22 - Second trench, 23 - Third trench, 11 - Second trench polysilicon, 12 - Third trench polysilicon, 3 - N+ layer, 4 - First trench polysilicon, 2 - Pbody layer (or P-type channel implantation layer), 5 - N-type carrier storage layer, 6 - Oxide layer, 7 - Zone-melted single crystal layer, 8 - Field stop layer, 9 - Collector, 10 - P-type carrier storage layer, 14 - Via hole. Detailed implementation manners
[0039] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system architectures, technologies, etc. are presented to thoroughly understand the embodiments of this application. However, those skilled in the art should clearly understand that this application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of this application.
[0040] It should be understood that when used in the specification and appended claims of this application, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or other features, wholes, steps, operations, elements, components, and / or their combinations.
[0041] It should also be understood that the term "and / or" used in the specification and appended claims of this application refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0042] As used in the specification of the present application and the appended claims, the term "if" may be construed, depending on the context, as "when", "once", "in response to determining", or "in response to detecting". Similarly, the phrases "if determined" or "if [the described condition or event] is detected" may be construed, depending on the context, as meaning "once determined", "in response to determining", "once [the described condition or event] is detected", or "in response to detecting [the described condition or event]".
[0043] In addition, in the description of the specification of the present application and the appended claims, the terms "first", "second", "third", etc. are only used for differentiating descriptions and cannot be construed as indicating or implying relative importance.
[0044] Reference to "one embodiment" or "some embodiments" or the like described in the specification of the present application means that a specific feature, structure, or characteristic described in connection with that embodiment is included in one or more embodiments of the present application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprising", "including", "having", and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.
[0045] The insulated gate bipolar transistor with switch adaptability provided by the present application will be described below by way of specific embodiments.
[0046] As Figure 1 shown, an insulated gate bipolar transistor with an adaptive switch provided by an embodiment of the present application includes a zone-melted single crystal layer 7, a deposited interlayer dielectric layer 13, and a front metal layer 1 sequentially arranged from bottom to top;
[0047] An N-type carrier storage layer 5 and a P-type carrier storage layer 10 that are interconnected are sequentially formed on the top of the zone-melted single crystal layer 7 through ion implantation and high-temperature annealing;
[0048] The photoresist exposed on the top surface of the zone-melted single crystal layer 8 is removed, and a trench structure is formed by etching; trenches are etched on the zone-melted single crystal layer 7 to form a first trench 21, a second trench 22, and a third trench 23;
[0049] The bottoms of a plurality of first trenches 21, a plurality of second trenches 22, and the third trench 23 are respectively located below the N-type carrier storage layer 5 and the P-type carrier storage layer 10;
[0050] An oxide layer 6 is formed on the inner wall of the trench;
[0051] The first trench polysilicon 4 is filled on the oxide layer 6 in the first trench 21;
[0052] The second trench polysilicon 11 is filled on the oxide layer 6 in the second trench 22;
[0053] The third trench polysilicon 12 is filled on the oxide layer 6 in the third trench 23;
[0054] The first trench polysilicon 4 and the third trench polysilicon 12 are led out through the gate bus on the outer periphery of the chip and converge at the Gate pad position of the chip to form a control gate;
[0055] On the zone-melted single-crystal layer 7, a Pbody layer 2 is provided on the side of the trench; on the top surface of the Pbody layer 2, an N+ layer 3 is provided on the side of the first trench 21 and is located on the top surface of the Pbody layer 2;
[0056] The Pbody layer 2 is connected to the P-type carrier storage layer 10, and the N+ layer 3 is connected to the interlayer dielectric layer 13;
[0057] A plurality of through holes 14 are provided on the interlayer dielectric layer 13;
[0058] The through holes 14 between the first trench 21 and the second trench 22 sequentially pass through the interlayer dielectric layer 13 and the N+ layer 3 and contact the Pbody layer 2;
[0059] The through holes 14 between the second trench 22 and the third trench 23 pass through the interlayer dielectric layer 13 and are connected to the Pbody layer 2;
[0060] The through holes 14 in the second trench 22 pass through the interlayer dielectric layer 13 and are connected to the second trench polysilicon 11; the two second trench polysilicons 11 are connected to the emitter through the through holes 14 to form an emitter trench structure;
[0061] The front metal layer 1 fills a plurality of through holes 14 respectively.
[0062] An electric field cutoff layer 8 is formed on the bottom surface of the zone-melted single-crystal layer 7 by sequentially implanting phosphorus ions and boron ions;
[0063] Finally, a collector 9 is formed on the bottom surface of the zone-melted single-crystal layer 7 by evaporating AlTi Ni Ag metal.
[0064] The front metal layer 1 is sequentially connected to the second trench polysilicon 11 and the N+ layer 3 on the top surface of the Pbody layer 2 on one side of the second trench 22 through the via hole 14, and finally forms the emitter of the switch adaptive insulated gate bipolar transistor. Among them, the second trench polysilicon 11 is connected to the emitter through the via hole 14 to form an emitter trench structure. The first trench polysilicon 4 and the first triple trench polysilicon 12 can be led out through the gate bus on the outer periphery of the chip and converge at the Gate pad position of the chip to form a control gate.
[0065] The following is a detailed introduction to the preparation process of the insulated gate bipolar transistor of the present invention with reference to examples:
[0066] As Figure 2 and Figure 3 shown, a prepared zone-melted single-crystal layer 7 is provided. First, device pattern transfer is performed using a mask plate, and an N-type carrier storage layer structure 5 and a P-type carrier storage layer 10 are sequentially formed on the top surface of the zone-melted single-crystal layer through ion implantation and high-temperature annealing. Among them, the dose of the P-type carrier storage layer 10 is 1e12~3e13;
[0067] Figure 4 As shown, first, device pattern transfer is performed using a mask plate, and then a plurality of first trenches 21, a plurality of second trenches 22, and a third trench 23 are etched on the zone-melted single-crystal layer 7 through dry etching. According to different requirements for device breakdown voltage, the trench depth is generally 5000~5500nm.
[0068] Remove the photoresist mask layer 17 remaining on the top surface of the single-crystal layer after etching.
[0069] As Figure 5 shown, in order to ensure the smoothness of the groove wall of the gate-like trench structure and the growth quality of the subsequent gate oxide, sacrificial oxidation is first performed, and the thickness of the sacrificial oxidation is 120~130nm. Then, gate oxide growth is carried out, and an oxide layer 6 with a thickness of 120~130nm is formed on the inner wall of the gate-like trench structure through thermal growth.
[0070] Since the oxide layer 6 is grown in a high-temperature furnace tube, the top surface of the zone-melted single-crystal layer 7 will also be naturally oxidized. Then, polysilicon deposition and back-etching are performed on the top surface to make the polysilicon surface in the trench flush with the silicon surface.
[0071] As Figure 6 shown, a Pbody layer 2 is formed on the top of the zone-melted single-crystal layer 7 through ion implantation and high-temperature annealing;
[0072] As Figure 7 shown, an N+ layer 3 is formed above the Pbody layer 2 on the top of the zone-melted single-crystal layer 7 through ion implantation and high-temperature annealing;
[0073] As Figure 8As shown, an interlayer dielectric layer 13 is deposited on the top surface of the zone-melted single crystal layer 7, with a thickness ranging from 1000 nm to 1200 nm;
[0074] As Figure 9 shown, a number of vias 14 are etched in the interlayer dielectric layer 13, wherein the second trench polysilicon 11 is connected to the emitter through the vias 14 to form an emitter trench structure;
[0075] The vias 14 between the first trench polysilicon 4 and the second trench polysilicon 11 sequentially pass through the interlayer dielectric layer 13 and the N+ layer 3 and extend into the Pbody layer 2;
[0076] The vias 14 between the second trench polysilicon 11 and the third trench polysilicon 12 pass through the interlayer dielectric layer 13 and contact the Pbody layer 2;
[0077] The vias 14 on the second trench polysilicon 11 extend downward from the interlayer dielectric layer 13 into the second trench polysilicon 11. Among them, the polycrystalline structure in the third trench 23 combines with the P-type carrier storage layer to achieve the switch self-adaptive function.
[0078] As Figure 10 , Ti, TiN, and tungsten are sequentially deposited in a number of vias 14; after tungsten is etched back, a front metal is sputter-deposited on the top surface to form a front metal layer 1, and the vias 14 and the front metal layer 1 form a connection part.
[0079] As Figure 1 , phosphorus ions and boron ions are sequentially implanted into the bottom surface of the zone-melted single crystal layer 7, and a laser annealing is performed to form an electric field cutoff layer 8;
[0080] Finally, a collector 9 is formed by evaporating Al, Ti, Ni, and Ag metals on the bottom surface.
[0081] The above is the preferred embodiment of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle described in the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.
Claims
1. An insulated gate bipolar transistor with reduced turn-off loss, comprising a zone melting single crystal layer (7), characterized in that: In addition to an N-type carrier storage layer (5) being provided on the top of the zone melting single crystal layer (7), a P-type carrier storage layer (10) with switch adaptability is also provided in the middle of the unit cell; A first groove (21), a second groove (22) and a third groove (23) are provided on the N-type carrier storage layer (5) and the P-type carrier storage layer (10); the first groove (21), the second groove (22) and the third groove (23) are independent of each other and are not connected to form a grid-like groove; An oxide layer (6) is grown in the first groove (21), the second groove (22) and the third groove (23) respectively and in sequence; A P-type channel injection layer (2) is provided on the top of the zone melting single crystal layer (7), and an N+ layer (3) is provided on the P-type channel injection layer (2) on both sides of the first groove (21); An interlayer dielectric layer (13) is provided on the zone melting single crystal layer (7), and a plurality of through holes (14) extending downward are provided on the interlayer dielectric layer (13); The through hole (14) between the first groove (21) and the second groove (22) sequentially passes through the interlayer dielectric layer (13) and the N+ layer (3) to contact the P-type channel injection layer (2); The through hole (14) between the second trench (22) and the third trench (23) passes through the interlayer dielectric layer (13) and is connected to the P-type channel injection layer (2); The through hole (14) in the second trench (22) passes through the interlayer dielectric layer (13) and is connected to the second trench polysilicon (11); the two second trench polysilicons (11) are connected to the emitter through the through hole (14) to form an emitter trench structure; The front metal layer (1) is filled with a plurality of through holes (14).
2. The insulated gate bipolar transistor with reduced turn-off loss according to claim 1, characterized in that: The oxide layer (6) in the first trench (21) is filled with first trench polysilicon (4); The oxide layer (6) in the second trench (22) is filled with second trench polysilicon (11); The third trench polysilicon (12) is filled on the oxide layer (6) in the third trench (23).
3. The insulated gate bipolar transistor with reduced turn-off loss according to claim 1, characterized in that: An electric field cutoff layer (8) and a collector electrode (9) are sequentially arranged on the bottom surface of the zone melting single crystal layer (7).
4. The insulated gate bipolar transistor with reduced turn-off loss according to claim 2, characterized in that: The cross-sectional areas of the first groove (21), the second groove (22) and the third groove (23) are equal, and the depths of the first groove (21), the second groove (22) and the third groove (23) are equal.
5. The insulated gate bipolar transistor with reduced turn-off loss according to claim 4, characterized in that: The depths of the first groove (21), the second groove (22) and the third groove (23) are respectively 5000-5500 nm.
6. The insulated gate bipolar transistor with reduced turn-off loss according to claim 4, characterized in that: The top surface of the first trench polysilicon (4), the top surface of the second trench polysilicon (11) and the top surface of the third trench polysilicon (12) are respectively located on the same horizontal plane.
7. The insulated gate bipolar transistor with reduced turn-off loss according to claim 1, characterized in that: The thickness of the oxide layer (6) is 120-200 nm.
8. The insulated gate bipolar transistor with reduced turn-off loss according to claim 1, characterized in that: The thickness of the interlayer dielectric layer (13) is 1000-1100 nm.
9. The insulated gate bipolar transistor with reduced turn-off loss according to claim 1, characterized in that: The thickness of the oxide layer (6) is smaller than the lateral cross-sectional width of the third trench polysilicon (12).
10. The insulated gate bipolar transistor with reduced turn-off loss according to claim 1, characterized in that: The height of the P-type carrier storage layer (10) is smaller than the height of the third trench polysilicon (12).