Intrinsically safe power supply

Abstract

The intrinsically safe power supply comprises a safety isolation transformer, a fuse, a rectification filtering and reverse connection prevention circuit, a lightning protection circuit, a surge and overvoltage protection circuit, a DC / DC conversion circuit and a two-stage overcurrent and overvoltage protection circuit. An R-type safety isolation transformer is matched with a primary side fuse and a secondary side fuse to provide a reliable SELV power supply, a DC / DC circuit is formed based on an LM2676-ADJ chip, a two-stage over-current and over-voltage rapid turn-off protection circuit is formed through a surge protection chip ADM1270, and the nonlinear rectangular power supply output characteristic is provided. The two-stage TVS is arranged at the input end of the DC / DC circuit and the input end of the ADM1270 chip and matched with the fuse for protection, the fuse is fused under the condition that the input voltage is abnormal or the DC / DC fails, the overvoltage protection effect is achieved, and the safety of the chip and the reliability of the power supply are ensured.

Description

Technical Field

[0001] The utility model relates to the technical field of safety explosion-proof systems, in particular to an intrinsically safe power supply. Background Art

[0002] The intrinsically safe power supply is an associated device in the intrinsically safe system. It is also called associated equipment in the earlier version of the GB / T3836.4-2021 standard. It is an electrical device that contains energy-limited and non-energy-limited circuits and is structurally capable of preventing non-intrinsically safe circuits from having adverse effects on intrinsically safe circuits. Whether its parameters match those of the intrinsically safe equipment is related to whether the entire intrinsically safe system meets the explosion-proof standards. The current intrinsically safe power supply can only provide commonly used fixed output voltage parameters. However, due to the diversity of intrinsically safe equipment and the restrictions on parameters such as voltage and current for different intrinsically safe explosion-proof energy-limited requirements, the commonly used voltage parameters cannot meet the power supply requirements of many intrinsically safe equipment with special voltage parameters. Most of the existing intrinsically safe power supplies are Class I equipment for mining, and fewer are suitable for Class II oil and gas environments. At present, the maximum voltage Um of Class II intrinsically safe power supplies is less than 36V, and they are subject to special restrictions on installation and use. During installation, there is a situation where non-safety isolated AC / DC high-frequency switching power supplies are used for power supply, which makes the system unable to meet explosion-proof standards. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide an intrinsically safe power supply.

[0004] The technical solution adopted by the utility model to solve the technical problems existing in the known technology is:

[0005] The utility model provides an intrinsically safe power supply, comprising: a safety isolation transformer, a fuse, a rectifier filter and anti-reverse connection circuit, an anti-lightning protection circuit, a surge and overvoltage protection circuit, a DC / DC conversion circuit and a two-stage overcurrent and overvoltage protection circuit; the fuse comprises a primary-side fuse and a secondary-side fuse, the safety isolation transformer is connected to an external low-voltage power supply through the primary-side fuse, and is connected to the rectifier filter and anti-reverse connection circuit through the secondary-side fuse to form a SELV DC power supply system; the surge and overvoltage protection circuit comprises a surge and overvoltage protection circuit of the DC / DC conversion circuit and a two-stage overcurrent and overvoltage protection circuit. The surge and overvoltage protection circuit of the DC / DC conversion circuit; the SELV DC power supply system is connected to the input end of the DC / DC conversion circuit, and a lightning protection circuit and a surge and overvoltage protection circuit of the DC / DC conversion circuit are arranged between the SELV DC power supply system and the DC / DC conversion circuit; the output end of the DC / DC conversion circuit is connected to the input end of the two-stage overcurrent and overvoltage protection circuit, and a surge and overvoltage protection circuit of the two-stage overcurrent and overvoltage protection circuit is arranged between the DC / DC conversion circuit and the two-stage overcurrent and overvoltage protection circuit, and the output end of the two-stage overcurrent and overvoltage protection circuit is the output end of the power supply.

[0006] The utility model can also adopt the following technical measures:

[0007] The safety isolation transformer is connected to the TN-S low-voltage power supply through the primary side fuse F1, the iron core of the safety isolation transformer is grounded, and is connected to the terminal plug J9 through the secondary side fuse F2, and the terminal plug J9 is connected to the terminal slot J1 through a wire; the full-wave rectifier bridge BRIDGE1 constitutes a rectifier, filter and anti-reverse connection circuit, the above-mentioned terminal slot J1 is connected to the AC input pin 1 and pin 3 of the full-wave rectifier bridge BRIDGE1, and the DC output pin 2 and pin 4 of the full-wave rectifier bridge BRIDGE1 are connected to the filter capacitor C3 to form a SELV DC power supply system.

[0008] The positive and negative electrodes of the power supply of the SELV DC power supply system are grounded through gas discharge tubes P1, P2 and high-voltage capacitors C1, C2 to form a lightning protection circuit; the positive electrode of the power supply of the SELV DC power supply system is connected to two parallel bidirectional TVS transient suppression diodes SMCJ24CA through a series fuse F3 to form a surge and overvoltage protection circuit of the DC / DC conversion circuit.

[0009] The DC / DC conversion circuit adopts a DC / DC conversion chip LM2676-ADJ, an input pin 2 of the DC / DC conversion chip LM2676-ADJ is connected to a low-frequency smoothing capacitor C6 and a high-frequency filter capacitor C8, and is connected to the positive pole of the power supply of the SELV DC power supply system; an output pin 1 of the DC / DC conversion chip LM2676-ADJ is connected to an inductor L1 and a Schottky diode MBR745, the inductor L1, the Schottky diode D1, and the output capacitor C9 form a BUCK loop, and the LM2676-ADJ output pin 1 outputs a PWM voltage regulation excitation signal; a pin 3 of the DC / DC conversion chip LM2676-ADJ is connected to the output pin 1 through a Cboost bootstrap capacitor C4, providing a deep conduction control voltage for the internal MOSFET; a voltage feedback pin 6 of the DC / DC conversion chip LM2676-ADJ is connected between the voltage output end and the negative pole of the DC / DC conversion circuit through a voltage divider network composed of resistors R4 and R3, so as to obtain a required output voltage regulation value.

[0010] The output end of the DC / DC conversion circuit is connected to the terminal J8 through the terminal J2, and the terminal J8 is connected to two parallel bidirectional TVS transient suppression diodes SMCJ7.5CA through the fuse F4, forming a surge and overvoltage protection circuit of the two-stage overcurrent and overvoltage protection circuit.

[0011] The first-stage overcurrent and overvoltage protection circuit and the second-stage overcurrent and overvoltage protection circuit in the two-stage overcurrent and overvoltage protection circuit both use the surge protection chip ADM1270, which are the first surge protection chip ADM1270 and the second surge protection chip ADM1270 respectively.

[0012] Corresponding to the first-stage overcurrent and overvoltage protection circuit, the terminal J8 is connected to the drain D of the reverse voltage suppression P-channel field effect transistor Q1 in the first-stage overcurrent and overvoltage protection circuit through the fuse F4, and the gate G of the P-channel field effect transistor Q1 is connected to the second pin of the first surge protection chip ADM1270; the source S of the P-channel field effect transistor Q1 is connected to the source S of the output P-channel field effect transistor Q2 through the current detection resistor R8 to form a back-to-back reverse power supply suppression circuit; the first and second pins of the first surge protection chip ADM1270 are connected to the first and second pins of the first surge protection chip ADM1270. Pin 16 is connected to the overcurrent protection sensing resistor R8 to form a 2A overcurrent protection circuit; the third pin VCAP of the first surge protection chip ADM1270 is connected to the fourth pin ISET; the third pin VCAP of the first surge protection chip ADM1270 is connected to the capacitor C7; the third pin VCAP of the first surge protection chip ADM1270 is connected to the seventh pin ENABLE; the fifth and sixth pins of the first surge protection chip ADM1270 are connected to the resistor formed by R2, R6, and R7 network; the 15th pin of the first surge protection chip ADM1270 is connected to the gate of the P-channel field effect transistor Q2; the 13th pin FLB of the first surge protection chip ADM1270 is connected to the voltage-dividing network formed by R9, R10, and R11; the 12th pin FB_PG of the first surge protection chip ADM1270 is connected to the voltage-dividing network formed by R9, R10, and R11; the 10th pin TIMER of the first surge protection chip ADM1270 is connected to the timing comparator charging capacitor C10; The 11th pin TIMER_OFF of the first surge protection chip ADM1270 is connected to the timing comparator charging capacitor C11; the 8th pin FAULT1 of the first surge protection chip ADM1270 is connected to LED1; the 14th pin PWRGD of the first surge protection chip ADM1270 is connected to LED3; the drain D of the P-channel field effect transistor Q2 is connected to LED2 through the current limiting resistor R19, and the drain D of the P-channel field effect transistor Q2 is connected to LED3 through the current limiting resistor R20.

[0013] Corresponding to the second-stage overcurrent and overvoltage protection circuit, the drain D of the P-channel field effect transistor Q2 at the positive output end of the first-stage overcurrent and overvoltage protection circuit is connected to the drain D of the P-channel field effect transistor Q3 for reverse voltage suppression in the second-stage overcurrent and overvoltage protection circuit, and the gate G of the P-channel field effect transistor Q3 is connected to the second pin of the second surge protection chip ADM1270; the source S of the P-channel field effect transistor Q3 is connected to the source S of the output P-channel field effect transistor Q4 through the current detection resistor R16 to form a back-to-back reverse power supply suppression circuit; the second surge protection chip ADM12 The 1st and 16th pins of 70 are connected to the overcurrent protection sensing resistor R16 to form a 2A overcurrent protection circuit; the 3rd pin VCAP of the second surge protection chip ADM1270 is connected to the 4th pin ISET; the 3rd pin VCAP of the second surge protection chip ADM1270 is connected to the capacitor C17; the 3rd pin VCAP of the second surge protection chip ADM1270 is connected to the 7th pin ENABLE; the 5th and 6th pins of the second surge protection chip ADM1270 are connected to the resistor network composed of R13, R14, and R15 ; The 15th pin of the second surge protection chip ADM1270 is connected to the gate of the P-channel field effect transistor Q4; the 13th pin FLB of the second surge protection chip ADM1270 is connected to the voltage-dividing network formed by R17, R18, and R21; the 12th pin FB_PG of the second surge protection chip ADM1270 is connected to the voltage-dividing network formed by R17, R18, and R21; the 10th pin TIMER of the second surge protection chip ADM1270 is connected to the timing comparator charging capacitor C15; the second surge protection chip ADM1 The 11th pin TIMER_OFF of 270 is connected to the timing comparator charging capacitor C16; the 8th pin FAULT2 of the second surge protection chip ADM1270 is connected to LED4; the 14th pin PWRGD of the second surge protection chip ADM1270 is connected to LED6; the drain D of the P-channel field effect transistor Q4 is connected to LED5 through the current limiting resistor R22, and the drain D of the P-channel field effect transistor Q4 is connected to LED6 through the current limiting resistor R24; the output end of the second-stage overvoltage and overcurrent protection circuit is connected to the terminal J10.

[0014] The advantages and positive effects of the utility model are:

[0015] The intrinsically safe power supply of the utility model adopts an R-type safety isolation transformer with primary and secondary side fuses to provide a reliable SELV power supply. The DC / DC circuit composed of the LM2676-ADJ chip obtains the required DC voltage between DC5 and 24V by selecting a suitable fixed feedback resistor, and forms a two-stage overcurrent and overvoltage fast shutdown protection circuit through the surge protection chip ADM1270 to provide a nonlinear rectangular power supply output characteristic. The energy-limiting protection circuit can operate in the voltage range of DC4 to 60V. Two-stage TVS with fuse protection is provided at the input end of the DC / DC circuit and the ADM1270 chip, which serves as overvoltage protection for the DC / DC chip and the ADM1270 chip. In the case of abnormal input voltage or DC / DC failure, the fuse is blown to play an overvoltage protection role, ensuring chip safety and power supply reliability; the utility model is also provided with a gas discharge tube and a high-voltage capacitor to prevent the common-mode high voltage generated by lightning from the shell from damaging the system insulation, effectively improving the system safety during use. Its maximum voltage Um is greater than AC250V, and its installation conditions are not restricted. It can be used in non-mining Class II oil and gas environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the architecture of the intrinsically safe power supply of the utility model;

[0017] Figure 2 The utility model is a circuit diagram of an intrinsically safe power supply. DETAILED DESCRIPTION

[0018] The technical solution of the utility model is described in detail below through the accompanying drawings and specific embodiments.

[0019] Depend on Figure 1 and Figure 2As shown, the intrinsically safe power supply of the utility model includes: a safety isolation transformer, a fuse, a rectifier filter and anti-reverse connection circuit, an anti-lightning protection circuit, a surge and overvoltage protection circuit, a DC / DC conversion circuit and a two-stage overcurrent and overvoltage protection circuit; the fuse includes a primary side fuse and a secondary side fuse, the safety isolation transformer is connected to an external low-voltage power supply through the primary side fuse, and is connected to the rectifier filter and anti-reverse connection circuit through the secondary side fuse to form a SELV DC power supply system; the surge and overvoltage protection circuit includes a surge and overvoltage protection circuit of the DC / DC conversion circuit and a two-stage overcurrent and overvoltage protection circuit. A surge and overvoltage protection circuit of the overvoltage protection circuit; the SELV DC power supply system is connected to the input end of the DC / DC conversion circuit, and a lightning protection circuit and a surge and overvoltage protection circuit of the DC / DC conversion circuit are arranged between the SELV DC power supply system and the DC / DC conversion circuit; the output end of the DC / DC conversion circuit is connected to the input end of the two-stage overcurrent and overvoltage protection circuit, and a surge and overvoltage protection circuit of the two-stage overcurrent and overvoltage protection circuit is arranged between the DC / DC conversion circuit and the two-stage overcurrent and overvoltage protection circuit, and the output end of the two-stage overcurrent and overvoltage protection circuit is the output end of the power supply.

[0020] The safety isolation transformer is an R-type safety isolation transformer, which is connected to the TN-S low-voltage power supply through the primary-side fuse F1. The iron core of the safety isolation transformer is grounded and connected to the terminal plug J9 through the secondary-side fuse F2. The terminal plug J9 is connected to the terminal slot J1 through a wire; the full-wave rectifier bridge BRIDGE1 constitutes a rectification, filtering and anti-reverse connection circuit. The above-mentioned terminal slot J1 is connected to the AC input pin 1 and pin 3 of the full-wave rectifier bridge BRIDGE1, and the DC output pin 2 and pin 4 of the full-wave rectifier bridge BRIDGE1 are connected to the filter capacitor C3 to form a SELV DC power supply system.

[0021] The positive and negative electrodes of the power supply of the SELV DC power supply system are grounded through gas discharge tubes P1, P2 and high-voltage capacitors C1, C2 to form a lightning protection circuit; the positive electrode of the power supply of the SELV DC power supply system is connected to two parallel bidirectional TVS transient suppression diodes SMCJ24CA through a series fuse F3 to form a surge and overvoltage protection circuit for the DC / DC conversion circuit.

[0022] The DC / DC conversion circuit uses a DC / DC conversion chip LM2676-ADJ. The input pin 2 of the DC / DC conversion chip LM2676-ADJ is connected to the low-frequency smoothing capacitor C6 and the high-frequency filter capacitor C8, and is connected to the positive pole of the power supply of the SELV DC power supply system; the output pin 1 of the DC / DC conversion chip LM2676-ADJ is connected to the inductor L1 and the Schottky diode MBR745. The inductor L1, the Schottky diode D1, and the output capacitor C9 form a BUCK loop. The output pin 1 of the LM2676-ADJ outputs a PWM voltage regulation excitation signal; the pin 3 of the DC / DC conversion chip LM2676-ADJ is connected to the output pin 1 through the Cboost bootstrap capacitor C4 to provide a deep conduction control voltage for the internal MOSFET; the voltage feedback pin 6 of the DC / DC conversion chip LM2676-ADJ is connected between the voltage output terminal and the negative pole of the DC / DC conversion circuit through a voltage divider network composed of resistors R4 and R3 to obtain the required output voltage regulation value.

[0023] The output end of the DC / DC conversion circuit is connected to the terminal J8 through the terminal J2, and the terminal J8 is connected to two parallel bidirectional TVS transient suppression diodes SMCJ7.5CA through the fuse F4, forming a surge and overvoltage protection circuit of the two-stage overcurrent and overvoltage protection circuit.

[0024] The first-stage overcurrent and overvoltage protection circuit and the second-stage overcurrent and overvoltage protection circuit in the two-stage overcurrent and overvoltage protection circuit both adopt the surge protection chip ADM1270, which are the first surge protection chip ADM1270 and the second surge protection chip ADM1270 respectively.

[0025] Corresponding to the first-stage overcurrent and overvoltage protection circuit, the terminal J8 is connected to the drain D of the reverse voltage suppression P-channel field effect transistor Q1 in the first-stage overcurrent and overvoltage protection circuit through the fuse F4, and the gate G of the P-channel field effect transistor Q1 is connected to the second pin of the first surge protection chip ADM1270; the source S of the P-channel field effect transistor Q1 is connected to the source S of the output P-channel field effect transistor Q2 through the current detection resistor R8 to form a back-to-back reverse power supply suppression circuit; the 1st and 16th pins of the first surge protection chip ADM1270 are connected to the overcurrent protection sensing resistor R8, A 2A overcurrent protection circuit is formed; the third pin VCAP of the first surge protection chip ADM1270 is connected to the fourth pin ISET to form a 50mv current detection threshold; the third pin VCAP of the first surge protection chip ADM1270 is connected to capacitor C7 to maintain the accuracy of the internal LDO voltage regulation output; the third pin VCAP of the first surge protection chip ADM1270 is connected to the seventh pin ENABLE to obtain the power-on enable control level; the fifth and sixth pins of the first surge protection chip ADM1270 are connected to R2, R The resistor network composed of R6 and R7 is used to obtain the appropriate overvoltage and undervoltage protection thresholds; the 15th pin of the first surge protection chip ADM1270 is connected to the gate of the P-channel field effect transistor Q2 to control the on and off of the P-channel field effect transistor Q2; the 13th pin FLB of the first surge protection chip ADM1270 is connected to the voltage divider network composed of R9, R10, and R11 to set the soft start limit current and the current adjustment limit under the fault state; the 12th pin FB_PG of the first surge protection chip ADM1270 is connected to R9, R10, R11 The voltage divider network formed is connected to set the normal threshold of the output voltage; the 10th pin TIMER of the first surge protection chip ADM1270 is connected to the timing comparator charging capacitor C10 to set the duration of the current limit adjustment process from the occurrence of the overcurrent fault to the shutdown. When a 22nF capacitor is selected, a shutdown adjustment time of about 2mS can be obtained; the 11th pin TIMER_OFF of the first surge protection chip ADM1270 is connected to the timing comparator charging capacitor C11 to set the time from shutdown to the next attempt to restart. When 0.When the capacitor is 47uF, about 1S delay restart time can be obtained; the 8th pin FAULT1 of the first surge protection chip ADM1270 is connected to LED1, and LED1 is connected to VCC1 through R23 for fault indication; the 14th pin PWRGD of the first surge protection chip ADM1270 is connected to LED3 for normal power indication; the drain D of the P-channel field effect transistor Q2 is connected to LED2 through the current limiting resistor R19 for power output indication, and the drain D of the P-channel field effect transistor Q2 is connected to LED3 through the current limiting resistor R20. R20 is the pull-up resistor of the open-drain output of PWRGD. When the power output is normal, PWRGD outputs the open-drain OD high level, and lights up LED3 through R20. When the power supply voltage is lower than the set threshold, PWRGD outputs a low level and LED3 goes out. The FAULT1 pin of this power supply is not connected to ENABLE, and the automatic restart mode is invalid. After an overcurrent or overvoltage fault occurs in the system, the fault lock state will be maintained until it is powered on again after power failure. In the figure, C5 is the filter capacitor of the over-voltage and under-voltage detection resistor network, which is used to filter out high-frequency interference and improve the stability of the over-voltage and under-voltage detection circuit; C12 is the high-frequency filter capacitor of the current adjustment limit setting resistor network, which filters out external electromagnetic noise interference and improves the reliability of the current limit setting circuit.

[0026] Corresponding to the second-stage overcurrent and overvoltage protection circuit, the drain D of the P-channel field effect transistor Q2 at the positive output end of the first-stage overcurrent and overvoltage protection circuit is connected to the drain D of the P-channel field effect transistor Q3 for reverse voltage suppression in the second-stage overcurrent and overvoltage protection circuit, and the gate G of the P-channel field effect transistor Q3 is connected to the second pin of the second surge protection chip ADM1270; the source S of the P-channel field effect transistor Q3 is connected to the source S of the output P-channel field effect transistor Q4 through the current detection resistor R16 to form a back-to-back reverse power supply suppression circuit; the 1st and 16th pins of the second surge protection chip ADM1270 are connected Connect the overcurrent protection sensing resistor R16 to form a 2A overcurrent protection circuit; connect the third pin VCAP of the second surge protection chip ADM1270 to the fourth pin ISET to form a 50mv current detection threshold; connect the third pin VCAP of the second surge protection chip ADM1270 to the capacitor C17 to maintain the accuracy of the internal LDO voltage regulation output; connect the third pin VCAP of the second surge protection chip ADM1270 to the seventh pin ENABLE to obtain the power-on enable control level; connect the fifth pin and the sixth pin of the second surge protection chip ADM1270 to the power-on enable control level. The first pin of the second surge protection chip ADM1270 is connected to the resistor network composed of R13, R14, and R15 to obtain the appropriate overvoltage and undervoltage protection thresholds; the 15th pin of the second surge protection chip ADM1270 is connected to the gate of the switch field effect transistor Q4 to control the on and off of the P-channel field effect transistor Q4; the 13th pin FLB of the second surge protection chip ADM1270 is connected to the voltage divider network composed of R17, R18, and R21 to set the soft start limit current and the current adjustment limit under the fault state; the 12th pin FB_PG of the second surge protection chip ADM1270 is connected to R17, R 18, R21 constitutes a voltage divider network connection, which is used to set the normal threshold of the output voltage; the 10th pin TIMER of the second surge protection chip ADM1270 is connected to the timing comparator charging capacitor C15, which is used to set the duration of the current limit adjustment process from the occurrence of the overcurrent fault to the shutdown. When a 22nF capacitor is selected, a shutdown adjustment time of about 2mS can be obtained; the 11th pin TIMER_OFF of the second surge protection chip ADM1270 is connected to the timing comparator charging capacitor C16, which is used to set the time from shutdown to the next attempt to restart. When 0.When the capacitor is 47uF, a delay restart time of about 1S can be obtained; the 8th pin FAULT2 of the second surge protection chip ADM1270 is connected to LED4, and LED4 is connected to VCC2 through R25 for fault indication; the 14th pin PWRGD of the second surge protection chip ADM1270 is connected to LED6 for normal power indication; the drain D of the P-channel field effect transistor Q4 is connected to LED5 through the current limiting resistor R22 for power output indication, and the drain D of the P-channel field effect transistor Q4 is connected to LED6 through the current limiting resistor R24. R24 is a pull-up resistor at the open-drain output end of PWRGD. When the power output is normal, PWRGD outputs an open-drain OD high level and lights up LED6 through R24. When the power supply voltage is lower than the set threshold, PWRGD outputs a low level and LED6 goes out; the output end of the second-level overvoltage and overcurrent protection circuit is connected to the terminal J10. The FAULT2 pin of this power supply is not connected to ENABLE, and the automatic restart mode is invalid. After an overcurrent or overvoltage fault occurs in the system, the fault lock state will be maintained until the power is turned on again after power failure. In the figure, C13 is the filter capacitor of the over- and under-voltage detection resistor network, which is used to filter out high-frequency interference and improve the stability of the over- and under-voltage detection circuit; C14 is the high-frequency filter capacitor of the current adjustment limit setting resistor network, which filters out external electromagnetic noise interference and improves the reliability of the current limit setting circuit. .

[0027] In the intrinsically safe power supply of the utility model, an R-type safety isolation transformer is used in combination with primary and secondary side fuses to provide a reliable SELV power supply. A DC / DC circuit composed of an LM2676-ADJ chip is used to obtain a required DC voltage between DC5 and 24V by selecting a suitable fixed feedback resistor. A two-stage overcurrent and overvoltage fast shutdown protection circuit is formed by a surge protection chip ADM1270. The circuit is a core intrinsically safe energy limiting circuit, providing a nonlinear rectangular power supply output characteristic. The energy limiting protection circuit can operate in a voltage range of DC4 to 60V. Two-stage TVS and fuse protection are provided at the input ends of the DC / DC and ADM1270 chips as overvoltage protection for the DC / DC chip and the ADM1270 chip. In the case of abnormal input voltage or DC / DC failure, the fuse is blown to play an overvoltage protection role, thereby ensuring chip safety and power supply reliability. A gas discharge tube and a high-voltage capacitor are provided to prevent the damage of the system insulation to surge common-mode high voltage generated by lightning striking the shell.

[0028] The overcurrent and overvoltage protection circuit uses a P-channel field-effect transistor to form a back-to-back structure, which can replace the Schottky diode to achieve reverse voltage protection. Based on the high-bandwidth current sensing amplifier of ADM1270, the short-circuit protection response time is 2μS, which limits and controls the short-circuit current within 2μs. Based on the TIMER timer capacitor charging time, the current limiting shutdown time is no more than 2ms.

[0029] The above is only a preferred embodiment of the utility model, and does not limit the utility model in any form. Although the utility model has been disclosed as a preferred embodiment as above, it is not used to limit the utility model. Any technician familiar with this profession will certainly make some changes or modifications to the disclosed technical content without departing from the scope of the technical solution of the utility model, and become an equivalent embodiment of equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the utility model without departing from the content of the technical solution of the utility model are within the scope of the technical solution of the utility model.

Claims

1. An intrinsically safe power supply, characterized in that: include: Safety isolation transformer, fuse, rectifier filter and anti-reverse connection circuit, lightning protection circuit, surge and overvoltage protection circuit, DC / DC conversion circuit and two-stage overcurrent and overvoltage protection circuit; the fuse includes a primary side fuse and a secondary side fuse. The safety isolation transformer is connected to the external low-voltage power supply through the primary side fuse, and is connected to the rectifier filter and anti-reverse connection circuit through the secondary side fuse to form a SELV DC power supply system; The surge and overvoltage protection circuit includes a surge and overvoltage protection circuit of a DC / DC conversion circuit and a surge and overvoltage protection circuit of a two-stage overcurrent and overvoltage protection circuit; the SELV DC power supply system is connected to the input end of the DC / DC conversion circuit, and a lightning protection circuit and a surge and overvoltage protection circuit of the DC / DC conversion circuit are arranged between the SELV DC power supply system and the DC / DC conversion circuit; the output end of the DC / DC conversion circuit is connected to the input end of the two-stage overcurrent and overvoltage protection circuit, and a surge and overvoltage protection circuit of the two-stage overcurrent and overvoltage protection circuit is arranged between the DC / DC conversion circuit and the two-stage overcurrent and overvoltage protection circuit, and the output end of the two-stage overcurrent and overvoltage protection circuit is the output end of the power supply.

2. The intrinsically safe power supply according to claim 1, characterized in that: The safety isolation transformer is connected to the TN-S low-voltage power supply through the primary-side fuse F1. The iron core of the safety isolation transformer is grounded and connected to the terminal plug J9 through the secondary-side fuse F2. The terminal plug J9 is connected to the terminal slot J1 through a wire; the full-wave rectifier bridge BRIDGE1 constitutes a rectification, filtering and anti-reverse connection circuit. The above-mentioned terminal slot J1 is connected to the AC input pin 1 and pin 3 of the full-wave rectifier bridge BRIDGE1, and the DC output pin 2 and pin 4 of the full-wave rectifier bridge BRIDGE1 are connected to the filter capacitor C3 to form a SELV DC power supply system.

3. The intrinsically safe power supply according to claim 2, characterized in that: The positive and negative electrodes of the power supply of the SELV DC power supply system are grounded through gas discharge tubes P1, P2 and high-voltage capacitors C1, C2 to form a lightning protection circuit; the positive electrode of the power supply of the SELV DC power supply system is connected to two parallel bidirectional TVS transient suppression diodes SMCJ24CA through a series fuse F3 to form a surge and overvoltage protection circuit for the DC / DC conversion circuit.

4. The intrinsically safe power supply according to claim 3, characterized in that: The DC / DC conversion circuit uses a DC / DC conversion chip LM2676-ADJ. The input pin 2 of the DC / DC conversion chip LM2676-ADJ is connected to the low-frequency smoothing capacitor C6 and the high-frequency filter capacitor C8, and is connected to the positive pole of the power supply of the SELV DC power supply system; the output pin 1 of the DC / DC conversion chip LM2676-ADJ is connected to the inductor L1 and the Schottky diode MBR745. The inductor L1, the Schottky diode D1, and the output capacitor C9 form a BUCK loop. The output pin 1 of the LM2676-ADJ outputs a PWM voltage regulation excitation signal; the pin 3 of the DC / DC conversion chip LM2676-ADJ is connected to the output pin 1 through the Cboost bootstrap capacitor C4 to provide a deep conduction control voltage for the internal MOSFET; the voltage feedback pin 6 of the DC / DC conversion chip LM2676-ADJ is connected between the voltage output terminal and the negative pole of the DC / DC conversion circuit through a voltage divider network composed of resistors R4 and R3 to obtain the required output voltage regulation value.

5. The intrinsically safe power supply according to claim 4, characterized in that: The output end of the DC / DC conversion circuit is connected to the terminal J8 through the terminal J2, and the terminal J8 is connected to two parallel bidirectional TVS transient suppression diodes SMCJ7.5CA through the fuse F4, forming a surge and overvoltage protection circuit of the two-stage overcurrent and overvoltage protection circuit.

6. The intrinsically safe power supply according to claim 5, characterized in that: The first-stage overcurrent and overvoltage protection circuit and the second-stage overcurrent and overvoltage protection circuit in the two-stage overcurrent and overvoltage protection circuit both adopt the surge protection chip ADM1270, which are the first surge protection chip ADM1270 and the second surge protection chip ADM1270 respectively.

7. The intrinsically safe power supply according to claim 6, characterized in that: Corresponding to the first-stage overcurrent and overvoltage protection circuit, the terminal J8 is connected to the drain D of the reverse voltage suppression P-channel field effect transistor Q1 in the first-stage overcurrent and overvoltage protection circuit through the fuse F4, and the gate G of the P-channel field effect transistor Q1 is connected to the second pin of the first surge protection chip ADM1270; the source S of the P-channel field effect transistor Q1 is connected to the source S of the output P-channel field effect transistor Q2 through the current detection resistor R8 to form a back-to-back reverse power supply suppression circuit; the first and second pins of the first surge protection chip ADM1270 are connected to the first and second pins of the first surge protection chip ADM1270. Pin 16 is connected to the overcurrent protection sensing resistor R8 to form a 2A overcurrent protection circuit; the third pin VCAP of the first surge protection chip ADM1270 is connected to the fourth pin ISET; the third pin VCAP of the first surge protection chip ADM1270 is connected to the capacitor C7; the third pin VCAP of the first surge protection chip ADM1270 is connected to the seventh pin ENABLE; the fifth and sixth pins of the first surge protection chip ADM1270 are connected to the resistor formed by R2, R6, and R7 network; the 15th pin of the first surge protection chip ADM1270 is connected to the gate of the P-channel field effect transistor Q2; the 13th pin FLB of the first surge protection chip ADM1270 is connected to the voltage-dividing network formed by R9, R10, and R11; the 12th pin FB_PG of the first surge protection chip ADM1270 is connected to the voltage-dividing network formed by R9, R10, and R11; the 10th pin TIMER of the first surge protection chip ADM1270 is connected to the timing comparator charging capacitor C10; The 11th pin TIMER_OFF of the first surge protection chip ADM1270 is connected to the timing comparator charging capacitor C11; the 8th pin FAULT1 of the first surge protection chip ADM1270 is connected to LED1; the 14th pin PWRGD of the first surge protection chip ADM1270 is connected to LED3; the drain D of the P-channel field effect transistor Q2 is connected to LED2 through the current limiting resistor R19, and the drain D of the P-channel field effect transistor Q2 is connected to LED3 through the current limiting resistor R20.

8. The intrinsically safe power supply according to claim 7, characterized in that: Corresponding to the second-stage overcurrent and overvoltage protection circuit, the drain D of the P-channel field effect transistor Q2 at the positive output end of the first-stage overcurrent and overvoltage protection circuit is connected to the drain D of the reverse voltage suppression P-channel field effect transistor Q3 in the second-stage overcurrent and overvoltage protection circuit, and the gate G of the P-channel field effect transistor Q3 is connected to the second pin of the second surge protection chip ADM1270; the source S of the P-channel field effect transistor Q3 is connected to the source S of the output P-channel field effect transistor Q4 through the current detection resistor R16 to form a back-to-back reverse power supply suppression circuit; The 1st and 16th pins of the second surge protection chip ADM1270 are connected to the overcurrent protection sensing resistor R16 to form a 2A overcurrent protection circuit; the 3rd pin VCAP of the second surge protection chip ADM1270 is connected to the 4th pin ISET; the 3rd pin VCAP of the second surge protection chip ADM1270 is connected to the capacitor C17; the 3rd pin VCAP of the second surge protection chip ADM1270 is connected to the 7th pin ENABLE; the 5th and 6th pins of the second surge protection chip ADM1270 are connected to the resistor network composed of R13, R14, and R15; the 15th pin of the second surge protection chip ADM1270 is connected to the gate of the P-channel field effect transistor Q4; the 13th pin FLB of the second surge protection chip ADM1270 is connected to the voltage divider network composed of R17, R18, and R21; The 12th pin FB_PG of the surge protection chip ADM1270 is connected to the voltage divider network composed of R17, R18, and R21; the 10th pin TIMER of the second surge protection chip ADM1270 is connected to the timing comparator charging capacitor C15; the 11th pin TIMER_OFF of the second surge protection chip ADM1270 is connected to the timing comparator charging capacitor C16; the 8th pin FAULT2 of the second surge protection chip ADM1270 is connected to LED4; the 14th pin PWRGD of the second surge protection chip ADM1270 is connected to LED6; the drain D of the P-channel field effect transistor Q4 is connected to LED5 through the current limiting resistor R22, and the drain D of the P-channel field effect transistor Q4 is connected to LED6 through the current limiting resistor R24; the output end of the second-stage overvoltage and overcurrent protection circuit is connected to the terminal J10.

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