Low-power-consumption multi-channel transceiving frequency agility device

Abstract

The utility model discloses a low power consumption multichannel transmit-receive frequency agility device, which comprises a fast hopping frequency source unit, an up-conversion channel unit, a down-conversion channel unit and a control and power supply unit, and a frequency source assembly comprises a one-to-two power divider A, a first phase-locked loop branch, a second phase-locked loop branch, a one-out-of-two switch, a one-to-two power divider B and a frequency multiplier. The first phase-locked loop branch and the second phase-locked loop branch are respectively connected between the one-to-two power divider A and the one-out-of-two switch, the one-out-of-two switch is connected with the one-to-two power divider B, the rear end of the one-to-two power divider B is provided with a first output branch and a second output branch, and the frequency multiplier is arranged in the second output branch; the up-conversion channel unit and the down-conversion channel unit are respectively connected with the frequency source assembly. Two phase-locked loop circuits are configured for a channel to form a set of architecture in which a local oscillator signal 1 and a local oscillator signal 2 share a frequency source, so that the use of phase-locked loops is reduced, and the power consumption and the heat consumption are reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of transceiver frequency conversion components of Ka-band satellite communications, and in particular to a low-power multi-channel transceiver agile frequency conversion device. Background Art

[0002] With the rapid development of the current national economy and society, various satellite communication services have penetrated into all areas of social and economic life and are widely used in industries and sectors such as communications, national defense, transportation, aviation, and aerospace. As a result, the demand for satellite communication security is increasing day by day. Frequency hopping communication is an important anti-interference technology. It makes it difficult for jammers to lock on to the target by quickly switching between multiple frequencies, thereby improving the security and reliability of communication. The faster the frequency hopping time, the better the anti-interference performance.

[0003] Most traditional transceiver frequency conversion devices use a superheterodyne architecture with secondary frequency conversion. For frequency conversion components that require high spurious indicators, short frequency hopping time, and small frequency hopping steps (within 100Hz), the local oscillator signal 1 and the local oscillator signal 2 of the frequency conversion channel usually use independent frequency sources, and one of the local oscillator signals is designed to jump in large steps, and the other local oscillator signal uses a small step jump. The two are matched with each other to complete the small step jump in the entire passband. At the same time, in order to achieve nanosecond switching of the local oscillator frequency, both local oscillator signals are switched through a "ping-pong loop" to achieve fast frequency hopping. Therefore, the local oscillator signal 1 and the local oscillator signal 2 of each frequency conversion channel require two phase-locked loops to achieve the above requirements through switch switching ("ping-pong loop").

[0004] For a frequency conversion component with N channels, 4N phase-locked loop circuits are required. Usually, the power consumption of a single phase-locked loop circuit is much greater than the power consumption of the RF device used in the channel. Therefore, excessive use of phase-locked loops will greatly increase the size, power consumption and heat dissipation of the component. Utility Model Content

[0005] The embodiment of the present application provides a low-power multi-channel transceiver agile frequency conversion device. To address the problem that a large number of phase-locked loops are used in small-step and agile frequency conversion components, resulting in high component power consumption and large size, the utility model reduces the number of phase-locked loops used through a new frequency source circuit to reduce the power consumption and heat dissipation of the multi-channel transceiver agile frequency conversion device.

[0006] The embodiment of the present application provides a low-power multi-channel transceiver frequency agile device, comprising:

[0007] Fast hopping frequency source unit, a frequency source component is configured for each channel, and the frequency source component includes: a one-to-two power divider A, a first phase-locked loop branch, a second phase-locked loop branch, a two-to-one switch, a one-to-two power divider B, and a frequency multiplier. The first phase-locked loop branch and the second phase-locked loop branch are respectively connected between the one-to-two power divider A and the two-to-one switch. The two-to-one switch is connected to the one-to-two power divider B. The one-to-two power divider B has a first output branch and a second output branch at the rear end, and the frequency multiplier is arranged in the second output branch;

[0008] Up-conversion channel unit, having at least one up-conversion channel. In the up-conversion channel, a first up-mixer and a second up-mixer are connected in series. The first up-mixer is electrically connected to the corresponding first output branch, and the second up-mixer is electrically connected to the corresponding second output branch. The up-conversion channel unit is used to receive an intermediate frequency signal sent by an external system and realize the up-conversion of the Ka-band transmission signal;

[0009] Down-conversion channel unit, having at least one down-conversion channel. In the down-conversion channel, a first down-mixer and a second down-mixer are connected in series. The first down-mixer is electrically connected to the corresponding first output branch, and the second down-mixer is electrically connected to the corresponding second output branch. The down-conversion channel unit is used to receive the K-band radio frequency signal sent by the antenna array and realize the two-way power division and down-conversion of the received radio frequency signal;

[0010] Control and power supply unit, electrically connected to the fast hopping frequency source unit, the up-conversion channel unit, and the down-conversion channel unit respectively. The control and power supply unit is used to control the up-conversion channel and the down-conversion channel to receive and transmit signals of different frequencies.

[0011] The beneficial effect of the above embodiment is that: in this solution, two phase-locked loop circuits are configured for each channel, forming an architecture that shares the frequency source for a set of local oscillator signal 1 (LO1) and local oscillator signal 2 (LO2), reducing the use of phase-locked loops, thereby reducing the power consumption and heat dissipation of the multi-channel transceiver fast frequency conversion device.

[0012] On the basis of the above embodiment, the embodiment of the present application can also be improved as follows:

[0013] In one embodiment of the present application: a plurality of amplifiers, filters, and attenuators are also connected in series in the up-conversion channel.

[0014] In one embodiment of the present application: there is one up-conversion channel, and a duplexer is configured at the input end of the up-conversion channel, and a detector is coupled at the output end.

[0015] In one embodiment of the present application: An amplifier, a filter, and an attenuator are also connected in series in the down-conversion channel.

[0016] In one embodiment of the present application: The down-conversion channel unit includes two such down-conversion channels. The two down-conversion channels are connected to a power splitter, and a detector is coupled to the output end of the down-conversion channel.

[0017] In one embodiment of the present application: A power splitter is configured at the input end of the fast frequency hopping source unit. The power splitter is also connected in series with an amplifier, a filter, and the one-to-two power splitter A. An attenuator, an amplifier, a filter, and a phase-locked loop are respectively connected in series in the first phase-locked loop branch and the second phase-locked loop branch. An amplifier and a filter are also respectively connected in series in the first output branch and the second output branch.

[0018] In one embodiment of the present application: The control and power supply unit includes an FPGA chip, and an MCU chip, a storage chip, and a power supply component connected to the FPGA chip. The FPGA chip is electrically connected to the fast frequency hopping source unit, the up-conversion channel unit, and the down-conversion channel unit. Description of the Drawings

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to actual scale.

[0020] Figure 1 It is the principle block diagram of the low-power multi-channel transceiver fast frequency conversion device;

[0021] Figure 2 It is the schematic diagram of the up-conversion channel unit;

[0022] Figure 3 It is the schematic diagram of the down-conversion channel unit;

[0023] Figure 4 It is the schematic diagram of the fast frequency hopping source unit;

[0024] Figure 5 It is the schematic diagram of the control and power supply unit. Detailed Embodiments

[0025] In this application, unless otherwise clearly specified and defined, the terms in this application should be understood in a broad sense. For example, a connection can be a fixed connection, a detachable connection or an integral one, can be directly connected, or can be indirectly connected through an intermediate medium. If it involves electrical or electronic devices, it can also be an electrical connection or a communication signal connection, etc. For those of ordinary skill in the art, the specific meanings of different terms in this utility model can be understood according to specific circumstances, and the scope of the specific meanings should be limited to the realization of the functions of this application.

[0026] In the description of this application, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to this utility model.

[0027] As Figure 1 shown, a low-power multi-channel transceiver frequency agile device includes: a fast-hopping frequency source unit, an up-conversion channel unit, a down-conversion channel unit, and a control and power supply unit.

[0028] Specifically, as Figures 1-5As shown in the figure, each channel of the fast-hopping frequency source unit is configured with a frequency source component. The frequency source component includes: a one-to-two power splitter A, a first phase-locked loop branch, a second phase-locked loop branch, a two-to-one switch, a one-to-two power splitter B, and a frequency multiplier. The first phase-locked loop branch and the second phase-locked loop branch are respectively connected between the one-to-two power splitter A and the two-to-one switch. The two-to-one switch is connected to the one-to-two power splitter B. The one-to-two power splitter B has a first output branch and a second output branch at its rear end. The frequency multiplier is arranged in the second output branch. The up-conversion channel unit has at least one up-conversion channel. In the up-conversion channel, a first up-mixer and a second up-mixer are connected in series. The first up-mixer is electrically connected to the corresponding first output branch, and the second up-mixer is electrically connected to the corresponding second output branch. The up-conversion channel unit is used to receive the intermediate-frequency signal sent by the external system and realize the up-conversion of the Ka-band transmission signal. The down-conversion channel unit has at least one down-conversion channel. In the down-conversion channel, a first down-mixer and a second down-mixer are connected in series. The first down-mixer is electrically connected to the corresponding first output branch, and the second down-mixer is electrically connected to the corresponding second output branch. The down-conversion channel unit is used to receive the K-band radio frequency signal sent by the antenna array and realize the two-way power splitting and down-conversion of the received radio frequency signal. The control and power supply unit is electrically connected to the fast-hopping frequency source unit, the up-conversion channel unit, and the down-conversion channel unit respectively. The control and power supply unit is used to control the up-conversion channel and the down-conversion channel to receive and transmit signals of different frequencies.

[0029] The specific structure of the up-conversion channel unit is described below.

[0030] Among them, as Figure 1 , 2 shown, there is one up-conversion channel in the up-conversion channel unit. The input end of the up-conversion channel is configured with a duplexer, and the output end is coupled with a detector. Several amplifiers, filters, and attenuators are also connected in series in the up-conversion channel.

[0031] Specifically, as Figure 2 shown, an amplifier, a low-pass filter, a first up-mixer, a band-pass filter, an amplifier, an attenuator, a second up-mixer, a filter, and an amplifier are successively connected in series after the duplexer. The last amplifier is connected to the output end. The output end outputs a radio frequency signal. The detector coupled to the output end is used to couple a small signal for output power detection.

[0032] Working principle of the up-conversion channel unit: The transmitted intermediate-frequency signal (1890 MHz) and the reference clock signal (100 MHz) enter through the transmitted intermediate-frequency port together. The intermediate-frequency signal and the reference clock signal are separated by a duplexer. The separated intermediate-frequency signal is amplified and filtered and then undergoes the first mixing. The generated second intermediate-frequency signal is subjected to mixing spurious suppression by a band-pass filter to ensure the purity of the signal entering the subsequent link. After being amplified again and digitally controlled attenuated, it undergoes the second mixing to generate the final radio-frequency signal, which is then filtered, amplified and sent to the front-end transmitting module for power amplification.

[0033] The specific structure of the down-conversion channel unit is described below.

[0034] Among them, as Figure 1 , 3 shown, the down-conversion channel unit includes two down-conversion channels. The two down-conversion channels are connected to a power divider. A detector is coupled to the output end of the down-conversion channel. An amplifier, a filter and an attenuator are also connected in series in the down-conversion channel.

[0035] Specifically, as Figure 3 shown, a band-pass filter is connected in series at the input end of the down-conversion channel unit. An amplifier and a power divider are connected in series after the band-pass filter. Two down-conversion channels are connected in parallel after the power divider. Taking one of the down-conversion channels as an example for description, the down-conversion channel includes a low-pass filter, a first down-mixer, a band-pass filter, an amplifier, an AGC (Automatic Gain Control module), a second down-mixer, a filter and an amplifier connected in series in sequence. The last amplifier is connected to the output end, and the radio-frequency signal is output at the output end. The detector coupled to the output end is used to couple a small signal for output power detection.

[0036] Working principle of the down-conversion channel unit: The radio-frequency signal is amplified after passing through the band-pass filter and the amplifier, and then is divided into two paths. The two radio-frequency signals are respectively subjected to image-frequency filtering and then the first mixing to generate a first intermediate-frequency signal. The first intermediate-frequency signal is filtered and amplified and then undergoes the second mixing. The second intermediate-frequency signal is filtered and amplified and then output. The local oscillator signals received by the two down-conversion channels are independent of each other and can receive radio-frequency signals of different frequencies respectively.

[0037] The specific structure of the fast frequency-hopping source unit is described below.

[0038] Among them, as Figure 1 , 4 shown, a power divider is configured at the input end of the fast frequency-hopping source unit. An amplifier, a filter and a one-to-two power divider A are also connected in series to the power divider. An attenuator, an amplifier, a filter and a phase-locked loop are respectively connected in series in the first phase-locked loop branch and the second phase-locked loop branch. An amplifier and a filter are also respectively connected in series in the first output branch and the second output branch.

[0039] Specifically, as Figure 4 shown, since this application has one up-conversion channel and two down-conversion channels, that is, three channels in total, the power splitter at the input end is a one-to-three power splitter. After the one-to-three power splitter, three branches are connected in parallel. Taking one of the branches as an example (shown in the figure, the other two branches are not shown, and the structures of the three branches are the same), after the one-to-three power splitter, an amplifier, a low-pass filter, and a one-to-two power splitter A are connected in series. The first phase-locked loop branch is successively connected with an attenuator, an amplifier, an attenuator, a low-pass filter, a first phase-locked loop, an attenuator, an amplifier, an attenuator, and a two-way switch is connected after the last attenuator; the second phase-locked loop branch is successively connected with an attenuator, an amplifier, an attenuator, a low-pass filter, a second phase-locked loop, an attenuator, an amplifier, an attenuator, and a two-way switch is connected after the last attenuator. After the two-way switch, a one-to-two power splitter B is connected. The first output branch includes an amplifier and a low-pass filter connected in series with the one-to-two power splitter B in sequence. The second output branch includes a frequency multiplier, an amplifier, and a low-pass filter connected in series with the one-to-two power splitter B in sequence.

[0040] Working principle of the fast-hopping frequency source unit: The fast-hopping frequency source unit is composed of a "ping-pong loop" architecture, that is, two phase-locked loop circuits are switched by a switch to alternately output their respective frequencies. The reference clock is amplified and filtered and then divided into two by a one-to-two power splitter A, and are respectively given to the first phase-locked loop branch and the second phase-locked loop branch as the phase discrimination reference frequency. The system sequentially issues frequency words to the first phase-locked loop and the second phase-locked loop according to a specific timing for frequency locking, and then controls the switch through a trigger command to output the phase-locked loop that has locked the frequency currently. After the phase-locked loop frequency passes through the one-to-two power splitter B, one path is directly used as the first local oscillator signal for mixing in the channel after being amplified and filtered; the other path is quadrupled in frequency and then amplified and filtered, and finally used as the second local oscillator signal for mixing in the channel.

[0041] In this solution, each frequency conversion channel only uses one "ping-pong loop" architecture (2 phase-locked loops) to generate two local oscillator signals. The specific implementation solution is as follows: By calculating the difference between the radio frequency and the intermediate frequency (f RF -f IF ), this value is the sum of the frequencies of the two local oscillator signals (local oscillator 1 and local oscillator 2) during the entire frequency conversion process (f LO1 +f LO2 ). By reasonably allocating the frequencies of the two local oscillator signals, the frequency output by the phase-locked loop is power-divided into two paths. One path is directly used as the local oscillator signal 1, and the other path is quadrupled in frequency and used as the local oscillator 2, that is, f 锁相环 =(f RF -f IF ) / 5. Both local oscillator signals are used as the low local oscillator during the mixing process.

[0042] The specific structure of the control and power supply unit is described below.

[0043] Among them, as Figure 1 , 5 shown, the control and power supply unit includes an FPGA chip, as well as an MCU chip, a storage chip, and a power supply component connected to the FPGA chip. The FPGA chip is electrically connected to the fast hopping frequency source unit, the up-conversion channel unit, and the down-conversion channel unit.

[0044] Specifically, as Figure 5 shown, the storage chip uses a Flash chip. The power supply component includes a DCDC chip and an LDO chip. The DCDC chip is connected to the power supply through an external interface for voltage conversion, and the LDO chip is used to regulate the voltage output by the DCDC to +5V and -5V.

[0045] Working principle of the control and power supply unit: The serial port and discrete line interface for external communication of this device are uniformly interacted through the FPGA. The internal BIT health management is completed by the MCU and then forwarded by the FPGA for output to the system. The frequency word control of the frequency source and the gain control of the transceiver channels are directly controlled by the FPGA according to the instructions issued by the system. The voltage used in the digital part of the power supply unit is directly converted by the DCDC chip and sent to the corresponding chips. The voltage used in the channels and frequency source is first converted by the DCDC chip to +5.5V and -5.5V, and then regulated to +5V and -5V by the LDO chip and sent to the corresponding chips.

[0046] In response to the situation of relatively high power consumption caused by the large number of frequency sources used in the secondary frequency conversion architecture of the agile frequency conversion channel, this solution designs an architecture that shares the frequency source for local oscillator signal 1 (LO1) and local oscillator signal 2 (LO2). By sharing the frequency source in the multi-channel transceiver agile frequency conversion component, the actual power consumption of the component can be effectively reduced. In this embodiment, 6 phase-locked loop circuits are used in total, saving 6 phase-locked loop circuits compared with the traditional solution, and the component can save 8 - 10W of power consumption. At the same time, the volume and cost are also reduced.

[0047] This solution can realize the reception of K-band RF signals and the transmission of Ka-band RF signals. It has features such as power-on self-check, periodic self-check, frequency source lock indication, and program remote download in terms of function, and features such as small volume, low power consumption, fast frequency hopping time, and AGC gain control in terms of performance.

[0048] The above are only embodiments of the present utility model. Specific structures and common knowledge such as characteristics that are well-known in the art are not described in detail herein. Those of ordinary skill in the art know all the common general technical knowledge in the technical field to which the utility model pertains before the application date or the priority date, can acquire all the existing technologies in this field, and have the ability to apply the conventional experimental means before this date. Those of ordinary skill in the art can, under the inspiration given in this application, combine their own abilities to complete and implement this solution. Some typical well-known structures or well-known methods should not become obstacles for those of ordinary skill in the art to implement this application. It should be noted that for those skilled in the art, without departing from the structure of the present utility model, several deformations and improvements can still be made, and these should also be regarded as the protection scope of the present utility model, and these will not affect the implementation effect of the present utility model and the practicality of the patent.

Claims

1. A low-power multi-channel transceiver with frequency agile conversion, characterized in that, Including: A fast-hopping frequency source unit, where a frequency source component is configured for each channel. The frequency source component includes: a one-to-two power divider A, a first phase-locked loop branch, a second phase-locked loop branch, a two-to-one switch, a one-to-two power divider B, and a frequency multiplier. The first phase-locked loop branch and the second phase-locked loop branch are respectively connected between the one-to-two power divider A and the two-to-one switch. The two-to-one switch is connected to the one-to-two power divider B. The one-to-two power divider B has a first output branch and a second output branch at its rear end. The frequency multiplier is arranged in the second output branch; An up-conversion channel unit having at least one up-conversion channel. In the up-conversion channel, a first up-mixer and a second up-mixer are connected in series. The first up-mixer is electrically connected to the corresponding first output branch, and the second up-mixer is electrically connected to the corresponding second output branch. The up-conversion channel unit is used to receive an intermediate-frequency signal sent by an external system and realize up-conversion of the Ka-band transmission signal; A down-conversion channel unit having at least one down-conversion channel. In the down-conversion channel, a first down-mixer and a second down-mixer are connected in series. The first down-mixer is electrically connected to the corresponding first output branch, and the second down-mixer is electrically connected to the corresponding second output branch. The down-conversion channel unit is used to receive the K-band radio-frequency signal sent by the antenna array and realize two-way power division and down-conversion of the received radio-frequency signal; A control and power supply unit is electrically connected to the fast-hopping frequency source unit, the up-conversion channel unit, and the down-conversion channel unit respectively. The control and power supply unit is used to control the up-conversion channel and the down-conversion channel to receive and transmit signals of different frequencies.

2. The low-power multi-channel transceiver fast frequency conversion device according to claim 1, characterized in that Several amplifiers, filters, and attenuators are also connected in series in the up-conversion channel.

3. The low-power multi-channel transceiver frequency agile device according to claim 2, wherein There is one up-conversion channel, and a duplexer is configured at the input end of the up-conversion channel, and a detector is coupled to the output end.

4. The low-power multi-channel transceiver frequency agile device according to claim 1, characterized in that Amplifiers, filters, and attenuators are also connected in series in the down-conversion channel.

5. The low-power multi-channel transceiver frequency agile device according to claim 4, wherein The down-conversion channel unit includes two down-conversion channels. The two down-conversion channels are connected to a power divider, and a detector is coupled to the output end of the down-conversion channel.

6. The low-power multi-channel transceiver frequency agile device according to claim 1, characterized in that, A power divider is configured at the input end of the fast-hopping frequency source unit. The power divider is also connected in series with an amplifier, a filter, and the one-to-two power divider A. Attenuators, amplifiers, filters, and phase-locked loops are respectively connected in series in the first phase-locked loop branch and the second phase-locked loop branch. Amplifiers and filters are also respectively connected in series in the first output branch and the second output branch.

7. The low-power multi-channel transceiver frequency agile device according to claim 1, wherein The control and power supply unit includes an FPGA chip, as well as an MCU chip, a storage chip, and a power supply component connected to the FPGA chip. The FPGA chip is electrically connected to the fast-hopping frequency source unit, the up-conversion channel unit, and the down-conversion channel unit.

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