Power switch control circuit based on FPGA
Through the FPGA-based power switch control circuit, the FPGA unit and field effect tube design in the device can achieve low standby power consumption in the shutdown state, solving the problem of high standby power consumption of portable devices, improving battery life and reducing costs.
Patent Information
- Application Number
- CN202422629746.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-08-15
- Estimated Expiration
- 2034-10-30
AI Technical Summary
Portable devices have high standby power consumption when shut down, resulting in the gradual exhaustion of battery power and affecting the user experience.
Using the FPGA-based power switch control circuit, the existing FPGA units in the equipment are used to design the power switch control circuit to achieve low standby power consumption of the equipment in the shutdown state through NMOS and PMOS field effect transistors, switch diodes and self-complex key switches.
Significantly reduce the standby power consumption of portable devices in the shutdown state, improve battery life, and reduce the cost of using the control device.
Smart Images
Figure CN223229881U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of power supply control circuits, in particular to a power supply switch control circuit based on FPGA. Background Art
[0002] Most portable devices rely on batteries for power. Even when these devices are off, their status detection and power management circuits continue to consume energy, resulting in standby power consumption. This power consumption gradually depletes the battery's charge. If the device is off for extended periods, the battery may be completely discharged, impacting the user experience. Therefore, it is imperative to design a power switch control circuit based on an FPGA (Field Programmable Gate Array) to significantly reduce the standby power consumption of portable devices when they are off, thereby extending battery life. Utility Model Content
[0003] The purpose of this utility model is to overcome the shortcomings of the existing technology and provide a power switch control circuit based on FPGA, which is used in the main power switch control of portable devices powered by batteries, so as to reduce the standby power consumption of portable devices when they are turned off and improve the battery life of portable devices in the off state.
[0004] In order to achieve the above purpose, a power switch control circuit based on FPGA is designed, including NMOS D1, D5, PMOS D2, switching diodes D3, D4, a self-resetting key switch SW1, an FPGA unit U1, resistors R1-R7, and a programmable logic device FPGA. The battery output power supply VCC IN is connected to the source of PMOS D2, the first end of resistor R3, the first end of resistor R4, and the first end of resistor R5; the system power supply VCC OUT is connected to the drain of PMOS D2 and the first end of resistor R1; the first end of the self-resetting key switch SW1 is grounded, and the second end of switch SW1 is connected to the second end of the switching diode, the second end of resistor R4, and the gate of NMOS D1; the source of NMOS D1 is connected to the second end of resistor R2 and ground, and the drain of NMOS D1 is connected to the second end of resistor R1, the first end of the FPGA unit, and the first end of resistor R2; the gate of NMOS D5 is connected to the second end of resistor R6, and the source of NMOS D5 is connected to ground. The drain of D5 is connected to the second end of resistor R5 and the second end of switching diode D4; the second end of FPGA unit U1 is connected to the first end of resistor R6 and the first end of resistor R7; the second end of resistor R3 is connected to the first end of switching diode D3, the first end of switching diode D4, and the gate of PMOS D2 tube.
[0005] Preferably, the control circuit provided by the present invention also includes other technical features, wherein the power switch control circuit includes an FPGA unit, a key switch control unit, a key state detection unit, an FPGA switch control unit and a power switch unit, the key switch control unit is composed of a switching diode D3 and a self-resetting switch SW1; the key state detection unit is composed of an NMOS D1, a resistor R1, a resistor R2, and a resistor R4; the function of the key switch control unit is to control the power switch PMOS D2 to be turned on by controlling the key to be pressed, the function of the key state detection unit is to detect the key state information and output it to the FPGA unit, the function of the FPGA switch control unit is to control the power switch PMOS D2 to be turned on by the switch opening control signal output by the FPGA, the function of the power switch unit is to control the system power VCC OUT output to be turned on and off by turning on and off the PMOS D2, and the function of the FPGA unit in the power switch control circuit is to detect the key state in real time and output the power switch opening control signal.
[0006] Preferably, the control circuit provided by the present invention also includes other technical features, wherein the switch type is self-resetting, the rated current of the selected PMOS D2 needs to meet the load current requirements of the equipment, and the signal output by the button status detection unit to the FPGA unit needs to consider the FPGA level requirements to adapt the resistors R1 and R2.
[0007] Compared with the prior art, the utility model has the following advantages:
[0008] 1. Using an FPGA-based power switch control circuit can enable portable devices to maintain extremely low standby power consumption when powered off, significantly improving battery life.
[0009] 2. The power switch control circuit is implemented using the key FPGA unit already in the device. Compared with traditional power control solutions, it reduces the use of some control components and thus reduces costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 , is a circuit diagram of the utility model. DETAILED DESCRIPTION
[0011] In order to make the purpose, principle and structure of the present invention more clear, it is further described below with reference to the accompanying drawings and specific embodiments.
[0012] Example 1:
[0013] This embodiment provides a power switch control circuit based on FPGA. Figure 1 .
[0014] Including: N-channel enhancement mode field effect transistor (NMOS) D1, N-channel enhancement mode field effect transistor (NMOS) D5, P-channel enhancement mode field effect transistor (PMOS) D2, switching diode D3, switching diode D4, self-resetting key switch SW1, FPGA unit U1, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, and programmable logic device (FPGA).
[0015] The battery output power VCC IN is connected to the source of the PMOS D2, the first end of the resistor R3, the first end of the resistor R4, and the first end of the resistor R5; the system power VCC OUT is connected to the drain of the PMOS D2 and the first end of the resistor R1.
[0016] A first end of the self-resetting key switch SW1 is grounded, and a second end of the switch SW1 is connected to the second end of the switching diode, the second end of the resistor R4, and the gate of the NMOS D1.
[0017] The source of NMOS D1 is connected to the second end of the resistor R2 and the ground, and the drain of NMOS D1 is connected to the second end of the resistor R1, the first end of the FPGA unit, and the first end of the resistor R2.
[0018] The gate of the NMOS D5 is connected to the second end of the resistor R6 , the source of the NMOS D5 is connected to the ground, and the drain of the NMOS D5 is connected to the second end of the resistor R5 and the second end of the switching diode D4 .
[0019] The second end of the FPGA unit U1 is connected to the first end of the resistor R6 and the first end of the resistor R7.
[0020] The second end of the resistor R3 is connected to the first end of the switching diode D3, the first end of the switching diode D4, and the gate of the PMOS D2.
[0021] The switch provided in this embodiment is of the resettable type. The rated current of the PMOS D2 must meet the load current requirements of the device. The signal output from the key state detection unit to the FPGA unit must consider the FPGA level requirements and adapt the resistors R1 and R2.
[0022] This embodiment can be divided into five units, namely: FPGA unit, key switch control unit, key state detection unit, FPGA switch control unit, and power switch unit.
[0023] The key switch control unit consists of a switching diode D3 and a self-resetting switch SW1. The key state detection unit consists of an NMOS D1, resistors R1, R2, and R4. The key switch control unit controls the power switch PMOS D2 by turning on the key. The key state detection unit detects key state information and outputs it to the FPGA. The FPGA switch control unit uses the switch on control signal output by the FPGA to turn on the power switch PMOS D2. The power switch unit controls the system power supply VCC OUT output on and off by turning PMOS D2 on and off. The FPGA unit's function in the power switch control circuit is to detect the key state in real time and output the power switch on control signal.
[0024] The specific working method of this embodiment is as follows:
[0025] The status of each unit in the device shutdown state is described as follows: the battery input power VCC IN is turned on; the key switch control unit does not work, and the second end of the switching diode D3 is driven high by the resistor R4 and the battery input power VCC IN; the key status detection unit does not work; the FPGA unit does not work; the FPGA switch control unit does not work, the gate of the NMOS D5 is driven low by the resistors R6 and R7, the NMOS D5 is turned off, and the second end of the switching diode D4 is driven high by the resistor R5 and the battery input power VCC IN; the gate of the power switch unit PMOS D2 is driven high by the resistor R3 and the battery input power VCC IN, the PMOS D2 is turned off, and the system power VCC OUT output is turned off.
[0026] During device startup, the states of each unit are as follows: Pressing the self-resetting button SW1 turns it on, driving the second terminal of the switching diode D3 low. This drives the gate of the PMOS D2 low, turning it on. This then turns on the system power supply, VCC OUT. After the system power supply is turned on, the FPGA unit, the button status detection unit, and the FPGA switch control unit can operate. At this point, button SW1 remains pressed. The gate of the NMOS D1 in the button status detection unit is driven low, turning NMOS D1 off. The drain of NMOS D1 is driven high by resistor R1 and the system power supply, VCC OUT, and then sent to the FPGA unit. When the FPGA receives a signal from its first terminal that the button has been pressed for a set duration, it determines that the device needs to be powered on. The second terminal of the FPGA outputs a high switch control signal to NMOS D5, turning it on. This drives the second terminal of the switching diode D4 low, driving the gate of PMOS D2 low simultaneously by the switching diodes D3 and D4. After this, the reset button SW1 can be released. The second terminal of the switching diode D3 is driven high by resistor R4 and the battery input power supply VCCIN. The gate of the PMOS D2 is driven low by the switching diode D4, maintaining the PMOS D2 on, and the system power output remains on. When the button SW1 is released, the gate of the NMOS D1 in the button state detection unit is driven high by resistor R4 and the battery input power supply VCCIN, turning NMOS D1 on. The drain of NMOS D1 drives a low level to the FPGA unit, which receives the button release status. This completes the device startup process.
[0027] During device shutdown, the states of each unit are as follows: Pressing the self-resetting button SW1 turns it on, driving the gate of NMOS D1 in the button status detection unit low. NMOS D1 is then turned off. Resistor R1 and the system power supply VCCOUT drive the drain of NMOS D1 high, sending it to the FPGA unit. When the FPGA receives a signal from the first terminal indicating that the button has been pressed for longer than a set duration, it determines that the device needs to shut down. The second terminal of the FPGA outputs a low-level switch control signal to NMOS D5, turning it off. The second terminal of switching diode 4 is driven high by resistor R5 and the battery input VCC IN. At this point, button SW1 remains pressed, driving the second terminal of switching diode D3 low. The gate of PMOS D2, driven by switching diode D3, remains low, maintaining PMOS D2 on, and the system power output remains on. When button SW1 is released, the second terminal of switching diode D3 is driven high by resistor R4 and the battery input power supply VCCIN. Consequently, the second terminals of both switching diodes D3 and D4 are driven high. The gate of PMOS MOSFET D2 is driven high by resistor R3 and the battery input VCCIN, turning off PMOS MOSFET D2 and shutting down the system power output. At this point, all system units remain in the shutdown state: the FPGA unit, the key switch control unit, the key status detection unit, and the FPGA switch control unit are all inoperative.
[0028] The above description is only a specific implementation method of this utility model, but the protection scope of this utility model is not limited thereto. Any technician familiar with this technical field, within the technical scope disclosed by this utility model, can make equivalent substitutions or changes based on the technical solutions and new concepts of this utility model, which should be covered by the protection scope of this utility model.
Claims
1. A power switch control circuit based on FPGA, comprising NMOS D1, D5, PMOS D2, switching diodes D3, D4, a self-resetting key switch SW1, an FPGA unit U1, resistors R1-R7, and a programmable logic device FPGA, characterized in that The battery output power source VCC IN is connected to the source of the PMOS D2, the first end of the resistor R3, the first end of the resistor R4, and the first end of the resistor R5; The system power supply VCC OUT is connected to the drain of the PMOS D2 and the first end of the resistor R1; A first terminal of the self-resetting key switch SW1 is grounded, and a second terminal of the switch SW1 is connected to the second terminal of the switching diode, the second terminal of the resistor R4, and the gate of the NMOS D1; The source of the NMOS D1 is connected to the second end of the resistor R2 and the ground, and the drain of the NMOS D1 is connected to the second end of the resistor R1, the first end of the FPGA unit, and the first end of the resistor R2; The gate of the NMOS D5 is connected to the second end of the resistor R6, the source of the NMOS D5 is connected to the ground, and the drain of the NMOS D5 is connected to the second end of the resistor R5 and the second end of the switching diode D4; The second end of the FPGA unit U1 is connected to the first end of the resistor R6 and the first end of the resistor R7; The second end of the resistor R3 is connected to the first end of the switching diode D3, the first end of the switching diode D4, and the gate of the PMOS D2.
2. The FPGA-based power switch control circuit according to claim 1, characterized in that The power switch control circuit includes an FPGA unit, a key switch control unit, a key state detection unit, an FPGA switch control unit and a power switch unit. The key switch control unit is composed of a switching diode D3 and a self-resetting switch SW1; the key state detection unit is composed of an NMOS D1, a resistor R1, a resistor R2, and a resistor R4; the key switch control unit functions to control the power switch PMOS D2 to be turned on by controlling the key to be pressed, the key state detection unit functions to detect the key state information and output it to the FPGA unit, the FPGA switch control unit functions to control the power switch PMOS D2 to be turned on by the switch opening control signal output by the FPGA, the power switch unit functions to control the system power VCC OUT output to be turned on and off by turning on and off the PMOS D2, and the function of the FPGA unit in the power switch control circuit is to detect the key state in real time and output the power switch opening control signal.
3. The FPGA-based power switch control circuit according to claim 2, characterized in that The switch type is self-resetting, the rated current of PMOS D2 needs to meet the load current requirements of the equipment, and the signal output by the key status detection unit to the FPGA unit needs to consider the FPGA level requirements to adapt the resistors R1 and R2.