Circuit suitable for soft start and anti-oscillation of farad capacitor

Abstract

The utility model discloses a circuit suitable for soft start and anti-oscillation of a farad capacitor, comprising a DCDC power supply module which is electrically connected with a system load and a back-up power supply circuit. The back-up power supply circuit is electrically connected with a system load; the back-up power supply circuit comprises a first charging circuit and a second charging circuit which are electrically connected with the farad capacitor. According to the utility model, the drive current of the power supply module is effectively reduced through the soft start mode of the backup power supply, the influence caused by capacitor springback is avoided through the mode of detecting the delay response of the chip, and the problem of repeated oscillation and restart of the load caused by capacitor voltage springback is solved.

Description

Technical Field

[0001] The utility model relates to the field of electricity, in particular to a circuit suitable for soft starting and anti-oscillation of a farad capacitor. Background Art

[0002] Compared to lithium batteries, farad capacitors are chemically stable and do not undergo any chemical reactions, even during storage. They also have a long lifespan and can be used for 10,000 to 500,000 deep charge and discharge cycles without any "memory effect" or over-discharge issues. They also feature fast charging speeds, strong high-current discharge capabilities, high energy conversion efficiency, minimal process losses, and pollution-free raw material composition, production, use, storage, and disassembly processes, making them ideal green and environmentally friendly power sources. These advantages have led to their widespread use in designs requiring fast charging and discharging, long life, and environmental friendliness.

[0003] The simplest and most direct application of a farad capacitor as a backup power supply is to connect it directly in parallel with the load. The main power supply simultaneously charges the backup power supply and powers the load. When the main power supply is disconnected, the backup power supply discharges and powers the load until it can no longer support the load, after which the power slowly depletes. Due to the high internal resistance of a farad capacitor, when it is insufficient to power the load, the voltage will briefly rise to the load's minimum operating voltage. Repeated cycles can cause the load power supply to oscillate, and in severe cases, can cause system disruption. Therefore, improvements are needed. Utility Model Content

[0004] In order to solve the above technical problems, the utility model proposes a circuit suitable for soft starting and anti-oscillation of farad capacitors.

[0005] The purpose of the utility model is achieved through the following technical solutions:

[0006] A circuit suitable for soft starting and anti-oscillation of a farad capacitor, comprising a DCDC power supply module, the DCDC power supply module being electrically connected to a system load and a backup power supply circuit; the backup power supply circuit being electrically connected to the system load; the backup power supply circuit comprising a first charging circuit and a second charging circuit electrically connected to the farad capacitor; the first charging circuit comprising a first resistor R1, one end of the first resistor R1 being electrically connected to the DCDC power supply module, the system load and the negative electrode V5P0 of the farad capacitor, and the other end being electrically connected to the positive electrode of a first diode D1, the negative electrode of the first diode D1 being electrically connected to the positive electrode V5P0_DR of the farad capacitor; the second charging circuit The circuit includes a second resistor R2, one end of the second resistor R2 is electrically connected to one end of the first resistor R1, the other end of the second resistor R2 is electrically connected to the source of the first semiconductor switching device V1, the drain of the first semiconductor switching device V1 is electrically connected to one end of the third resistor R3, one end of the first capacitor C1 and the drain of the second semiconductor switching device V2; the source of the second semiconductor switching device V2 is electrically connected to the positive electrode V5P0_DR of the farad capacitor; the gate of the first semiconductor switching device V1, the gate of the second semiconductor switching device V2, the other end of the third resistor R3 and the other end of the first capacitor C1 are all electrically connected to the voltage detection circuit.

[0007] As a further improvement, the voltage detection circuit includes a delayed voltage detection chip U1, the fifth pin of the delayed voltage detection chip U1 is electrically connected to the gate of the third semiconductor switching device V3, the drain of the third semiconductor switching device V3 is electrically connected to the gate of the first semiconductor switching device V1, the gate of the second semiconductor switching device V2, the other end of the third resistor R3 and the other end of the first capacitor C1, and the source of the third semiconductor switching device V3 is electrically connected to the third pin of the delayed voltage detection chip U1 and is grounded.

[0008] As a further improvement, the source of the third semiconductor switching device V3 is also electrically connected to one end of the fifth capacitor C5, one end of the sixth capacitor C6 and one end of the fourth capacitor C4; the other end of the fifth capacitor C5 and the other end of the sixth capacitor C6 are electrically connected to the fourth pin of the delayed voltage detection chip U1; the other end of the fourth capacitor C4 is electrically connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is electrically connected to the positive electrode V5P0_DR of the farad capacitor.

[0009] As a further improvement, the first semiconductor switch device V1 and the second semiconductor switch device V2 are PMOS tubes or triodes, and the third semiconductor switch device V3 is an NMOS tube or triode.

[0010] As a further improvement, the gate of the third semiconductor switching device V3 is also electrically connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is electrically connected to one end of the fifth resistor R5 and the positive electrode V5P0_DR of the farad capacitor, and the other end of the fifth resistor R5 is electrically connected to the first pin of the delayed voltage detection chip U1, one end of the sixth resistor R6 and one end of the third capacitor C3; the other end of the sixth resistor R6 and the other end of the third capacitor C3 are electrically connected to the source of the third semiconductor switching device V3.

[0011] Further improvement, the model of the delayed voltage detection chip U1 is BLE2816A18M5G

[0012] The beneficial effects of the present invention are:

[0013] The utility model solves the "hiccup" phenomenon that occurs when the power module cannot carry the load during the power-on process by designing a response delay circuit. A fast and slow charging switching circuit for the farad capacitor is designed. When the power is first turned on or turned on again after a long time, the farad capacitor is soft-started to limit the charging current of the farad capacitor. When the farad capacitor is charged to the detection voltage threshold, the charging current is increased. At this time, the farad capacitor is in a fast charging state until the voltage stabilizes. The main power supply is disconnected and the backup farad capacitor begins to discharge. When the farad capacitor voltage drops to the detection voltage, due to the existence of the response delay circuit, the farad capacitor continues to discharge. At this time, the capacitor voltage is already below the detection threshold voltage until the response delay circuit output changes. The farad capacitor stops discharging. After the discharge stops, even if the farad capacitor voltage rises briefly, it cannot reach the detection voltage threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a circuit diagram of the utility model. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solutions and advantages of the utility model more clear, the utility model is further described in detail below with reference to the accompanying drawings and examples.

[0016] Refer to the following Figure 1 The structure of the present utility model will be described in detail.

[0017] The DCDC power module outputs the V5P0 voltage, one end of which is directly connected to the system load and the other end to the backup power circuit. On the backup power circuit side, one path passes through resistor R1 and diode D1 to the farad capacitor, and the other path passes through resistor R2, PMOS tube V1, and PMOS tube V2 to the farad capacitor. The positive electrode V5P0_DR of the farad capacitor is connected to the input VIN pin of the delay voltage detection chip through the voltage divider resistors R5 and R6, and the output pin of the delay voltage detection chip is connected to the control gate of the NMOS tube V3. Several situations that occur during the operation of the circuit are as follows:

[0018] First, during normal power-on operation: The DC-DC power module simultaneously supplies power to the system load and the supercapacitor. If the supercapacitor charging current is not limited, the power module may not be able to handle supercapacitive loads of this magnitude, or the power module's instantaneous output current may be very high. This design utilizes a method whereby, during initial power-up, the supercapacitor is slowly charged with a small current through current-limiting resistor R1 and unidirectional conducting diode D1. This charging process does not affect the normal operation of the system load. Delayed voltage detection chip U1 continuously monitors the supercapacitor voltage V5P0_DR. When the supercapacitor voltage continues to rise but has not yet reached the set threshold voltage, U1 outputs a low level to the control gate of NMOS transistor V3, turning NMOS transistor V3 off. Consequently, the other charging path for the supercapacitor, current-limiting resistor R2, PMOS transistors V1, and PMOS transistors V2, also turn off. When the voltage detection chip U1 detects that V5P0_DR reaches the designed voltage, U1 outputs a high level to the control gate of the NMOS tube V3, V3 is turned on, and then the two back-to-back connected PMOS tubes V1 and V2 are turned on. At this time, the main charging path of the farad capacitor becomes the resistor R2, PMOS tubes V1 and V2. Through this path, the farad capacitor is quickly charged until the farad capacitor is fully charged and V5P0_DR is maintained stable.

[0019] During the first normal power-off, when the DC-DC input loses power, the system load is powered by the supercapacitor. Because V5P0_DR is greater than the designed threshold voltage, NMOS transistor V3 remains on, and the PMOS transistors V1 and V2 also remain on. At this point, the supercapacitor discharge current flows from V5P0_DR to PMOS transistor V2, then PMOS transistor V1, resistor R2, and finally the system load. Because voltage detection chip U1 can be programmed with a delay response time through capacitors C5 and C6, when the voltage on V5P0_DR drops below U1's designed threshold voltage, U1's output does not respond immediately but with a delay. During this time, the supercapacitor continues to discharge below the threshold voltage. When U1's output shifts, NMOS transistor V3 is turned off, shutting down the supercapacitor discharge path. After the path is shut down, even if the supercapacitor voltage rebounds, it will not rebound above the threshold voltage. Furthermore, the delay ensures reliable shutdown of the discharge path.

[0020] Abnormal power failure and power-on: When the DCDC power module powers up immediately after a power failure, the presence of the farad capacitor causes a voltage drop to the system load, but this does not affect the load's operation. In extreme cases, the DCDC module powers up immediately after the farad capacitor drops to near the designed threshold voltage and is about to shut down and discharge, or immediately after it is shut down. In this circuit, due to the presence of a delayed-response voltage detection chip, in extreme cases, the load may only operate normally, the farad capacitor may charge rapidly, or the load may have lost power and require powering up again, slowly charging the farad capacitor and then switching to a fast-charging state. This circuit design reliably solves this problem.

[0021] In this design, the advantage of connecting two PMOS transistors in series is that when the gate is controlled to turn on the transistor, current can flow either from left to right or from right to left. When the gate is controlled to turn off the transistor, resistor R3 can achieve mutual exclusion, similar to the function of a reverse diode. Adding NMOS transistor V3 allows V1 or V2 to be turned on or off by controlling the gate of V3, achieving the goal of controlling two with one transistor. The benefit of adding a voltage detection chip with adjustable delay is mainly reflected in the voltage rebound at the moment of initial power-up and after the farad capacitor stops discharging, which may cause the load to repeatedly restart.

[0022] This circuit is designed for low power consumption and reliability in practical applications. The various functions in the design can also be implemented in other ways. For example, transistors can be used instead of the MOS tubes in this design to achieve the same function. The delayed response drive circuit can also be built using peripheral components. The integrated IC used in this design is more reliable and consumes less power. Furthermore, if cost is not a concern, a high-power DC-DC power module can also be used as a replacement.

[0023] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the essence and scope of the technical solution of the present invention.

Claims

1. A circuit suitable for soft starting and anti-oscillation of farad capacitors, characterized in that: The invention comprises a DCDC power supply module, the DCDC power supply module is electrically connected to a system load and a backup power supply circuit; the backup power supply circuit is electrically connected to the system load; the backup power supply circuit comprises a first charging circuit and a second charging circuit electrically connected to a farad capacitor; the first charging circuit comprises a first resistor (R1), one end of the first resistor (R1) is electrically connected to the DCDC power supply module (1), the system load (2) and the negative electrode (V5P0) of the farad capacitor, and the other end is electrically connected to the positive electrode of a first diode (D1), and the negative electrode of the first diode (D1) is electrically connected to the positive electrode (V5P0_DR) of the farad capacitor; the second charging circuit comprises a second resistor (R2), one end of the second resistor (R2) is electrically connected to one end of the first resistor (R1), the other end of the second resistor (R2) is electrically connected to the source of a first semiconductor switch device (V1), and the drain of the first semiconductor switch device (V1) is electrically connected to one end of a third resistor (R3), one end of a first capacitor (C1) and the drain of the second semiconductor switch device (V2); The source of the second semiconductor switch device (V2) is electrically connected to the positive electrode (V5P0_DR) of the farad capacitor; the gate of the first semiconductor switch device (V1), the gate of the second semiconductor switch device (V2), the other end of the third resistor (R3) and the other end of the first capacitor (C1) are all electrically connected to the voltage detection circuit.

2. The anti-oscillation circuit suitable for soft start with a source-connected farad capacitor as claimed in claim 1, characterized in that: The voltage detection circuit comprises a time-delay voltage detection chip (U1), a fifth pin of the time-delay voltage detection chip (U1) is electrically connected to the gate of a third semiconductor switch device (V3), a drain of the third semiconductor switch device (V3) is electrically connected to the gate of the first semiconductor switch device (V1), the gate of the second semiconductor switch device (V2), the other end of a third resistor (R3) and the other end of a first capacitor (C1), and a source of the third semiconductor switch device (V3) is electrically connected to the third pin of the time-delay voltage detection chip (U1) and is grounded.

3. The circuit suitable for soft starting and anti-oscillation of a farad capacitor as claimed in claim 2, characterized in that: The source of the third semiconductor switch device (V3) is also electrically connected to one end of a fifth capacitor (C5), one end of a sixth capacitor (C6), and one end of a fourth capacitor (C4); the other end of the fifth capacitor (C5) and the other end of the sixth capacitor (C6) are electrically connected to the fourth pin of the delayed voltage detection chip (U1); the other end of the fourth capacitor (C4) is electrically connected to one end of the second capacitor (C2), and the other end of the second capacitor (C2) is electrically connected to the positive electrode (V5P0_DR) of the farad capacitor.

4. The circuit suitable for soft starting and anti-oscillation of a farad capacitor as claimed in claim 3, characterized in that: The first semiconductor switch device (V1) and the second semiconductor switch device (V2) are PMOS tubes or triodes, and the third semiconductor switch device (V3) is an NMOS tube or triode.

5. The circuit suitable for soft starting and anti-oscillation of a farad capacitor as claimed in claim 2, characterized in that: The gate of the third semiconductor switch device (V3) is also electrically connected to one end of a fourth resistor (R4); the other end of the fourth resistor (R4) is electrically connected to one end of a fifth resistor (R5) and the positive electrode (V5P0_DR) of the farad capacitor; the other end of the fifth resistor (R5) is electrically connected to the first pin of the delayed voltage detection chip (U1), one end of a sixth resistor (R6) and one end of the third capacitor (C3); the other end of the sixth resistor (R6) and the other end of the third capacitor (C3) are electrically connected to the source of the third semiconductor switch device (V3).

6. The circuit suitable for soft starting and anti-oscillation of a farad capacitor as claimed in claim 2, characterized in that: The model of the delayed voltage detection chip (U1) is BLE2816A18M5G.

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