Shifting register, driving circuit and display device

Abstract

The utility model provides a shift register, a driving circuit and a display device, and relates to the technical field of display. The shift register includes: a shift circuit configured to control potentials of a first node and a second node and supply a first power supply voltage or a second power supply voltage to a first output terminal as a first output signal; the gating circuit is configured to provide a gating signal from a gating end to a third node under the control of a first input signal, a second input signal from a second input end and a first output signal; the control circuit is configured to provide the potential of the first node to the fourth node and provide the potential of the second node to the fifth node under the control of the potential of the third node; and the output circuit is configured to provide the first power supply voltage or the second power supply voltage to the second output end as a second output signal under the control of the potential of the fourth node and the potential of the fifth node.

Description

TECHNICAL FIELD

[0001] The utility model relates to display technical field especially relates to a shift register, drive circuit and display device. BACKGROUND

[0002] In order to achieve good compatibility in power consumption and high refresh frequency, display products usually adopt area refresh technology, and through the control of the output of driving signal in a frame, the data signal of only part of lines in the display product can be updated.

[0003] The display product usually uses TFT (Thin Film Transistor) as a switching tube or a driving tube. Since the TFT has a leakage phenomenon, when the area refresh technology is adopted, flickering bright and dark lines and other problems are prone to occur at the critical position of refresh frequency switching. SUMMARY

[0004] To at least partially solve the above problems, the utility model provides a shift register, drive circuit and display device.

[0005] One aspect of the utility model provides a shift register, comprising: shift circuit, be configured as under the control of first clock signal from first clock end, second clock signal from second clock end, first power supply voltage of first power supply, second power supply voltage of second power supply and first input signal from first input end, control the electric potential of first node and second node, and provide first power supply voltage or second power supply voltage to first output end as first output signal;Gate circuit, be configured as under the control of first input signal, second input signal from second input end and first output signal, provide the gate signal from gate to third node;Control circuit, be configured as under the control of the electric potential of third node, provide the electric potential of first node to fourth node, provide the electric potential of second node to fifth node;And output circuit, be configured as under the control of the electric potential of fourth node and the electric potential of fifth node, provide first power supply voltage or second power supply voltage to second output end as second output signal.

[0006] Another aspect of the utility model provides a drive circuit, comprising the cascade of M shift registers as described above, and M is an integer greater than 1.

[0007] Another aspect of the utility model provides a display device, comprising the drive circuit as described above. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other objects, features and advantages of the utility model will be more apparent from the following description of the utility model embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1A A structural schematic diagram of an example pixel circuit is shown.

[0010] Figure 1B A signal timing diagram of an example pixel circuit is shown.

[0011] Figure 2 A structural schematic diagram of an example shift register is shown.

[0012] Figure 3 A schematic diagram of a bright band of an example display panel is shown.

[0013] Figure 4 A signal timing diagram of an example shift register is shown.

[0014] Figure 5 A signal waveform diagram of an example shift register is shown.

[0015] Figure 6 A block diagram of a shift register according to an embodiment of the present application is shown schematically.

[0016] Figure 7 A structural schematic diagram of a shift register according to another embodiment of the present application is shown schematically.

[0017] Figure 8 A waveform diagram of an output signal of a shift register of a high refresh frequency region according to an embodiment of the present application is shown schematically.

[0018] Figure 9 A waveform diagram of an output signal of a shift register of a low refresh frequency region according to an embodiment of the present application is shown schematically.

[0019] Figure 10 A waveform diagram of an output signal of a shift register of a high refresh frequency region switching to a low refresh frequency region according to an embodiment of the present application is shown schematically.

[0020] Figure 11 A signal timing diagram of a shift register 700 according to an embodiment of the present application is shown schematically.

[0021] Figure 12 A signal waveform diagram of a shift register 700 according to an embodiment of the present application is shown schematically.

[0022] Figure 13 An effect diagram of two driving circuits according to an embodiment of the present application is shown schematically.

[0023] Figure 14 A structural schematic diagram of a shift register according to another embodiment of the present application is shown schematically.

[0024] Figure 15 A structure diagram of a shift register according to another embodiment of the present application is schematically shown.

[0025] Figure 16 A structure diagram of a shift register according to another embodiment of the present application is schematically shown.

[0026] Figure 17 A structure diagram of a shift register according to another embodiment of the present application is schematically shown.

[0027] Figure 18 A structure diagram of a shift register according to another embodiment of the present application is schematically shown.

[0028] Figure 19 A structure diagram of a shift register according to another embodiment of the present application is schematically shown.

[0029] Figure 20 A structure diagram of a driving circuit according to an embodiment of the present application is schematically shown.

[0030] Figure 21 A structure diagram of a driving circuit according to another embodiment of the present application is schematically shown.

[0031] Figure 22A A plan view of a semiconductor layer according to an embodiment of the present application is schematically shown.

[0032] Figure 22B A plan view of a first conductive layer according to an embodiment of the present application is schematically shown.

[0033] Figure 22C A plan view of a second conductive layer according to an embodiment of the present application is schematically shown.

[0034] Figure 22D A plan view of a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer according to an embodiment of the present application is schematically shown.

[0035] Figure 22E A plan view of a third conductive layer and a fourth conductive layer according to an embodiment of the present application is schematically shown.

[0036] Figure 22F A plan view of a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer according to an embodiment of the present application is schematically shown.

[0037] Figure 22G A plan view of a fifth conductive layer according to an embodiment of the present application is schematically shown.

[0038] Figure 22H A plan view of a sixth conductive layer according to an embodiment of the present application is schematically shown.

[0039] Figure 22I A plan view of a semiconductor layer, a second conductive layer, a fifth conductive layer, and a sixth conductive layer according to an embodiment of the present application is schematically shown.

[0040] Figure 22J A plan view of a fourth conductive layer and a sixth conductive layer according to an embodiment of the present application is schematically shown.

[0041] Figure 22K A plan view of a semiconductor layer, a second conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer according to an embodiment of the present application is schematically shown.

[0042] Figure 23 A structure diagram of a display device according to an embodiment of the present application is schematically shown.

[0043] Figure 24 A flowchart of a driving method according to an embodiment of the present application is schematically shown. DETAILED DESCRIPTION

[0044] In order to make the objects, technical solutions, and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application but not all. Based on the described embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present application. It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals. In the following description, some specific embodiments are only for the purpose of description and should not be understood as any limitation on the present application, but only as examples of the embodiments of the present application. When it may cause confusion to the understanding of the present application, the conventional structure or configuration will be omitted. It should be noted that the shapes and sizes of the components in the drawings do not reflect the true size and ratio, but only illustrate the content of the embodiments of the present application.

[0045] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the general meaning understood by those skilled in the art. The "first", "second", and similar words used in the embodiments of the present application do not represent any order, quantity, or importance, but are only used to distinguish different components.

[0046] Further, in the description of the embodiments of the present application, the term "electrically connected" can mean that two components are directly connected to each other, or that two components are connected to each other via one or more other components. Further, the two components can be connected or coupled by wire or wirelessly.

[0047] The source and the drain of the switching transistor used in the embodiments of the present application are symmetrical, so the source and the drain can be interchangeable. In the embodiments of the present application, according to the functions, one of the source and the drain can be referred to as a first pole, and the other of the source and the drain can be referred to as a second pole.

[0048] Further, in the description of the embodiments of the present application, the terms "first power supply voltage" and "second power supply voltage" are only used to distinguish the amplitudes of the two power supply voltages. For example, in the following description, the "first power supply voltage" is taken as a relatively low voltage, and the "second power supply voltage" is taken as a relatively high voltage. Those skilled in the art can understand that the present application is not limited thereto.

[0049] It should be noted that in the description of the embodiments of the present application, INPUT1 can represent both a first input signal terminal and a first input signal provided by a first input terminal. Similarly, the symbol CK can represent both a first clock terminal and a first clock signal provided by the first clock terminal; the symbol CB can represent both a second clock terminal and a second clock signal provided by the second clock terminal; OUT1 can represent both a first output terminal and a first output signal output by the first output terminal; VGL can represent both a first power supply and a first power supply voltage; VGH can represent both a second power supply and a second power supply voltage; MS1 can represent both a first gate terminal and a first gate signal, and so on. The following embodiments are the same as this, and will not be described again.

[0050] Figure 1A A structural schematic diagram of an example pixel circuit is shown, Figure 1B A signal timing diagram of an example pixel circuit is shown.

[0051] As Figure 1A shown, the pixel circuit 100 can be a 7T1C pixel circuit. In the pixel circuit 100, the transistors M1 to M2, the transistors M4 to M7 can be switching tubes, the transistor M3 is a driving tube, the transistors M3 to M7 are P-type tubes, and the transistors M1 and M2 are N-type tubes.

[0052] As Figure 1BAs shown, in the T1 stage when the pixel circuit 100 is working, the enable signal EM is high to turn off the transistor M5 and the transistor M6; the reset signal RST1 is high to turn on the transistor M1, so as to pull the potential of the node Q1 to the initialization signal Vinit1, and thus the capacitor Cst can be reset by the initialization signal Vinit.

[0053] In the T2 stage when the pixel circuit 100 is working, the reset signal RST1 is low to turn off the transistor M1; the driving signal NGate is high to turn on the transistor M2, the driving signal PGate is low to turn on the transistor M4, and the data signal Vdata charges the capacitor Cst through the transistor M4, the driving transistor M3 and the transistor M2. When the Vgs of the driving transistor M3 is V(Q1)-V(Q2)=V(Q1)-Vdata=Vth, the driving transistor M3 is turned off, and the voltage maintained by the capacitor Cst is V(Q1)=Vdata+Vth. At the same time, the driving signal PGate is low to turn on the transistor M7, so as to reset the anode of the light emitting element EL by the initialization signal Vinit.

[0054] In the T3 stage when the pixel circuit 100 is working, the driving signal NGate is low to turn off the transistor M2, the driving signal PGate is high to turn off the transistor M4 and the transistor M7, the enable signal EM is low to turn on the transistor M5 and the transistor M6, and the Vgs of the driving transistor M3 is V(Q1)-V(Q2)=Vdata+Vth-ELVDD, so that the light emitting element EL can emit light according to the potential of the data signal Vdata.

[0055] In the pixel circuit of the example, if the driving signal NGate is high, the transistor M2 is turned on, and the data signal Vdata can be written into the pixel circuit 100, so as to update the brightness of the light emitting element EL of the pixel circuit 100. Correspondingly, the pixel row where the pixel circuit 100 is located is refreshed in the current frame. If the driving signal NGate is low, the transistor M2 is always turned off, and the data signal Vdata cannot be written into the pixel circuit 100, so that the brightness of the light emitting element EL does not change, and the brightness of the pixel row where the pixel circuit 100 is located is maintained in the current frame.

[0056] Therefore, by controlling the potential of the driving signal NGate, whether the pixel brightness is refreshed can be realized, so as to realize the partial refresh of the display picture. In the display product, the shift register can be usually used to realize the gating of the driving signal NGate.

[0057] Figure 2 A structure schematic diagram of an example shift register is shown.

[0058] As shown in Figure 2 An example shift register 200 can be a 16T3C+10T4C circuit.

[0059] In the high frequency region, the selection signal MS is low. When the input signal Scan(n-1) and the input signal Q9(n-2) are low at the same time, the transistor M8 and the transistor M9 are turned on, the selection signal MS applies low level to the node Q3, the transistor M10 is turned on, and the potential of the node Q4 is equal to the potential of the node Q5. When the input signal Scan(n-1) is high, the potentials of the node Q5 and the node Q4 are both low, the transistor M11 is turned on, and the driving signal NGate output from the output terminal is VGH. When the input signal Scan(n-1) is low, the potentials of the node Q5 and the node Q4 are both high, the transistor M11 is turned off, and the transistor M12 is turned on. In addition, when the clock signal CB is low, the potential of the node Q6 is further pulled down, and the potential of the node Q7 is also a potential lower than VGL, so the transistor M13 is turned on, and the driving signal NGate output from the output terminal is VGL.

[0060] In the low frequency region, the selection signal MS is high. When the input signal Scan(n-1) and the input signal Q9(n-2) are low at the same time, the transistor M8 and the transistor M9 are turned on, the selection signal MS applies high level to the node Q3, and the transistor M10 is turned off. When the input signal Scan(n-1) is low, the potential of the node Q5 is high, and the potential of the node Q8 is low, so the output terminal outputs a step signal. When the clock signal CB is converted from high level to low level, the potentials of the node Q6 and the node Q7 are further pulled down due to the self-boosting effect of the capacitor, and at this time, the driving signal NGate output from the output terminal is VGL. When the input signal Scan(n-1) is high, the low potential of the node Q5 cannot be applied to the node Q4 due to the turn-off of the transistor M10, so the node Q4 remains high, the transistor M11 remains turned off, the node Q7 remains low, the transistor M13 remains turned on, and the driving signal NGate output from the output terminal is VGL.

[0061] Thus, in the high frequency region, the level of the driving signal NGate output from the output terminal can change with the change of the input signal Scan(n-1), and in the low frequency region, the driving signal NGate output from the output terminal is always VGL regardless of whether the input signal Scan(n-1) is high or low, so the selection of the driving signal NGate can be realized.

[0062] Due to the precision and process factors of components, the shift register cannot work in an ideal state, which leads to a high incidence of the critical position bright band problem of the refresh frequency switching. The bright band of the display panel is as shown in Figure 3As shown in FIG. 6, when the selection signal MS is switched from high frequency to low frequency, the signal timing diagram and the signal waveform diagram of the shift register 200 can be as shown in FIG. 7 and FIG. 8, respectively. Figure 4 and Figure 5 .

[0063] Figure 3 A schematic diagram of a bright band of an example display panel is shown, Figure 4 A signal timing diagram of an example shift register is shown, Figure 5 A signal waveform diagram of an example shift register is shown. In Figure 5 , the solid line can represent the signal waveform of the last row of the high frequency area, and the dashed line can represent the signal waveform of the normal row of the high frequency area.

[0064] As shown in FIG. 6, when the selection signal MS is switched from high frequency to low frequency, the signal timing diagram and the signal waveform diagram of the shift register 200 can be as shown in FIG. 7 and FIG. 8, respectively. Figure 3 , Figure 4 and Figure 5 In this example, when the selection signal MS is switched from high frequency to low frequency, the selection signal MS needs to go through a process of switching from low level to high level. At this time, the gate voltage of the transistor M8 and the transistor M9 of the last row of the high frequency area is different from that of the normal row of the high frequency area, so that the off degree of the transistor M8 and the transistor M9 is not sufficient, resulting in that the high level of the selection signal MS is applied to the node Q3 through leakage, thereby affecting the potential of the node Q3. The potential of the node Q3 slowly rises, so that the on degree of the transistor M10 and the transistor M12 is not sufficient, so that the potential of the node Q7 is not low enough, thereby making the on degree of the transistor M13 not as sufficient as that of the normal row of the high frequency area, resulting in that the drive signal NGate output by the last row of the high frequency area is not low enough, and the drive signal NGate output by the last row of the high frequency area has a higher step. Therefore, there is a difference between the pixel current output by the last row of the high frequency area and the pixel current output by the normal row of the high frequency area, and the last row of the high frequency area will have problems such as flickering bright and dark lines.

[0065] For example, a plurality of shift registers 200 in cascade can drive a plurality of pixel rows in a pixel array. For example, the low levels of a plurality of drive signals NGate output by the plurality of shift registers 200 in cascade are sequentially shifted. For example, when the drive signal NGate is at a high level, the pixel circuit can be refreshed by a data signal, and at this time, the effective level of the drive signal NGate is high. When the effective level of the drive signal NGate output by the shift register lasts for a long time, the drive signals NGate output by adjacent two shift registers have a period of time when they are simultaneously at a high level. For example, when the drive signal NGate output by the mth shift register jumps from a high level to a low level, the drive signal NGate output by the m+1th shift register jumps from a low level to a high level.

[0066] When the plurality of shift registers 200 in cascade scan the plurality of pixel rows row by row, the level of the selection signal MS can jump. For example, the plurality of shift registers 100 in cascade can include 1000 shift registers. When the first 500 shift registers output the driving signal NGate in turn, the selection signal MS is at low level, and at this time, the first 500 shift registers output the driving signal NGate in turn to refresh the first 500 pixel rows in the pixel circuit. When the last 500 shift registers output the driving signal NGate in turn, the selection signal MS jumps from low level to high level, and at this time, the last 500 shift registers output the driving signal NGate in turn at high level, and the last 500 pixel rows in the pixel circuit are not refreshed.

[0067] When the driving signal NGate output by the 500th shift register jumps from high level to low level, the selection signal MS can jump from low level to high level. At this time, the time of the level jump of the selection signal MS can occur after the driving signal NGate output by the 501th shift register jumps from low level to high level and before the driving signal NGate jumps from high level to low level. At this time, the driving signal NGate output by the 501th shift register is at high level. In this case, as described above, the transistor M2 in the pixel circuit 100 is briefly opened, causing the data signal to be partially written, so that the 501th pixel row will have display abnormality.

[0068] Therefore, the utility model provides a shift register to at least partially solve the problem of flickering bright and dark lines when high frequency is switched to low frequency.

[0069] Figure 6 A block diagram of a shift register according to an embodiment of the utility model is schematically shown.

[0070] As shown in Figure 6 The shift register 600 can include a shift circuit 610, a selection circuit 620, a control circuit 630, and an output circuit 640.

[0071] The shift circuit 610 can be electrically connected with a first clock terminal CK, a second clock terminal CB, a first power supply VGL, a second power supply VGH, and a first input terminal INPUT1. Under the control of a first clock signal CK from the first clock terminal CK, a second clock signal CB from the second clock terminal CB, a first power supply voltage VGL of the first power supply VGL, a second power supply voltage VGH of the second power supply VGH, and a first input signal INPUT1 from the first input terminal INPUT1, the shift circuit 610 can control the potentials of a first node N1 and a second node N2, and provide the first power supply voltage VGL or the second power supply voltage VGH to a first output terminal OUT1 as a first output signal OUT1.

[0072] The gating circuit 620 can be electrically connected with the gating terminal MS, the first input terminal INPUT1, the second input terminal INPUT2, and the first output terminal OUT1. Under the control of the first input signal INPUT1, the second input signal INPUT2 from the second input terminal INPUT2, and the first output signal OUT1, the gating circuit 620 can provide a gate signal MS from the gating terminal MS to the third node N3.

[0073] For example, the first input signal INPUT1, the second input signal INPUT2, and the first output signal OUT1 can jointly control the gating circuit 620 to switch between the conductive state and the non-conductive state. When the first input signal INPUT1, the second input signal INPUT2, and the first output signal OUT1 jointly control the gating circuit to be in the conductive state, the gate signal MS is written to the third node N3. When the first input signal INPUT1, the second input signal INPUT2, and the first output signal OUT1 jointly control the gating circuit 620 to be in the non-conductive state, the potential of the third node N3 can maintain the state of the last stage.

[0074] Under the control of the potential of the third node N3, the control circuit 630 can provide the potential of the first node N1 to the fourth node N4, and provide the potential of the second node N2 to the fifth node N5.

[0075] For example, the potential of the third node N3 can control the control circuit 630 to switch between the conductive state and the non-conductive state. When the potential of the third node N3 controls the control circuit 630 to be in the conductive state, the potential of the second node N2 is written to the fifth node N5. When the potential of the third node N3 controls the control circuit 630 to be in the non-conductive state, the potential of the fifth node N5 can maintain the state of the last stage.

[0076] The output circuit 640 is electrically connected with the first power supply VGL, the second power supply VGH, and the second output terminal OUT2. Under the control of the potential of the fourth node N4 and the potential of the fifth node N5, the output circuit 640 can provide the first power supply voltage VGL or the second power supply voltage VGH to the second output terminal OUT2 as the second output signal OUT2.

[0077] For example, the potential of the fourth node N4 can control the second power supply VGH to be in the conductive state or the non-conductive state with the second output signal OUT2. When the second power supply VGH is in the conductive state with the second output signal OUT2, the output circuit 640 provides the second power supply voltage VGH to the second output terminal OUT2, and the second output terminal OUT2 outputs a high-level signal.

[0078] For example, the potential of the fifth node N5 can control the first power supply VGL and the second output signal OUT2 to be in a communication state or a cutoff state. When the first power supply VGL and the second output signal OUT2 are in the communication state, the output circuit 640 provides the first power supply voltage VGL to the second output terminal OUT2, and the second output terminal OUT2 outputs a low-level signal.

[0079] In the embodiment of the utility model, the second output signal OUT2 can be a scanning signal, which is used for driving the transistor M2 in the pixel circuit 100 described above. For example, when the level of the second output signal OUT2 is high, the transistor M2 is turned on, and the data signal can be written, so as to realize picture refreshing. When the level of the second output signal OUT2 is low, the transistor M2 is cut off, and the data signal cannot be written, so as to realize picture non-refreshing and keeping unchanged.

[0080] In the embodiment of the utility model, the first output signal OUT1 output by the shift circuit 610 is connected to the gate-on circuit 620 as the input of the gate-on circuit 620, so as to utilize the phase difference between the first output signal OUT1 and the first input signal INPUT1, reduce the leakage of the gate-on signal MS from the gate-on terminal MS to the first node N1 in the switching process of the gate-on signal MS, and thus reduce the influence of the leakage on the open state of the transistor, improve the bright band problem of the critical position of the refreshing frequency switching, and effectively improve the display performance.

[0081] Optionally, under the control of the first clock signal CK, the first power supply voltage VGL and the first input signal INPUT1, the shift circuit 610 can provide at least one of the second clock signal CB and the second power supply voltage VGH to the first node N1.

[0082] For example, based on the first clock signal CK and the first power supply voltage VGL, the shift circuit 610 can control the second clock terminal CB and the first node N1 to be in a communication state or a cutoff state. Based on the first clock signal CK and the first input signal INPUT1, the shift circuit 610 can control the second power supply VGH and the first node N1 to be in a communication state or a cutoff state.

[0083] When the second clock terminal CB and the first node N1 are in the communication state, the shift circuit 610 provides the second clock signal CB to the first node N1. Or when the second power supply VGH and the first node N1 are in the communication state, the shift circuit 610 provides the second power supply voltage VGH to the first node N1. Or when the second clock terminal CB and the first node N1 are in the communication state and the second power supply VGH and the first node N1 are in the communication state, the shift circuit 310 provides the second clock signal CB and the second power supply voltage VGH to the first node N1.

[0084] Optionally, under the control of the first clock signal CK, the shift circuit 610 can provide the first input signal INPUT1 to the second node N2.

[0085] For example, based on the first clock signal CK1, the shift circuit 610 can control the first input terminal INPUT1 and the second node N2 to be in a communication state or a cutoff state. When the first input terminal INPUT1 and the second node N2 are in a communication state, the shift circuit 610 provides the first input signal INPUT1 to the second node N2.

[0086] Optionally, under the control of the potential of the first node N1, the potential of the second node N2 and the first power voltage VGL, the shift circuit 610 can provide the first power voltage VGL or the second power voltage VGH to the first output terminal OUT1 as the first output signal OUT1.

[0087] For example, based on the potential of the second node N2 and the first power voltage VGL, the shift circuit can control the first power VGL and the first output terminal OUT1 to be in a communication state or a cutoff state.

[0088] In the embodiment of the utility model, the first output signal OUT1 output by the first output terminal OUT1 is provided to other shift registers cascaded with the shift register, for realizing the shift driving of the cascaded multiple shift registers.

[0089] For example, the shift register can be the mth shift register, the first output signal OUT1 can be provided to the first input terminal of the m+1th shift register, and the first output signal OUT1 can also be provided to the first input terminal of the m+2th shift register.

[0090] Optionally, the control circuit 630 can also be electrically connected with the second power VGH and the second output terminal OUT2. Under the control of the potential of the fifth node N5 and the second output signal OUT2, the control circuit can control the potential of the fourth node N4 by using the second power voltage VGH.

[0091] For example, based on the potential of the fifth node N5 and the second output terminal OUT2, the control circuit can control the communication state or the cutoff state between the fourth node N4 and the second power VGH. When the fourth node N4 and the second power VGH are in a communication state, the control circuit 630 can provide the second power voltage VGH to the fourth node N4, and at this time, the voltage of the fourth node N4 is high. Under the control of the high level, the second output terminal OUT2 and the second power VGH are in a cutoff state, so as to avoid the influence of the second power voltage VGH on the output of the low level signal by the second output terminal OUT2.

[0092] Optionally, the gating circuit 720 can also be electrically connected with the first power supply VGL and the third input terminal INPUT3. Under the control of the third input signal INPUT3 from the third input terminal INPUT3, the gating circuit can control the potential of the third node N3 by using the first power supply VGL voltage.

[0093] In the embodiment of the utility model, the gating circuit is electrically connected with the third input terminal INPUT3, the third node N3 and the first power supply VGL. Under the control of the third input signal INPUT3, the gating circuit can reset the third node N3 by using the first power supply voltage VGL and pull down the potential of the third node N3.

[0094] For example, based on the third input signal INPUT3, the gating circuit can control the first power supply VGL and the third node N3 to be in a communication state or a cutoff state. When the first power supply VGL and the third node N3 are in a communication state, the gating circuit 720 provides the first power supply voltage VGL to the third node N3. For example, the first input signal INPUT1, the second input signal INPU2 and the first output signal OUT1 can control the gating terminal MS and the third node N3 to be in a communication state, so as to write the gating signal MS into the third node N3; and the third input signal INPUT3 can control the first power supply VGL and the third node N3 to be in a communication state, so as to write the first power supply voltage VGL into the third node N3 and reset the potential of the third node N3.

[0095] For example, when the potential of the third node N3 is high, the second output signal OUT2 output by the output circuit 740 does not refresh the corresponding pixel row. After refreshing a frame of the display picture, the gating circuit 720 pulls down the potential of the third node N3 again, so that in the refreshing process of the next frame of picture, the gating signal MS controls the potential of the third node N3 again. When the potential of the third node N3 is low after refreshing a frame of the display picture, the gating circuit 720 also writes the first power supply voltage VGL into the third node N3, so as to ensure that the potential of the third node N3 is stably kept at a low potential. Based on the reset of the potential of the third node N3 by the gating circuit 720, the working stability of the circuit can be improved.

[0096] Optionally, the gating signal MS can come from other shift registers cascaded with the shift register. The gating signal MS provided by the other shift register can be used for the gating of the second output signal OUT2 output by the shift register.

[0097] For example, the shift register can be an mth shift register, and the gating terminal MS can be electrically connected with the second output terminal OUT2 of the (m-1)th shift register and the (m-2)th shift register respectively.

[0098] Optionally, the gating circuit 620 comprises a first transistor T1, a second transistor T2 and a third transistor T3. The first transistor T1, the second transistor T2 and the third transistor T3 are connected in series between the third node N3 and the gating terminal, the gate of the first transistor T1 is connected with the first output terminal OUT1, the gate of the second transistor T2 is connected with the first input terminal INPUT1, and the gate of the third transistor T3 is connected with the second input terminal INPUT2. The following will be described in combination with Figures 7-19 .

[0099] Figure 7 The structure schematic diagram of the shift register according to another embodiment of the present application is schematically shown.

[0100] As Figure 7 shown, the shift register 700 can comprise a shift circuit 710, a gating circuit 720, a control circuit 730 and an output circuit 740.

[0101] The gating circuit 720 can comprise a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4.

[0102] The first pole of the first transistor T1 is connected with the third node N3, and the second pole of the first transistor T1 is connected with the sixth node N6.

[0103] The first pole of the second transistor T2 is connected with the sixth node N6, and the second pole of the second transistor T2 is connected with the seventh node N7.

[0104] The first pole of the third transistor T3 is connected with the seventh node N7, and the second pole of the third transistor T3 is connected with the gating terminal.

[0105] The gate of the fourth transistor T4 is connected with the third input terminal INPUT3, the first pole of the fourth transistor T4 is connected with the third node N3, and the second pole of the fourth transistor T4 is connected with the first power supply VGL.

[0106] The control circuit 730 can comprise a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a first capacitor C1.

[0107] The gate of the fifth transistor T5 is connected with the third node N3, the first pole of the fifth transistor T5 is connected with the second node N2, and the second pole of the fifth transistor T5 is connected with the fifth node N5.

[0108] The gate of the sixth transistor T6 is connected with the third node N3, the first pole of the sixth transistor T6 is connected with the first node N1, and the second pole of the sixth transistor T6 is connected with the fourth node N4.

[0109] The gate of the seventh transistor T7 is connected with the fifth node N5, the first electrode of the seventh transistor T7 is connected with the second electrode of the eighth transistor T8, the second electrode of the seventh transistor T7 is connected with the second power supply VGH, the gate of the eighth transistor T8 is connected with the second output terminal OUT2, and the first electrode of the eighth transistor T8 is connected with the fourth node N4.

[0110] The first end of the first capacitor C1 is connected with the fourth node N4, and the second end of the first capacitor C1 is connected with the third node N3.

[0111] The output circuit 740 can include a ninth transistor T9, a tenth transistor T10, a second capacitor C2 and a third capacitor C3.

[0112] The gate of the ninth transistor T9 is connected with the fourth node N4, the first electrode of the ninth transistor T9 is connected with the second power supply VGH, and the second electrode of the ninth transistor T9 is connected with the second output terminal OUT2.

[0113] The gate of the tenth transistor T10 is connected with the fifth node N5, the first electrode of the tenth transistor T10 is connected with the second output terminal OUT2, and the second electrode of the tenth transistor T10 is connected with the first power supply VGL.

[0114] The first end of the second capacitor C2 is connected with the fourth node N4, and the second end of the second capacitor C2 is connected with the second power supply VGH.

[0115] The first end of the third capacitor C3 is connected with the fifth node N5, and the second end of the third capacitor C3 is connected with the second output terminal OUT2.

[0116] The shift circuit 710 can include eleventh to twenty-seventh transistors T11-T27 and fourth to seventh capacitors C4-C7.

[0117] The gate of the eleventh transistor T11 is connected with the first power supply VGL, the first electrode of the eleventh transistor T11 is connected with the twelfth node N12, and the second electrode of the eleventh transistor T11 is connected with the tenth node N10.

[0118] The gate of the twelfth transistor T12 is connected with the first power supply VGL, the first electrode of the twelfth transistor T12 is connected with the second node N2, and the second electrode of the twelfth transistor T12 is connected with the eighth node N8.

[0119] The gate of the thirteenth transistor T13 is connected with the control terminal NCX, the first electrode of the thirteenth transistor T13 is connected with the second power supply VGH, and the second electrode of the thirteenth transistor T13 is connected with the second node N2.

[0120] The gate of the fourteenth transistor T14 is connected with the second clock end CB, the first electrode of the fourteenth transistor T14 is connected with the thirteenth node N13, and the second electrode of the fourteenth transistor T14 is connected with the fourth node N4.

[0121] The gate of the fifteenth transistor T15 is connected with the first power supply VGL, the first electrode of the fifteenth transistor T15 is connected with the fourteenth node N14, and the second electrode of the fifteenth transistor T15 is connected with the ninth node N9.

[0122] The gate of the sixteenth transistor T16 is connected with the ninth node N9, the first electrode of the sixteenth transistor T16 is connected with the eighth node N8, and the second electrode of the sixteenth transistor T16 is connected with the ninth node N9.

[0123] The gate of the seventeenth transistor T17 is connected with the ninth node N9, the first electrode of the seventeenth transistor T17 is electrically connected to the ninth node N9, and the second electrode of the seventeenth transistor T17 is connected with the fifth node N5.

[0124] The gate of the eighteenth transistor T18 is connected with the fifth node N5, the first electrode of the eighteenth transistor T18 is connected with the first node N1, and the second electrode of the eighteenth transistor T18 is connected with the second power supply VGH.

[0125] The gate of the nineteenth transistor T19 is connected with the first node, the first electrode of the nineteenth transistor T19 is connected with the second power supply VGH, and the second electrode of the nineteenth transistor T19 is connected with the first output end OUT1.

[0126] The gate of the twentieth transistor T20 is connected with the eighth node N8, the first electrode of the twentieth transistor T20 is connected with the first output end OUT1, and the second electrode of the twentieth transistor T20 is connected with the first power supply VGL.

[0127] The gate of the twenty-first transistor T21 is connected with the first clock end CK, the first electrode of the twenty-first transistor T21 is connected with the first input end INPUT1, and the second electrode of the twenty-first transistor T21 is connected with the second node N2.

[0128] The gate of the twenty-second transistor T22 is connected with the second node N2, the first electrode of the twenty-second transistor T22 is connected with the twelfth node N12, and the second electrode of the twenty-second transistor T22 is connected with the first clock end CK.

[0129] The gate of the twenty-third transistor T23 is connected with the first clock end CK, the first electrode of the twenty-third transistor T23 is connected with the first power supply VGL, and the second electrode of the twenty-third transistor T23 is connected with the twelfth node N12.

[0130] The gate of the twenty-fourth transistor T24 is connected with the first clock end CK, the first electrode of the twenty-fourth transistor T24 is connected with the first input end INPUT1, and the second electrode of the twenty-fourth transistor T24 is connected with the fourteenth node N14.

[0131] The gate of the twenty-fifth transistor T25 is connected with the twelfth node N12, the first electrode of the twenty-fifth transistor T25 is connected with the second power supply VGH, and the second electrode of the twenty-fifth transistor T25 is connected with the eleventh node N11.

[0132] The gate of the twenty-sixth transistor T26 is connected with the tenth node N10, the first electrode of the twenty-sixth transistor T26 is connected with the second clock end CB, and the second electrode of the twenty-sixth transistor T26 is connected with the thirteenth node N13.

[0133] The gate of the twenty-seventh transistor T27 is connected with the ninth node N9, the first electrode of the twenty-seventh transistor T27 is connected with the eleventh node N11, and the second electrode of the twenty-seventh transistor T27 is connected with the second clock end CB.

[0134] The first end of the fourth capacitor C4 is connected with the first node N1, and the second end of the fourth capacitor C4 is connected with the second power supply VGH.

[0135] The first end of the fifth capacitor C5 is connected with the first output end OUT1, and the second end of the fifth capacitor C5 is connected with the first power supply VGL.

[0136] The first end of the sixth capacitor C6 is connected with the eleventh node N11, and the second end of the sixth capacitor C6 is connected with the ninth node N9.

[0137] The first end of the seventh capacitor C7 is connected with the tenth node N10, and the second end of the seventh capacitor C7 is connected with the thirteenth node N13.

[0138] In the embodiment of the utility model, the first transistor T1 to the twenty-seventh transistor T27 are P type TFT transistor. For example, the active layer is low temperature doped polysilicon (LTPS) thin film transistor. Those skilled in the art can understand that the first transistor T1 to the twenty-seventh transistor T27 in the utility model can also be N type TFT transistor, for example, the active layer is indium gallium zinc oxide (IGZO) thin film transistor, and the level of the gate drive signal of each transistor can be changed accordingly.

[0139] In addition, those skilled in the art can understand that the capacitor can be realized as a single capacitor or a plurality of parallel or series capacitor units, as long as it can realize its corresponding function.

[0140] In the description of this utility model embodiment, the first node N1 to the fourteenth node N14 do not represent actual existing components, but rather represent the junction points of related circuit connections in the circuit diagram.

[0141] Optionally, for multiple cascaded shift drivers, the shift register can be the m-th stage shift driver. The first input terminal INPUT1 can be connected to the first output terminal OUT1 of the (m-1)-th stage shift driver, the second input terminal INPUT2 can be connected to the thirteenth node N13 of the (m-2)-th stage shift driver, and the third input terminal INPUT3 can be connected to the eleventh node N11 of the (m-1)-th stage shift driver.

[0142] Figure 8 The diagram schematically illustrates the waveform of the output signal of the shift register in the high refresh rate region according to an embodiment of the present invention. Figure 9 The diagram schematically illustrates the waveform of the output signal of the shift register in the low refresh rate region according to an embodiment of the present invention. Figure 10 The diagram schematically illustrates the waveform of the output signal of the shift register switching between the high refresh rate region and the low refresh rate region according to an embodiment of the present invention. Figure 11 The schematic diagram illustrates the signal timing of a shift register 700 according to an embodiment of the present invention. Figure 12 The diagram schematically illustrates the signal waveforms of a shift register 700 according to an embodiment of the present invention. Figure 13 The diagram schematically illustrates the effect of two driving circuits according to embodiments of the present invention. Figure 12 In this diagram, lines of different gray levels can represent the signal waveforms of the last high-frequency line and the normal high-frequency line, respectively. Darker gray lines represent the signal waveform of the last high-frequency line, while lighter gray lines represent the signal waveform of the normal high-frequency line.

[0143] The following is based on Figure 7 Taking the structure of the shift register 700 shown as an example, combined with... Figures 8-12 The working process of the shift register 700 provided in this embodiment of the present invention is described. Out(1) to out(4) are signal waveform diagrams of the high refresh frequency region, and Out(5) to out(8) are signal waveform diagrams of the low refresh frequency region.

[0144] like Figures 8 to 12 As shown, in the high refresh rate region, the strobe signal MS is at a low level.

[0145] At the t1 period, the first input signal INPUT1, the second input signal INPUT2 and the first output signal OUT1 are low, the first transistor T1, the second transistor T2 and the third transistor T3 are turned on, the low level of the strobe signal MS is written into the third node N3, and the sixth transistor T6 is turned on. At this time, the voltage of the fourth node N4 and the voltage of the first node N1 are both high. The ninth transistor T9 is turned off.

[0146] At the t2 period, the first input signal INPUT1 is high, the voltage of the fourth node N4 and the voltage of the first node N1 are both low, and the ninth transistor T9 is turned on. The second output signal OUT2 is high. In addition, the level of the third node N3 is low, and the fifth transistor T5 is turned on. The voltage of the second node N2, the eighth node N8 and the fifth node N5 are all high, and the tenth transistor T10 is turned off.

[0147] At the t3 period, the first input signal INPUT1 is low, the voltage of the second node N2, the eighth node N8 and the ninth node N9 are all low, and the voltage of the fifth node N5 is higher than the first power voltage VGL due to the threshold voltage Vth of the twenty-fourth transistor T24 and the fifteenth transistor T15. Therefore, the tenth transistor T10 is not fully turned on, and the second output signal OUT is higher than the first power voltage VGL.

[0148] At the t4 period, the second clock signal CB changes from high to low, and the voltage of the fifth node N5 is lower than the first power voltage VGL due to the capacitor self-boosting effect of the capacitor C2. The tenth transistor T10 is fully turned on, and the voltage of the second output signal OUT2 is the same as the first power voltage VGL.

[0149] In the low refresh frequency region, the strobe signal MS is high.

[0150] At the t1 period, the first input voltage INPUT1, the second input voltage INPUT2 and the first output signal OUT1 are low, the first transistor T1, the second transistor T2 and the third transistor T3 are turned on, the high level of the strobe signal MS is written into the third node N3, and the sixth transistor is turned off. The voltage of the fourth node N4 remains high at the previous moment, the ninth transistor T9 is turned off, and the second power supply and the second output end are in a turned-off state. At this time, the voltage of the second node N2, the eighth node N8 and the ninth node N9 are low, the voltage of the fifth node N5 is low, the tenth transistor T10 is turned on, the first power supply VGL is in communication with the second output end OUT2, and the second output end OUT2 outputs the first power voltage VGL.

[0151] At the t2 period, the first input voltage INPUT1 is high level, the first node N1 is low level, the third node N3 is high level, the sixth transistor T6 is off, the fourth node N4 voltage keeps the high level of the last moment, the ninth transistor T9 is off, the second power supply VGH and the second output terminal OUT2 are in the off state. At this time, the voltage of the second node T2, the eighth node N8 and the ninth node N9 is high level, the sixteenth transistor, the seventeenth transistor and the fifth transistor are off, the fifth node N5 maintains the low level of the last moment, the tenth transistor T10 connects the second output terminal OUT2 and the first power supply VGL, and the output second output terminal OUT outputs the first power supply voltage VGL.

[0152] At the t3 period, the voltage of the first input signal INPUT1 is low level, the voltage of the second node N2, the eighth node N8 and the ninth node N9 is low level, and the voltage of the fifth node N5 is higher than the first power supply voltage VGL due to the threshold voltage Vth of the twenty-fourth transistor T24 and the fifteenth transistor T15, so that the tenth transistor T10 is not fully turned on, thereby causing the second output signal OUT2 to be higher than the first power supply voltage VGL.

[0153] At the t4 period, the second clock signal CB changes from high level to low level, the voltage of the fifth node 5 is lower than the first power supply voltage VGL due to the capacitor self-boosting effect of the capacitor C2, and the tenth transistor T10 is fully turned on to output the first power supply voltage VGL as the second output signal OUT2.

[0154] In the shift register 700, the first output terminal OUT1 is connected with the gate of the first transistor T1, so as to control the turn-on and turn-off state of the first transistor T1 by using the first output signal OUT1. Based on the phase difference between the first output signal OUT1 and the first input signal INPUT1, the time of the leakage current from the gate of the third transistor T3 to the third node N3 can be reduced, so that the voltage levels of the third node N3 and the seventh node N7 tend to be consistent, the influence of the leakage current on the opening state of the fifth transistor T5 is reduced, and the bright band problem of the critical position of the refresh frequency switching can be improved, thereby effectively improving the display performance.

[0155] Reference Figure 13 The first driving circuit can include a plurality of cascaded shift registers 200. The second driving circuit can include a plurality of cascaded shift registers 700. Based on Figure 13 As shown in the signal waveform, there is a significant difference between the output signal of the high-frequency normal row and the output signal of the high-frequency last row of the first driving circuit, and the output signal of the high-frequency normal row and the output signal of the high-frequency last row of the second driving circuit of the embodiment of the present application tend to be consistent.

[0156] Figure 14 A schematic diagram of the structure of a shift register according to another embodiment of the present invention is shown.

[0157] like Figure 14 As shown, the shift register 1400 may include a shift circuit 1410, a gating circuit 1420, a control circuit 1430, and an output circuit 1440. The shift circuit 1410, control circuit 1430, and output circuit 1440 are similar to the shift circuit 710, control circuit 730, and output circuit 740 described above, and will not be repeated for simplicity. The connection method of the transistors in the gating circuit 1420 is not limited to the connection method shown in the gating circuit 720.

[0158] For example, the gating circuit 1420 may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0159] The first terminal of the first transistor T1 is connected to the third node N3, and the second terminal of the first transistor T1 is connected to the sixth node N6.

[0160] The first terminal of the second transistor T2 is connected to the seventh node N7, and the second terminal of the second transistor T2 is connected to the gate terminal.

[0161] The first terminal of the third transistor T3 is connected to the sixth node N6, and the second terminal of the third transistor T3 is connected to the seventh node N7.

[0162] The gate of the fourth transistor T4 is connected to the third input terminal INPUT3, the first terminal of the fourth transistor T4 is connected to the third node N3, and the second terminal of the fourth transistor T4 is connected to the first power supply VGL.

[0163] Figure 15 A schematic diagram of the structure of a shift register according to another embodiment of the present invention is shown.

[0164] like Figure 15 As shown, the shift register 1500 may include a shift circuit 1510, a gating circuit 1520, a control circuit 1530, and an output circuit 1540. The shift circuit 1510, control circuit 1530, and output circuit 1540 are similar to the shift circuit 710, control circuit 730, and output circuit 740 described above, and will not be repeated for simplicity. The connection method of the transistors in the gating circuit 1520 is not limited to the connection method shown in the gating circuit 720.

[0165] For example, the gating circuit 1520 may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0166] The first electrode of the first transistor T1 is connected with the sixth node N6, and the second electrode of the first transistor T1 is connected with the seventh node N7.

[0167] The first electrode of the second transistor T2 is connected with the third node N3, and the second electrode of the second transistor T2 is connected with the sixth node N6.

[0168] The first electrode of the third transistor T3 is connected with the seventh node N7, and the second electrode of the third transistor T3 is connected with the gate.

[0169] The gate of the fourth transistor T4 is connected with the third input terminal INPUT3, the first electrode of the fourth transistor T4 is connected with the third node N3, and the second electrode of the fourth transistor T4 is connected with the first power supply VGL.

[0170] Figure 16 The structure schematic diagram of the shift register according to another embodiment of the utility model is shown.

[0171] As Figure 16 shown, the shift register 1600 can include a shift circuit 1610, a gate circuit 1620, a control circuit 1630 and an output circuit 1640. Among them, the shift circuit 1610, the control circuit 1630 and the output circuit 1640 are similar to the shift circuit 710, the control circuit 730 and the output circuit 740 described above respectively, and are not described again for simplicity. The connection mode of the transistor in the gate circuit 1620 is not limited to the connection mode shown in the gate circuit 720.

[0172] For example, the gate circuit 1620 can include a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4.

[0173] The first electrode of the first transistor T1 is connected with the seventh node N7, and the second electrode of the first transistor T1 is connected with the gate.

[0174] The first electrode of the second transistor T2 is connected with the third node N3, and the second electrode of the second transistor T2 is connected with the sixth node N6.

[0175] The first electrode of the third transistor T3 is connected with the sixth node N6, and the second electrode of the third transistor T3 is connected with the seventh node N7.

[0176] The gate of the fourth transistor T4 is connected with the third input terminal INPUT3, the first electrode of the fourth transistor T4 is connected with the third node N3, and the second electrode of the fourth transistor T4 is connected with the first power supply VGL.

[0177] Figure 17 The structure schematic diagram of the shift register according to another embodiment of the utility model is shown.

[0178] As Figure 17 shown in FIG. 17, the shift register 1700 can include a shift circuit 1710, a gating circuit 1720, a control circuit 1730, and an output circuit 1740. Among them, the shift circuit 1710, the control circuit 1730, and the output circuit 1740 are similar to the shift circuit 710, the control circuit 730, and the output circuit 740 described above respectively, and will not be described again for the sake of simplicity. The connection mode of the transistors in the gating circuit 1720 is not limited to the connection mode shown in the gating circuit 720.

[0179] For example, the gating circuit 1720 can include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0180] The first electrode of the first transistor T1 is connected with the sixth node N6, and the second electrode of the first transistor T1 is connected with the seventh node N7.

[0181] The first electrode of the second transistor T2 is connected with the seventh node N7, and the second electrode of the second transistor T2 is connected with the gating end.

[0182] The first electrode of the third transistor T3 is connected with the third node N3, and the second electrode of the third transistor T3 is connected with the sixth node N6.

[0183] The gate of the fourth transistor T4 is connected with the third input end INPUT3, the first electrode of the fourth transistor T4 is connected with the third node N3, and the second electrode of the fourth transistor T4 is connected with the first power supply VGL.

[0184] Figure 18 The structure schematic diagram of the shift register according to another embodiment of the present application is schematically shown.

[0185] As Figure 18 shown in FIG. 18, the shift register 1800 can include a shift circuit 1810, a gating circuit 1820, a control circuit 1830, and an output circuit 1840. Among them, the shift circuit 1810, the control circuit 1830, and the output circuit 1840 are similar to the shift circuit 710, the control circuit 730, and the output circuit 740 described above respectively, and will not be described again for the sake of simplicity. The connection mode of the transistors in the gating circuit 1820 is not limited to the connection mode shown in the gating circuit 720.

[0186] For example, the gating circuit 1820 can include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0187] The first electrode of the first transistor T1 is connected with the seventh node N7, and the second electrode of the first transistor T1 is connected with the gating end.

[0188] The first electrode of the second transistor T2 is connected with the sixth node N6, and the second electrode of the second transistor T2 is connected with the seventh node N7.

[0189] The first electrode of the third transistor T3 is connected with the third node N3, and the second electrode of the third transistor T3 is connected with the sixth node N6.

[0190] The gate of the fourth transistor T4 is connected with the third input terminal INPUT3, the first electrode of the fourth transistor T4 is connected with the third node N3, and the second electrode of the fourth transistor T4 is connected with the first power supply VGL.

[0191] Figure 19 The structure schematic diagram of the shift register according to another embodiment of the utility model is schematically shown.

[0192] As Figure 19 shown, the shift register 1900 can include a shift circuit 1910, a gating circuit 1920, a control circuit 1930 and an output circuit 1940. Among them, the shift circuit 1910, the control circuit 1930 are similar to the shift circuit 710, the control circuit 730 and the output circuit 740 described above respectively, and are not described again for simplicity. The transistors in the gating circuit 1920 are not limited to the transistors shown in the gating circuit 720.

[0193] For example, the gating circuit 1920 can include a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4. Among them, the second transistor T2 is a double-gate transistor, and similarly, at least one of the first transistor T1 and the third transistor T3 can also be a double-gate transistor in the embodiments of the utility model.

[0194] The first electrode of the first transistor T1 is connected with the third node N3, and the second electrode of the first transistor T1 is connected with the sixth node N6.

[0195] The first electrode of the second transistor T2 is connected with the sixth node N6, and the second electrode of the second transistor T2 is connected with the seventh node N7.

[0196] The first electrode of the third transistor T3 is connected with the seventh node N7, and the second electrode of the third transistor T3 is connected with the gating terminal.

[0197] The gate of the fourth transistor T4 is connected with the third input terminal INPUT3, the first electrode of the fourth transistor T4 is connected with the third node N3, and the second electrode of the fourth transistor T4 is connected with the first power supply VGL.

[0198] Figure 20 The structure schematic diagram of the driving circuit according to the embodiment of the utility model is schematically shown.

[0199] As Figure 20As shown, the driving circuit 2000 includes M cascaded shift registers, M being a positive integer greater than 1. The M shift registers include a first-stage shift register ST1, an mth-stage shift register STm, and an Mth-stage shift register STM.

[0200] In the embodiments of the present application, the shift register ST1 can be any one of the shift registers 600, 700, 1400, 1500, 1600, 1700, 1800, and 1900 described above. For example, the M shift registers are all shift registers 600. For example, the M shift registers are all shift registers 700. Details are not described herein.

[0201] In the embodiments of the present application, in the M cascaded shift registers, the input signal INPUT1 of the first input terminal INPUT1 of the first-stage shift register ST1 is the start signal GSTV.

[0202] Figure 21 The structure schematic diagram of the driving circuit according to another embodiment of the present application is schematically shown.

[0203] In the embodiments of the present application, the driving circuit 2100 includes M cascaded shift registers.

[0204] In the embodiments of the present application, the first input terminal INPUT1 of the mth-stage shift register STm is electrically connected with the first output terminal OUT1 of the (m-1)th-stage shift register STm-1, the second input terminal INPUT2 of the mth-stage shift register STm is electrically connected with the thirteenth node N13 of the (m-2)th-stage shift register, the third input terminal INPUT3 of the mth-stage shift register is electrically connected with the eleventh node N11 of the (m-1)th-stage shift register, 2 < m ≤ M, m is an integer, and M is an integer greater than 2.

[0205] In the embodiments of the present application, the first output terminal OUT1 of the mth-stage shift register STm is further connected with the gate of the first transistor T1 in the mth-stage shift register STm. The first output terminal OUT1 of the (m-1)th-stage shift register STm-1 is connected with the gate of the first transistor T1 in the (m-1)th-stage shift register STm-1. The first output terminal OUT1 of the (m-2)th-stage shift register STm-2 is connected with the gate of the first transistor T1 in the (m-2)th-stage shift register STm-2.

[0206] In the embodiment of the utility model, the first clock end CK of the mth shift register is electrically connected with the clock signal line ck, and the second clock end CB of the mth shift register is electrically connected with the clock signal line cb.

[0207] In the embodiment of the utility model, the gate end MS is electrically connected with the gate signal line ms.

[0208] The following takes the film layer of the shift register 1500 as an example to describe each film layer of the shift register in the embodiment of the utility model.

[0209] Figure 22A The plan view of the semiconductor layer according to the embodiment of the utility model is schematically shown, Figure 22B The plan view of the first conductive layer according to the embodiment of the utility model is schematically shown, Figure 22C The plan view of the second conductive layer according to the embodiment of the utility model is schematically shown, Figure 22D The plan view of the semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer according to the embodiment of the utility model is schematically shown, Figure 22E The plan view of the third conductive layer and the fourth conductive layer according to the embodiment of the utility model is schematically shown, Figure 22F The plan view of the semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer according to the embodiment of the utility model is schematically shown.

[0210] As shown in Figures 22A to 22F The semiconductor layer 2210 can be formed by patterning a semiconductor material. The semiconductor layer 2210 includes the active part of at least one of the transistors. Exemplarily, the semiconductor layer 2210 can be used to fabricate the active part of the transistors T1 to T27 in the shift register 1500. The active part of each transistor includes a channel part and a doped part on both sides of the channel part.

[0211] The part on both sides of each channel part is doped by ion doping or other processes to form a doped part of each transistor. The doped part includes a source and a drain on both sides of the channel part, i.e. the first pole and the second pole.

[0212] It is additionally explained that the source and the drain of each transistor can be symmetrical in structure, so the source and the drain can be indistinguishable in physical structure. In the embodiment of the utility model, in order to distinguish the transistors, one pole is described as the first pole and the other pole is described as the second pole in addition to the gate as the control pole, so the first pole and the second pole of all or part of the transistors in the embodiment of the utility model can be interchangeable as needed.

[0213] The first conductive layer 2220 includes conductive portions GA1 to GA24. At least part of the conductive portions GA1 to GA24 can overlap with a channel portion of a transistor to form a gate electrode of the transistor.

[0214] For example, the active portion of the first transistor T1 includes a channel portion CH1a and a doped portion on both sides of the channel portion CH1a. The conductive portion GA1 overlaps with the channel portion CH1a of the first transistor T1 to form a gate electrode of the first transistor T1.

[0215] The active portion of the second transistor T2 includes a channel portion CH1b and a doped portion on both sides of the channel portion CH1b. The conductive portion GA2 overlaps with the channel portion CH1b of the second transistor T2 to form a gate electrode of the second transistor T2.

[0216] The active portion of the third transistor T3 includes a channel portion CH1c and a doped portion on both sides of the channel portion CH1c. The conductive portion GA3 overlaps with the channel portion CH1c of the third transistor T3 to form a gate electrode of the third transistor T3.

[0217] The active portion of the fourth transistor T4 includes a channel portion CH2 and a doped portion on both sides of the channel portion CH2. The conductive portion GA4 overlaps with the channel portion CH2 of the fourth transistor T4 to form a gate electrode of the fourth transistor T4.

[0218] The active portion of the fifth transistor T5 includes a channel portion CH3 and a doped portion on both sides of the channel portion CH3. The conductive portion GA5 overlaps with the channel portion CH3 of the fifth transistor T5 to form a gate electrode of the fifth transistor T5.

[0219] The active portion of the sixth transistor T6 includes a channel portion CH4a and a doped portion on both sides of the channel portion CH4a. The conductive portion GA6 overlaps with the channel portion CH4a of the sixth transistor T6 to form a gate electrode of the sixth transistor T6.

[0220] The active portion of the seventh transistor T7 includes a channel portion CH4b and a doped portion on both sides of the channel portion CH4b. The conductive portion GA7 overlaps with the channel portion CH4b of the seventh transistor T7 to form a gate electrode of the seventh transistor T7.

[0221] The active portion of the eighth transistor T8 includes a channel portion CH4c and a doped portion on both sides of the channel portion CH4c. The conductive portion GA8 overlaps with the channel portion CH4c of the eighth transistor T8 to form a gate electrode of the eighth transistor T8.

[0222] The active portion of the ninth transistor T9 includes a channel portion CH5a and a doped portion on both sides of the channel portion CH5a. The conductive portion GA9 overlaps with the channel portion CH5a of the ninth transistor T9 to form a gate electrode of the ninth transistor T9.

[0223] The active region of the tenth transistor T10 includes a channel region CH5b and doped regions on both sides of the channel region CH5b. The conductive region GA7 overlaps with the channel region CH7b of the tenth transistor T10 to form a gate of the tenth transistor T10.

[0224] The active region of the eleventh transistor T11 includes a channel region CH6a and doped regions on both sides of the channel region CH6a. The conductive region GA10 overlaps with the channel region CH6a of the eleventh transistor T11 to form a gate of the eleventh transistor T11.

[0225] The active region of the twelfth transistor T12 includes a channel region CH7a and doped regions on both sides of the channel region CH7a. The conductive region GA11 overlaps with the channel region CH7a of the twelfth transistor T12 to form a gate of the twelfth transistor T12.

[0226] The active region of the thirteenth transistor T13 includes a channel region CH7b and doped regions on both sides of the channel region CH7b. The conductive region GA12 overlaps with the channel region CH7b of the thirteenth transistor T13 to form a gate of the thirteenth transistor T13.

[0227] The active region of the fourteenth transistor T14 includes a channel region CH8 and doped regions on both sides of the channel region CH8. The conductive region GA13 overlaps with the channel region CH8 of the fourteenth transistor T14 to form a gate of the fourteenth transistor T14.

[0228] The active region of the fifteenth transistor T15 includes a channel region CH9 and doped regions on both sides of the channel region CH9. The conductive region GA10 overlaps with the channel region CH9 of the fifteenth transistor T15 to form a gate of the fifteenth transistor T15.

[0229] The active region of the sixteenth transistor T16 includes a channel region CH7c and doped regions on both sides of the channel region CH7c. The conductive region GA14 overlaps with the channel region CH7c of the sixteenth transistor T16 to form a gate of the sixteenth transistor T16.

[0230] The active region of the seventeenth transistor T17 includes a channel region CH7d and doped regions on both sides of the channel region CH7d. The conductive region GA14 overlaps with the channel region CH7d of the seventeenth transistor T17 to form a gate of the seventeenth transistor T17.

[0231] The active region of the eighteenth transistor T18 includes a channel region CH7e and doped regions on both sides of the channel region CH7e. The conductive region GA15 overlaps with the channel region CH7e of the eighteenth transistor T18 to form a gate of the eighteenth transistor T18.

[0232] The active region of the nineteenth transistor T19 includes a channel region CH10a and doped regions on both sides of the channel region CH10a. The conductive region GA16 overlaps with the channel region CH10a of the nineteenth transistor T19 to form a gate of the nineteenth transistor T19.

[0233] The active region of the twentieth transistor T20 includes a channel region CH10b and doped regions on both sides of the channel region CH10b. The conductive region GA17 overlaps with the channel region CH10b of the twentieth transistor T20 to form a gate of the twentieth transistor T20.

[0234] The active region of the twenty-first transistor T21 includes a channel region CH11 and doped regions on both sides of the channel region CH11. The conductive region GA18 overlaps with the channel region CH11 of the twenty-first transistor T21 to form a gate of the twenty-first transistor T21.

[0235] The active region of the twenty-second transistor T22 includes a channel region CH6b and doped regions on both sides of the channel region CH6b. The conductive region GA15 overlaps with the channel region CH6b of the twenty-first transistor T22 to form a gate of the twenty-first transistor T22.

[0236] The active region of the twenty-third transistor T23 includes a channel region CH12 and doped regions on both sides of the channel region CH12. The conductive region GA18 overlaps with the channel region CH12 of the twenty-third transistor T23 to form a gate of the twenty-third transistor T23.

[0237] The active region of the twenty-fourth transistor T24 includes a channel region CH13 and doped regions on both sides of the channel region CH13. The conductive region GA18 overlaps with the channel region CH13 of the twenty-fourth transistor T24 to form a gate of the twenty-fourth transistor T24.

[0238] The active region of the twenty-fifth transistor T25 includes a channel region CH14 and doped regions on both sides of the channel region CH14. The conductive region GA19 overlaps with the channel region CH14 of the twenty-fifth transistor T25 to form a gate of the twenty-fifth transistor T25.

[0239] The active region of the twenty-sixth transistor T26 includes a channel region CH15 and doped regions on both sides of the channel region CH15. The conductive region GA20 overlaps with the channel region CH15 of the twenty-sixth transistor T26 to form a gate of the twenty-sixth transistor T26.

[0240] The active region of the twenty-seventh transistor T27 includes a channel region CH16 and doped regions on both sides of the channel region CH16. The conductive region GA14 overlaps with the channel region CH16 of the twenty-seventh transistor T27 to form a gate of the twenty-seventh transistor T27.

[0241] The second conductive layer 2230 includes conductive portions GB1 to GB8. At least some of the conductive portions GA1 to GA24 can overlap with the conductive portions GB1 to GB8 to form capacitances.

[0242] For example, the conductive portion GB1 overlaps with the conductive portion GA5 to form a first capacitance C1. The conductive portion GB2 overlaps with the conductive portion GA9 to form a second capacitance C2. The conductive portion GB3 overlaps with the conductive portion CA7 to form a third capacitance C3. The conductive portion GB4 overlaps with the conductive portion GA14 to form a fourth capacitance C4. The conductive portion GB5 overlaps with the conductive portion GA21 to form a fifth capacitance C5. The conductive portion GB6 overlaps with the conductive portion GA22 to form a sixth capacitance C6. The conductive portion GB7 overlaps with the conductive portion GA20 to form a seventh capacitance C7.

[0243] The third conductive layer includes contacts GC1 to GC44. Based on the contacts, the above-mentioned semiconductor layer 2210, the first conductive layer 2220, and the second conductive layer 2230 can be connected to obtain a plurality of film layers 2240. The fourth conductive layer includes a first input signal line input1 connected to the first input terminal INPUT1, a second input signal line input2 connected to the second input terminal INPUT2, a first power supply line vgl connected to the first power supply VGL, a second power supply line vgh connected to the second power supply VGL, a first clock signal line ck connected to the first clock signal terminal CK, a second clock signal line cb connected to the clock signal terminal CB, a control signal line ncx, a gate signal line ms, a wire L1, and a wire L2. The third conductive layer and the fourth conductive layer can be connected to obtain a plurality of film layers 2250. Based on the contacts, the above-mentioned semiconductor layer 2210, the first conductive layer 2220, the second conductive layer 2230, and the fourth conductive layer can be connected to obtain a plurality of film layers 2260.

[0244] For example, the gate of the first transistor T1 is connected to the second electrode of the nineteenth transistor T19 and the first electrode of the twentieth transistor T20 through the contact GC41, the first electrode of the first transistor T1 is connected to the second electrode of the second transistor T2, and the second electrode of the first transistor T1 is connected to the first electrode of the third transistor T3.

[0245] The gate of the second transistor T2 is connected to the first input signal line input1 through the contact GC20, the first electrode of the second transistor T2 is connected to the second terminal of the first capacitor C1 through the wire L1, and the second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1.

[0246] The gate of the third transistor T3 is connected to the second input signal line input2, the first electrode of the third transistor T3 is connected to the second electrode of the first transistor T1, and the second electrode of the third transistor T3 is connected to the gate signal line ms through the contact GC5.

[0247] The first electrode of the fourth transistor T4 is connected with the second end of the first capacitor C1 through the adapter GC39, and the second electrode of the fourth transistor T4 is connected with the first power signal line vgl through the adapter GC38.

[0248] The gate of the fifth transistor T5 is connected with the second end of the first capacitor C1, the first electrode of the fifth transistor T5 is connected with the first electrode of the twelfth transistor T12 through the adapter GC18, and the second electrode of the fifth transistor T5 is connected with the gate of the tenth transistor T10 through the adapter GC40, the adapter GC42 and the adapter GC22.

[0249] The gate of the sixth transistor T6 is connected with the second end of the first capacitor C1 through the adapter GC28, the first electrode of the sixth transistor T6 is connected with the gate of the nineteenth transistor T19 through the adapter GC21, and the second electrode of the sixth transistor T6 is connected with the gate of the ninth transistor T9 through the adapter GC29.

[0250] The gate of the seventh transistor T7 is connected with the gate of the tenth transistor T10, the first electrode of the seventh transistor T7 is connected with the second electrode of the eighth transistor T8, the second electrode of the seventh transistor T7 is connected with the second power signal line Vgh through the adapter GC35, the gate of the eighth transistor T8 is connected with the second output terminal OUT2, and the first electrode of the eighth transistor T8 is connected with the gate of the ninth transistor T9 through the adapter GC29.

[0251] The gate of the ninth transistor T9 is connected with the first end of the second capacitor C2, the first electrode of the ninth transistor T9 is connected with the second power line vgh through the adapter GC6, and the second electrode of the ninth transistor T9 is connected with the second output terminal OUT2.

[0252] The gate of the tenth transistor T10 is connected with the first end of the third capacitor C3, the first electrode of the tenth transistor T10 is connected with the second output terminal OUT2, and the second electrode of the tenth transistor T10 is connected with the first power line Vgl.

[0253] The gate of the eleventh transistor T11 is connected with the first power line vgl through the adapter GC15, the first electrode of the eleventh transistor T11 is connected with the second electrode of the twenty-third transistor T23 through the adapter GC16, and the second electrode of the eleventh transistor T11 is connected with the gate of the twenty-sixth transistor T26 through the adapter GC17.

[0254] The gate of the twelfth transistor T12 is connected with the first power supply line vgl through the adapter GC15, the first electrode of the twelfth transistor T12 is connected with the second electrode of the twenty-first transistor T21, and the second electrode of the twelfth transistor T12 is connected with the gate of the twentieth transistor T20 through the connecting piece GC33.

[0255] The gate of the thirteenth transistor T13 is connected with the control signal line ncx through the adapter GC26, the first electrode of the thirteenth transistor T13 is connected with the second power supply line vgh, and the second electrode of the thirteenth transistor T13 is connected with the second node N2.

[0256] The gate of the fourteenth transistor T14 is connected with the second clock signal line cb, the first electrode of the fourteenth transistor T14 is connected with the second end of the seventh capacitor C7, and the second electrode of the fourteenth transistor T14 is connected with the gate of the ninth transistor T9 through the adapter GC11.

[0257] The gate of the fifteenth transistor T15 is connected with the first power supply signal line vgl through the adapter GC15, the first electrode of the fifteenth transistor T15 is connected with the second electrode of the twenty-fourth transistor T24 through the adapter GC7, and the second electrode of the fifteenth transistor T15 is connected with the gate of the seventeenth transistor T17 through the adapter GC23.

[0258] The gate of the sixteenth transistor T16 is connected with the gate of the seventeenth transistor T17, the first electrode of the sixteenth transistor T16 is connected with the gate of the twentieth transistor T20 through the adapter GC33, and the second electrode of the sixteenth transistor T16 is connected with the gate of the seventeenth transistor T17 through the adapter GC32.

[0259] The gate of the seventeenth transistor T17 is connected with the gate of the sixteenth transistor T16, the first electrode of the seventeenth transistor T17 is connected with the gate of the sixteenth transistor T16 through the adapter GC32, and the second electrode of the seventeenth transistor T17 is connected with the gate of the tenth transistor T10 through the adapter GC40 and the adapter GC42.

[0260] The gate of the eighteenth transistor T18 is connected with the twenty-first transistor T21, the first electrode of the eighteenth transistor T18 is connected with the gate of the ninth transistor T9, and the second electrode of the eighteenth transistor T18 is connected with the second power supply line vgh.

[0261] The gate of the nineteenth transistor T19 is connected with the gate of the ninth transistor T9, the first electrode of the nineteenth transistor T19 is connected with the second power supply line vgh through the adapter GC19, and the second electrode of the nineteenth transistor T19 is connected with the first output end OUT1.

[0262] The gate of the twentieth transistor T20 is connected to the second electrode of the twelfth transistor T20 through the adapter GC33, the first electrode of the twentieth transistor T20 is connected to the first output terminal OUT1, and the second electrode of the twentieth transistor T20 is connected to the first power supply line vgl.

[0263] The gate of the twenty-first transistor T21 is connected to the first clock signal line ck, the first electrode of the twenty-first transistor T21 is connected to the first input terminal INPUT1 through the adapter GC2, and the second electrode of the twenty-first transistor T21 is connected to the gate of the twenty-second transistor T22 through the adapter GC8.

[0264] The gate of the twenty-second transistor T22 is connected to the second electrode of the twenty-first transistor T21 through the adapter GC8, the first electrode of the twenty-second transistor T22 is connected to the second electrode of the twenty-third transistor T23, and the second electrode of the twenty-second transistor T22 is connected to the first clock signal line ck.

[0265] The gate of the twenty-third transistor T23 is connected to the first clock signal line ck, the first electrode of the twenty-third transistor T23 is connected to the first power supply line vgl, and the second electrode of the twenty-third transistor T23 is connected to the first electrode of the eleventh transistor T11.

[0266] The gate of the twenty-fourth transistor T24 is connected to the first clock signal line ck, the first electrode of the twenty-fourth transistor T24 is connected to the first input terminal INPUT1 through the adapter GC2, and the second electrode of the twenty-fourth transistor T24 is connected to the first electrode of the fifteenth transistor T15 through the adapter GC7.

[0267] The gate of the twenty-fifth transistor T25 is connected to the second electrode of the twenty-third transistor T23 through the adapter GC16, the first electrode of the twenty-fifth transistor T25 is connected to the second power supply line vgh through the adapter GC25, and the second electrode of the twenty-fifth transistor T25 is connected to the first electrode of the twenty-seventh transistor T27.

[0268] The gate of the twenty-sixth transistor T26 is connected to the second electrode of the eleventh transistor T11 through the adapter GC17, the first electrode of the twenty-sixth transistor T26 is connected to the second clock signal line cb, and the second electrode of the twenty-sixth transistor T26 is connected to the first electrode of the fourteenth transistor.

[0269] The gate of the twenty-seventh transistor T27 is connected to the gate of the seventeenth transistor T17, the first electrode of the twenty-seventh transistor T27 is connected to the first electrode of the twenty-fifth transistor T25 through the adapter GC24 and the adapter GC37, and the second electrode of the twenty-seventh transistor T27 is connected to the second clock signal line cb through the adapter GC31.

[0270] The first end of the first capacitor C1 is connected with the gate of the ninth transistor T9 through the adapter GC29, and the second end of the first capacitor C1 is connected with the first electrode of the second transistor T2.

[0271] The first end of the second capacitor C2 is connected with the gate of the ninth transistor T9 through the adapter GC6, and the second end of the second capacitor C2 is connected with the second power line vgh.

[0272] The first end of the third capacitor C3 is connected with the gate of the seventh transistor T7, and the second end of the third capacitor C3 is connected with the second output end OUT2.

[0273] The first end of the fourth capacitor C4 is connected with the gate of the ninth transistor T9, and the second end of the fourth capacitor C4 is connected with the second power line vgh.

[0274] The first end of the fifth capacitor C5 is connected with the first output end OUT1, and the second end of the fifth capacitor C5 is connected with the first power line vgl through the adapter GC44.

[0275] The first end of the sixth capacitor C6 is connected with the second electrode of the twenty-fifth transistor T25, and the second end of the sixth capacitor C6 is connected with the gate of the seventeenth transistor T17.

[0276] The first end of the seventh capacitor C7 is connected with the gate of the twenty-sixth transistor T26, and the second end of the seventh capacitor C7 is connected with the second electrode of the twenty-sixth transistor T26 through the adapter GC3.

[0277] The connecting relationship of the device is not limited to the above Figure 22F The connecting relationship of the plurality of film layers 2260 is shown. Figure 22G A plan view of the fifth conductive layer is schematically shown, Figure 22H A plan view of the sixth conductive layer is schematically shown, Figure 22I A plan view of the semiconductor layer, the second conductive layer, the fifth conductive layer and the sixth conductive layer is schematically shown, Figure 22J A plan view of the fourth conductive layer and the sixth conductive layer is schematically shown, Figure 22K A plan view of the semiconductor layer, the second conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer is schematically shown.

[0278] As Figures 22G to 22JAs shown, the fifth conductive layer 2270 includes conductive portions GD1-GD24. The shapes and positions of the conductive portions GD2-GD24 are similar to those of the conductive portions GA2-GA24, and thus are not repeated here. The sixth conductive layer 2280 includes transfer portions GE1-GE44. The shapes and positions of the transfer portions GE1-GE19, GE21-GE40, GE42-GE44 are similar to those of the transfer portions GC1-GC19, GC21-GC40, GC42-GC44. The shape of the conductive portion GD1 is different from that of the conductive portion GA1, the shape of the transfer portion GE20 is different from that of the transfer portion GC20, and the shape of the transfer portion GE41 is different from that of the transfer portion GC41.

[0279] In the plurality of film layers 2290, the conductive portion GD1 and the transfer portion GC20 are connected, and the conductive portion GD3 and the transfer portion GE41 can be connected, so that the connection relationship of the first transistor T1 and the third transistor T3 is exchanged, so that the connection relationship of the first transistor T1 and the third transistor T3 in the plurality of film layers 2290 is different from that in the plurality of film layers 2280. In other embodiments of the present application, the connection relationship of the first transistor T2 and the third transistor T3 can also be exchanged, and thus is not repeated here. The other connection relationships of the first transistor T2, the first transistor T2 and the third transistor T3 can refer to the shift register 600, the shift register 700, the shift register 1400, the shift register 1600, the shift register 1700, the shift register 1800 and the shift register 1900 described above, and thus is not repeated here.

[0280] Figure 23 A structural schematic diagram of a display device according to an embodiment of the present application is schematically shown.

[0281] As shown in Figure 23 , the display device 2300 can include a drive circuit 2310.

[0282] In an embodiment of the present application, the drive circuit 2310 can be any one of the drive circuits 2000 and 2100 described above, and thus is not repeated here.

[0283] Figure 24 A flowchart of a driving method according to an embodiment of the present application is schematically shown.

[0284] As shown in Figure 24 , the driving method can include operations S2410-S2420.

[0285] In operation S2410, in the gating stage, the control signal is controlled to be at a first level.

[0286] In operation S2420, in the non-gating phase, the control signal is at the second level.

[0287] In the embodiments of the present application, operations S2410 to S2420 are similar to the operations performed by the shift register 600 described above, and will not be described again here.

[0288] The flowcharts and block diagrams in the drawings illustrate the possible implementation architectures, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowcharts or block diagrams can represent a module, a program segment, or a part of code, which contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in different orders than those noted in the drawings. For example, two blocks indicated in succession can actually be executed substantially in parallel, and sometimes they can be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams or flowcharts, and the combination of blocks in the block diagrams or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0289] Those skilled in the art can understand that the features described in various embodiments and / or claims of the present application can be combined and / or integrated in various combinations, even if such combinations are not explicitly described in the present application. In particular, the features described in various embodiments and / or claims of the present application can be combined and / or integrated in various combinations without departing from the spirit and teachings of the present application. All these combinations and / or integrations fall within the scope of the present application. The embodiments of the present application have been described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present application. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present application is defined by the appended claims and their equivalents. Without departing from the scope of the present application, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present application.

Claims

1. A shift register, characterized in that, include: The shift circuit is configured to control the potentials of the first node and the second node under the control of a first clock signal from a first clock terminal, a second clock signal from a second clock terminal, a first power supply voltage from a first power supply, a second power supply voltage from a second power supply, and a first input signal from a first input terminal, and to provide the first power supply voltage or the second power supply voltage to the first output terminal as a first output signal. The gating circuit is configured to provide a gating signal from the gating terminal to the third node under the control of the first input signal, the second input signal from the second input terminal, and the first output signal; The control circuit is configured to provide the potential of the first node to the fourth node and the potential of the second node to the fifth node under the control of the potential of the third node. as well as The output circuit is configured to provide either the first power supply voltage or the second power supply voltage to the second output terminal as a second output signal, under the control of the potential of the fourth node and the potential of the fifth node.

2. The shift register according to claim 1, characterized in that, The gating circuit includes a first transistor, a second transistor, and a third transistor; The first transistor, the second transistor, and the third transistor are connected in series between the third node and the gate terminal. The gate of the first transistor is connected to the first output terminal, the gate of the second transistor is connected to the first input terminal, and the gate of the third transistor is connected to the second input terminal.

3. The shift register according to claim 2, characterized in that, The first terminal of the first transistor is connected to the third node, and the second terminal of the first transistor is connected to the sixth node; the first terminal of the second transistor is connected to the sixth node, and the second terminal of the second transistor is connected to the seventh node; the first terminal of the third transistor is connected to the seventh node, and the second terminal of the third transistor is connected to the gate terminal.

4. The shift register according to claim 2, characterized in that, The first terminal of the first transistor is connected to the third node, and the second terminal of the first transistor is connected to the sixth node; the first terminal of the third transistor is connected to the sixth node, and the second terminal of the third transistor is connected to the seventh node; the first terminal of the second transistor is connected to the seventh node, and the second terminal of the second transistor is connected to the gate terminal.

5. The shift register according to claim 2, characterized in that, The first terminal of the second transistor is connected to the third node, and the second terminal of the second transistor is connected to the sixth node; the first terminal of the first transistor is connected to the sixth node, and the second terminal of the first transistor is connected to the seventh node; the first terminal of the third transistor is connected to the seventh node, and the second terminal of the third transistor is connected to the gate terminal.

6. The shift register according to claim 2, characterized in that, The first terminal of the second transistor is connected to the third node, and the second terminal of the second transistor is connected to the sixth node; the first terminal of the third transistor is connected to the sixth node, and the second terminal of the third transistor is connected to the seventh node; the first terminal of the first transistor is connected to the seventh node, and the second terminal of the first transistor is connected to the gate terminal.

7. The shift register according to claim 2, characterized in that, The first terminal of the third transistor is connected to the third node, and the second terminal of the third transistor is connected to the sixth node; the first terminal of the first transistor is connected to the sixth node, and the second terminal of the first transistor is connected to the seventh node; the first terminal of the second transistor is connected to the seventh node, and the second terminal of the second transistor is connected to the gate terminal.

8. The shift register according to claim 2, characterized in that, The first terminal of the third transistor is connected to the third node, and the second terminal of the third transistor is connected to the sixth node; the first terminal of the second transistor is connected to the sixth node, and the second terminal of the second transistor is connected to the seventh node; the first terminal of the first transistor is connected to the seventh node, and the second terminal of the first transistor is connected to the gate terminal.

9. The shift register according to claim 1, characterized in that, The gating circuit is also electrically connected to the first power supply and the third input terminal; The gating circuit is further configured to control the potential of the third node using the first power supply voltage under the control of a third input signal from the third input terminal.

10. The shift register according to claim 9, characterized in that, The gating circuit also includes a fourth transistor; The gate of the fourth transistor is connected to the third input terminal, the first terminal of the fourth transistor is connected to the third node, and the second terminal of the fourth transistor is connected to the first power supply.

11. The shift register according to claim 1, characterized in that, The shift circuit is configured as follows: Under the control of the first clock signal, the first power supply voltage, and the first input signal, at least one of the second clock signal and the second power supply voltage is provided to the first node; Under the control of the first clock signal, the first input signal is provided to the second node; as well as Under the control of the potential of the first node, the potential of the second node, and the first power supply voltage, the first power supply voltage or the second power supply voltage is provided to the first output terminal as the first output signal.

12. A driving circuit, characterized in that, Includes M cascaded shift registers as described in any one of claims 1-11, where M is an integer greater than 1, wherein... The first input terminal of the m-th stage shift register is electrically connected to the first output terminal of the (m-1)-th stage shift register, and the second input terminal of the m-th stage shift register is electrically connected to the (m-2)-th stage shift register, where 2 < m ≤ M, m is an integer, and M is an integer greater than 2.

13. The driving circuit according to claim 12, characterized in that, The third input terminal of the m-th stage shift register is electrically connected to the (m-1)-th stage shift register.

14. A display device, characterized in that, include: The driving circuit as described in claim 12 or 13.

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