Multi-memory parallel test system

Abstract

The utility model discloses a parallel test system for multiple memories. The parallel test system comprises a ZYNQ unit, a PHY chip, a network transformer and a network switch which are arranged on a test circuit board, the test circuit board is provided with a plurality of test clamps corresponding to the plurality of memories, and two sides of the test clamps are provided with elastic pin headers corresponding to the memories; the ZYNQ unit is provided with a plurality of external communication interfaces corresponding to the plurality of memories, and the memories are connected with a network socket and a network switch through a network transformer; the ZYNQ unit is connected with the PHY chip, the PHY chip is used for realizing analog-to-digital conversion of network signals in Ethernet communication, and the PHY chip is connected with the network switch through the network transformer; and the network switch is connected with the upper computer. According to the utility model, the positions of a plurality of memories are fixed through a plurality of test clamps on the test circuit board, network ports of the memories are led out through the network transformer and the network socket, and the memories are connected to a network switch through network cables during test; the device is simple in structure, can quickly test a plurality of memories in parallel, and has better practicability.

Description

Technical Field

[0001] This utility model belongs to the technical field of memory testing, and specifically relates to a multi-memory parallel testing system. Background Technology

[0002] Existing memory testing equipment uses tooling to test the four-channel serial port function and one-channel network port function of a single memory chip; it uses adapter chips to connect the memory chips and uses professional testing software for testing. However, it has the following drawbacks:

[0003] 1) The platform setup took a long time and the wiring connections were complex, leading to connection errors that caused test anomalies;

[0004] 2) The testing software involves many operations, requiring the opening of different testing software multiple times, resulting in long testing times and making the operation difficult;

[0005] 3) The testing is highly specialized. For example, relevant test items require the input of corresponding test commands. If the test fails due to an incorrect command input, the command must be re-entered, which makes it difficult for personnel to get started and makes it difficult to train production personnel.

[0006] 4) The original testing plan and technology could only test one embedded recording module product at a time, and the entire process required manual operation, which greatly reduced the utilization rate of production personnel and increased the company's labor costs.

[0007] 5) The original testing plan and technology required manual recording of data and test results after each individual project test, which was greatly influenced by human factors. Utility Model Content

[0008] The purpose of this invention is to provide a multi-memory parallel testing system, which aims to enable simultaneous testing of multiple memories.

[0009] This utility model is mainly achieved through the following technical solutions:

[0010] A multi-memory parallel testing system includes a ZYNQ unit, a PHY chip, a network transformer, and a network switch mounted on a test circuit board. The test circuit board has several test fixtures corresponding to several memories, with flexible pin headers on both sides of each fixture corresponding to a memory. Each ZYNQ unit has several external communication interfaces corresponding to several memories. The memories are connected to a network socket and a network switch via the network transformer. Each ZYNQ unit is connected to a PHY chip, which performs analog-to-digital conversion of network signals in Ethernet communication. The PHY chip is also connected to the network switch via the network transformer. The network switch is connected to a host computer.

[0011] To better realize this utility model, it further includes several Hall current sensors, each of which is connected to a memory chip in a one-to-one correspondence. The Hall current sensors are used to detect the current consumed by each memory chip. The ZYNQ unit is connected to the Hall current sensors via XADC.

[0012] To better realize this utility model, the Hall current sensor is further specified as ACS724LLCTR-05AB.

[0013] To better realize this utility model, the ZYNQ unit is model XC7Z010-2CLG400I or XC7Z030-2FFG676I; the network transformer connected to the memory is model EPG4014SE-RC or EPF8181S; the network transformer connected to the PHY chip is model EPG4014SE-RC; and the PHY chip is model 88E1512-A0-NNP2I000.

[0014] To better realize this utility model, it further includes a power conversion unit and a current and voltage detection circuit. The voltage and current detection circuit is used to detect the working status of the parallel test system; the power conversion unit is used to convert the externally provided power signal into the operating voltage of each component.

[0015] To better realize this utility model, the test fixture further includes several locking angles, and locking angles are respectively provided at the corners on the upper and lower sides of the test fixture, and the several locking angles form a locking groove for locking with the memory.

[0016] To better realize this utility model, the test fixture further includes a cover, the cover is detachably provided on the outside of the snap-fit ​​groove, and a memory is provided between the snap-fit ​​groove and the cover.

[0017] The beneficial effects of this utility model are as follows:

[0018] (1) This utility model uses several test fixtures on the test circuit board to fix the positions of several memory devices, and uses a network transformer and a network socket to bring out the network ports of the memory devices, and connects them to a network switch via a network cable during testing; and uses a ZYNQ unit, a network PHY chip, and a network transformer to achieve network communication and connect to a network switch; this utility model has a simple structure and can quickly test several memory devices in parallel, and has good practicality.

[0019] (2) This utility model can detect the current consumed by each memory chip through the Hall current sensor and send it to the XADC of the ZYNQ unit for analog-to-digital conversion, and then calculate the power consumed by the memory chip, which has good practicality.

[0020] (3) This utility model can quickly hold the memory through the snap-fit ​​groove in the test fixture and fix the memory through the cover, which is convenient for subsequent vibration testing and has good practicality. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the multi-memory parallel testing system of this utility model;

[0022] Figure 2 This is a schematic diagram showing the connection between the Hall current sensor, the ZYNQ unit, and the memory.

[0023] Figure 3 This is a block diagram of the power supply of this utility model;

[0024] Figure 4 This is a block diagram illustrating the principle of software testing in this utility model.

[0025] Figure 5 This is a schematic diagram of the actual product used for the test fixture;

[0026] Figure 6 A schematic diagram illustrating the working state of the memory being held by the test fixture;

[0027] Figure 7 This is a schematic diagram of the testing working state of this utility model. Detailed Implementation

[0028] Example 1:

[0029] A multi-memory parallel testing system, such as Figure 1 , Figure 2 and Figure 7 As shown, based on ZYNQ, eight memory chips can be measured simultaneously. Specifically, this includes a power conversion unit, a ZYNQ unit, a ZYNQ debugging circuit, a current and voltage checking circuit, and an external communication interface for interacting with multiple memory chips, all mounted on the test circuit board. Figure 3 As shown, a power supply module is used to power the test system and the memory, and a power conversion unit is used to convert the externally supplied power signal into the operating voltage of each component.

[0030] like Figure 1 and Figure 2As shown, the ZYNQ debugging circuit includes a PHY chip, a network transformer, and a network switch. The ZYNQ unit is connected to the host computer through the ZYNQ debugging circuit. The ZYNQ unit is connected to several memory devices under test (MDTs) through an external communication interface. The MDTs are connected to a network socket and a network switch through the network transformer to achieve connection with the host computer.

[0031] Preferably, eight memory chips are tested. The external interface of the parallel test system includes one 100Mbps Ethernet port and eight TTL-level UART ports. Eight network transformers and eight network sockets are designed on the parallel test system to bring out the network ports of the memory chips, which are then connected to a network switch via network cables during testing. A 32-channel UART is implemented using a ZYNQ PL chip to test the UARTs of the eight memory circuit boards. Network communication is achieved using a ZYNQ PS chip, a network PHY chip, and network transformers, and connected to the network switch.

[0032] like Figure 2 and Figure 3 As shown, in order to detect the power consumption of the circuit board, an ACS724 Hall current sensor is used to sample the current. This sensor can convert the current into voltage proportionally to detect the current consumed by each memory chip and send it to ZYNQ's XADC for analog-to-digital conversion. Since the power supply voltage of the memory is 3.3V, the power consumed by the memory can be calculated.

[0033] Preferably, such as Figures 5-7 As shown, a corresponding test fixture was specially designed to install the memory chip onto the parallel test system. This test fixture is used to place the memory chip into the elastic pin header. Each slot has 4 screw holes, which can be used to install a cover to fix the memory chip for subsequent vibration testing.

[0034] The testing method of this utility model is existing technology and will not be described in detail here. For example, in use, a network switch and host computer testing software can be used to quickly test multiple memory chips. The host computer testing software can be used to set test parameters, load upgrade programs, and read test results. Specifically, as shown... Figure 4 As shown, the software of the automated parallel testing system mainly includes the ZYNQ software system and the host computer UI interface software. The ZYNQ software system includes the FPGA function software on the ZYNQ PL side and the platform software on the ZYNQ PS side.

[0035] The ZYNQ PL-side FPGA function software is loaded and executed via FSBL after the ZYNQ PS-side is powered on. It is mainly used for the implementation of the 32-channel UART interface controller on the ZYNQ PL-side, the acquisition of the power supply voltage and current of the memory under test, the health management of this board, the communication of 48-channel GPIO, and the reset and power-on control of 8 memory under test.

[0036] The Vivado built-in IP core AXI UART16550 is used to instantiate a 32-channel UART interface controller, which is interconnected with the PS end via the AXI bus. After writing these 32 interrupts into a 32-bit register (used by the PS end to determine which UART receive interrupt is introduced to the PS end via AXI), all interrupts are ANDed and sent to IRQ_F2P[0] for use as UART receive interrupts. The power supply voltage and current of the tested memory are acquired through the 16 channels of XADC and sent to the PS end of ZYNQ through the PS_XADC interface to obtain the current and voltage values ​​and the internal temperature of the ZYNQ chip. The LTC2991 acquires the power supply voltage of the chip on this board to realize the health check and management functions of this board.

[0037] The 48 GPIO channels perform path testing by checking signal level changes. Reset and power-on controls for the memory under test are directly introduced to the PS terminal via EMO and controlled directly by the PS terminal. When testing multiple chips simultaneously, the configuration and test information sent by the PS terminal are received via the AXI bus and stored in the corresponding registers. Synchronous testing is triggered by a flag, and tests are performed in parallel within the same CLK. Test data is stored in the corresponding registers for easy access by the PS via AXI.

[0038] The ZYNQ PS platform software includes a BSP and hardware drivers, containing the Board Support Package (BSP) and related hardware drivers required for the automated parallel test system to run the VxWorks operating system. The application program implements functions such as memory status monitoring, fault handling, and data parsing. The VxWorks system is booted via FSBL, creating two TCP servers within VxWorks, one for data pass-through and the other for communication interface control. For data pass-through, the TCP receives data and directly transmits it to the PL's serial port for distribution. Data received from the corresponding serial port is sent directly to the client via the data pass-through TCP. For communication interface control, upon receiving corresponding control commands, the system controls the interface and the test flow. During parallel testing, when test data and configuration data are received from the host computer, they are placed into the corresponding PL registers via the AXI bus. After configuration, the system waits for a start command from the host computer and then sends a start trigger signal to the PL. Upon receiving this signal, the PL triggers multi-chip parallel testing. Test data is accessed through the AXI bus to obtain values ​​from the corresponding registers, and the test results are then uploaded to the host computer via TCP.

[0039] The host computer UI software is mainly used to edit and send test commands and test data, and to access multiple memory chips one by one via FTP to download test data, and to verify and judge the downloaded test data. ZYNQ reports UART and GPIO test status, board health management and power supply voltage, current and power consumption data of the board under test, and displays them dynamically on the PC interface, providing testers with a simple and convenient software interface.

[0040] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present utility model shall fall within the protection scope of the present utility model.

Claims

1. A multi-memory parallel testing system, characterized in that, The system includes a ZYNQ unit, a PHY chip, a network transformer, and a network switch mounted on a test circuit board. The test circuit board has several test fixtures corresponding to several memory units, with flexible pin headers on both sides of each fixture corresponding to a memory unit. Each ZYNQ unit has several external communication interfaces corresponding to several memory units. The memory units are connected to a network socket and a network switch via the network transformer. Each ZYNQ unit is connected to a PHY chip, which performs analog-to-digital conversion of network signals in Ethernet communication. The PHY chip is also connected to the network switch via the network transformer. The network switch is connected to a host computer.

2. The multi-memory parallel testing system according to claim 1, characterized in that, It also includes several Hall current sensors, each connected to a memory chip in a one-to-one correspondence, and the Hall current sensors are used to detect the current consumed by each memory chip; the ZYNQ unit is connected to the Hall current sensors via XADC.

3. The multi-memory parallel testing system according to claim 2, characterized in that, The Hall current sensor is model ACS724LLCTR-05AB.

4. A multi-memory parallel testing system according to any one of claims 1-3, characterized in that, The ZYNQ unit is model XC7Z010-2CLG400I or XC7Z030-2FFG676I; the network transformer connected to the memory is model EPG4014SE-RC or EPF8181S; the network transformer connected to the PHY chip is model EPG4014SE-RC; and the PHY chip is model 88E1512-A0-NNP2I000.

5. A multi-memory parallel testing system according to claim 1, characterized in that, It also includes a power conversion unit and a current and voltage detection circuit. The current and voltage detection circuit is used to detect the working status of the parallel test system. The power conversion unit is used to convert the externally supplied power signal into the operating voltage of each component.

6. The multi-memory parallel testing system according to claim 1, characterized in that, The test fixture includes several locking angles, and locking angles are respectively set at the corners on the upper and lower sides of the test fixture. The several locking angles form a locking slot for locking with the memory.

7. A multi-memory parallel testing system according to claim 6, characterized in that, The test fixture also includes a cover, which is detachably provided on the outside of the snap-fit ​​slot, and a memory is provided between the snap-fit ​​slot and the cover.

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