Combined passivation back contact battery

Abstract

The utility model discloses a combined passivation back contact cell, comprising a silicon wafer, a third semiconductor layer and an anti-reflection layer which are successively arranged on the front surface of the silicon wafer, and a second semiconductor opening area, a first semiconductor opening area and a transition area which are arranged on the back surface of the silicon wafer. The third semiconductor layer is composed of a second intrinsic amorphous silicon layer and a microcrystalline silicon layer which are sequentially deposited on the front face of the silicon wafer, and the second semiconductor opening area is composed of a first intrinsic amorphous silicon layer, a P-type microcrystalline silicon / amorphous silicon layer, a fullerene transmission film, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer. The first semiconductor opening area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer, and an opening is etched in the surface of the transition area to form an insulating groove to isolate the first semiconductor and the second semiconductor. A layer of fullerene film is added to serve as a buffer layer, so that the electronic impedance is reduced, the carrier injection and transmission efficiency is improved, and the cell efficiency is improved.

Description

Technical Field

[0001] This utility model relates to the field of back contact battery technology, and in particular to a combined passivated back contact battery. Background Technology

[0002] Existing back-contact heterojunction solar cells comprise an N-type monocrystalline silicon wafer, with a pyramidal textured surface, an intrinsic amorphous silicon layer, and an antireflection layer sequentially disposed on the front side of the wafer. On the back side of the wafer, on the surface of the P-region, are an intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film layer, and a metal grid layer. On the back side of the wafer, on the surface of the N-region, are also sequentially disposed an intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a transparent conductive film layer, and a metal grid layer. The P-type amorphous silicon layer is in direct contact with the transparent conductive film layer, which facilitates the transfer of charge carriers from the P-type amorphous silicon layer to the electrodes. The transparent conductive film (TCO) layer is typically deposited using magnetron sputtering. During deposition, the sputtered material is directional, resulting in a film that cannot adequately cover the textured pyramidal surface, especially the valleys of the pyramids, where contact with the TCO is incomplete. Furthermore, the TCO layer is typically made of indium oxycarbonate (ITO), which has a lower work function than P-type silicon, leading to an energy level mismatch and a higher series resistance in the cell. Utility Model Content

[0003] To address the aforementioned issues, this invention provides a combined passivated back contact battery that effectively reduces electronic impedance caused by band mismatch and improves carrier injection and transport efficiency.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is: a combined passivated back contact battery, including a silicon wafer, a third semiconductor layer and an anti-reflection layer sequentially disposed on the front side of the silicon wafer, and a transition region between the second semiconductor opening region and the first semiconductor opening region and the second semiconductor opening region and the first semiconductor opening region disposed on the back side of the silicon wafer. The third semiconductor layer is composed of a second intrinsic amorphous silicon layer, a microcrystalline silicon layer and an anti-reflection layer sequentially deposited on the front side of the silicon wafer. The second semiconductor opening region is composed of a first intrinsic amorphous silicon layer, a P-type microcrystalline silicon / amorphous silicon layer, a fullerene transport film, a transparent conductive film and a metal electrode sequentially disposed on the back side of the silicon wafer. The first semiconductor opening region is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film and a metal electrode sequentially disposed on the back side of the silicon wafer. The transition region is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a first intrinsic amorphous silicon layer, a P-type microcrystalline silicon / amorphous silicon layer, a fullerene transport film and a transparent conductive film sequentially disposed on the back side of the silicon wafer. An opening is etched on the transparent conductive film on the surface of the transition region to form an insulating trench.

[0005] Furthermore, the tunneling oxide layer is formed by a dry process and has a thickness of 1-2 nm; the N-type polycrystalline silicon layer is deposited by LPCVD and then diffused, and has a thickness of 100-200 nm.

[0006] Furthermore, the first intrinsic amorphous silicon layer is formed by plate-type PECVD deposition, with a thickness of 5-12 nm.

[0007] Furthermore, the third semiconductor layer is formed by depositing a second intrinsic amorphous silicon layer with a thickness of 4-8 nm and a microcrystalline silicon layer with a thickness of 6-20 nm using plate-type PECVD.

[0008] Furthermore, the P-type microcrystalline silicon / amorphous silicon layer is formed by plate-type PECVD deposition, with a thickness of 10-30 nm.

[0009] Furthermore, the fullerene transport film is a C60 film, which is prepared by radio frequency plasma-assisted evaporation technology using boron-doped atoms, and its thickness is 10~40 nm.

[0010] Furthermore, the transparent conductive film is a conductive film doped with indium oxide or tin oxide, formed by PVD deposition, and has a thickness of 50-150 nm.

[0011] As can be seen from the above description of this utility model, compared with the prior art, this utility model has the following advantages:

[0012] 1. This invention adds a fullerene film between a p-type microcrystalline silicon / amorphous silicon layer and a transparent conductive film (ITO): the energy level structure of the film is controlled by chemical doping, surface treatment, structural design and other methods, so that its work function is between that of p-type silicon and ITO. Appropriate band bending between the p-type silicon and ITO materials forms a p-type silicon-fullerene film-ITO structure gradient band, which helps to reduce the obstruction of charge carriers at the interface. This band matching helps to improve charge transport efficiency and improve device performance.

[0013] 2. Fullerene thin films utilize plasma-assisted evaporation technology. Due to the lower excitation energy, the energy of the deposited atoms is also lower, which can reduce particle deposition damage. It can act as a sputtering buffer layer before ITO film deposition, reducing sputtering damage to the NP layer caused by sputtering ITO film deposition. This helps to improve the open-circuit voltage (Voc) of the device. The directionality of the deposited material is relatively low compared to sputtering deposition, which can form better film smoothness and uniformity. The uniformity of coverage on the P-type silicon surface is improved, which improves the problem of poor contact between the valley of the silicon wafer textured pyramid and ITO, reduces series resistance, and also helps to improve FF, thus improving battery efficiency. Attached Figure Description

[0014] The accompanying drawings, which form part of this application, are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an undue limitation of the present invention. In the drawings:

[0015] Figure 1 This is a cross-sectional view of a combined passivated back contact battery according to the present invention. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0017] Example

[0018] refer to Figure 1 A combined passivated back contact solar cell includes a silicon wafer 101, a third semiconductor layer C and an antireflection layer 501 sequentially disposed on the front side of the silicon wafer 101, and a transition region D disposed on the back side of the silicon wafer 101 between a second semiconductor opening region B and a first semiconductor opening region A, and between the second semiconductor opening region B and the first semiconductor opening region A. The third semiconductor layer C is composed of a second intrinsic amorphous silicon layer 401 and a microcrystalline silicon layer 402 sequentially deposited on the front side of the silicon wafer. The second semiconductor opening region B is composed of a first intrinsic amorphous silicon layer 301, a P-type microcrystalline silicon / amorphous silicon layer 302, and a fullerene layer sequentially disposed on the back side of the silicon wafer. The first semiconductor opening region A is composed of a tunneling oxide layer 201, an N-type polycrystalline silicon layer 202, a transparent conductive film 701, and a metal electrode 801 sequentially disposed on the back side of the silicon wafer. The transition region D is composed of a tunneling oxide layer 201, an N-type polycrystalline silicon layer 202, a first intrinsic amorphous silicon layer 301, a P-type microcrystalline silicon / amorphous silicon layer 302, a fullerene transport film 601, and a transparent conductive film 701 sequentially disposed on the back side of the silicon wafer. An insulating groove 901 is formed by etching an opening in the transparent conductive film on the surface of the transition region D.

[0019] A method for preparing the aforementioned combined passivated back contact battery, the method comprising the following steps:

[0020] S01. Provide polished and cleaned N-type monocrystalline silicon wafers;

[0021] S02. A first semiconductor layer and a mask layer are formed on the back side of a silicon wafer; the first semiconductor layer includes a tunneling oxide layer and an N-type polysilicon layer.

[0022] S03. An opening is made on the back side of the silicon wafer obtained in S02 by laser etching to remove the mask layer, N-type polysilicon layer and tunneling oxide layer in the second semiconductor opening area.

[0023] S04. The silicon wafer obtained in S03 is texturized and cleaned to remove the residual mask layer, N-type polysilicon layer and tunneling oxide layer in the second semiconductor opening region, and a textured surface is formed on the silicon wafer surface.

[0024] S05. Deposit a first intrinsic amorphous silicon layer, which is the second semiconductor layer, on the back side of the silicon wafer obtained in S04.

[0025] S06. A third semiconductor layer is formed on the front side of the silicon wafer obtained in S05;

[0026] S07. Deposit a P-type microcrystalline silicon / amorphous silicon layer 302, a second semiconductor layer, on the back side of the silicon wafer obtained in S06.

[0027] S08. Deposit a fullerene transport film on the back side of the silicon wafer obtained in S07;

[0028] S09. Deposit an anti-reflection layer on the front side of the silicon wafer obtained in S08;

[0029] S010. An opening is made on the back side of the silicon obtained in S09 by laser etching to form a first semiconductor opening region that is spaced apart from the opening region of the second semiconductor +C60 thin film, and then it is cleaned.

[0030] S11. Deposit a transparent conductive film on the back side of the silicon wafer obtained in S010;

[0031] S12. An insulating trench is formed by etching an opening in the transparent conductive film on the surface of the transition region between the opening region of the second semiconductor and the fullerene transport film on the back side of the silicon wafer obtained in S11 and the opening region of the first semiconductor, thereby isolating the first semiconductor layer and the second semiconductor layer.

[0032] S13. Metal electrodes are formed on the surfaces of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer obtained in S12.

[0033] The tunneling oxide layer 201 is formed by a dry process and has a thickness of 1-2 nm; the N-type polysilicon layer 202 is formed by LPCVD deposition of an intrinsic polysilicon layer followed by diffusion and has a thickness of 100-200 nm; the mask layer 301 is silicon nitride, formed by PECVD deposition and has a thickness of 60-80 nm.

[0034] The first intrinsic amorphous silicon layer 301 is formed by plate-type PECVD deposition and has a thickness of 5-12 nm. The P-type microcrystalline silicon / amorphous silicon layer 302 is formed by plate-type PECVD deposition and has a thickness of 10-30 nm. The third semiconductor layer is formed by plate-type PECVD deposition of a second intrinsic amorphous silicon layer 401 with a thickness of 4-8 nm and a microcrystalline silicon layer 402 with a thickness of 6-20 nm.

[0035] The fullerene transport film 601 is a C60 film, which is prepared by radio frequency plasma-assisted evaporation technology using boron-doped atoms, and its thickness is 10~40 nm. The specific method for preparing the C60 film is as follows: 1) The pre-vacuum chamber is 0.00001~0.0001 Pa; 2) C60 powder gas is prepared by a thermal evaporation device. The C60 powder is placed in a quartz boat, and the quartz boat is heated to a temperature range of 400~800 degrees Celsius, so that the C60 powder sublimates into gas through heating; 3) At the same time, a mixture of diborane and reactive gases (2% B2H6 and 98% H2) is introduced, and the gas flow rate is precisely controlled by a mass flow meter, with the flow rate set to a range of 20~500 sccm; 4) The C60 powder vaporized body is mixed with the diborane gas, using 13.56 A MHz radio frequency power supply excites the mixed gas into the plasma state. During the deposition process, the working pressure is maintained at 0.001 Pa to 0.01 Pa, and the power supply range is 20 to 500 W, resulting in a C60 film with a thickness of 10-40 nm.

[0036] The C60 thin film is treated with a combination of heating and light: a. Annealing process: a vacuum annealing furnace is used to heat the film layer at a temperature of 150~200 degrees Celsius for 20~50 minutes; b. Light irradiation process: a white light source is used with an irradiance of 1000~4000W / m2 for 20~500s and a temperature of 80~150 degrees Celsius.

[0037] The transparent conductive film 701 is a conductive film doped with indium oxide or tin oxide, formed by PVD deposition, and has a thickness of 50-150 nm.

[0038] This invention adds a fullerene film between a p-type microcrystalline silicon / amorphous silicon layer and a transparent conductive film (ITO). The energy level structure of the film is controlled by chemical doping, surface treatment, and structural design, so that its work function is between that of p-type silicon and ITO. Appropriate band bending between the p-type silicon and ITO materials forms a gradient energy band structure of p-type silicon-fullerene film-ITO, which helps to reduce the obstruction of charge carriers at the interface. This band matching helps to improve charge transport efficiency and enhance device performance.

[0039] Fullerene thin films utilize plasma-assisted evaporation technology. Due to the lower excitation energy, the energy of the deposited atoms is also lower, which can reduce particle deposition damage. It can act as a sputtering buffer layer before ITO film deposition, reducing sputtering damage to the NP layer caused by sputtering ITO film deposition. This helps to improve the open-circuit voltage (Voc) of the device. The directionality of the deposited material is relatively low compared to sputtering deposition, which can form better film smoothness and uniformity. The uniformity of coverage on the P-type silicon surface is improved, which improves the problem of poor contact between the valley of the silicon wafer textured pyramid and ITO, reduces series resistance, and also helps to improve FF, thus improving battery efficiency.

[0040] By employing a combined heating and light treatment to process the internal structure of the thin film, the synergistic effect of heating and light treatment is achieved, resulting in dual optimization of the film's structure and performance. This promotes internal structural adjustment, reduces defects, and improves carrier mobility, thereby enhancing the carrier transport performance of the film layer and ensuring the stability of the film structure.

[0041] Using the C60 thin film in the implementation case as an example, the FTIR spectrum of the thin film was tested. The characteristic peaks of C60 in the processed film (527, 576, 1183 and 1428 cm⁻¹) were observed. -1 The relatively weakened intensity indicates that more C60 molecules may be doped, which promotes the diffusion of boron atoms in the film, improves the uniformity of doping distribution, reduces defects and increases carrier mobility, thus improving the low carrier transport performance and enhancing the stability of C60 films.

[0042] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A co-passivated back contact cell, characterized by: The application relates to a silicon wafer, a third semiconductor layer and an anti-reflection layer arranged on the front surface of the silicon wafer in sequence, a second semiconductor opening area arranged on the back surface of the silicon wafer, a first semiconductor opening area and a transition area between the second semiconductor opening area and the first semiconductor opening area, the third semiconductor layer is composed of a second intrinsic amorphous silicon layer, a microcrystalline silicon layer and an anti-reflection layer deposited on the front surface of the silicon wafer in sequence, the second semiconductor opening area is composed of a first intrinsic amorphous silicon layer, a P-type microcrystalline silicon / amorphous silicon layer, a fullerene transmission film, a transparent conductive film and a metal electrode arranged on the back surface of the silicon wafer in sequence, the first semiconductor opening area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film and a metal electrode arranged on the back surface of the silicon wafer in sequence, the transition area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a first intrinsic amorphous silicon layer, a P-type microcrystalline silicon / amorphous silicon layer, a fullerene transmission film and a transparent conductive film arranged on the back surface of the silicon wafer in sequence, and an insulating groove is formed by etching an opening in the surface transparent conductive film of the transition area.

2. The co-passivated back contact cell of claim 1, wherein: The tunneling oxide layer is formed by a dry method and has a thickness of 1-2 nm; and the N-type polycrystalline silicon layer is formed by diffusing an intrinsic polycrystalline silicon layer deposited by LPCVD and has a thickness of 100-200 nm.

3. The co-passivated back contact cell of claim 1 wherein: The first intrinsic amorphous silicon layer is formed by plate PECVD deposition and has a thickness of 5-12 nm.

4. The co-passivated back contact cell of claim 1 wherein: The third semiconductor layer is formed by plate PECVD deposition of a second intrinsic amorphous silicon layer with a thickness of 4-8 nm and a microcrystalline silicon layer with a thickness of 6-20 nm.

5. The co-passivated back contact cell of claim 1 wherein: The P-type microcrystalline silicon / amorphous silicon layer is formed by plate PECVD deposition and has a thickness of 10-30 nm.

6. The co-passivated back contact cell of claim 1, wherein: The fullerene transmission film is a C60 film and has a thickness of 10-40 nm.

7. The co-passivated back contact cell of claim 1 wherein: The transparent conductive film is a conductive film of an indium oxide doping system or a tin oxide system and is formed by PVD deposition and has a thickness of 50-150 nm.

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