DSP sampling conditioning circuit
By combining a voltage regulator circuit, an inverting proportional operational circuit, and an adder circuit, the problem that existing DSP sampling conditioning circuits cannot condition AC and DC signals to a suitable voltage range is solved, thus achieving effective sampling control of the DSP processor.
Patent Information
- Application Number
- CN202520709024.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-15
- Publication Date
- 2026-03-20
- Estimated Expiration
- 2035-04-15
AI Technical Summary
Existing DSP sampling and conditioning circuits struggle to condition the sampled signal, which contains both AC and DC signals, to a suitable voltage range, making sampling control difficult for the DSP processor.
A combination of a voltage regulator circuit, an inverting proportional operational circuit, and an adder circuit is used. The voltage regulator circuit outputs a stable voltage, which is then divided by the inverting proportional operational circuit. Finally, the adder circuit adds the sensor output voltage to the boosted voltage output by the inverting proportional operational circuit to obtain the voltage within the sampling range of the DSP processor.
This achieves the conditioning of the input signal to a voltage within the sampling range of the DSP processor, ensuring the accuracy and stability of signal processing.
Smart Images
Figure CN224021711U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of digital signal processing technology, and in particular to a DSP sampling and conditioning circuit. Background Technology
[0002] A Digital Signal Processor (DSP) is a programmable chip specifically designed for digital signal processing. When using a DSP for sampling control, if the range of the external input signal exceeds the chip's allowable range, the input signal needs to be converted to a signal within the chip's allowed range. This requires designing a signal conditioning circuit.
[0003] In the existing technology, DSP sampling and conditioning circuits often construct bias voltage regulation stages through operational amplifiers. Because the bias voltage is fixed, it is difficult to condition the sampling signal, which contains both AC and DC, to a suitable voltage range. Utility Model Content
[0004] This utility model provides a DSP sampling conditioning circuit that can solve the problem in the prior art where it is impossible to perform sampling control on the DSP processor and condition the voltage to a suitable range.
[0005] This utility model embodiment provides a DSP sampling conditioning circuit, including: a voltage regulator circuit, an inverting proportional operation circuit, and an adder circuit. The output terminal of the voltage regulator circuit is connected to the input terminal of the inverting proportional operation circuit. The output terminal of the inverting proportional operation circuit is connected to one input terminal of the adder circuit. The other input terminal of the adder circuit receives a sensor signal. The output terminal of the adder circuit is connected to the input terminal of the DSP.
[0006] Further, the voltage stabilizing circuit comprises a voltage stabilizing chip LM317, a resistor R1, a resistor R2, a first digital ground wire DGND, a second digital ground wire DGND, a third digital ground wire DGND, a capacitor C1, a capacitor C2, a capacitor C4, a capacitor C3, a diode D1, a diode D2 and a power supply voltage; an input end INPUT of the voltage stabilizing chip LM317 is connected with the power supply voltage; an adjusting end ADJUST of the voltage stabilizing chip LM317 is connected with the resistor R1 and the first digital ground wire DGND in sequence, the resistor R1 is connected with the capacitor C1 in parallel; an output end OUTPUT / 2 of the voltage stabilizing chip LM317 is connected with one end of the resistor R2, the other end of the resistor R2 is connected to a circuit between the resistor R1 and the voltage stabilizing chip LM317, the resistor R2 is connected with the diode D1 in parallel, and a negative electrode of the diode D1 is connected with the output end OUTPUT / 2; the output end OUTPUT of the voltage stabilizing chip LM317 is connected with an input end of the inverting proportional operation circuit, one end of the capacitor C4 and a positive electrode of the diode D2 respectively; the other end of the capacitor C4 is connected with the second digital ground wire DGND; a negative electrode of the diode D2 is connected with an output end of the power supply voltage and one end of the capacitor C3 respectively, the other end of the capacitor C3 is connected with the third digital ground wire DGND, and the capacitor C3 is connected with the capacitor C2 in parallel.
[0007] Further, the voltage stabilizing circuit comprises a voltage stabilizing chip LM317, a resistor R1, a resistor R2, a first digital ground wire DGND, a second digital ground wire DGND, a third digital ground wire DGND, a capacitor C1, a capacitor C2, a capacitor C4, a capacitor C3, a diode D1, a diode D2 and a power supply voltage; an input end INPUT of the voltage stabilizing chip LM317 is connected with the power supply voltage; an adjusting end ADJUST of the voltage stabilizing chip LM317 is connected with the resistor R1 and the first digital ground wire DGND in sequence, the resistor R1 is connected with the capacitor C1 in parallel; an output end OUTPUT / 2 of the voltage stabilizing chip LM317 is connected with one end of the resistor R2, the other end of the resistor R2 is connected to a circuit between the resistor R1 and the voltage stabilizing chip LM317, the resistor R2 is connected with the diode D1 in parallel, and a negative electrode of the diode D1 is connected with the output end OUTPUT / 2; the output end OUTPUT of the voltage stabilizing chip LM317 is connected with an input end of the inverting proportional operation circuit, one end of the capacitor C4 and a positive electrode of the diode D2 respectively; the other end of the capacitor C4 is connected with the second digital ground wire DGND; a negative electrode of the diode D2 is connected with an output end of the power supply voltage and one end of the capacitor C3 respectively, the other end of the capacitor C3 is connected with the third digital ground wire DGND, and the capacitor C3 is connected with the capacitor C2 in parallel.
[0008] Further, the adder circuit comprises resistance R9, resistance R8, resistance R10, capacitor C6, operational amplifier U5A and sixth digital ground DGND; the non-inverting input terminal of the operational amplifier U5A is connected with the output terminal of the sensor; the inverting input terminal of the operational amplifier U5A is connected with one end of the resistance R8 and one end of the resistance R9 respectively; the other end of the resistance R8 is connected with the output terminal of the inverting proportional operational circuit; the other end of the resistance R9 is connected with the output terminal of the operational amplifier U5A, and the resistance R9 is connected with the capacitor C6 in parallel; the output terminal of the operational amplifier U5A is also connected with the input terminal of the DSP and one end of the resistance R10 respectively, and the other end of the resistance R10 is connected with the sixth digital ground DGND.
[0009] Further, the sensor is a voltage sensor, a current sensor or a temperature sensor.
[0010] Further, the DSP model adopts TMSF28335.
[0011] The embodiment of the utility model provides a DSP sampling conditioning circuit, and compared with prior art, it has the beneficial effects as follows:
[0012] The voltage outputted stably by the voltage stabilizing circuit is inputted into the inverting proportional operational circuit, the inverting proportional operational circuit divides the inputted voltage and outputs stably into the adder circuit, the adder circuit adds the output voltage of the sensor and the lifting voltage outputted by the inverting proportional operational circuit, so as to obtain the voltage in the sampling range of the DSP processor, and output to the DSP processor. BRIEF DESCRIPTION OF DRAWINGS
[0013] Figure 1 The circuit connection schematic diagram provided by the embodiment of the utility model. DETAILED DESCRIPTION
[0014] In order to make the above-mentioned purpose, features and advantages of the utility model more apparent, obvious and easy to understand, the specific embodiment of the utility model is described in detail below. In the following description, a lot of specific details are set forth in order to fully understand the utility model. But the utility model can be implemented in many other ways different from the description, and those skilled in the art can make similar improvements without departing from the connotation of the utility model, so the utility model is not limited by the following disclosed specific embodiments.
[0015] In the description of the utility model, it is understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the utility model.
[0016] In addition, the terms "first" and "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the utility model, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise specifically limited.
[0017] In the utility model, unless otherwise specifically defined and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship of two elements, unless otherwise specifically limited. For ordinary skilled in the art, the specific meaning of the above terms in the utility model can be understood according to the specific circumstances.
[0018] In the utility model, unless otherwise specifically defined and limited, the first feature is "on" or "under" the second feature, which can be direct contact between the first and second features, or indirect contact between the first and second features through an intermediate medium. Moreover, the first feature "above", "above" and "above" the second feature can be directly above or obliquely above the first feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature can be directly below or obliquely below the first feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.
[0019] It is to be understood that when an element as a preamble is referred to as being "on" or "connected" to another element, it can be directly on the other element or intervening elements can also be present. In addition, the term "connected" as used herein means the element is either directly connected to the other element or intervening elements can be present. As used herein, the terms "vertical", "horizontal", "upper", "lower", "left", "right", and the like as used herein are used for illustration only and not meant to be limiting.
[0020] Referring to Figure 1 The embodiment of the utility model provides a kind of DSP sampling conditioning circuit, comprising: the output end of voltage stabilizing circuit is connected with the input end of inverting proportional operation circuit, the output end of inverting proportional operation circuit is connected with the input end of adder circuit;Another input end of adder circuit is connected with the output end of sensor, for receiving sensor signal;The output end of adder circuit is connected with the input end of digital signal processor DSP;Adder circuit is used to add the voltage of inverting proportional operation circuit output and the voltage of sensor output to obtain the voltage in the range of DSP sampling.
[0021] Wherein, voltage stabilizing circuit outputs stable voltage to inverting proportional operation circuit, inverting proportional operation circuit divides voltage after input, and stably outputs to adder circuit, and adder circuit adds sensor output voltage and the lifting voltage of inverting proportional operation circuit output, to obtain the voltage in the range of DSP processor sampling, and output to DSP processor.
[0022] 1, the specific connection mode of voltage stabilizing circuit is as follows:
[0023] Voltage stabilizing circuit includes: voltage stabilizing chip LM317, resistance R1, resistance R2, first digital ground wire DGND, second digital ground wire DGND, third digital ground wire DGND, capacitor C1, capacitor C2, capacitor C4, capacitor C3, diode D1, diode D2 and power voltage.
[0024] The input end INPUT of the voltage stabilizing chip LM317 is connected with the power voltage; the adjusting end ADJUST of the voltage stabilizing chip LM317 is connected with the resistor R1 and the first digital ground wire DGND in sequence, the resistor R1 is connected with the capacitor C1 in parallel; the output end OUTPUT / 2 of the voltage stabilizing chip LM317 is connected with one end of the resistor R2, the other end of the resistor R2 is connected to the circuit between the resistor R1 and the voltage stabilizing chip LM317, the resistor R2 is connected with the diode D1 in parallel, and the negative electrode of the diode D1 is connected with the output end OUTPUT / 2; the output end OUTPUT of the voltage stabilizing chip LM317 is connected with the input end of the inverting proportional operation circuit, one end of the capacitor C4 and the positive electrode of the diode D2 respectively; the other end of the capacitor C4 is connected with the second digital ground wire DGND; the negative electrode of the diode D2 is connected with the output end of the power voltage and one end of the capacitor C3 respectively, the other end of the capacitor C3 is connected with the third digital ground wire DGND, and the capacitor C3 is connected with the capacitor C2 in parallel.
[0025] 2. The specific connection mode of the inverting proportional operation circuit is as follows:
[0026] The inverting proportional operation circuit comprises the resistor R3, the resistor R4, the resistor R7, the resistor R5, the resistor R6, the capacitor C5, the operational amplifier U5B, the fourth digital ground wire DGND and the fifth digital ground wire DGND.
[0027] The inverting input end of the operational amplifier U5B is connected with one end of the resistor R7 and one end of the resistor R5 respectively; the other end of the resistor R7 is connected with the output end of the operational amplifier U5B; the other end of the resistor R5 is connected with one end of the resistor R3 and one end of the resistor R4 respectively; the other end of the resistor R3 is connected with the output end of the voltage stabilizing circuit; the other end of the resistor R4 is connected with the fourth digital ground wire DGND, and the resistor R4 is connected with the capacitor C5 in parallel; the non-inverting input end of the operational amplifier U5B is connected with one end of the resistor R6, and the other end of the resistor R6 is connected with the fifth digital ground wire DGND; the output end of the operational amplifier U5B is connected with the input end of the adder circuit.
[0028] 3. The specific connection mode of the adder circuit is as follows:
[0029] The adder circuit comprises the resistor R9, the resistor R8, the resistor R10, the capacitor C6, the operational amplifier U5A and the sixth digital ground wire DGND.
[0030] The non-inverting input terminal of the operational amplifier U5A is connected with the output terminal of the sensor; the inverting input terminal of the operational amplifier U5A is connected with one end of the resistor R8 and one end of the resistor R9 respectively; the other end of the resistor R8 is connected with the output terminal of the inverting proportional operational circuit; the other end of the resistor R9 is connected with the output terminal of the operational amplifier U5A, and the resistor R9 is connected with the capacitor C6 in parallel; the output terminal of the operational amplifier U5A is also connected with the input terminal of the DSP and one end of the resistor R10 respectively, and the other end of the resistor R10 is connected with the sixth digital ground wire DGND.
[0031] 6. The sensor is a voltage sensor, a current sensor or a temperature sensor, and the DSP model adopts TMSF28335.
[0032] One specific implementation is as follows:
[0033] The DSP model adopts TMSF28335, and the current sensor model is LA25-NP / SP11. Firstly, the voltage stabilizing circuit is set to generate a 5V voltage, the resistor R2 and the resistor R3 adopt 1kΩ resistors to divide voltage to 2.5V, according to the actual DSP range requirement, the resistor R8 adopts 5.49kΩ resistor, and the resistor R9 adopts 3.3kΩ resistor.
[0034] The above-mentioned embodiments only express several implementation manners of the utility model, the description is more specific and detailed, but it cannot be understood as the limitation of the utility model patent range. It should be pointed out that for ordinary skilled person in the art, on the premise of not departing from the utility model concept, a plurality of modifications and improvements can be made, which belong to the protection range of the utility model. Therefore, the protection range of the utility model patent should be subject to the appended claims.
Claims
1. A DSP sampling conditioning circuit, characterized in that, include: The circuit includes a voltage regulator circuit, an inverting proportional amplifier circuit, and an adder circuit. The output of the voltage regulator circuit is connected to the input of the inverting proportional amplifier circuit. The output of the inverting proportional amplifier circuit is connected to one input of the adder circuit. The other input of the adder circuit receives a sensor signal. The output of the adder circuit is connected to the input of the DSP.
2. The DSP sampling conditioning circuit as described in claim 1, characterized in that, The voltage regulator circuit includes: a voltage regulator chip LM317, resistors R1 and R2, a first digital ground line DGND, a second digital ground line DGND, a third digital ground line DGND, capacitors C1, C2, C4, and C3, diodes D1 and D2, and a power supply voltage. The input terminal INPUT of the voltage regulator chip LM317 is connected to the power supply voltage; The adjustment terminal ADJUST of the voltage regulator chip LM317 is connected in sequence to the resistor R1 and the first digital ground line DGND, and the resistor R1 is connected in parallel with the capacitor C1. The output terminal OUTPUT / 2 of the voltage regulator chip LM317 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the circuit between the resistor R1 and the voltage regulator chip LM317. The resistor R2 is connected in parallel with the diode D1, and the cathode of the diode D1 is connected to the output terminal OUTPUT / 2. The output terminal OUTPUT of the voltage regulator chip LM317 is connected to the input terminal of the inverting proportional operational circuit, one end of the capacitor C4, and the positive terminal of the diode D2, respectively. The other end of capacitor C4 is connected to the second digital ground line DGND. The negative terminal of diode D2 is connected to the output terminal of the power supply voltage and one end of capacitor C3, respectively. The other end of capacitor C3 is connected to the third digital ground line DGND. Capacitor C3 is connected in parallel with capacitor C2.
3. The DSP sampling conditioning circuit as described in claim 1, characterized in that, The inverting proportional operational circuit includes: resistors R3, R4, R7, R5, and R6; capacitor C5; operational amplifier U5B; fourth digital ground line DGND; and fifth digital ground line DGND. The inverting input terminal of the operational amplifier U5B is connected to one end of the resistor R7 and one end of the resistor R5, respectively. The other end of resistor R7 is connected to the output terminal of operational amplifier U5B; the other end of resistor R5 is connected to one end of resistor R3 and one end of resistor R4 respectively. The other end of resistor R3 is connected to the output terminal of the voltage regulator circuit; the other end of resistor R4 is connected to the fourth digital ground line DGND, and resistor R4 is connected in parallel with capacitor C5. The non-inverting input terminal of the operational amplifier U5B is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the fifth digital ground line DGND. The output terminal of the operational amplifier U5B is connected to the input terminal of the adder circuit.
4. The DSP sampling conditioning circuit as described in claim 1, characterized in that, The adder circuit includes: resistors R9, R8, and R10; capacitor C6; operational amplifier U5A; and sixth digital ground line DGND. The non-inverting input terminal of the operational amplifier U5A is connected to the output terminal of the sensor; The inverting input terminal of the operational amplifier U5A is connected to one end of resistor R8 and one end of resistor R9, respectively. The other end of resistor R8 is connected to the output of the inverting proportional operational circuit; the other end of resistor R9 is connected to the output of operational amplifier U5A, and resistor R9 is connected in parallel with capacitor C6. The output terminal of the operational amplifier U5A is also connected to the input terminal of the DSP and one end of the resistor R10, and the other end of the resistor R10 is connected to the sixth digital ground line DGND.
5. The DSP sampling conditioning circuit as described in claim 1, characterized in that, The sensor is a voltage sensor, a current sensor, or a temperature sensor.
6. The DSP sampling conditioning circuit as described in claim 1, characterized in that, The DSP model used is TMSF28335.