A universal MOS and IGBT testing circuit

Abstract

The utility model discloses a kind of test circuit of general MOS tube and IGBT, comprising: positive and negative double electric power supply, FPGA control board, MOS / IGBT drive circuit and oscilloscope.The utility model is generated accurate PWM drive signal by design FPGA control board, so that MOS / IGBT drive circuit drives MOS / IGBT to be measured according to the duty ratio control signal and frequency control signal of outside;So as to utilize oscilloscope to complete the test of the frequency of MOS / IGBT to be measured.Compared with the complex measuring instrument in prior art, the utility model realizes the test of the frequency of MOS / IGBT to be measured using only a small amount of measuring instrument, greatly saves test cost, provides a lower cost measurement mode for user only needing to test frequency.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor testing, specifically relating to a test circuit for general-purpose MOSFETs and IGBTs. Background Technology

[0002] An Insulated Gate Bipolar Transistor (IGBT) is a composite, fully controllable, voltage-driven power semiconductor device composed of a bipolar junction transistor (BJT) and an insulated gate field-effect transistor (MOS). As a novel power semiconductor field-controlled self-turn-off device, the IGBT integrates the high-speed performance of a power MOSFET with the low resistance of a bipolar device. It features high input impedance, low voltage control power consumption, simple control circuitry, high voltage resistance, and high current handling capacity, making it widely used in high-voltage frequency converters, high-voltage static var generators, and locomotive and rolling stock traction converters. The widespread application of IGBTs requires high reliability and safety, making frequency testing of the IGBT drive circuit particularly important.

[0003] Most existing testing technologies use dedicated IGBT testing instruments to test various parameters of IGBTs or MOSFETs. This results in time-consuming testing and many test parameters being meaningless for scenarios where only the frequency of the IGBT needs to be tested. Furthermore, dedicated IGBT testing instruments are mostly expensive, making them too costly for users who only need to test the frequency. Utility Model Content

[0004] To address the aforementioned problems in the existing technology, this utility model provides a general-purpose test circuit for MOSFETs and IGBTs. The technical problem to be solved by this utility model is achieved through the following technical solution:

[0005] This utility model embodiment provides a test circuit for general-purpose MOSFETs and IGBTs, including:

[0006] The system includes a dual positive and negative power supply, an FPGA control board, a MOS / IGBT drive circuit, and an oscilloscope; among which,

[0007] The positive and negative dual power supplies are respectively connected to the MOS / IGBT drive circuit and the FPGA control board, and are used to supply power to the MOS / IGBT drive circuit and the FPGA control board.

[0008] The FPGA control board is connected to the MOS / IGBT drive circuit and is used to output corresponding PWM drive signals according to external duty cycle control signals and frequency control signals.

[0009] The MOS / IGBT driving circuit is connected to the MOS / IGBT under test and is used to drive the MOS / IGBT under test according to the driving signal.

[0010] The oscilloscope is connected to the MOS / IGBT under test and is used to obtain the frequency of the MOS / IGBT under test based on the input and output signals of the MOS / IGBT under test.

[0011] In one embodiment of this utility model, the positive and negative dual power supply includes:

[0012] The system comprises: a first switching power supply chip, a second switching power supply chip, diodes D1 and D2, a positive power indicator light D3, a negative power indicator light D4, inductors L1 and L2, capacitors C1, C2, C3, C4, C5, C6, C7, C8, and C10, and resistors R1, R2, R3, R4, R5, and R6; among which...

[0013] The VIN terminal of the first switching power supply chip is connected to the first terminal of capacitor C5, the GND terminal is grounded, the BOOT terminal is connected to the first terminal of capacitor C1, the PH terminal is connected to the second terminal of capacitor C1, and the VSNS terminal is connected to the second terminal of resistor R1.

[0014] The VIN terminal of the second switching power supply chip is connected to the first terminal of capacitor C10, the GND terminal is connected to the second terminal of resistor R4, the BOOT terminal is connected to the first terminal of capacitor C6, the PH terminal is connected to the second terminal of capacitor C6, and the VSNS terminal is connected to the first terminal of resistor R2.

[0015] The input terminal of diode D1 is connected to the second terminal of resistor R4, and the output terminal is connected to the second terminal of capacitor C1.

[0016] The input terminal of diode D2 is grounded, and its output terminal is connected to the second terminal of capacitor C6.

[0017] The input terminal of the positive power indicator D3 is connected to the second terminal of resistor R5, and the output terminal is grounded;

[0018] The input terminal of the positive power indicator D4 is connected to the first terminal of the resistor R6, and the output terminal is connected to the voltage VEE.

[0019] The first end of the inductor L1 is connected to the second end of the capacitor C1, and the second end is connected to the first end of the capacitor C2.

[0020] The first end of the inductor L2 is connected to the second end of the capacitor C6, and the second end is connected to the first end of the resistor R3.

[0021] The first terminal of capacitor C2 is connected to the first terminal of capacitor C3, and the second terminal is grounded;

[0022] The first terminal of capacitor C3 is connected to voltage VDD, and the second terminal is grounded.

[0023] The first terminal of capacitor C4 is connected to the first terminal of capacitor C10, and the second terminal is grounded.

[0024] The first terminal of capacitor C5 is connected to the first terminal of capacitor C4, and the second terminal is grounded.

[0025] The first terminal of capacitor C7 is grounded, and the second terminal is connected to voltage VEE.

[0026] The first terminal of capacitor C8 is connected to the first terminal of capacitor C7, and the second terminal is connected to the second terminal of capacitor C7.

[0027] The first terminal of the capacitor C10 is connected to the input terminal of the positive and negative dual power supply, and the second terminal is grounded;

[0028] The first end of resistor R1 is connected to the first end of capacitor C3, and the second end is connected to the first end of resistor R2.

[0029] The second terminal of the resistor R2 is grounded;

[0030] The first end of resistor R3 is connected to the first end of capacitor C8, and the second end is connected to the first end of resistor R4.

[0031] The second terminal of resistor R4 is connected to the second terminal of capacitor C8;

[0032] The first terminal of the resistor R5 is connected to the voltage VDD;

[0033] The second terminal of resistor R6 is grounded.

[0034] In one embodiment of this utility model, the first switching power supply chip and the second switching power supply chip are of model number TPS5430.

[0035] In one embodiment of this utility model, the MOS / IGBT driving circuit is composed of an optocoupler driving chip and its peripheral circuits cascaded together.

[0036] In one embodiment of this utility model, the optical coupling driver chip is model A316JN.

[0037] In one embodiment of this utility model, the FPGA control board includes:

[0038] Phase-locked loop (PLL), frequency acceleration module, and modulation module (PWMStep); among them...

[0039] The phase-locked loop pll is used to provide a stable clock signal for the modulation module pwmstep;

[0040] The frequency acceleration module is used to accelerate the system frequency and provide the accelerated frequency to the modulation module pwmstep.

[0041] The modulation module pwmstep is used to output corresponding drive signals based on external duty cycle control signals and frequency control signals.

[0042] The beneficial effects of this utility model are:

[0043] In the solution provided by this embodiment, an FPGA control board is designed to generate precise PWM drive signals based on external duty cycle and frequency control signals, thereby driving the MOS / IGBT under test via the MOS / IGBT drive circuit. An oscilloscope is then used to test the frequency of the MOS / IGBT under test. Compared to the complex measuring instruments used in existing technologies, this invention achieves frequency testing of the MOS / IGBT under test with only a few instruments, significantly reducing testing costs and providing a lower-cost measurement method for users who only need to test the frequency. Attached Figure Description

[0044] Figure 1 A schematic diagram of a test circuit for a general-purpose MOS transistor and IGBT provided in an embodiment of this utility model;

[0045] Figure 2 A schematic diagram of the positive and negative dual power supply structure in a test circuit for a general-purpose MOS transistor and IGBT provided for an embodiment of this utility model;

[0046] Figure 3 A schematic diagram of the MOS / IGBT drive circuit in a test circuit for a general MOS transistor and IGBT provided in this embodiment of the present invention;

[0047] Figure 4 A schematic diagram of the FPGA control board in a test circuit for a general-purpose MOS transistor and IGBT provided in this embodiment of the present invention;

[0048] Figure 5 This is a diagram of the output signals of the FPGA control board provided in an embodiment of the present invention. Detailed Implementation

[0049] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0050] This utility model embodiment provides a test circuit for general-purpose MOSFETs and IGBTs, such as... Figure 1 As shown, it may include:

[0051] The system includes a dual positive and negative power supply, an FPGA control board, a MOS / IGBT drive circuit, and an oscilloscope; among which,

[0052] A dual positive and negative power supply is connected to the MOS / IGBT drive circuit and the FPGA control board respectively, and is used to supply power to the MOS / IGBT drive circuit and the FPGA control board.

[0053] The FPGA control board, connected to the MOS / IGBT drive circuit, is used to output corresponding PWM drive signals according to the external duty cycle control signal and frequency control signal.

[0054] A MOS / IGBT driving circuit, connected to the MOS / IGBT under test, is used to drive the MOS / IGBT under test according to the driving signal;

[0055] An oscilloscope, connected to the MOS / IGBT under test, is used to obtain the frequency of the MOS / IGBT under test based on its input and output signals.

[0056] The test circuit for general-purpose MOSFETs and IGBTs uses an FPGA control board to generate precise PWM drive signals based on external duty cycle and frequency control signals. This enables the MOSFET / IGBT drive circuit to drive the MOSFET / IGBT under test, allowing the frequency of the MOSFET / IGBT under test to be tested using an oscilloscope.

[0057] To facilitate understanding, the following section introduces each module of the test circuit for this general-purpose MOSFET and IGBT.

[0058] Positive and negative dual power supply, such as Figure 2 As shown, it may include:

[0059] The system comprises: a first switching power supply chip, a second switching power supply chip, diodes D1 and D2, a positive power indicator light D3, a negative power indicator light D4, inductors L1 and L2, capacitors C1, C2, C3, C4, C5, C6, C7, C8, and C10, and resistors R1, R2, R3, R4, R5, and R6; among which...

[0060] The VIN terminal of the first switching power supply chip is connected to the first terminal of capacitor C5, the GND terminal is grounded, the BOOT terminal is connected to the first terminal of capacitor C1, the PH terminal is connected to the second terminal of capacitor C1, and the VSNS terminal is connected to the second terminal of resistor R1.

[0061] The VIN terminal of the second switching power supply chip is connected to the first terminal of capacitor C10, the GND terminal is connected to the second terminal of resistor R4, the BOOT terminal is connected to the first terminal of capacitor C6, the PH terminal is connected to the second terminal of capacitor C6, and the VSNS terminal is connected to the first terminal of resistor R2.

[0062] The input terminal of diode D1 is connected to the second terminal of resistor R4, and the output terminal is connected to the second terminal of capacitor C1.

[0063] The input terminal of diode D2 is grounded, and its output terminal is connected to the second terminal of capacitor C6.

[0064] The input terminal of the positive power indicator D3 is connected to the second terminal of resistor R5, and the output terminal is grounded;

[0065] The input terminal of the positive power indicator D4 is connected to the first terminal of the resistor R6, and the output terminal is connected to the voltage VEE.

[0066] The first end of the inductor L1 is connected to the second end of the capacitor C1, and the second end is connected to the first end of the capacitor C2.

[0067] The first end of the inductor L2 is connected to the second end of the capacitor C6, and the second end is connected to the first end of the resistor R3.

[0068] The first terminal of capacitor C2 is connected to the first terminal of capacitor C3, and the second terminal is grounded;

[0069] The first terminal of capacitor C3 is connected to voltage VDD, and the second terminal is grounded.

[0070] The first terminal of capacitor C4 is connected to the first terminal of capacitor C10, and the second terminal is grounded.

[0071] The first terminal of capacitor C5 is connected to the first terminal of capacitor C4, and the second terminal is grounded.

[0072] The first terminal of capacitor C7 is grounded, and the second terminal is connected to voltage VEE.

[0073] The first terminal of capacitor C8 is connected to the first terminal of capacitor C7, and the second terminal is connected to the second terminal of capacitor C7.

[0074] The first terminal of the capacitor C10 is connected to the input terminal of the positive and negative dual power supply, and the second terminal is grounded;

[0075] The first end of resistor R1 is connected to the first end of capacitor C3, and the second end is connected to the first end of resistor R2.

[0076] The second terminal of the resistor R2 is grounded;

[0077] The first end of resistor R3 is connected to the first end of capacitor C8, and the second end is connected to the first end of resistor R4.

[0078] The second terminal of resistor R4 is connected to the second terminal of capacitor C8;

[0079] The first terminal of the resistor R5 is connected to the voltage VDD;

[0080] The second terminal of resistor R6 is grounded.

[0081] Understandable. Figure 2 JP1 represents the input header, which serves as the input terminal for the positive and negative dual power supplies. P1, P2, P3, and P4 are the corresponding ports for the positive and negative dual power supplies, respectively.

[0082] This dual-power supply receives a 24V DC input and outputs a ±5V DC dual power supply. The first and second switching power supply chips in this dual-power supply are TPS5430, which have built-in regulation functions to ensure a stable output voltage.

[0083] MOS / IGBT drive circuit, such as Figure 3 As shown, it consists of a cascaded optically coupled driver chip and its peripheral circuits, and may include:

[0084] The components include an optocoupler driver chip, resistors R7, R8, R9, R10, R11, R12, and R13, capacitors C11, C12, C13, C14, C15, C16, C17, and C18, power indicator LEDA, power indicator LEDB, a TVS diode DG, a Zener diode Z11, a fast recovery diode US1M, and a power supply QA03.

[0085] The VIN+ terminal of the optocoupler driver chip is connected to the first terminal of resistor R7, the VIN- terminal is connected to the second terminal of resistor R7, the VCC1 terminal is connected to the first terminal of capacitor C11, the GND1 terminal is connected to the second terminal of capacitor C11, the RESET terminal is connected to the RES signal output by the FPGA control board via the input header, the FAU terminal is connected to the FAU signal output by the FPGA control board via the input header, the VLED1+ terminal is connected to the input terminal of power indicator LEDA, the VLED1- terminal is connected to the output terminal of power indicator LEDA, the VE terminal is connected to the first terminal of capacitor C13, the VLED2+ terminal is connected to the input terminal of power indicator LEDA, the DESAT terminal is connected to the first terminal of resistor R9, the VCC2 terminal is connected to the first terminal of capacitor C16, the VC terminal is connected to the first terminal of capacitor C16, the VOUT terminal is connected to the first terminal of resistor R13, and the VEE terminal is connected to the second terminal of capacitor C16.

[0086] The first end of resistor R7 is connected to a 5V voltage, and the second end is connected to the PWM drive signal output by the FPGA control board via the input header.

[0087] The first end of resistor R8 is connected to the first end of capacitor C11, and the second end is connected to the FAULT terminal of the optocoupler driver chip.

[0088] The first terminal of resistor R9 is connected to the second terminal of capacitor C15, and the second terminal of R9 is connected to the first terminal of capacitor C16.

[0089] The first end of resistor R10 is connected to pin 6 of power supply QA03, and the second end is connected to the second end of resistor R11.

[0090] The first terminal of resistor R11 is connected to the first terminal of resistor R13;

[0091] The first end of resistor R12 is connected to the first end of resistor R9, and the second end is connected to the input end of Zener diode Z11;

[0092] The second terminal of capacitor C11 is connected to the VLED1- terminal of the optocoupler driver chip;

[0093] The first terminal of capacitor C12 is connected to a voltage of 24V+, and the second terminal is connected to a voltage of 24V-.

[0094] The first terminal of capacitor C13 is connected to the first terminal of capacitor C14, and the second terminal is connected to the first terminal of capacitor C16.

[0095] The first terminal of capacitor C14 is connected to the output terminal of power indicator LEDB, and the second terminal is connected to the second terminal of capacitor C16.

[0096] The first terminal of capacitor C15 is connected to the first terminal of resistor R10, and the second terminal is connected to the first terminal of resistor R9.

[0097] The first terminal of capacitor C17 is connected to the second terminal of resistor R13, and the second terminal is connected to terminal 1 of capacitor C18.

[0098] The first terminal of capacitor C18 is connected to the first terminal of capacitor C15, serving as the third output terminal of the MOS / IGBT drive circuit;

[0099] The output terminal of the power indicator LEDA is connected to the 5V+ voltage output of the positive and negative dual power supply via the input header;

[0100] The output terminal of the power indicator LEDB is connected to the first terminal of capacitor C15.

[0101] The output terminal of TVS transistor DG is connected to the output terminal of resistor R10, serving as the first output terminal of the MOS / IGBT drive circuit.

[0102] The output terminal of Zener diode Z11 is connected to the input terminal of fast recovery diode US1M;

[0103] The output terminal of the fast recovery diode US1M is used as the second output terminal of the MOS / IGBT drive circuit.

[0104] Pin 1 of power supply QA03 is connected to the first end of capacitor C12, pin 2 is connected to the second end of capacitor C12, pin 5 is connected to the first end of capacitor C17, pin 6 is connected to the second end of capacitor C17, and pin 7 is connected to the second end of capacitor C18.

[0105] The inputs of this MOS / IGBT drive circuit are 24V voltage, a dual DC power supply of ±5V, a PWM control signal, and a RES reset start signal.

[0106] In this MOS / IGBT drive circuit, the optocoupler driver chip can be model A316JN, which is a high-performance inverter module driver IC. The power supply QA03 can be a Mornsun power supply, which has built-in regulation capabilities and can output asymmetrical positive and negative voltages, ensuring stable and reliable voltage.

[0107] FPGA control board, such as Figure 4 As shown, it may include:

[0108] Phase-locked loop (PLL), frequency acceleration module, and modulation module (PWMStep); among them...

[0109] The phase-locked loop (PLL) is used to provide a stable clock signal for the modulation module (PWMStep).

[0110] The frequency acceleration module is used to accelerate the system frequency and provide the accelerated frequency to the modulation module pwmstep.

[0111] The modulation module pwmstep is used to output corresponding drive signals based on external duty cycle control signals and frequency control signals.

[0112] The FPGA control board has functions for frequency adjustment and duty cycle adjustment, and the output PWM control signal is adjustable. The res signal is used as the start signal of A316JN.

[0113] Specifically, the FPGA control board has four input buttons: duty cycle increment, duty cycle decrement, frequency increment, and frequency decrement. Users can adjust the duty cycle and frequency according to their needs, allowing the FPGA control board to receive the corresponding external duty cycle and frequency control signals. After power-on, the phase-locked loop (PLL) receives a reference clock signal from an external crystal oscillator or clock source. The PLL then uses an internal voltage-controlled oscillator, frequency divider, phase detector, and loop filter to multiply or divide the reference clock to a very stable and high-frequency system clock. This high-frequency clock serves as the time base for the entire FPGA's internal logic operation. External systems (such as microcontrollers or host computers) input frequency control signals (digital values, such as 16-bit binary numbers representing the target frequency) and duty cycle control signals (digital values, such as 8-bit or 10-bit binary numbers representing the target duty cycle of 0-100%) to the FPGA through its general-purpose input / output pins. The FPGA's internal logic captures and latches these control signals.

[0114] The latched frequency control signal is sent to the frequency acceleration module. The core task of the frequency acceleration module is to accelerate the latched frequency control signal to obtain the target frequency value.

[0115] The modulation process of the modulation module pwmstep includes:

[0116] Use a loop counter to generate a triangular wave, and set a cutoff value (set value) for the triangular wave. Compare the count value with the set value. When the count value is less than the set value, the PWM drive signal is high. When the count value is greater than or equal to the set value, the PWM drive signal is low. (Changing the set value changes the duty cycle). Changing the maximum value of the loop counter changes the output frequency of the PWM drive signal.

[0117] The output signal diagram of the FPGA control board is as follows: Figure 5 As shown, from Figure 5 This shows the PWM modulation process.

[0118] The first output terminal of the MOS / IGBT drive circuit is connected to the gate terminal of the MOS / IGBT under test, and the signal at the gate terminal of the MOS / IGBT under test is denoted as G. The second and third output terminals are connected to the source and drain terminals of the MOS / IGBT under test, respectively, and the signals at the source and drain terminals of the MOS / IGBT under test are denoted as C and E, respectively.

[0119] An oscilloscope is connected to the MOS / IGBT under test. Based on the input and output signals of the MOS / IGBT under test, the frequency of the MOS / IGBT under test is obtained.

[0120] Specifically, during testing, the oscilloscope observes the input signals (G and GND) and output signals (C and E) of the MOS / IGBT under test, thereby obtaining the frequency of the device under test. This allows users to select appropriate devices for their corresponding circuits based on the frequencies of each device.

[0121] This test circuit for general-purpose MOSFETs and IGBTs utilizes an FPGA control board to generate precise PWM drive signals based on external duty cycle and frequency control signals. This drives the MOSFET / IGBT under test, allowing the frequency of the MOSFET / IGBT to be measured using an oscilloscope. Compared to the complex measuring instruments used in existing technologies, this invention achieves frequency testing of the MOSFET / IGBT under test with only a few instruments, significantly reducing testing costs and providing a lower-cost measurement method for users who only need to test the frequency.

[0122] It should be noted that, in the description of this utility model, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0123] The above description is merely a preferred embodiment of this utility model and is not intended to limit the scope of protection of this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model are included within the scope of protection of this utility model.

Claims

1. A test circuit for general-purpose MOSFETs and IGBTs, characterized in that, include: The system includes a dual positive and negative power supply, an FPGA control board, a MOS / IGBT drive circuit, and an oscilloscope; among which, The positive and negative dual power supplies are respectively connected to the MOS / IGBT drive circuit and the FPGA control board, and are used to supply power to the MOS / IGBT drive circuit and the FPGA control board. The FPGA control board is connected to the MOS / IGBT drive circuit and is used to output corresponding PWM drive signals according to external duty cycle control signals and frequency control signals. The MOS / IGBT driving circuit is connected to the MOS / IGBT under test and is used to drive the MOS / IGBT under test according to the driving signal. The oscilloscope is connected to the MOS / IGBT under test and is used to obtain the frequency of the MOS / IGBT under test based on the input and output signals of the MOS / IGBT under test.

2. The test circuit for a general-purpose MOSFET and IGBT according to claim 1, characterized in that, The positive and negative dual power supply includes: The system comprises: a first switching power supply chip, a second switching power supply chip, diodes D1 and D2, a positive power indicator light D3, a negative power indicator light D4, inductors L1 and L2, capacitors C1, C2, C3, C4, C5, C6, C7, C8, and C10, and resistors R1, R2, R3, R4, R5, and R6; among which... The VIN terminal of the first switching power supply chip is connected to the first terminal of capacitor C5, the GND terminal is grounded, the BOOT terminal is connected to the first terminal of capacitor C1, the PH terminal is connected to the second terminal of capacitor C1, and the VSNS terminal is connected to the second terminal of resistor R1. The VIN terminal of the second switching power supply chip is connected to the first terminal of capacitor C10, the GND terminal is connected to the second terminal of resistor R4, the BOOT terminal is connected to the first terminal of capacitor C6, the PH terminal is connected to the second terminal of capacitor C6, and the VSNS terminal is connected to the first terminal of resistor R2. The input terminal of diode D1 is connected to the second terminal of resistor R4, and the output terminal is connected to the second terminal of capacitor C1. The input terminal of diode D2 is grounded, and its output terminal is connected to the second terminal of capacitor C6. The input terminal of the positive power indicator D3 is connected to the second terminal of resistor R5, and the output terminal is grounded; The input terminal of the positive power indicator D4 is connected to the first terminal of the resistor R6, and the output terminal is connected to the voltage VEE. The first end of the inductor L1 is connected to the second end of the capacitor C1, and the second end is connected to the first end of the capacitor C2. The first end of the inductor L2 is connected to the second end of the capacitor C6, and the second end is connected to the first end of the resistor R3. The first terminal of capacitor C2 is connected to the first terminal of capacitor C3, and the second terminal is grounded; The first terminal of capacitor C3 is connected to voltage VDD, and the second terminal is grounded. The first terminal of capacitor C4 is connected to the first terminal of capacitor C10, and the second terminal is grounded. The first terminal of capacitor C5 is connected to the first terminal of capacitor C4, and the second terminal is grounded. The first terminal of capacitor C7 is grounded, and the second terminal is connected to voltage VEE. The first terminal of capacitor C8 is connected to the first terminal of capacitor C7, and the second terminal is connected to the second terminal of capacitor C7. The first terminal of capacitor C10 is connected to the input terminal of the positive and negative dual power supply, and the second terminal is grounded; The first end of resistor R1 is connected to the first end of capacitor C3, and the second end is connected to the first end of resistor R2. The second terminal of the resistor R2 is grounded; The first end of resistor R3 is connected to the first end of capacitor C8, and the second end is connected to the first end of resistor R4. The second terminal of resistor R4 is connected to the second terminal of capacitor C8; The first terminal of the resistor R5 is connected to the voltage VDD; The second terminal of resistor R6 is grounded.

3. The test circuit for a general-purpose MOSFET and IGBT according to claim 2, characterized in that, The first and second switching power supply chips are both TPS5430.

4. The test circuit for a general-purpose MOSFET and IGBT according to claim 1, characterized in that, The MOS / IGBT driving circuit is composed of an optocoupled driving chip and its peripheral circuits cascaded together.

5. The test circuit for a general-purpose MOSFET and IGBT according to claim 4, characterized in that, The optical coupling driver chip is model A316JN.

6. The test circuit for a general-purpose MOSFET and IGBT according to claim 1, characterized in that, The FPGA control board includes: Phase-locked loop (PLL), frequency acceleration module, and modulation module (PWMStep); among them... The phase-locked loop pll is used to provide a stable clock signal for the modulation module pwmstep; The frequency acceleration module is used to accelerate the system frequency and provide the accelerated frequency to the modulation module pwmstep. The modulation module pwmstep is used to output corresponding drive signals according to external duty cycle control signals and frequency control signals.

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