Solar cell and photovoltaic module

Abstract

The utility model discloses a solar cell and photovoltaic module, solar cell includes: silicon substrate has opposite first surface and second surface to and the at least one cutting surface of connecting first surface and second surface, protection layer covers at least cutting surface and covers part first surface and / or part second surface. Solar cell and photovoltaic module of the utility model can enhance the side passivation of solar cell, reduce the side electric leakage risk, improve the battery efficiency.

Description

Technical Field

[0001] This utility model belongs to the field of photovoltaic cell technology, specifically relating to a solar cell and a photovoltaic module. Background Technology

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in the domestic and international photovoltaic markets are constantly increasing, and industry manufacturers are focusing on the research and development of high-efficiency cells.

[0003] Slab technology (also known as "shingled technology") is an advanced packaging process that improves the power density and reliability of solar modules through special cutting and stacking methods. It is mainly used in the manufacturing of high-efficiency photovoltaic modules. Slab technology refers to dividing standard-sized solar cells into multiple smaller pieces along a specific direction, such as two-piece, three-piece, and four-piece slabs. Slab technology has the following advantages: it can reuse the normal areas of defective cells, improving the utilization rate of cells; after slabification, the current path of the cells is shortened, and the internal series resistance is reduced, thereby reducing energy loss and increasing output power; it reduces the area and current of individual cells, resulting in lower temperatures during localized heating (hot spots) and reducing the probability of module damage; after slabification, the gaps between cells are smaller, increasing the effective light-receiving area of ​​the module and the power output per unit area; it reduces system costs; it promotes technological innovation and industrial upgrading, as well as environmental friendliness. These advantages make slab technology one of the important development directions in the photovoltaic industry.

[0004] However, existing solar cells have exposed side junction and base regions without passivation after being slab-sized, resulting in severe side recombination and a significant loss of cell efficiency. When multiple slab cells are connected in series or parallel using solder ribbons, the solder ribbons come into contact with the exposed junction regions on the sides of the slab cells, leading to increased leakage current. Utility Model Content

[0005] The purpose of this invention is to provide a solar cell and a photovoltaic module that can enhance the side passivation of the solar cell, reduce the risk of side leakage, and improve the battery efficiency.

[0006] To achieve the above objectives, the technical solution provided by a specific embodiment of this utility model is as follows:

[0007] A solar cell, comprising:

[0008] A silicon substrate having a first surface and a second surface disposed opposite to each other, and at least one diced surface connecting the first surface and the second surface;

[0009] A protective layer that at least covers the cut surface and covers a portion of the first surface and / or a portion of the second surface.

[0010] In one or more embodiments of this utility model, the protective layer extends from the cut surface to cover a portion of the first surface;

[0011] A first doped layer, a first passivation layer, and a first antireflection layer are sequentially stacked on the first surface. The doping type of the first doped layer is opposite to that of the silicon substrate. The protective layer covers a portion of the first antireflection layer.

[0012] In one or more embodiments of the present invention, the first surface includes a first region and a second region distributed adjacent to each other, the second region being disposed close to the cut surface;

[0013] The protective layer extends from the cut surface to cover at least a second region of the first surface, or the protective layer extends from the cut surface to cover a second region of the first surface and a portion of the first region.

[0014] In one or more embodiments of this utility model, the second region is recessed relative to the first region; and / or,

[0015] The width of the second region is 50μm to 400μm.

[0016] In one or more embodiments of the present invention, the first doped layer is disposed only on a first region of the first surface;

[0017] The first passivation layer and the first antireflection layer are disposed on the first region and the second region of the first surface.

[0018] In one or more embodiments of the present invention, on the first surface, the protective layer extends horizontally by a distance of 1 mm to 10 mm in the direction close to the center of the silicon substrate.

[0019] In one or more embodiments of this utility model, the protective layer extends from the cut surface to cover a portion of the second surface;

[0020] A tunneling layer, a second doped layer, a second passivation layer, and a second antireflection layer are sequentially stacked on the second surface. The doping type of the second doped layer is the same as that of the silicon substrate. The protective layer covers a portion of the second antireflection layer.

[0021] In one or more embodiments of the present invention, the second surface includes a third region and a fourth region that are distributed adjacently, the fourth region being disposed close to the cut surface;

[0022] The protective layer extends from the cut surface to cover at least a fourth region of the second surface, or the protective layer extends from the cut surface to cover a fourth region of the second surface and a portion of the third region.

[0023] In one or more embodiments of this utility model, the fourth region is recessed relative to the third region; and / or,

[0024] The width of the second region is 50μm to 400μm.

[0025] In one or more embodiments of this utility model, the tunneling layer and the second doped layer are disposed only on the third region of the second surface;

[0026] The second passivation layer is disposed on the third and fourth regions of the second surface, or the second passivation layer is disposed on a portion of the second surface and the horizontal coverage distance of the second passivation layer on the second surface from the cutting surface toward the center of the silicon substrate is greater than or equal to 5 mm;

[0027] The second antireflective layer is disposed on the third and fourth regions of the second surface.

[0028] In one or more embodiments of the present invention, on the second surface, the protective layer extends horizontally by a distance of 1 mm to 10 mm in the direction close to the center of the silicon substrate.

[0029] In one or more embodiments of this utility model, the protective layer comprises a stacked film formed by one or more of the following: an aluminum oxide layer, a silicon nitride layer, and an amorphous silicon layer, with a thickness of 10 nm to 100 nm.

[0030] In one or more embodiments of the present invention, the silicon substrate has at least one uncut surface connecting the first surface and the second surface, and a third passivation layer and a third antireflection layer are sequentially stacked on the uncut surface.

[0031] A photovoltaic module comprising at least one of the aforementioned solar cells.

[0032] Compared with the prior art, the solar cell and photovoltaic module of this invention improve the passivation performance of the cut surface, reduce the risk of leakage current at the cut surface, and improve the battery efficiency by setting a protective layer on the cut surface and extending it to cover part of the first surface and / or part of the second surface. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the structure of the solar cell in Embodiment 1 of this utility model;

[0035] Figure 2 This is a schematic diagram of the structure of the solar cell in Embodiment 2 of this utility model;

[0036] Figure 3 This is a schematic diagram of the structure of the solar cell in Embodiment 3 of this utility model;

[0037] Figure 4 This is a schematic diagram of the structure of the solar cell in Embodiment 4 of this utility model. Detailed Implementation

[0038] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0039] This utility model discloses a solar cell, including a silicon substrate and a protective layer. The silicon substrate has a first surface and a second surface disposed opposite to each other and at least one cut surface connecting the first surface and the second surface. The protective layer at least covers the cut surface and covers a portion of the first surface and / or a portion of the second surface.

[0040] The solar cell of this invention improves the passivation performance of the cut surface, reduces the risk of leakage current, and improves the cell efficiency by setting a protective layer on the cut surface and extending it to cover part of the first surface and / or part of the second surface.

[0041] In one embodiment, a first doped layer, a first passivation layer, and a first antireflection layer are sequentially stacked on a first surface. The doping type of the first doped layer is opposite to that of the silicon substrate, and a protective layer covers a portion of the first antireflection layer.

[0042] In one embodiment, the first surface includes a first region and a second region distributed adjacent to each other, the second region being disposed close to the cutting surface; the protective layer extends from the cutting surface to at least cover the second region of the first surface, or the protective layer extends from the cutting surface to cover the second region of the first surface and a portion of the first region.

[0043] In the above embodiments, the first doped layer is disposed only on the first region of the first surface; the first passivation layer and the first antireflection layer are disposed on the first region and the second region of the first surface.

[0044] In the above technical solution, the solar cell of this utility model, by dividing the first surface into a first region and a second region and not setting the first doped layer in the second region near the cut surface, can prevent the problem of increased leakage current caused by the solder ribbon contacting the junction region composed of the first doped layer and the silicon substrate at the cut surface of the solar cell when multiple solar cells are connected in series or in parallel using solder ribbon.

[0045] In one embodiment, a tunneling layer, a second doped layer, a second passivation layer, and a second antireflection layer are sequentially stacked on the second surface. The doping type of the second doped layer is the same as that of the silicon substrate, and a protective layer covers a portion of the second antireflection layer.

[0046] In one embodiment, the second surface includes a third region and a fourth region that are adjacent to each other, with the fourth region disposed close to the cutting surface; the protective layer extends from the cutting surface to cover at least the fourth region of the second surface, or the protective layer extends from the cutting surface to cover the fourth region of the second surface and a portion of the third region.

[0047] In the above embodiments, the tunneling layer and the second doped layer are only disposed on the third region of the second surface; the second passivation layer is disposed on the third and fourth regions of the second surface, or the second passivation layer covers a portion of the second surface and the horizontal coverage distance of the second passivation layer on the second surface from the cutting direction toward the center of the silicon substrate is greater than or equal to 5 mm; the second antireflection layer is disposed on the third and fourth regions of the second surface.

[0048] In one embodiment, the silicon substrate further has at least one uncut surface connecting the first surface and the second surface, and a third passivation layer and a third antireflection layer are sequentially stacked on the uncut surface.

[0049] This utility model also discloses a photovoltaic module, including at least one of the above-described solar cells.

[0050] The present invention will be further explained below with reference to specific examples.

[0051] Example 1:

[0052] refer to Figure 1 As shown, the solar cell 100 in this embodiment is illustrated using a TOPCon solar cell as an example. It includes a silicon substrate 10, which has a first surface S1 and a second surface S2 disposed opposite to each other. The first surface S1 is the front side (i.e., the light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlighting surface) of the silicon substrate 10. The silicon substrate 10 also includes at least one diced surface S3 connecting the first surface S1 and the second surface S2, and at least one non-diced surface S4 connecting the first surface S1 and the second surface S2.

[0053] In this embodiment, the silicon substrate 10 is an N-type silicon wafer with a resistivity of 0.3 Ω·cm to 21 Ω·cm and a thickness of 100 μm to 200 μm. A textured surface structure with a reflectivity of 8% to 11% (not shown) is formed on both the first surface S1 and the second surface S2 of the silicon substrate 10 by alkaline etching.

[0054] refer to Figure 1 As shown, in this embodiment, a first doped layer 11 (i.e., emitter) is formed at the first surface S1 of the silicon substrate 10 through a diffusion process or a PECVD process. The doping type of the first doped layer 11 is opposite to that of the silicon substrate 10, thereby forming a PN junction, which generates minority carrier-hole pairs after illumination. For example, the first doped layer 11 is a P-type doped layer (i.e., a P+ emitter), which is formed below the first surface S1 of the silicon substrate (i.e., inside the silicon substrate) through a boron diffusion process, with a diffusion depth of 0.1 μm to 5 μm and a surface doping concentration of 1E18 cm⁻¹. -3 ~1E19cm -3 The sheet resistance is 200 ohm / sq to 800 ohm / sq.

[0055] In this embodiment, a first passivation layer 21 and a first antireflection layer 31 are sequentially stacked on the first doped layer 11 of the first surface S1 of the silicon substrate 10 along a direction away from the silicon substrate 10. The first passivation layer 21 can provide excellent passivation effect, and the first antireflection layer 31 can reduce reflectivity and increase light utilization.

[0056] For example, the first passivation layer 21 is an aluminum oxide passivation layer with a thickness of 3nm to 10nm; the first antireflection layer 31 can be a stacked film formed by any one or more of silicon nitride, silicon oxynitride, and silicon oxide layers with a thickness of 65nm to 90nm, preferably a silicon nitride layer. Silicon nitride is chemically inactive and has strong resistance to acid and alkali corrosion, which can reduce the battery's sensitivity to the environment.

[0057] In this embodiment, the first passivation layer 21 can be prepared by a single ALD deposition process, and the first antireflection layer 31 can be deposited by a single PECVD process. The film materials and thicknesses deposited in the same deposition process are the same.

[0058] In this embodiment, a tunneling passivation contact structure is formed on the second surface S2 of the silicon substrate 10. Specifically, a tunneling layer 12 and a second doped layer 13 are sequentially stacked on the second surface S2 of the silicon substrate 10 in a direction away from the silicon substrate 10. The tunneling layer 12 can provide a good interface passivation effect, and the doping type of the second doped layer 13 is the same as that of the silicon substrate 10. The second doped layer 13 can provide a field passivation effect, and at the same time improve the contact and reduce the resistance.

[0059] The tunneling layer 12 is one or a combination of silicon oxide layer and silicon oxynitride layer, preferably silicon oxide layer, with a thickness of 15nm~35nm; the second doped layer 13 is phosphorus-doped polycrystalline silicon layer, with a thickness of 90nm~130nm.

[0060] In this embodiment, a second passivation layer 22 and a second antireflection layer 32 are sequentially stacked on the second doped layer 13 of the second surface S2 of the silicon substrate 10 along a direction away from the silicon substrate 10. The second passivation layer 22 can provide excellent passivation effect, and the second antireflection layer 32 can reduce reflectivity and increase light utilization.

[0061] For example, the second passivation layer 22 is an aluminum oxide passivation layer with a thickness of 3nm to 10nm; the second antireflection layer 32 can be a stacked film formed by any one or more of silicon nitride, silicon oxynitride, and silicon oxide layers with a thickness of 60nm to 90nm, preferably a silicon nitride layer. Silicon nitride is chemically inactive and has strong resistance to acid and alkali corrosion, which can reduce the battery's sensitivity to the environment.

[0062] In this embodiment, the second passivation layer 22 can be prepared by a single ALD deposition process, and the second antireflection layer 32 can be deposited by a single PECVD process. The film materials and thicknesses deposited in the same deposition process are the same.

[0063] In other embodiments, the second passivation layer 22 may also be deposited only on a portion of the second surface S2. For example, the second passivation layer 22 extends from the cut surface S3 toward the center of the silicon substrate 10 on the second surface S2, and the horizontal extension covers a distance greater than or equal to 5 mm.

[0064] Continue to refer to Figure 1 As shown, in this embodiment, a protective layer 14 is provided on the cutting surface S3, and the protective layer 14 extends from the cutting surface S3 to cover part of the first surface S1 and part of the second surface S2.

[0065] Specifically, the protective layer 14 covers a portion of the first antireflective layer 31 on the first surface S1, and the protective layer 14 also covers a portion of the second antireflective layer 32 on the second surface S2. Preferably, the extent to which the protective layer 14 covers the first antireflective layer 31 is defined as follows: the horizontal extension distance L1 of the protective layer 14 from the cut surface S3 along the direction close to the center of the silicon substrate 10 is 1 mm to 10 mm. The extent to which the protective layer 14 covers the second antireflective layer 32 is defined as follows: the horizontal extension distance L2 of the protective layer 14 from the cut surface S3 along the direction close to the center of the silicon substrate 10 is 1 mm to 10 mm.

[0066] It is understood that the horizontal extension distance L1 of the protective layer 14 on the first antireflection layer 31 can be the same as the horizontal extension distance L2 of the protective layer 14 on the second antireflection layer 32. Alternatively, the horizontal extension distance L1 of the protective layer 14 on the first antireflection layer 31 can also be different from the horizontal extension distance L2 of the protective layer 14 on the second antireflection layer 32. The protective layer 14 comprises a stacked film formed by one or more of the following: an aluminum oxide layer, a silicon nitride layer, and an amorphous silicon layer, with a thickness of 10 nm to 100 nm.

[0067] Since the entire solar cell is not passivated on the cut surface after dicing, in this embodiment, a protective layer 14 is formed on the cut surface S3 and extends to the first surface S1 and the second surface S2. The protective layer 14 can improve the passivation performance of the cut surface, thereby improving the cell efficiency. It can also prevent the solder ribbon from contacting the junction area on the cut surface after the cells are connected in series or in parallel, which would lead to increased leakage.

[0068] It is understood that in other embodiments, the protective layer 14 may extend from the cutting surface S3 to cover only a portion of the first surface S1; or, the protective layer 14 may extend from the cutting surface S3 to cover only a portion of the second surface S2, which can also achieve the above-mentioned technical effects.

[0069] Continue to refer to Figure 1 As shown, in this embodiment, a third passivation layer 23 and a third antireflection layer 33 are sequentially stacked on the non-cut surface S4. The third passivation layer 23 provides excellent passivation effect, and the third antireflection layer 33 reduces reflectivity and increases light utilization. The third passivation layer 23 is integrally connected to the first passivation layer 21 on the first surface S1 and the second passivation layer 22 on the second surface S2, respectively. The third antireflection layer 33 is integrally connected to the first antireflection layer 31 on the first surface S1 and the second antireflection layer 32 on the second surface S2, respectively.

[0070] For example, the third passivation layer 23 is an aluminum oxide passivation layer with a thickness of 3nm to 10nm; the third antireflection layer 33 can be a stacked film formed by any one or more of silicon nitride, silicon oxynitride, and silicon oxide layers with a thickness of 60nm to 90nm, preferably a silicon nitride layer. Silicon nitride is chemically inactive and has strong resistance to acid and alkali corrosion, which can reduce the battery's sensitivity to the environment.

[0071] In this embodiment, the third passivation layer 23 can be prepared by a single ALD deposition process, and the third antireflection layer 33 can be deposited by a single PECVD process. The film materials and thicknesses deposited in the same deposition process are the same.

[0072] It is understandable that only passivation layers or only antireflection layers may be deposited on the first surface S1, the second surface S2, and the non-cut surface S4 of the silicon substrate 10. Passivation layers may be deposited only in some areas, or antireflection layers may be deposited only in some areas. The materials and thicknesses of different passivation layers or different antireflection layers may also be different, which will not be elaborated here.

[0073] In addition, in this embodiment, the first electrode (not shown) is located on the first surface S1 of the silicon substrate 10 and is in contact with the first doped layer 11, and the second electrode (not shown) is located on the second surface S2 of the silicon substrate 10 and is in contact with the second doped layer 13.

[0074] Example 2:

[0075] refer to Figure 2 As shown, the solar cell 100 in this embodiment is largely the same as that in Embodiment 1, except that in this embodiment, the first surface S1 includes a first region S11 and a second region S12 distributed adjacent to each other, with the second region S12 disposed near the cut surface S3; and the first doped layer 11 is disposed only on the first region S11 of the first surface S1. Preferably, the second region S12 is recessed relative to the first region S11.

[0076] Specifically, the upper surface of the entire solar cell may include a functional area and a dicing area. After the first doped layer 11 is formed, the dicing area of ​​the entire solar cell is grooved. A laser is used to remove all of the first doped layer 11 and part of the silicon substrate 10 from the dicing area. Therefore, the recess depth of the dicing area needs to be greater than the thickness (i.e., diffusion depth) of the first doped layer 11. It is worth noting that in this embodiment, the recess depth is the height difference between the surface of the silicon substrate 10 in the second region S12 and the surface of the first doped layer 11 in the first region S11.

[0077] In the solar cells obtained after grooving and dicing, the first doped layer 11 is retained only in the first region S11, while the first doped layer in the second region S12 is completely removed.

[0078] Preferably, the width W1 of the second region S12 is 50μm to 400μm.

[0079] For example, the laser used in the laser process is a 532nm green PS laser with a spot width of 20μm~500μm. The 532nm green PS laser (Pulse Solid-state Laser) is a pulsed green laser generated by combining a solid laser medium (such as Nd:YAG, Nd:YVO4) with nonlinear frequency conversion technology (such as KTP crystal frequency doubling). It is characterized by high brightness, high monochromaticity and excellent focusing performance.

[0080] In this embodiment, the second region S12 is described using the example of equal width and equal depth. In other embodiments, the second region S12 may have different widths and / or different depths at different locations. Correspondingly, the second region S12 may have different recess depths at different locations.

[0081] In addition, after laser grooving the dicing area, damage will occur on the surface of the silicon substrate 10 in the dicing area. In this invention, a textured structure (not shown) is formed on the surface of the silicon substrate 10 in the dicing area by a texturing process. This can etch and modify the damaged area, reduce surface recombination, reduce optical loss in the dicing area, avoid loss of open circuit voltage Voc and fill factor FF in the dicing area, and thus improve battery efficiency.

[0082] In this embodiment, the first passivation layer 21 and the first antireflection layer 31 are sequentially stacked on the first region S11 and the second region S12 of the first surface S1, and cover the connection surface of the first region S11 and the second region S12.

[0083] The protective layer 14 can extend from the cut surface S3 to cover the second region S12 of the first surface S1, the interface between the first region S11 and the second region S12, and a portion of the first region S11. The horizontal extension distance L3 of the protective layer 14 on the first surface S1 from the cut surface S3 along a direction close to the center of the silicon substrate 10 is 1 mm to 10 mm. This horizontal extension distance L3 can be the same as the horizontal extension distance L2 of the protective layer 14 on the second antireflection layer 32; or it can be different from the horizontal extension distance L2 of the protective layer 14 on the second antireflection layer 32.

[0084] In other embodiments, the protective layer 14 may extend only from the cut surface S3 to cover the second region S12 of the first surface S1.

[0085] In this embodiment, by dividing the first surface S1 into a first region S11 and a second region S12 and not setting the first doped layer 11 in the second region S12 near the cut surface S3, while covering it with a protective layer 14, it is possible to prevent the solder ribbon from contacting the junction region composed of the first doped layer 11 and the silicon substrate 10 at the cut surface S3 of the solar cell when multiple solar cells are connected in series or in parallel using solder ribbon, which would lead to increased leakage current.

[0086] Example 3:

[0087] refer to Figure 3As shown, the solar cell 100 in this embodiment is largely the same as that in Embodiment 2, except that in this embodiment, the second surface S2 includes a third region S21 and a fourth region S22 distributed adjacently, with the fourth region S22 disposed near the cut surface S3; and the tunneling layer 12 and the second doped layer 13 are disposed only on the third region S21 of the second surface S2. Preferably, the fourth region S22 is recessed relative to the third region S21.

[0088] Similarly, the lower surface of the entire solar cell may include functional areas and dicing areas. After forming the tunneling layer 12 and the second doped layer 13, grooving is performed on the dicing areas of the entire solar cell. A laser is used to remove all of the tunneling layer 12 and the second doped layer 13, as well as part of the silicon substrate 10, from the dicing areas. Therefore, the recess depth of the dicing areas must be greater than the sum of the thicknesses of the tunneling layer 12 and the second doped layer 13. It is worth noting that in this embodiment, the recess depth is the height difference between the surface of the silicon substrate 10 in the fourth region S22 and the surface of the second doped layer 13 in the third region S21.

[0089] In the solar cells obtained after grooving and dicing, the tunneling layer 12 and the second doped layer 13 are retained only in the third region S21, while the tunneling layer 12 and the second doped layer 13 in the fourth region S22 are completely removed.

[0090] Preferably, the width W2 of the fourth region S22 is 50μm~400μm.

[0091] For example, the laser used in the laser process is a 532nm green PS laser with a spot width of 100μm~600μm. The 532nm green PS laser (Pulse Solid-state Laser) is a pulsed green laser generated by combining a solid laser medium (such as Nd:YAG, Nd:YVO4) with nonlinear frequency conversion technology (such as KTP crystal frequency doubling). It is characterized by high brightness, high monochromaticity and excellent focusing performance.

[0092] In this embodiment, the second passivation layer 22 and the second antireflection layer 32 are sequentially stacked on the third region S21 and the fourth region S22 of the second surface S2, and cover the connection surface of the third region S21 and the fourth region S22.

[0093] The protective layer 14 can extend from the cut surface S3 to cover the fourth region S22, the third region S21, the connection surface of the fourth region S22, and a portion of the third region S21 on the second surface S2. The horizontal extension distance L4 of the protective layer 14 on the second surface S2 from the cut surface S3 along a direction close to the center of the silicon substrate 10 is 1 mm to 10 mm. This horizontal extension distance L4 can be the same as the horizontal extension distance L3 of the protective layer 14 on the first surface S1; or it can be different from the horizontal extension distance L3 of the protective layer 14 on the first surface S1.

[0094] In other embodiments, the protective layer 14 may extend only from the cut surface S3 to cover the fourth region S22 of the second surface S2.

[0095] Example 4:

[0096] refer to Figure 4 As shown, the solar cell 100 in this embodiment is largely the same as that in Embodiment 3, except that Embodiment 3 is for two-cell solar cells, so three sides of the solar cell 100 are non-cut surfaces S4, and one side is a cut surface S3. This embodiment, however, is for three-cell or four-cell solar cells, etc., where the cell slabs in the middle region after dicing have two oppositely arranged cut surfaces S3. Therefore, the second region S12 and the fourth region S22 can also have two slabs, respectively positioned close to the two cut surfaces S3. In this embodiment, each cut surface S3, as well as a portion of the first surface S1 and a portion of the second surface S2, are passivated using a protective layer 14. The protective layer 14 is exactly the same as in Embodiment 3, and will not be described further here.

[0097] Compared with the prior art, the solar cell and photovoltaic module of this invention improve the passivation performance of the cut surface, reduce the risk of leakage current at the cut surface, and improve the battery efficiency by setting a protective layer on the cut surface and extending it to cover part of the first surface and / or part of the second surface.

[0098] It should be understood that the above embodiments use TOPCon batteries as an example for illustration. This utility model is also applicable to other types of solar cells, such as PERC batteries and HJT batteries. Any technical solution that uses a protective layer to passivate and protect the cut surface and part of the first surface and / or part of the second surface is within the scope of protection of this utility model.

[0099] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0100] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A solar cell, characterized in that, include: A silicon substrate having a first surface and a second surface disposed opposite to each other, and at least one diced surface connecting the first surface and the second surface; A protective layer that at least covers the cut surface and covers a portion of the first surface and / or a portion of the second surface.

2. The solar cell according to claim 1, characterized in that, The protective layer extends from the cut surface and covers a portion of the first surface; A first doped layer, a first passivation layer, and a first antireflection layer are sequentially stacked on the first surface. The doping type of the first doped layer is opposite to that of the silicon substrate. The protective layer covers a portion of the first antireflection layer.

3. The solar cell according to claim 2, characterized in that, The first surface includes a first region and a second region that are distributed adjacent to each other, with the second region located close to the cut surface; The protective layer extends from the cut surface to cover at least a second region of the first surface, or the protective layer extends from the cut surface to cover a second region of the first surface and a portion of the first region.

4. The solar cell according to claim 3, characterized in that, The second region is recessed relative to the first region; and / or, The width of the second region is 50μm to 400μm.

5. The solar cell according to claim 3, characterized in that, The first doped layer is disposed only on a first region of the first surface; The first passivation layer and the first antireflection layer are disposed on the first region and the second region of the first surface.

6. The solar cell according to claim 2, characterized in that, On the first surface, the protective layer extends horizontally for a distance of 1 mm to 10 mm in the direction close to the center of the silicon substrate.

7. The solar cell according to claim 1, characterized in that, The protective layer extends from the cut surface and covers a portion of the second surface; A tunneling layer, a second doped layer, a second passivation layer, and a second antireflection layer are sequentially stacked on the second surface. The doping type of the second doped layer is the same as that of the silicon substrate. The protective layer covers a portion of the second antireflection layer.

8. The solar cell according to claim 7, characterized in that, The second surface includes a third region and a fourth region that are distributed adjacent to each other, the fourth region being located close to the cut surface; The protective layer extends from the cut surface to cover at least a fourth region of the second surface, or the protective layer extends from the cut surface to cover a fourth region of the second surface and a portion of the third region.

9. The solar cell according to claim 8, characterized in that, The fourth region is recessed relative to the third region; and / or, The width of the second region is 50μm to 400μm.

10. The solar cell according to claim 8, characterized in that, The tunneling layer and the second doped layer are disposed only on the third region of the second surface; The second passivation layer is disposed on the third and fourth regions of the second surface, or the second passivation layer is disposed on a portion of the second surface and the horizontal coverage distance of the second passivation layer on the second surface from the cutting surface toward the center of the silicon substrate is greater than or equal to 5 mm; The second antireflective layer is disposed on the third and fourth regions of the second surface.

11. The solar cell according to claim 7, characterized in that, On the second surface, the protective layer extends horizontally for a distance of 1 mm to 10 mm in the direction close to the center of the silicon substrate.

12. The solar cell according to claim 1, characterized in that, The protective layer comprises a stacked film formed by one or more of the following: an aluminum oxide layer, a silicon nitride layer, and an amorphous silicon layer, with a thickness of 10 nm to 100 nm.

13. The solar cell according to claim 1, characterized in that, The silicon substrate has at least one uncut surface connecting the first surface and the second surface, and a third passivation layer and a third antireflection layer are sequentially stacked on the uncut surface.

14. A photovoltaic module, characterized in that, The photovoltaic module includes at least one solar cell as described in any one of claims 1 to 13.

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