Spi communication power supply reverse connection protection circuit and electronic equipment

Abstract

The utility model discloses a kind of SPI communication power supply anti-reverse connection protection circuit and electronic equipment, it is related to electronic circuit field, solve SPI high-speed communication line RC too big and produce communication anomaly to cause signal attenuation, it simultaneously solves the problem that power supply reverse connection or power supply negative pulse leads to chip damage.When power supply reverse connection or negative pulse appears, power switch tube switches to closed state, the leakage current of power supply reverse connection cannot fill to drive chip, reach the effect of power supply reverse connection protection, avoid the clamping diode in the inside of drive chip and break down due to overcurrent, effectively protect drive chip.Simultaneously, by the wire connection distance of power switch tube and drive chip is designed to be less than the wire connection distance of micro control unit, can effectively reduce the parasitic capacitance between power switch tube and drive chip, improve the reliability of SPI communication.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuits, and in particular to an SPI communication power supply reverse connection protection circuit and electronic equipment. Background Technology

[0002] In the design of microcontroller unit circuits in the automotive electronics field, many driver chips are used. The driver chips are controlled through the serial peripheral interface (SPI) of the microcontroller unit (MCU). Through the SPI communication protocol, multiple driver chips can share a set of communication lines, which can greatly save the MCU's input / output (IO) resources, but the flexibility and timeliness are poor.

[0003] To improve the timeliness of the control driver chip via SPI and reduce the MCU load rate, it is necessary to increase the SPI communication rate. The SPI communication rate can be increased by reducing the series resistance on the SPI communication harness, because the series resistance and parasitic capacitance form a resistor-capacitance (RC) filter circuit, leading to signal attenuation and potentially causing communication anomalies.

[0004] However, reducing the series resistance introduces new problems. For some driver chips, if the current limiting capability of the leakage circuit is insufficient when the power supply is reversed or a negative pulse occurs at the power supply terminal, the driver chip can easily be damaged. This is because after reducing the series resistance, current can more easily pass through the leakage circuit, and insufficient current limiting capability cannot effectively limit the current magnitude, which may cause the driver chip to be subjected to excessive current surges and be damaged.

[0005] Therefore, it is evident that solving the communication anomalies caused by excessive RC in the SPI high-speed communication line leading to signal attenuation, and also resolving chip damage caused by reverse power connection or negative power pulse, are technical problems that urgently need to be solved by those in the field. Utility Model Content

[0006] The purpose of this invention is to provide an SPI communication power supply reverse connection protection circuit and electronic device, which solves the problem of communication abnormalities caused by excessive RC in the SPI high-speed communication line leading to signal attenuation, and also solves the problem of chip damage caused by reverse power connection or power supply negative pulse.

[0007] To solve the above technical problems, this utility model provides an SPI communication power supply reverse connection protection circuit, including: multiple reverse connection protection modules; the input terminal of each reverse connection protection module is connected to the master device data input / slave device data output port of the microcontroller unit, and the output terminal of each reverse connection protection module is respectively connected to the master device data input / slave device data output port of multiple driver chips;

[0008] The anti-reverse module includes: a power switch with a body diode and a first resistor;

[0009] The first terminal of the power switch is connected to the master device data input / slave device data output port of the microcontroller unit, the second terminal of the power switch is connected to the master device data input / slave device data output port of the driver chip, the control terminal of the power switch is connected to the first terminal of the first resistor, and the second terminal of the first resistor is connected to the power supply.

[0010] The wire connection distance between the power switch and the driver chip is less than the wire connection distance between the power switch and the microcontroller unit.

[0011] As an optional solution, in the above-mentioned SPI communication power reverse connection protection circuit, the reverse connection protection module further includes: a first diode;

[0012] The anode of the first diode is connected to the second terminal of the power switch, and the cathode of the first diode is connected to the control terminal of the power switch.

[0013] As an optional solution, the above-mentioned SPI communication power reverse connection protection circuit also includes: a control switch module;

[0014] The input terminal of the control switch module is connected to the start signal source of the microcontroller unit, and the output terminal of the control switch module is connected to the second terminal of the first resistor of each of the anti-reverse modules.

[0015] As an optional solution, in the above-mentioned SPI communication power reverse connection protection circuit, the control switch module includes: a second resistor, a third resistor, and a first transistor;

[0016] The second end of each of the first resistors is connected to the first end of the first transistor, and the second end of the first transistor is connected to the start signal source of the microcontroller; the second end of the first transistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the control terminal of the first transistor and the first end of the second resistor, and the second end of the second resistor is grounded.

[0017] As an optional solution, in the above-mentioned SPI communication power reverse connection protection circuit, the second terminal of the first transistor is connected to the enable terminal of the microcontroller.

[0018] As an optional solution, in the above-mentioned SPI communication power reverse connection protection circuit, each of the reverse connection protection modules further includes: a fourth resistor;

[0019] The fourth resistor is connected in parallel between the second terminal of the power switch and the control terminal of the power switch.

[0020] As an optional solution, the above-mentioned SPI communication power reverse connection protection circuit also includes: an output reverse connection protection unit; and an input reverse connection protection unit.

[0021] The first end of the output anti-reverse unit is connected to the master device data output / slave device data input port and clock port of the microcontroller unit, and the second end of the output anti-reverse unit is connected to the master device data output / slave device data input port and clock port of the driver chip.

[0022] The first end of the input anti-reverse unit is connected to the chip select port of the microcontroller unit, and the second end of the input anti-reverse unit is connected to the chip select port of the driver chip.

[0023] As an optional solution, in the above-mentioned SPI communication power reverse connection protection circuit, the output reverse connection protection unit includes: a fifth resistor and a sixth resistor; the input reverse connection protection unit includes: a seventh resistor;

[0024] The master data output / slave data input port of the microcontroller is connected to the master data output / slave data input port of the driver chip through the fifth resistor; the clock port of the microcontroller is connected to the clock port of the driver chip through the sixth resistor; the chip select port of the microcontroller is connected to the chip select port of the driver chip through the seventh resistor.

[0025] The distance between the fifth resistor and the wire of the driver chip is less than the distance between the fifth resistor and the wire of the microcontroller unit; the distance between the sixth resistor and the wire of the driver chip is less than the distance between the sixth resistor and the wire of the microcontroller unit; the distance between the seventh resistor and the wire of the microcontroller unit is less than the distance between the seventh resistor and the wire of the driver chip.

[0026] As an optional solution, in the above-mentioned SPI communication power reverse connection protection circuit, the power switch with body diode is an NMOS transistor;

[0027] The gate of the NMOS transistor is connected to the first terminal of the first resistor, the source of the NMOS transistor is connected to the master data input / slave data output port of the driver chip, and the drain of the NMOS transistor is connected to the master data input / slave data output port of the microcontroller unit.

[0028] To solve the above-mentioned technical problems, this utility model also provides an electronic device, including the above-mentioned SPI communication power reverse connection protection circuit.

[0029] The SPI communication power reverse connection protection circuit provided by this utility model includes multiple reverse connection protection modules. These modules are connected between the master data input / slave data output ports of the microcontroller and the master data input / slave data output ports of multiple driver chips. During normal operation, the power switch is turned on, and its internal resistance is low. The output signal of the driver chip is transmitted to the microcontroller through the power switch, minimizing the impact on communication signal transmission. When the power supply is reversed or a negative pulse occurs, the power switch switches to the off state. The leakage current from the reverse power connection cannot flow to the driver chip, achieving the reverse power connection protection function and preventing the clamping diode inside the driver chip from breaking down due to overcurrent, effectively protecting the driver chip.

[0030] Meanwhile, by designing the connection distance between the power switch and the driver chip to be smaller than that between the power switch and the microcontroller, the parasitic capacitance between the power switch and the driver chip can be effectively reduced, improving the reliability of SPI communication. The reverse polarity protection module allows this circuit to be easily applied to SPI communication connections between multiple driver chips and microcontrollers, resolving the conflict between high-speed SPI communication and reverse power protection, without requiring major modifications to the existing SPI communication architecture.

[0031] In addition, this utility model also provides an electronic device, including the above-mentioned SPI communication power reverse connection protection circuit, with the same effect. Attached Figure Description

[0032] To more clearly illustrate the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of a conventional SPI communication method.

[0034] Figure 2 A circuit diagram of an SPI communication power supply reverse connection protection circuit is provided in this application embodiment;

[0035] Figure 3 This application provides a schematic diagram of an SPI communication power supply reverse connection protection circuit according to an embodiment of the present application.

[0036] Figure 4A circuit diagram of another SPI communication power reverse connection protection circuit is provided for embodiments of this application;

[0037] Figure 5 This application provides a schematic diagram of another SPI communication power supply reverse connection protection circuit for embodiments of the present application;

[0038] Figure 6 This is a schematic diagram illustrating the connection of multiple driver chips according to an embodiment of this application;

[0039] Figure 7 This application provides a partial circuit diagram of an SPI communication power supply reverse connection protection circuit according to an embodiment of the present application.

[0040] The reference numerals in the attached diagram are as follows: anti-reverse module 11, control unit 12, and driver chip 13. Detailed Implementation

[0041] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0042] The core of this invention is to provide an SPI communication power supply reverse connection protection circuit and electronic device.

[0043] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] When a microcontroller unit (MCU) communicates with a single driver chip via SPI, a series resistor can be placed near the signal source to prevent signal reflection and improve the EMI performance of the MCU. When the MCU communicates with multiple driver chips via SPI, sharing the Clock, MOSI, and MISO ports, the connecting wires increase in length, and the PCB traces generate parasitic capacitance. This parasitic capacitance is even greater when the control unit is large and the traces are long. This parasitic capacitance, along with the series resistor on the lines, forms an RC filter, attenuating the communication signal and distorting the original square wave signal. This can prevent the chip from recognizing effective highs and lows, leading to communication failures.

[0045] To improve communication waveform quality, the series resistance can be reduced. However, due to the characteristics of the chip's internal circuitry, a smaller series resistance may cause the chip to be damaged due to excessive leakage current during reverse power connection or negative pulse tests. Furthermore, reducing the series resistance may damage the driver chip during reverse power connection or negative pulse tests. Figure 1As shown, D2 and D3 are built-in clamping diodes for the MCU's I / O pins, protecting the MCU's I / O pins; D6 and D4 are internal pin protection clamping diodes of the driver chip. Clamping diodes are designed to protect the chip from certain input voltage surges, a common design principle in chip design; D5 is the internal power supply reverse protection diode of the driver chip. Some driver chips do not integrate this internally, requiring external reverse protection circuitry. When the controller experiences reverse power connection or a negative pulse at the power supply terminal, leakage current will occur in the direction of the arrow. If R1's current limiting is insufficient, it may cause the D6 clamping diode to break down, damaging the driver chip. Furthermore, if D6 breaks down, it may further damage D2 and D4 due to overcurrent. Therefore, based on the driver chip's own circuit design characteristics, a current-limiting resistor is essential. When the current-limiting resistor is large enough to limit the leakage current, D6 will not break down and damage the chip. In practical applications, reverse protection can be added at the VB position, but the high current at the drive end makes the reverse protection too costly. Alternatively, the PCB traces could be shortened, but in practical applications, the traces may not be able to be shortened due to factors such as controller size and chip placement.

[0046] In summary, considering the characteristics of current mainstream driver chips, current-limiting resistors seem to be indispensable. If the current-limiting resistor is too small, the chip will be damaged when the power supply is reversed or when there is a negative pulse on the power supply. If the current-limiting resistor is too large, it will prevent the SPI communication rate from being increased, making the chip unable to meet the requirements of practical applications.

[0047] To solve the above technical problems, this utility model provides an SPI communication power supply reverse connection protection circuit, such as... Figure 2 As shown, it includes: multiple anti-reverse modules 11; the input terminal of each anti-reverse module 11 is connected to the master device data input / slave device data output port of the microcontroller unit 12, and the output terminal of each anti-reverse module 11 is connected to the master device data input / slave device data output port of multiple driver chips 13 respectively;

[0048] The anti-reverse module 11 includes: a power switch Q1 with a body diode and a first resistor R1;

[0049] The first terminal of the power switch Q1 is connected to the master data input / slave data output port of the microcontroller 12, the second terminal of the power switch Q1 is connected to the master data input / slave data output port of the driver chip 13, the control terminal of the power switch Q1 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is connected to the power supply.

[0050] The wire connection distance between the power switch Q1 and the driver chip 13 is less than the wire connection distance between the power switch Q1 and the microcontroller unit 12.

[0051] The power switch Q1 with a body diode mentioned in this embodiment is typically a MOSFET, but it can also be an insulated-gate bipolar transistor (IGBT). This application uses an insulated-gate field-effect transistor (MOSFET) as an example. Since the master device data input / slave device data output (MISO) port outputs signals from the driver chip 13 and receives signals from the microcontroller unit 12, the power switch Q1 transmits signals from the second terminal to the first terminal under normal operating conditions.

[0052] Specifically, the power switch Q1 with a body diode is an N-channel metal-oxide-semiconductor field-effect transistor (NMOS transistor); the gate of the NMOS transistor is connected to the first terminal of the first resistor R1, the source of the NMOS transistor is connected to the master data input / slave data output port of the driver chip 13, and the drain of the NMOS transistor is connected to the master data input / slave data output port of the microcontroller unit 12.

[0053] The first resistor R1 limits the gate current to prevent excessive gate current from damaging the power switch Q1. It also helps stabilize the gate voltage.

[0054] To reduce the impact of parasitic capacitance, the wire connection distance between the power switch Q1 and the driver chip 13 is shorter than the wire connection distance between the power switch Q1 and the microcontroller unit 12. Reducing parasitic capacitance helps to reduce signal attenuation during transmission and improve signal integrity. Figure 2 The capacitor C1 in the figure is a parasitic capacitor and is not an actual component.

[0055] Under normal operating conditions, when the MISO port of driver chip 13 outputs a low level (0V), the gate voltage of the NMOS transistor is approximately 12V (assuming VB is 12V), and the source (S) voltage is 0V. At this time, the Vgs voltage of the NMOS transistor is 12V, which is much greater than the turn-on voltage of the NMOS transistor (usually 2-3V), and the NMOS transistor is turned on. Therefore, the MCU receives a low-level signal.

[0056] When the MISO port of driver chip 13 outputs a high level (5V), the gate (G) voltage of the NMOS transistor is still 12V, and the source (S) voltage is 5V. At this time, the Vgs voltage of the NMOS transistor is 7V, which is still greater than the turn-on voltage of the NMOS transistor, so the NMOS transistor is turned on. Therefore, the MCU receives a high-level signal.

[0057] Furthermore, even if the VB voltage is low and cannot meet the Vgs voltage requirement for the NMOS transistor to turn on, a high-level signal can still be sent to the MCU through the NMOS transistor's body diode. This is because the NMOS transistor's body diode conducts when forward biased, ensuring that the high-level signal can be transmitted to the MCU.

[0058] like Figure 3 When the power supply is reversed or a negative pulse occurs, the gate (G) voltage of the NMOS transistor is 0V. At this time, the Vgs voltage of the NMOS transistor is 0V, and the NMOS transistor is turned off. Therefore, the leakage current from the reverse power supply cannot flow into the driver chip 13 through the NMOS transistor, thus protecting the driver chip 13 from damage by reverse voltage.

[0059] It should be noted that although this application is applied to SPI communication between a single microcontroller unit 12 and multiple driver chips 13, in practical applications it can be applied to any environment that requires SPI communication.

[0060] The SPI communication power reverse connection protection circuit provided by this invention includes multiple reverse connection protection modules 11. These modules 11 are connected between the master data input / slave data output ports of the microcontroller unit 12 and the master data input / slave data output ports of multiple driver chips 13. During normal operation, the power switch Q1 is turned on, and its internal resistance is low. The output signal of the driver chip 13 is transmitted to the microcontroller unit 12 through the power switch Q1, minimizing the impact on communication signal transmission. When the power supply is reversed or a negative pulse occurs, the power switch Q1 switches to the off state. The leakage current from the reverse power supply cannot flow to the driver chip 13, achieving reverse power connection protection and preventing the clamping diode inside the driver chip 13 from breaking down due to overcurrent, effectively protecting the driver chip 13. Simultaneously, by designing the wire connection distance between the power switch Q1 and the driver chip 13 to be less than the wire connection distance with the microcontroller unit 12, the parasitic capacitance between the power switch Q1 and the driver chip 13 can be effectively reduced, improving the reliability of SPI communication. The anti-reverse module 11 allows the circuit to be easily applied to the SPI communication connection between multiple driver chips 13 and microcontroller unit 12, resolving the contradiction between high-speed SPI communication and reverse power protection, without requiring major modifications to the existing SPI communication architecture.

[0061] According to the above embodiment, in order to further protect the gate of the power switch Q1 (NMOS transistor), the anti-reverse module 11 further includes: a first diode D1;

[0062] The anode of the first diode D1 is connected to the second terminal of the power switch Q1, and the cathode of the first diode D1 is connected to the control terminal of the power switch Q1.

[0063] In certain situations, such as power supply voltage fluctuations or external interference, the gate voltage may exceed its safe operating range. The first diode D1 absorbs any potential surges across the gate and source of Q1. If a reverse voltage is present in the circuit, the first diode D1 prevents the reverse voltage from being applied between the gate and source, further protecting the gate.

[0064] The newly added first diode D1 can further protect the gate of the NMOS transistor, prevent the gate voltage from being affected by abnormal conditions, and ensure the stability and reliability of the circuit.

[0065] According to the above embodiments, it further includes: a control switch module;

[0066] The input terminal of the control switch module is connected to the start signal source of the microcontroller unit 12, and the output terminal of the control switch module is connected to the second terminal of the first resistor R1 of each anti-reverse module 11.

[0067] The main purpose of the newly added control switch module is to control the activation of multiple anti-reverse modules 11 via the start signal source of the microcontroller unit 12 (MCU) during system startup. This ensures that the anti-reverse modules 11 can be activated correctly during system startup, thereby improving the reliability and stability of the system.

[0068] When the system starts up, the MCU sends a signal input to the control switch module through the start signal source, and then passes it to the second terminal of the first resistor R1 of the anti-reverse module 11 through the control switch module to control the gate voltage of the NMOS transistor and ensure that the NMOS transistor is in the correct state when the system starts up.

[0069] The control switch module can be any type of switch circuit, as long as it meets the control function. The start signal source can be a signal output from a GPIO pin of the MCU, or other forms of start signal, as long as it can trigger the control switch module.

[0070] Specifically, such as Figure 4 As shown, the control switch module includes: a second resistor R2, a third resistor R3, and a first transistor Q2;

[0071] The second end of each first resistor R1 is connected to the first end of the first transistor Q2, and the second end of the first transistor Q2 is connected to the start signal source of the microcontroller 12; the second end of the first transistor Q2 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is connected to the control terminal of the first transistor Q2 and the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.

[0072] When the system starts up, the MCU sends a control signal through the start signal source. This signal is transmitted to the base of the first transistor Q2 through the third resistor R3. When the start signal is high, the first transistor Q2 turns on, transmitting voltage to the second terminal of the first resistor R1, thereby providing a stable voltage to the gate of the NMOS transistor.

[0073] During system startup, power supply voltage fluctuations may occur, potentially leading to unstable gate voltages in the NMOS transistors. By controlling the switching module, it can be ensured that the gate voltage is correctly controlled during system startup, preventing abnormal behavior caused by voltage fluctuations.

[0074] The first transistor Q2 acts as an enable control switch for the NMOS transistor. When the MCU does not enable the first transistor Q2, the NMOS transistor is in the off state. When a reverse power connection occurs, the VGS of the first transistor Q2 does not reach the turn-on voltage, so the first transistor Q2 is turned off, and consequently, the NMOS transistor is also turned off. The first transistor Q2 can be either a PNP transistor or a PMOS transistor.

[0075] During system startup, the MCU sends a high-level signal via a startup signal source. This signal is transmitted to the base of the first transistor Q2 through the third resistor R3. The first transistor Q2 turns on, transferring the VB voltage to the second terminal of the first resistor R1, thus providing a stable voltage to the gate of the NMOS transistor. The second resistor R2 limits the base current, protecting the first transistor Q2 from damage due to excessive current.

[0076] Under normal operating conditions, low-level transmission: When the MISO port of driver chip 13 outputs a low level (0V), the gate voltage of the NMOS transistor is approximately 12V (assuming VB is 12V), and the source (S) voltage is 0V. At this time, the Vgs voltage of the NMOS transistor is 12V, which is much greater than the turn-on voltage of the NMOS transistor (usually 2-3V), and the NMOS transistor is turned on. Therefore, the MCU receives a low-level signal.

[0077] High-level transmission: When the MISO port of driver chip 13 outputs a high level (5V), the gate (G) voltage of the NMOS transistor is still 12V, and the source (S) voltage is 5V. At this time, the Vgs voltage of the NMOS transistor is 7V, which is still greater than the turn-on voltage of the NMOS transistor, so the NMOS transistor is turned on. Therefore, the MCU receives a high-level signal.

[0078] like Figure 5 As shown, when the power supply is reversed, the gate voltage of the first transistor Q2 is close to the source voltage, which cannot meet the turn-on condition. The first transistor Q2 is turned off, and the VGS voltage of the NMOS transistor is basically 0. The NMOS transistor is also turned off. The leakage current of the reverse power supply cannot be pumped to the driver chip 13, thus achieving the function of reverse power supply protection.

[0079] The startup signal source for the microcontroller 12 can be the power supply of the microcontroller 12 board to achieve synchronous power-on.

[0080] Specifically, the second terminal of the first transistor Q2 is connected to the enable terminal of the microcontroller unit 12.

[0081] During system startup, the MCU sends a control signal via the enable pin. This signal is transmitted to the base of the first transistor Q2 through the third resistor R3. When the enable signal is high, the first transistor Q2 turns on, transmitting the VB voltage to the second terminal of the first resistor R1, thereby providing a stable voltage to the gate of the NMOS transistor. The enable pin is activated whenever the microcontroller unit 12 is powered on normally.

[0082] Specifically, each anti-reverse module 11 also includes: a fourth resistor R4;

[0083] The fourth resistor R4 is connected in parallel between the second terminal of the power switch Q1 and the control terminal of the power switch Q1.

[0084] The fourth resistor, R4, is connected in parallel between the gate and source of the NMOS transistor as a bias resistor. Its main functions include providing bias voltage and protecting the gate from electrostatic damage. It also acts as a discharge resistor to protect the gate and source.

[0085] According to the above embodiments, it further includes: an output anti-reverse unit; and an input anti-reverse unit;

[0086] The first end of the output anti-reverse unit is connected to the master device data output / slave device data input port and clock port of the microcontroller unit 12, and the second end of the output anti-reverse unit is connected to the master device data output / slave device data input port and clock port of the driver chip 13.

[0087] The first end of the input anti-reverse unit is connected to the chip select port of the microcontroller unit 12, and the second end of the input anti-reverse unit is connected to the chip select port of the driver chip 13.

[0088] The main purpose of the newly added output reverse protection unit and input reverse protection unit is to provide additional reverse power protection for the master data output / slave data input (MOSI) port, clock (SCLK) port, and chip select (CS) port between the microcontroller unit 12 (MCU) and the driver chip 13 in SPI communication. This design ensures that these critical signal lines will not be damaged in the event of reverse power connection or negative pulse, thereby improving the reliability and stability of the system.

[0089] Specifically, such as Figure 7 As shown, the output anti-reverse unit includes: the fifth resistor R5 and the sixth resistor R6; the input anti-reverse unit includes: the seventh resistor R7.

[0090] The master data output / slave data input port of the microcontroller 12 is connected to the master data output / slave data input port of the driver chip 13 through the fifth resistor R5; the clock port of the microcontroller 12 is connected to the clock port of the driver chip 13 through the sixth resistor R6; the chip select port of the microcontroller 12 is connected to the chip select port of the driver chip 13 through the seventh resistor R7.

[0091] The wire connection distance between the fifth resistor R5 and the driver chip 13 is less than the wire connection distance between the fifth resistor R5 and the microcontroller unit 12; the wire connection distance between the sixth resistor R6 and the driver chip 13 is less than the wire connection distance between the sixth resistor R6 and the microcontroller unit 12; the wire connection distance between the seventh resistor R7 and the microcontroller unit 12 is less than the wire connection distance between the seventh resistor R7 and the driver chip 13.

[0092] The fifth resistor R5 and the sixth resistor R6 limit the current through the MOSI and SCLK signal lines, preventing reverse current from damaging the MCU or driver chip 13 during reverse power connection or negative pulse. The seventh resistor R7 limits the current through the chip select (CS) signal line, preventing reverse current from damaging the MCU or driver chip 13 during reverse power connection or negative pulse.

[0093] The resistors need to be placed closer to the signal output terminal. The fifth resistor R5 and the sixth resistor R6 are closer to the driver chip 13, and the seventh resistor R7 is closer to the microcontroller unit 12. This reduces the impact of parasitic capacitance and resistance on the signal, thereby improving the signal integrity and communication reliability.

[0094] By adding a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7, the protection function for critical signal lines is further enhanced, ensuring that these signal lines will not be damaged in the event of reverse power connection or negative pulse. This design not only improves communication performance but also enhances the reliability and stability of the system.

[0095] Finally, this application also provides an electronic device including the aforementioned SPI communication power reverse connection protection circuit.

[0096] Electronic devices can be any devices that require data exchange via SPI communication, such as automotive electronic control units (ECUs), industrial control systems, and smart home devices. The SPI communication power reverse connection protection circuit includes multiple reverse connection protection modules 11. These modules 11 are connected between the master data input / slave data output ports of the microcontroller unit 12 and the master data input / slave data output ports of multiple driver chips 13. During normal operation, the power switch Q1 is turned on, and its internal resistance is low. The output signal of the driver chip 13 is transmitted to the microcontroller unit 12 through the power switch Q1, minimizing the impact on communication signal transmission. When the power supply is reversed or a negative pulse occurs, the power switch Q1 switches to the off state. The leakage current from the reverse connection cannot flow to the driver chip 13, achieving reverse connection protection and preventing the clamping diode inside the driver chip 13 from breaking down due to overcurrent, effectively protecting the driver chip 13. Meanwhile, by designing the wire connection distance between the power switch Q1 and the driver chip 13 to be smaller than the wire connection distance with the microcontroller unit 12, the parasitic capacitance between the power switch Q1 and the driver chip 13 can be effectively reduced, improving the reliability of SPI communication. The anti-reverse connection module 11 allows this circuit to be easily applied to SPI communication connections between multiple driver chips 13 and the microcontroller unit 12, resolving the conflict between high-speed SPI communication and reverse power connection protection, without requiring major modifications to the existing SPI communication architecture.

[0097] The foregoing provides a detailed description of the SPI communication power supply reverse connection protection circuit and electronic device provided by this utility model. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this utility model without departing from the principle of this utility model, and these improvements and modifications also fall within the protection scope of the claims of this utility model.

[0098] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A reverse connection protection circuit for SPI communication power supply, characterized in that, include: Multiple anti-reverse modules (11); the input terminal of each anti-reverse module (11) is connected to the master device data input / slave device data output port of the microcontroller unit (12), and the output terminal of each anti-reverse module (11) is connected to the master device data input / slave device data output port of multiple driver chips (13); The anti-reverse module (11) includes: a power switch with a body diode and a first resistor; The first end of the power switch is connected to the master device data input / slave device data output port of the microcontroller (12), the second end of the power switch is connected to the master device data input / slave device data output port of the driver chip (13), the control end of the power switch is connected to the first end of the first resistor, and the second end of the first resistor is connected to the power supply. The wire connection distance between the power switch and the driver chip (13) is less than the wire connection distance between the power switch and the microcontroller unit (12).

2. The SPI communication power supply reverse connection protection circuit according to claim 1, characterized in that, The anti-reverse module (11) further includes: a first diode; The anode of the first diode is connected to the second terminal of the power switch, and the cathode of the first diode is connected to the control terminal of the power switch.

3. The SPI communication power supply reverse connection protection circuit according to claim 1, characterized in that, Also includes: Control switch module; The input terminal of the control switch module is connected to the start signal source of the microcontroller (12), and the output terminal of the control switch module is connected to the second terminal of the first resistor of each of the anti-reverse modules (11).

4. The SPI communication power supply reverse connection protection circuit according to claim 3, characterized in that, The control switch module includes: a second resistor, a third resistor, and a first transistor; The second end of each of the first resistors is connected to the first end of the first transistor, and the second end of the first transistor is connected to the start signal source of the microcontroller (12); the second end of the first transistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the control terminal of the first transistor and the first end of the second resistor, and the second end of the second resistor is grounded.

5. The SPI communication power supply reverse connection protection circuit according to claim 4, characterized in that, The second terminal of the first transistor is connected to the enable terminal of the microcontroller unit (12).

6. The SPI communication power supply reverse connection protection circuit according to claim 1, characterized in that, Each of the aforementioned anti-reverse modules (11) further includes: a fourth resistor; The fourth resistor is connected in parallel between the second terminal of the power switch and the control terminal of the power switch.

7. The SPI communication power supply reverse connection protection circuit according to claim 1, characterized in that, Also includes: Output anti-reverse unit; Input anti-reverse unit; The first end of the output anti-reverse unit is connected to the master device data output / slave device data input port and clock port of the microcontroller unit (12), and the second end of the output anti-reverse unit is connected to the master device data output / slave device data input port and clock port of the driver chip (13). The first end of the input anti-reverse unit is connected to the chip select port of the microcontroller unit (12), and the second end of the input anti-reverse unit is connected to the chip select port of the driver chip (13).

8. The SPI communication power supply reverse connection protection circuit according to claim 7, characterized in that, The output anti-reverse unit includes: a fifth resistor and a sixth resistor; the input anti-reverse unit includes: a seventh resistor; The master data output / slave data input port of the microcontroller (12) is connected to the master data output / slave data input port of the driver chip (13) through the fifth resistor; the clock port of the microcontroller (12) is connected to the clock port of the driver chip (13) through the sixth resistor; the chip select port of the microcontroller (12) is connected to the chip select port of the driver chip (13) through the seventh resistor. The wire connection distance between the fifth resistor and the driving chip (13) is less than the wire connection distance between the fifth resistor and the microcontroller unit (12); the wire connection distance between the sixth resistor and the driving chip (13) is less than the wire connection distance between the sixth resistor and the microcontroller unit (12); the wire connection distance between the seventh resistor and the microcontroller unit (12) is less than the wire connection distance between the seventh resistor and the driving chip (13).

9. The SPI communication power supply reverse connection protection circuit according to claim 2, characterized in that, The power switch with a body diode is an NMOS transistor; The gate of the NMOS transistor is connected to the first end of the first resistor, the source of the NMOS transistor is connected to the master data input / slave data output port of the driver chip (13), and the drain of the NMOS transistor is connected to the master data input / slave data output port of the microcontroller unit (12).

10. An electronic device, characterized in that, Includes the SPI communication power reverse connection protection circuit as described in any one of claims 1-9.

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