Device for operating passive infrared sensors

Abstract

Device for operating a passive infrared detector (PIR) - wherein at least one of the terminals of the passive infrared detector (PIR) is connected by an electrical circuit arrangement (R G ) is discharged and - wherein the electrical circuit arrangement (R G ) comprises a switched capacitor circuit and - where the switched capacitor circuit comprises two strands and - where each strand comprises several transfer gates and - where each string comprises several storage capacities and - where the transfer gates are switched alternately with one of two non-overlapping clocks (ϕ1,ϕ2) and - where, apart from the non-overlapping, one measure is the inverse of the other measure and - whereby the storage capacities are designed to transport a certain amount of charge with each half cycle by one node and - wherein the respective strands are designed to be operated in a half-cycle staggered manner to cause a continuous charge discharge and - where the discharge rate depends on the input voltage.

Description

Introduction

[0001] Various methods are known for measuring infrared radiation. A key sensor principle is the use of passive infrared detectors (PIR detectors).

[0002] These are characterized by simple and cost-effective production.

[0003] Such PIR detectors are two-terminal and can be symbolized in the equivalent circuit by a current source that supplies a current I PIR depending on the change in irradiation and thus the temperature and which has a capacity C PIR connected in parallel. (See also Fig. 1.)

[0004] When evaluating the signal from a PIR sensor, various problems arise: On the one hand, the operating point of the PIR detector is shifted due to self-charging. On the other hand, the current source I PIRusually only a very low current with a relatively high internal resistance. This internal resistance R PIR is in Fig. 1. These boundary conditions result in the requirement for a large dynamic range and a very high internal resistance for the subsequent amplifier and analog-to-digital converter circuit (evaluation circuit).

[0005] However, due to the high internal resistance of an optimal evaluation circuit, charges once generated can no longer flow away. This can lead to the circuit leaving the evaluation circuit's operating range, as it is overloaded.

[0006] An object detection device is known from US 2013 / 0 082 179 A1. The object detection device of US 2013 / 0 082 179 A1 comprises: • a pyroelectric element configured to output a current signal in response to a change in an amount of infrared light; • an I / V conversion circuit including an operational amplifier, a capacitive element serving as a feedback circuit, and a discharge circuit, and configured to convert the current signal into a voltage signal; • an A / D conversion circuit configured to convert the voltage signal into a first digital signal; • a digital filter configured to extract a detection component having a frequency included in a frequency band associated with an object from a waveform represented by the first digital signal by subjecting the first digital signal to arithmetic processing, and generate a second digital signal representing a waveform of the detection component; • a judgment circuit configured to detect the target based on the second digital signal; and • a control unit configured to control the discharge circuit based on a period corresponding to a predetermined frequency not greater than a lower limit of the frequency band to discharge electric charges stored in the capacitive element.

[0007] WO 2004 / 090570 A2 discloses a sensor device for detecting a physical parameter such as radiation, temperature, or the like. The sensor device of WO 2004 / 090570 A2 comprises an analog sensor element that is sensitive to the physical parameter to be detected and outputs an analog signal. The sensor device of WO 2004 / 090570 A2 comprises an analog-to-digital converter (ADC) with a MOS input stage for receiving the analog output signal of the sensor element in order to convert the analog output signal into a digital output signal.

[0008] US 4,825,079 A discloses a pyroelectric infrared detector used, for example, in a burglar alarm system. The pyroelectric infrared detector of US 4,825,079 A has a pyroelectric element, a FET for receiving the output of the pyroelectric element, a capacitor connected in parallel with the pyroelectric element, and other circuit components. According to US 4,825,079 A, these components of the device of US 4,825,079 A are integrated into a housing.

[0009] From WO 2007 / 057 179 A2 a method for testing a passive infrared sensor is known. The sensor of WO 2007 / 057 179 A2 comprises a housing in which an infrared sensor element with two connection pins and a circuit connected to the connection pins of the infrared sensor element are arranged. The method of WO 2007 / 057 179 A2 comprises the steps of repeatedly generating and applying individual known electrical charges to one of the connection pins at a predetermined frequency per unit time and measuring the voltage between the two connection pins and indicating a failure of the passive infrared sensor if the voltage deviates from a desired voltage by more than a predetermined value. Object of the invention

[0010] The object of the invention is to provide an evaluation method and a high-impedance measuring circuit with a wide dynamic range for evaluating the signal of a PIR detector without the risk of overloading due to charging of the inputs of the PIR detector evaluation circuit. At the same time, the current consumption should be minimized.

[0011] This object is achieved by a device according to claim 1. Further embodiments are the subject of the subclaims. Description of the technical solution

[0012] The invention relates to a device for operating a passive infrared detector (PIR). According to the invention, at least one of the terminals of the passive infrared detector (PIR) is controlled by an electrical circuit arrangement (R G ) discharged. According to the invention, the electrical circuit arrangement (R G) a switched capacitor circuit. According to the invention, the switched capacitor circuit comprises two strands. Each strand comprises, according to the invention, a plurality of transfer gates and a plurality of storage capacitors. According to the invention, the transfer gates are alternately switched with one of two non-overlapping clock pulses (ϕ1, ϕ2), wherein, apart from the non-overlapping, one clock pulse is the inverse of the other clock pulse. According to the invention, the storage capacitors are configured to each transport a certain amount of charge by one node with each half-clock pulse and to be operated offset by one half-clock pulse in order to cause a continuous charge discharge. The device for operating a passive infrared detector (PIR) is configured according to the invention such that the discharge clock pulse depends on the input voltage.

[0013] In a first variant according to the invention, the equivalent resistance has a resistance value greater than 1 MOhm and / or greater than 10 MOhm and / or greater than 100 MOhm and / or greater than 1 GOhm and / or greater than 10 GOhm at least at one operating point.

[0014] In a second variant of the invention, the device according to the invention is designed to switch off the clock during measuring phases.

[0015] In a third variant according to the invention, the device for operating a passive infrared detector (PIR) is designed such that at least two of the terminals of the passive infrared detector (PIR) are discharged by an electrical circuit arrangement whose equivalent resistance in at least one operating point each has a resistance value greater than 1 MOhm and / or greater than 10 MOhm and / or greater than 100 MOhm and / or greater than 1 GOhm and / or greater than 10 GOhm.

[0016] In a fourth variant according to the invention, the device for operating a passive infrared detector (PIR) is designed such that at least one of the terminals of the passive infrared detector (PIR) is discharged by an electrical circuit arrangement whose equivalent resistance is greater at least at one operating point than at another operating point.

[0017] In a fifth variant according to the invention, the device for operating a passive infrared detector (PIR) is designed such that, firstly, the current through the switched capacitor circuit current path depends on the input voltage between the electrical connections of the passive infrared detector (PIR) and / or on the voltage between at least this electrical connection of the passive infrared detector (PIR) and a reference potential and, secondly, in a predetermined first range (A) of said voltage, the current disappears except for a leakage current and, thirdly, with increasing absolute value difference of the input voltage between the electrical connections of the passive infrared detector (PIR), the discharge current outside this range (B, C) increases and / or is greater than in said first range (A).

[0018] In a sixth variant according to the invention, the device for operating a passive infrared detector (PIR) is designed such that the average equivalent resistance of at least one electrical circuit arrangement for discharging at least one terminal of the passive infrared detector (PIR) is different at different times, wherein, since the equivalent resistance depends on the clock (ϕ1, ϕ2), the averaging of the equivalent resistance is related to several periods of this clock.

[0019] In a seventh variant of the invention, each of the outputs of said passive infrared detector (PIR) is connected to the control input of a respective associated input transistor (T1, T2).

[0020] In an eighth variant according to the invention, one contact of each of these input transistors (T1, T2) is connected to an associated current divider output I a1 , I a2 ) of a controllable current divider (MUX, RM1 to R Mn ) and the current divider (MUX, R M1 to R Mn ) divides the current of a reference current source (I ref ) depending on a control input (Val) to the current divider outputs I a1 , I a2 ) on.

[0021] In a ninth variant according to the invention, one contact of each of the transistors (T1, T2) is connected to an integrating filter and / or a capacitor (C1, C2).

[0022] In a tenth variant of the invention, the device is configured to compare the output values of these integrating filters and / or capacitors (C1, C2) with one another by at least one comparator (CP). In an eleventh variant of the invention, the device is configured to control the comparator output signal (CPO) of this comparator (CP) to control at least one digital integrating filter (Int).

[0023] In a twelfth variant of the invention, the control input (Val) of the current divider (MUX, R M1 to R Mn ), which measures the current of a reference current source (I ref ) depends directly or indirectly on the numerical value of the digital integrating filter (Int).

[0024] In a thirteenth variant according to the invention, the device comprises a differential amplifier stage, wherein the control electrode of the first transistor (T1) and the control electrode of the second transistor (T2) form the differential input of the differential amplifier stage.

[0025] In a fourteenth variant of the invention, the differential amplifier stage has a reference current source (I ref ) and a resistor (R M1 to R Mn ), whereby this resistance (R M1 to R Mn ) has a controllable tap connected to said reference current source (I ref). In this fourteenth variant of the invention, the connection of the resistor (R M , to R Mn ) is connected to a first transistor (T1) and the other terminal of the resistor (R M1 to R Mn ) is connected to a second transistor (T2). In this fourteenth variant of the invention, the control of the tap can be controlled by an external variable. In this fourteenth variant of the invention, each transistor (T1, T2) is connected by its third terminal to a load resistor (R1, R2, C1, C2, IW1, IW2), which may be a differential load resistor.

[0026] In a fifteenth variant according to the invention, the controllable resistor comprises an analog 1:(n-1) multiplexer or an analog 1:n multiplexer or an analog 1:(n+1) multiplexer (MUX), which are connected to the single output representing the tap of the controllable resistor to said reference current source (Iref), wherein the controllable resistor comprises a resistor chain of n resistors (R M1 to R Mn ) as resistance (R M , to R Mn ) and wherein each of the (n-1) nodes is connected between two of the n resistors (R M1 to R Mn ) is connected to an input / output of the analog multiplexer (MUX). In this fifteenth variant according to the invention, in the case of a 1:n multiplexer (MUX), the end or the beginning of the resistor chain consisting of the resistors (R M1 to R Mn) is connected to the multiplexer (MUX). In this fifteenth variant of the invention, in the case of a 1:(n+1) multiplexer (MUX), the end and the beginning of the resistor chain consisting of the resistors (R M1 to R Mn ) is connected to the multiplexer (MUX). In this fifteenth variant of the invention, the beginning of the resistor chain consists of the resistors (R M1 to R Mn ) with at least one first transistor (T1) and the end of the resistor chain from the resistors (R M1 to R Mn ) is connected to at least one second transistor (T2).

[0027] In the following, the technical background and the effects of the technical solutions as well as the environment of the invention are explained in more detail.

[0028] A proposed system is in Fig. 1. The passive infrared detector (PIR) is connected with its two connecting lines to a discharge network R GThis, in turn, is connected to an analog-to-digital converter (ADC). The output of the analog-to-digital converter is connected via a first bus (T) with a first bus bandwidth to a digital filter (DF), whose output Out typically has a larger second bus bandwidth than the first bus bandwidth. During the development of the proposed method for operating a passive infrared detector (PIR), it was recognized that the charging of the inputs represents a significant obstacle to correct operation of the system. As will be explained in more detail later, the proposed ΔΣ converter (ADC) is sensitive to such operating point drift. However, this increased sensitivity of the proposed ΔΣ converter (ADC) enables particularly efficient suppression of quantization errors by the comparator of the proposed ΔΣ converter (ADC).Therefore, the proposed ΔΣ converter and the discharge of the passive infrared detector via the proposed discharge network (R. G ) a proposed unit. Based on this finding of faulty charging of the inputs, the simplest solution to this problem can be achieved by discharging the input nodes by means of a switch when the voltage at the detector reaches the dynamic range. In this case, no evaluation of the voltage at the detector can be made during the discharge and shortly thereafter. Alternatively, the discharge can be prevented by a bleeder resistor between the terminals of the sensor or from the terminals to reference ground (R dis_1 , R dis_2). A significant disadvantage of this solution is the continuous attenuation of the signal and the inherent noise of the detector. Furthermore, a giga-ohm resistor cannot be implemented in low-cost CMOS technology at a reasonable cost. During development, it was recognized that discharging the second output via the internal resistance of the PIR sensor's (PIR) current source does not lead to satisfactory results. It has been shown that the resistance value of these bleeder resistors should be greater than 1 MOhm and / or preferably greater than 10 MOhm and / or preferably greater than 100 MOhm and / or preferably greater than 1 GOhm and / or preferably greater than 10 GOhm. The optimal bleeder value depends on the respective PIR detector and the respective application and should be adapted on a case-by-case basis.In the case of large charge shifts due to rapid temperature changes (temperature shock), disproportionately low leakage resistance values would be required, which would virtually eliminate the signal to be detected. It is clear that the leakage resistances of the discharge network (R G) should preferably be identical and as symmetrical as possible, in technical terms "matching". These bleeder resistors can also be more complex circuits which, among other things, also perform the function of a bleeder resistor. During the development of the proposal, it was recognized as advantageous to implement the bleeder resistors at least partially as a switched capacitor circuit. With such circuits, the relatively high-ohmic bleeder resistors that may be required can be implemented relatively easily. For the operation of such a switched capacitor network, it is particularly advantageous if these networks are operated with a non-overlapping two-phase clock. Single-phase and multi-phase clocks can of course also be used, but these are generally more complex to implement.

[0029] The requirement for reliable discharge of the PIR detector is in conflict with the highest possible input resistance of the evaluation circuit. Within the framework of the proposal, it was therefore recognized that it makes sense to make the average equivalent resistance of at least the discharge resistors of the passive infrared detector dependent on whether a measurement of the infrared radiation potential is currently being performed using the passive infrared sensor (PIR detector). Before a measurement, the discharge resistors are switched to a very high-resistance state (measurement state). After the measurement, the discharge resistors are switched to a state with a lower resistance than the measurement state.

[0030] Alternatively, the state of charge (voltage at the detector) can be measured and the size of the discharge resistors can be adjusted depending on the state of charge.

[0031] It is conceivable that other operating conditions also require switching. For example, it is conceivable to discharge the PIR detector in a controlled manner via a switch. In such a mode, switching the discharge resistors to high resistance would also be useful. In extreme cases, the measurement state could therefore mean completely disconnecting a discharge resistor.

[0032] The resistance values are always based on average values over several cycles of the operating cycle of the respective switched capacitor network, if one is used to implement the discharge resistors. Therefore, a key idea of the proposed approach is that the discharge resistors of the PIR detector assume different values depending on the states of the sensor system, whereby at least the measurement and no measurement / discharge states should be realized.

[0033] The proposed ΔΣ converter (ADC) consists, among other things, of a differential amplifier whose current source is not symmetrically divided into two branches with symmetrical control of the transistors of the differential amplifier, as is usual with normal differential amplifiers. Instead, instead of the normally present common junction point for the transistors in the branches of the differential amplifier and the operating current source, it has a current divider that divides the current differently depending on an external control value. It can be assumed that the operating current source has a finite internal resistance. In this respect, the use of a real voltage source is also possible. In the proposed device, this current divider is implemented by a resistor chain, one end of which is connected to a transistor of the differential amplifier and the other end to the other transistor of the differential amplifier.A multiplexer then connects the operating current source to a node in this resistor chain depending on the external control value. The current divider thus behaves like a digitally controlled potentiometer whose tap is adjusted by the external parameter. This sets a different current negative feedback for the various branches of the differential amplifier. The current is divided in such a way that the gate-source voltages of the transistors are adjusted by the voltage drop across the resistors of the current divider so that the total current through the two branches corresponds to the current of the operating current source. The other terminals of the transistors are each connected to a load resistor. It has proven particularly advantageous if these load resistors are implemented as real current sources, since the differential load resistance and thus the differential gain are then particularly high.

[0034] Capacitors can be connected in parallel to these load resistors to integrate the output signal. The use of Miller capacitors is also conceivable. In the case of the proposed ΔΣ converter, these capacitors perform the summing Σ function of the ΔΣ converter, thus eliminating the quantization error caused by a downstream comparator.

[0035] The following procedure is suitable for operating a passive infrared detector: Each of the outputs of the passive infrared detector is connected to the control input of a corresponding input transistor of the differential amplifier described. One contact of each of these input transistors is connected to a corresponding current divider output of a controllable current divider. The current divider distributes the current from a reference current source (I ref) to the current divider outputs depending on a control input. The other contacts of the transistors are each connected to a load resistor, preferably an integrating filter or a capacitor (C1, C2). The output values of these integrating filters, load resistors and capacitors are then compared with each other by at least one comparator. This generates an unavoidable quantization error which is minimized by the feedback described below. The comparator output signal of this comparator is connected to a digital integrating filter which performs a second integration in addition to the said capacitors. The control input of said current divider, which divides the current of an operating current source, is connected to the output of the digital integrating filter.If the current divider is controlled analogically, a digital-to-analog converter (DAC) and / or a signal format converter is required to convert the output signal of the digital integrating filter into a suitable format. However, this is not necessary in the example described here, as the multiplexer can be controlled digitally.

[0036] A similar approach may be required when adapting a digital control input for the current divider to the digital output of the digital integrating filter. In addition to this two-phase version, a single-phase version of an evaluation circuit can also be used. In this case, an output of the passive infrared detector controls at least a second current source. This second current source feeds current into a first current source (S b ). This first node (S b ) is connected via an integrating filter to the input of a comparator which determines the signal level of this first node (S b) with an internal level. The output of this comparator is again connected directly or indirectly to the aforementioned digital integrating filter and thus controls it. The output of this digital integrating filter now controls a digital-to-analog converter (DAC). The output of this digital-to-analog converter now controls a first current source (I1), which in turn also feeds its current into the first node (S b ). In contrast to the previous version, in this version, one terminal of the passive infrared detector is connected to ground, while the other terminal is connected to the previously described evaluation circuit. This type of circuit is also suitable for evaluating thermopiles.

[0037] For both methods, it is advantageous if the digital integrating filter is implemented as an up / down counter that counts at a predefined or programmable rate during measurement phases. The counting direction is preferably determined by the comparator output. The counting increment and the time intervals at which counting occurs can also be constant, predefined, or programmable. In some applications, it has proven useful to make the counting increment dependent on the counter reading itself to avoid overflow or underflow, which could result in total inoperability.

[0038] If the counter reading exceeds a critical upper value, this can be detected, for example, and cause the measuring state to be exited and the discharge state of the detector element to be activated. This is particularly useful for the one-handed version, as it is capable of measuring the absolute level of an input signal. The output of the digital integrating filter represents the measured value.

[0039] In any case, however, it is still advisable to add another digital filter (DF) downstream of the digital integrating filter before the measured value is used. This suppresses quantization errors above a certain cutoff frequency.

[0040] It can be shown that the quantization error becomes zero at a frequency of 0 Hz in the noise spectrum and tends towards a finite value for infinitely high frequencies. The cutoff frequencies depend essentially on the aforementioned load capacitances (C1, C2) and the resistance (RM ) of the current divider and can therefore be easily adjusted.

[0041] Of course, it makes sense to run essential parts of this process in a signal processor. Only the input stages would then be implemented in specially designed electronics. Such a device would then be capable of implementing the process described above.

[0042] The proposal is explained below using the attached figures: Fig. Figure 1 shows the basic blocks of a proposed passive infrared detector device. The device consists of a passive infrared detector (PIR) connected to the discharge network R GThe task of this discharge network is to eliminate charges from the PIR detector and to keep the PIR detector at a favorable operating point for the downstream analog-to-digital converter without burdening the system's dynamics. The analog-to-digital converter converts the signal from the discharge network into a first digital signal on a bus T with a first bus width (number of bits). A downstream digital filter (DF) filters the signal on the first bus T and outputs the data with greater resolution via an output bus (Out). Therefore, the output bus Out typically has a larger bus width than the first bus T. Fig. Figure 2 shows the non-claimed equivalent circuit of a passive infrared detector (PIR) with an equivalent power source (I PIR ) and a series circuit of parasitic detector capacitance (C PIR ) and associated loss resistance R PIR_Cand the internal resistance of the backup power source (R PIR ). This internal resistance of the current source (R PIR ) is parallel to the current source (I PIR ) and is typically very high. Excessive loading of the detector will therefore cause the output voltage to collapse. Fig. 3 shows a one-handed version of the analog-to-digital converter (ADC) from Fig. 1. A first controlled current source (I1) (also referred to as further current source) is controlled by the feedback path and feeds into the first node (Sb). A second controlled current source (I2) (also referred to as current source) is controlled by an output of the passive infrared detector and also feeds into the first node (S b ). The sum of the two current source currents charges a capacitance (C 1b) charges or discharges them. If the control loop is stable, the second current source (I2) supplies a current with a different sign but the same magnitude as the first current source (I1). The comparator (CP b ) is connected to its input with this capacitor (C 1b ) and compares the voltage value at this capacitor and thus at the first node (S b ) with an internal comparison value. The up / down counter (Int b ) now counts in this example with each system clock either by one up or by one down depending on whether the input of the comparator (CP b ) above or below the switching threshold of the comparator (CP b ) is located. 6 bits of the counter value of the up / down counter (Int b ) are used, for example, for feedback. In this example, these 6 bits are converted by a digital-to-analog converter (DAC) into an analog signal that controls the additional current source (I1). A digital filter (DF) filters the counter reading of the up-down counter (Int b ) to the output signal (Out), which is the output bus of the digital filter DF. Fig. 4 also shows a one-handed version of the analog-to-digital converter (ADC) from Fig. 1. However, instead of the controllable current source, the source of the reference signal is now implemented in such a way that the counter reading (Val) of the up / down counter (Int b ) now the tap (IN FB ) on a resistance cascade (R FS ) of individual resistors (not shown). This tap can then be fed to a differential transconductance amplifier, which has the current output (CS). The current outputs each charge and discharge a capacitor (C1, C2). The resulting voltages across the capacitors (C1, C2) are compared by a comparator (CP), which in turn controls the up / down counter (Int b ) controls. Fig. 5 shows a controllable current divider as part of a proposed differential stage consisting of the resistor chain of n resistors R M1 to R Mn , which are typically but not necessarily identical. Of the n+1 taps of the resistor chain in this example, an analog multiplexer (MUX) connects one of them to the operating current source (I ref ). The bus width of the control bus (Val) of the analog multiplexer (Mux) must be sufficiently wide and should typically be greater than the logarithm of n to the base 2. The current divider, the current source, and the transistors (T1, T2) form a proposed differential stage. Fig. 6 Shows the differential level Fig. 5 with two working resistors (R L1 , R L2 ). It is obvious that the current divider resistors (R M1 to R Mn) can lead to different current feedback for the two branches of the differential amplifier. This different current feedback is set by the control signal (Val). In this example, two exemplary outputs (ON, OP) are shown. Fig. 7 shows the differential level from Fig. 6 as part of a construction according to Fig. 3. Instead of the working resistors (R L1 , R L2 ) out of Fig. 6, a capacitor (C1, C2) is connected in parallel with a load resistor (R1, R2). The passive infrared sensor (PIR) is connected to the terminals IN and IP according to the Fig. 1 and Fig. 2 connected. Fig. 8 corresponds to Fig. 7 with the difference that the resistors (R1, R2) are connected by real current sources (I w1 , I w2). This has the advantage that they have an increased differential resistance. When implemented as an integrated semiconductor circuit, this design represents a solution that is robust against parametric fluctuations. The design is very simple and therefore consumes very little power. At the same time, it has a very high input resistance. Since the source terminals follow the respective gate voltages (on average) due to the negative feedback via the current divider, the gate-source voltages do not fluctuate. Therefore, the complex input impedances are very high. The gate-source capacitances do not need to be significantly recharged. The quantization noise of the analog-to-digital converter increases with the number n of resistors R Mi lower. The above-mentioned points represent significant advantages of the proposal over the state of the art. Fig. 9 shows a possible implementation of the discharge circuit R G out of Fig. 1 or the discharge resistances (R dis_1 , R dis_2 ) in Fig. 1. These resistors must have a relatively high resistance value and should typically be as equal as possible. Fig. The switch-capacitor implementation shown in Figure 9 operates with transfer gates that are alternately switched with one of two non-overlapping clock cycles (ϕ1 ϕ2). Apart from the non-overlapping nature, one clock cycle is the inverse of the other. The storage capacitors each transport a certain amount of charge one node further with each half-clock cycle. The figure shows two phases. The phases are operated offset by one half-clock cycle. This results in a continuous charge drain. If the clock cycles are switched off, which is preferably the case during the measurement phases, no more current flows. The resulting load resistance becomes high-impedance. If the discharge cycle is selected to be dependent on the input voltage, the discharge can, for example, be controlled so that it is greater for larger input voltage differences and smaller for smaller input voltage differences, and disappears within a predefined range. Fig. 10 shows another example of a discharge network R G as an active network. Transistors T3 and T4 are switched on depending on the input voltage difference between IP and IN. The differential amplifier calculates the difference at its inputs OP and ON and opens transistors T3 and T4 according to a predefined function depending on this difference. Since the characteristic curve of the transistors is non-linear, a vanishing input voltage difference between IP and IN leads to a vanishing conductance of transistors T3 and T4. Fig. 11 shows another possible implementation of a discharge network R GA first current source supplies half of the current I to MOS diodes T9 and T14. The current through MOS diode T14 is reduced by T13. The current through MOS diode T9 is reduced by T11. A second current source supplies a current that is typically 80% of the value of the first current source. Since the transistor T11 forms a current mirror with the MOS diode T12 and the transistor T13 forms a current mirror with the same MOS diode T12, an offset current typically related to 80% of the current I is attracted by the currents through T9 and T14, respectively. If the inputs IP and IN are biased unequally, this leads to an unbalanced current distribution through the differential stage consisting of T5 and T6. This then manifests itself in the fact that additional current can flow through the MOS diodes T9 or T14, which leads to the opening of transistors T7 and T15 or T8 and T16 and thus to a discharge of the input nodes IP and IN. Fig. 12 shows an exemplary discharge resistance characteristic of a circuit according to Fig. 11. By appropriately selecting the current mirror and transistor ratios, it is possible to achieve that the characteristic curve of the input resistance has an extremely high-ohmic region A in which the input resistance is practically only determined by the leakage current of the circuit and a region B in which voltage limitation occurs and a region C in which the input resistance is very low-ohmic.

[0043] The two terminals are thus discharged through this electrical circuit arrangement, the equivalent resistance of which is significantly greater at an operating point in region A than at an operating point in regions B or C.

[0044] This allows a passive infrared detector to be operated in such a way that the electrical connections are discharged through a current path when the voltage lies outside a predetermined range A. The discharge current through this circuit depends on the input voltage between the electrical connections IP and IN. In the range A of the input voltage specified by the dimensions, the discharge current disappears except for the leakage current of the transistors. The discharge current increases with increasing difference in the input voltage outside this range A. The input resistance RIN(IP-IN) depends on the differential voltage V(IP-IN) between the inputs IP and IN of the network R GThe input resistance considered here can be assumed to be located between the terminals IP and IN as well as between a terminal IP or IN on the one hand and the reference potential, for example ground, on the other. The behavior in Fig. 12 should preferably be similar in each of these two cases. List of reference symbols A voltage range in which the discharge network is high-resistance ADC Analog to Digital Converter B Voltage range in which the discharge network has a medium conductivity C Voltage range in which the discharge network has a higher conductivity C1 First Capacity C 1b First integrating filter (third capacity) C2 Second capacity CP comparator CP b Comparator CPO comparator output C PIRParasitic capacitance of the PIR sensor PIR CS Current output of the differential transconductance amplifier DAC digital-to-analog converter DF Downstream digital filter I1 Additional power source I2 current source I a1 First current divider output I a2 Second current divider output IN First connection for the PIR sensor Int integrating filter (in the simplest case an up / down counter) Int b Integrating filter (in the simplest case an up / down counter) IN Second connection for the PIR sensor IN FB Tapping on a resistor cascade (R FB ) from individual resistors I PIR Current source of the PIR sensor equivalent circuit I ref Reference current source IW1 First current source used as a load resistor IW2 Second current source used as a load resistor MUX Analog 1:(n-1) or 1:n or 1:(n+1) multiplexer. n preferably has a value greater than three and / or 4. Values of n=(2 m -2) with m>2 or m>3. In this example, m=6 is chosen. ON First output of the differential stage OP Second output of the differential stage Out output bus of the digital filter DF (=downstream filter DF) ϕ1 First clock of the SC network to form a discharge resistor ϕ2 Second clock of the SC network for forming a discharge resistor. This clock is essentially inverse to ϕ1 and does not overlap with ϕ1. PIR PIR sensor R1 First working resistor R2 Second working resistor R dis_1This is the first unfavorable discharge resistance in the prior art. This leads to a load on the output IP and a reduction in the output signal. In the proposed device, this resistance is modulated. R dis_2 A second disadvantageous discharge resistance in the prior art. This leads to a load on the IN output and a reduction in the output signal. In the proposed device, this resistance is modulated. R FB Resistor cascade of individual resistors. A control signal (Val) controls the tap of the output signal IN FB . The resistor cascade behaves like a potentiometer controlled by the variable Val. Its implementation is similar to the current divider consisting of the multiplexer MUX and the resistor cascade R. M1 to R Mn . R GDischarge network. This discharge network prevents the PIR sensor from charging against ground and the PIR sensor terminals from charging against each other. RIN(IP-IN) Input resistance of the network R dependent on the differential voltage V(IP-IN) between the inputs IP and IN G The input resistance can be assumed to be located between the terminals IP and IN as well as between a terminal IP or IN on the one hand and the reference potential, for example ground, on the other hand. The behavior in Fig. 12 should preferably be similar in each of these two cases. R L1 First working resistance R L2 Second working resistor R M Resistance of the current divider. This is the sum value of the resistor chain R M1 to R Mn from n resistors. R M1 to R MnResistances of the resistor chain consisting of n resistors of the current part of the proposed differential stage R PIR Internal resistance of the PIR sensor PIR, which is parallel to the outputs of the PIR sensor (see Fig. 1) R PIR_C Series resistance of the parasitic capacitance C PIR . S b First node T ADC output with typically smaller bit width than the bus out T1 First transistor of the differential stage T2 Second transistor of the differential stage T3 Third transistor T4 Fourth transistor T5 to T16 transistors of an exemplary further discharge network. Val control input of the multiplexer MUX V(IP-IN) Voltage between the outputs of the PIR sensor and thus between the inputs of the discharge network R G V ref Reference voltage

Claims

[1] Device for operating a passive infrared detector (PIR) - wherein at least one of the terminals of the passive infrared detector (PIR) is connected by an electrical circuit arrangement (R G ) is discharged and - wherein the electrical circuit arrangement (R G ) comprises a switched capacitor circuit and - where the switched capacitor circuit comprises two strands and - where each strand comprises several transfer gates and - where each strand comprises several storage capacities and - where the transfer gates are switched alternately with one of two non-overlapping clocks (ϕ1,ϕ2) and - where, apart from the non-overlapping, one measure is the inverse of the other measure and - whereby the storage capacities are designed to transport a certain amount of charge with each half cycle by one node and - wherein the respective strands are designed to be operated in a half-cycle staggered manner to cause a continuous discharge of charge and - where the discharge rate depends on the input voltage. [2] Apparatus for operating a passive infrared detector (PIR) according to claim 1. - wherein the equivalent resistance of the electrical circuit arrangement (RG) has a resistance value greater than 1 MOhm and / or greater than 10 MOhm and / or greater than 100 MOhm and / or greater than 1 GOhm and / or greater than 10 GOhm at least at one operating point [3] Device for operating a passive infrared detector (PIR) according to claim 1 or 2, - wherein the device is designed to switch off the clock during measuring phases. [4] Apparatus for operating a passive infrared detector (PIR) according to claim 1, wherein - at least two of the terminals of the passive infrared detector (PIR) are connected by the electrical circuit arrangement (R G ) whose equivalent resistance in at least one operating point has a resistance value greater than 1 MOhm and / or greater than 10 MOhm and / or greater than 100 MOhm and / or greater than 1 GOhm and / or greater than 10 GOhm. [5] Device for operating a passive infrared detector (PIR) according to one of the preceding claims, wherein - at least one of the terminals of the passive infrared detector (PIR) is connected to the electrical circuit arrangement (R G ) whose equivalent resistance is greater at least at one operating point than at another operating point. [6] Device for operating a passive infrared detector (PIR) according to one of the preceding claims, - wherein the current through the switched capacitor circuit depends on the input voltage between the electrical terminals of the passive infrared detector (PIR) and / or on the voltage between at least this electrical terminal of the passive infrared detector (PIR) and a reference potential, and - wherein in a predetermined first range (A) of said voltage the current disappears except for a leakage current and - wherein the discharge current increases with increasing difference in the input voltage between the electrical terminals of the passive infrared detector (PIR) outside this area (B, C) and / or is greater than in said first area (A). [7] Device for operating a passive infrared detector (PIR) according to one of claims 1 to 6, wherein - the average equivalent resistance of the electrical circuit arrangement (R G) to discharge at least one terminal of the passive infrared detector (PIR) is different at different times and - where, since the equivalent resistance depends on the clock (ϕ1, ϕ2), the averaging of the equivalent resistance is related to several periods of this clock. [8] Device for operating a passive infrared detector (PIR) according to one of the preceding claims - wherein each of the outputs of said passive infrared detector (PIR) is connected to the control input of a respective associated input transistor (T1, T2). [9] Device for operating a passive infrared detector (PIR) according to the preceding claim, - wherein one contact of each of these input transistors (T1, T2) is connected to an associated current divider output I a1 , I a2 ) of a controllable current divider (MUX, R M1 to R Mn ) and - where the said current divider (MUX, R M1 to R Mn ) the current of a reference current source (I ref ) depending on a control input (Val) to the current divider outputs I a1 , I a2 ) is divided. [10] Device for operating a passive infrared detector (PIR) according to one of the two preceding claims, - wherein each contact of the transistors (T1, T2) is connected to an integrating filter and / or a capacitor (C1, C2). [11] Device for operating a passive infrared detector (PIR) according to the preceding claim, - wherein the device is arranged such that the output values of these integrating filters and / or capacitances (C1, C2) are compared with each other by at least one comparator (CP). [12] Device for operating a passive infrared detector (PIR) according to the preceding claim, - wherein the device is arranged such that the comparator output signal (CPO) of this comparator (CP) controls at least one digital integrating filter (Int). [13] Apparatus for operating a passive infrared detector (PIR) according to the preceding claim and claim 9, - where the control input (Val) of the current divider (MUX, R M1 to R Mn ), which determines the current of the reference current source (I ref ) depends directly or indirectly on the numerical value of the digital integrating filter (Int). [14] Apparatus for operating a passive infrared detector (PIR) according to any one of the preceding claims and claim 8, - comprising a differential amplifier stage and - wherein the control electrode of the first transistor (T1) and the control electrode of the second transistor (T2) form the differential input of the differential amplifier stage. [15] Device according to the preceding claim, - wherein the differential amplifier stage comprises a reference current source (I ref ) and - a resistor (R M1 to R Mn ) and - where this resistance (R M1 to R Mn ) has a controllable tap connected to said reference current source (I ref ) and - where one terminal of the resistor (R M , to R Mn ) is connected to the first transistor (T1) and the other terminal of the resistor (R M , to R Mn ) is connected to the second transistor (T2) and - where the control of the tap is controllable by an external variable and - wherein each transistor (T1, T2) is connected by its third terminal to a load resistor (R1, R2, C1, C2, IW1, IW2), which may be a differential load resistor. [16] Device according to the preceding claim, - wherein the controllable resistor comprises an analog 1:(n-1) multiplexer or an analog 1:n multiplexer, or an analog 1:(n+1) multiplexer (MUX) connected to the single output representing the tap of the controllable resistor with said reference current source (Iref) and - where the controllable resistor is a resistor chain of n resistors (R M1 to R Mn ) as resistance (R M , to R Mn ) and - where each of the (n-1) nodes is connected between two of the n resistors (R M1 to R Mn ) is connected to an input / output of the analog multiplexer (MUX) and - where in the case of a 1:n multiplexer (MUX) the end or the beginning of the resistor chain from the resistors (R M1 to R Mn ) is connected to the multiplexer (MUX) and - where in the case of a 1:(n+1) multiplexer (MUX) the end and the beginning of the resistor chain are additionally determined from the resistors (R M1 to R Mn ) are connected to the multiplexer (MUX) and - where the beginning of the resistance chain consists of the resistors (R M1 to R Mn ) is connected to at least the first transistor (T1) and - the end of the resistance chain consisting of resistors (R M1 to R Mn ) is connected to at least the second transistor (T2).

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