Switched capacitor circuit

Abstract

To provide a switched capacitor circuit capable of providing a common mode feedback circuit so as not to fluctuate an output potential of an operational amplifier as much as possible.SOLUTION: A control circuit 12 turns on a first switch group Sf1y and a fourth switch group Sf1x in synchronization with a first common control signal Φ1dcmfb provided depending on a first control signal Φ1din, and turns on a second switch group Sf2x and a third switch group Sf2y in synchronization with a second common control signal Φ2dcmfb provided depending on a second control signal Φ2din. At this time, in the first common control signal Φ1dcmfb and the second common control signal Φ2dcmfb, a sum connection capacitance value connecting the output of a first operational amplifier OP1 and any of first capacitors Caa and Cab, second capacitors Cba and Cbb, and third capacitors Cca and Ccb of a common mode feedback circuit CMFB1 is equal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to switched capacitor circuits. [Background technology]

[0002] For example, Patent Document 1 discloses a device that includes an amplifier that amplifies an analog signal in proportion to the ratio between the first and second capacitances of a capacitive differential circuit to provide the analog signal, and provides a technology for integrating the analog signal amplified by the amplifier with an integrator. Patent Document 2 also discloses an example of a device that generates a digital output signal based on an analog differential signal amplified by a capacitive differential amplifier circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,158,335 [Patent Document 2] U.S. Patent No. 10,135,459 Summary of the Invention [Problem to be solved by the invention]

[0004] According to conventional technology, when the common mode feedback circuit is switched by a switch, the switch connection seen from the output side of the operational amplifier changes, so the capacitance value seen from the common mode feedback circuit side changes within one cycle, making the output potential of the operational amplifier more likely to fluctuate.

[0005] An object of the present disclosure is to provide a switched capacitor circuit in which a common mode feedback circuit can be provided so as to minimize fluctuations in the output potential of an operational amplifier. [Means for solving the problem]

[0006] The invention of claim 1 comprises a main circuit section having a sampling capacitor and a first operational amplifier, a common mode feedback circuit, and a control circuit. The sampling capacitor of the main circuit section samples the input signal when the input chopping switch is turned on by different first and second control signals.

[0007] The common mode feedback circuit includes a first capacitor connected between the output of the first operational amplifier and a bias current potential (Vbias) of the first operational amplifier, a second capacitor connected in parallel to the first capacitor via a first switch group, a third capacitor connected in parallel to the first capacitor via a second switch group, and a third switch group and a fourth switch group that apply an output common mode reference potential (Vref) and a bias current reference potential (Vbias_ref) of the first operational amplifier to the second capacitor and the third capacitor, respectively.

[0008] The control circuit turns on the first switch group and the fourth switch group in synchronization with a first common control signal that is set depending on the first control signal, and turns on the second switch group and the third switch group in synchronization with a second common control signal that is set depending on the second control signal. At this time, the control circuit is configured so that the total connection capacitance value connecting the output of the first operational amplifier and any of the first capacitor, second capacitor, and third capacitor of the common mode feedback circuit is equal in the first common phase and the second common phase.

[0009] According to the invention described in claim 1, the total connected capacitance value on the common mode feedback circuit side as seen from the output side of the first operational amplifier can be made equal in both the phase when the first common control signal is on and the phase when the second common control signal is on, thereby eliminating errors caused by asymmetry between the respective phases. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is an electrical configuration diagram of a common mode feedback circuit according to a first embodiment; [Figure 2] Electrical configuration diagram of a switched capacitor circuit in the first embodiment [Figure 3] Timing chart of control signals given to switches in the first embodiment [Figure 4] Electrical configuration diagram of a common mode feedback circuit in a comparative example [Figure 5] FIG. 10 is a diagram showing the relationship between the operating frequencies of the circuit stages in the second embodiment. [Figure 6] FIG. 10 is an explanatory diagram of the operation of the common mode feedback circuit according to the second embodiment; [Figure 7] Relationship diagram of operating frequencies of each circuit stage in the comparative example [Figure 8] 1 is a diagram illustrating the operation of a common mode feedback circuit according to a comparative example; [Figure 9] Electrical configuration diagram of a switched capacitor circuit according to a third embodiment [Figure 10] FIG. 10 is an electrical configuration diagram of a common-mode feedback circuit of a second operational amplifier according to the third embodiment. [Figure 11] 10 is a timing chart showing the outline of changes in signals at various parts in the third embodiment; [Figure 12] A diagram showing the correspondence between control signals given to each switch in the third embodiment. [Figure 13] Electrical configuration diagram of a switched capacitor circuit according to a fourth embodiment [Figure 14] A diagram showing the correspondence between control signals given to each switch in the fourth embodiment. [Figure 15] 10 is a timing chart showing the outline of changes in signals at various parts in the fourth embodiment; [Figure 16] Electrical configuration diagram of a switched capacitor circuit according to a fifth embodiment [Figure 17] A diagram showing the correspondence between control signals given to each switch in the fifth embodiment. [Figure 18] 10 is a timing chart showing the outline of changes in signals at various parts in the fifth embodiment; [Figure 19] 10 is a timing chart showing the outline of changes in signals at various parts in the sixth embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0011] Several embodiments of switched-capacitor circuits will be described below with reference to the drawings. In each embodiment, substantially identical or similar parts are designated by the same or similar reference numerals, and descriptions thereof will be omitted as necessary. Each embodiment will focus on the characteristic parts. In addition, the following embodiments will be described using a differential circuit, and circuit components having a symmetrical differential configuration are illustrated with suffixes a and b. As necessary, supplementary suffixes, such as (S1a, S1b), will be added in parentheses, or the suffixes a and b will be omitted.

[0012] (First embodiment) The first embodiment will be described with reference to Fig. 1 to Fig. 4. As shown in Fig. 2, a switched capacitor circuit 10 includes a capacitively coupled amplifier 11 and a control circuit 12. The control circuit 12 is configured by a microcomputer or a logic circuit, and is a circuit that outputs control signals to switches S1 (S1a, S1b) and S2 (S2a, S2b) that configure the switched capacitor circuit 10 to turn them on and off. The switches S1 (S1a, S1b) and S2 (S2a, S2b) configure an input chopping switch 170.

[0013] The capacitively coupled amplifier 11, which serves as the main circuit, is primarily composed of a fully differential first operational amplifier OP1. A parallel circuit of resistors R1 (R1a, R1b) and feedback capacitors C3 (C3a, C3b) is connected between the input and output of the first operational amplifier OP1. The resistors R1 (R1a, R1b) are provided to determine the input voltage of the first operational amplifier OP1. Capacitors C1 (C1a, C1b), which serve as sampling capacitances, are connected between input terminals Ina, Inb and the inverting and non-inverting input terminals of the first operational amplifier OP1, respectively. Differential analog input signals Vinp, Vinm are input to the capacitively coupled amplifier 11 via the input terminals Ina, Inb. A voltage of approximately Vinp-Vinm = ±100 mV is applied.

[0014] Switches S1a and S2b are connected between the input terminal Ina and the inverting input terminal and non-inverting input terminal of the first operational amplifier OP1, respectively. Switches S2a and S1b are connected between the input terminal Inb and the inverting input terminal and non-inverting input terminal of the first operational amplifier OP1, respectively. The control circuit 12 turns the input chopping switch 170 on and off, thereby inverting the polarity of the analog input signals Vinp and Vinm and inputting them to the first operational amplifier OP1. The switches S1a, S1b, S2a, and S2b are connected between the input of the capacitive coupling amplifier 11 and the capacitors C3a and C3b. Note that no switches are connected between the input and output of the first operational amplifier OP1.

[0015] The sampling capacitors C1 (C1a, C1b) sample the analog input signals Vinp and Vinm by turning on the switches S1 (S1a, S1b) and S2 (S2a, S2b) with different first and second control signals Φ1din and Φ2din. In the example shown in Fig. 3, the control circuit 12 turns on the switches S1 (S1a, S1b) with the first control signal Φ1din and turns on the switches S2 (S2a, S2b) with the second control signal Φ2din.

[0016] 1, the capacitively coupled amplifier 11 includes a first common-mode feedback circuit CMFB1 at the output of a first operational amplifier OP1. The first common-mode feedback circuit CMFB1 includes a first capacitor Ca (Caa, Cab), a second capacitor Cb (Cba, Cbb), a third capacitor Cc (Cca, Ccb), a first switch group Sf1y, a second switch group Sf2x, a third switch group Sf2y, and a fourth switch group Sf1x.

[0017] The first capacitor Ca (Caa, Cab) is connected between the output of the first operational amplifier OP1 and a supply node of a bias current potential Vbias of the first operational amplifier OP1. The second capacitor Cb (Cba, Cbb) is connected in parallel to the first capacitor Ca (Caa, Cab) via a first switch group Sf1y. The third capacitor Cc (Cca, Ccb) is connected in parallel to the first capacitor Ca (Caa, Cab) via a second switch group Sf2x.

[0018] The third switch group Sf2y applies the output common-mode reference potential Vref and the reference potential Vbias_ref for the bias current of the first operational amplifier OP1 to the second capacitors Cb (Cba, Cbb) when turned on by the control circuit 12. The fourth switch group Sf1x applies the output common-mode reference potential Vref and the reference potential Vbias_ref for the bias current of the first operational amplifier OP1 to the third capacitors Cc (Cca, Ccb) when turned on by the control circuit 12.

[0019] The control circuit 12 turns on the first switch group Sf1y and the fourth switch group Sf1x in synchronization with the first common control signal Φ1dcmfb, which is set depending on the first control signal Φ1din. Here, the first control signal Φ1din and the first common control signal Φ1dcmfb are assumed to be dependent on each other, but as shown in Fig. 3, they may be the same control signal, or the first common control signal Φ1dcmfb may have a frequency half or twice that of the first control signal Φ1din. In this case, synchronization is sufficient.

[0020] The control circuit 12 turns on the second switch group Sf2x and the third switch group Sf2y in synchronization with the second common control signal Φ2dcmfb, which is set depending on the second control signal Φ2din. Here, the second control signal Φ2din and the second common control signal Φ2dcmfb are also considered to be dependent on each other, but they may be the same control signal as shown in Figure 3, or the second common control signal Φ2dcmfb may have a frequency half or twice that of the second control signal Φ2din. In this case, synchronization is sufficient.

[0021] As a representative example, the operation of the capacitive coupling amplifier 11 will be described when the first control signal Φ1din and the first common control signal Φ1dcmfb are the same control signal, and the second control signal Φ2din and the second common control signal Φ2dcmfb are the same control signal, as shown in FIG. 3.

[0022] <First control signal Φ1din and first common control signal Φ1dcmfb are on> 3, when the control circuit 12 turns on the first control signal Φ1din, it also turns on the first common control signal Φ1dcmfb. At this time, the switches S1 (S1a, S1b) are turned on, and the analog input signals Vinp and Vinm are sampled by the sampling capacitors C1 (C1a, C1b).

[0023] 1 is turned on while the second switch group Sf2x and the third switch group Sf2y are turned off, the first capacitors Ca (Caa, Cab) and the second capacitors Cb (Cba, Cbb) are connected in parallel, and charge distribution is performed. As will be described later, when the second control signal Φ2din is on, a constant difference voltage between the bias current reference potential Vbias_ref and the output common-mode reference potential Vref is applied to the second capacitors Cb (Cba, Cbb).

[0024] Therefore, when the first control signal Φ1din is turned on, charge distribution occurs, causing the bias current potential Vbias to approach the bias current reference potential Vbias_ref, and the output common mode of the first operational amplifier OP1 to approach the output common mode reference potential Vref. Also, because the fourth switch group Sf1x is turned on, the difference voltage between the bias current reference potential Vbias_ref and the output common mode reference potential Vref is applied to the third capacitor Cc (Cca, Ccb). This stabilizes the voltage across each terminal of the third capacitor Cc (Cca, Ccb).

[0025] <Second control signal Φ2din and second common control signal Φ2dcmfb are both on> 3, when the control circuit 12 turns on the second control signal Φ2din, it also turns on the second common control signal Φ2dcmfb. At this time, the switch S2 (S2a, S2b) turns on, drawing charge from the sampling capacitor C1 (C1a, C1b) to the input terminals Ina, Inb. As a result, charge transfer occurs, and the analog input signals Vinp, Vinm are amplified by the action of the first operational amplifier OP1, resistors R1 (R1a, R1b), and feedback capacitor C3 (C3a, C3b).

[0026] At the same time, the third switch group Sf2y shown in FIG. 1 is turned on while the fourth switch group Sf1x and the first switch group Sf1y are turned off, so that the first capacitor Ca (Caa, Cab) and the third capacitor Cc (Cca, Ccb) are connected in parallel, and charge distribution is performed. As described above, when the first control signal Φ1din is on, a constant difference voltage between the bias current reference potential Vbias_ref and the output common-mode reference potential Vref is applied to the third capacitor Cc (Cca, Ccb). Therefore, when the second control signal Φ2din is on, charge distribution is performed, and the bias current potential Vbias approaches the bias current reference potential Vbias_ref, and the output common-mode of the first operational amplifier OP1 approaches the output common-mode reference potential Vref. Furthermore, because the third switch group Sf2y is turned on, the difference voltage between the bias current reference potential Vbias_ref and the output common-mode reference potential Vref is applied to the second capacitor Cb (Cba, Cbb). This stabilizes the voltage across each of the second capacitors Cb (Cba, Cbb).

[0027] The first phase in which the first control signal Φ1din is ON and the second phase in which the second control signal Φ2din is ON are repeated. In this case, even if the connection states of the switch groups Sf1y, Sf2x, Sf2y, and Sf1x are changed in the first common phase in which the first common control signal Φ1dcmfb is ON and the second common phase in which the second common control signal Φ2dcmfb is ON, the connection configurations of the first capacitor Ca (Caa, Cab), second capacitor Cb (Cba, Cbb), and third capacitor Cc (Cca, Ccb) when viewed from the output side of the first operational amplifier OP1 remain the same.

[0028] Therefore, when the first common control signal Φ1dcmfb is on and when the second common control signal Φ2dcmfb is on, the total connected capacitance value connecting the output of the first operational amplifier OP1 to any of the first capacitor Ca (Caa, Cab), second capacitor Cb (Cba, Cbb), and third capacitor Cc (Cca, Ccb) of the first common mode feedback circuit CMFB1 is equal. As a result, when the capacitively coupled amplifier 11 amplifies the input signals Vinp and Vinm, the capacitance value on the output side of the first operational amplifier OP1 can be kept unchanged both in the phase when the first control signal Φ1din is on and in the phase when the second control signal Φ2din is on, and errors caused by asymmetry between the respective phases can be eliminated.

[0029] Figure 4 shows a common-mode feedback circuit CMFBb as a comparative example. As shown in Figure 4, when the third capacitor Cc (Cca, Ccb) is connected to only one side of the first capacitor Ca (Caa, Cab), the first phase when the first control signal Φ1din is on and the second phase when the second control signal Φ2din is on are repeated, causing the total capacitance value seen from the output side of the first operational amplifier OP1 to differ between the first phase and the second phase, resulting in an imbalance. As a result, there is an effect of errors caused by the asymmetry between the phases.

[0030] According to the configuration of this embodiment, the total connection capacitance value connecting the output of the first operational amplifier OP1 and any of the first capacitor Ca (Caa, Cab), second capacitor Cb (Cba, Cbb), and third capacitor Cc (Cca, Ccb) of the first common mode feedback circuit CMFB1 is configured to be equal in the first common phase when the first common control signal Φ1dcmfb is on and in the second common phase when the second common control signal Φ2dcmfb is on, thereby eliminating errors caused by asymmetry between the respective phases.

[0031] (Second embodiment) The second embodiment will be described with reference to FIGS. 5 to 8. As shown in FIG. 5, an integrator 13 is connected to the rear stage of a capacitively coupled amplifier 11. The integrator 13 is a switched-capacitor integrator and is configured by combining a second operational amplifier OP2 with a switch and a capacitor (not shown). A second common-mode feedback circuit CMFB2 having the same configuration as the first common-mode feedback circuit CMFB1 described above is connected to the output of the second operational amplifier OP2 that constitutes the integrator 13. The second common-mode feedback circuit CMFB2 has the same configuration as that shown in FIG. 10 described in the third embodiment, but its description will be omitted here.

[0032] The capacitively coupled amplifier 11 amplifies the analog input signals Vinp and Vinm by charging and discharging the capacitors C1 and C3 as the input chopping switch 170 turns on and off at a frequency Fs / 2 that is half the reference frequency Fs. At this time, the integrator 13 is also configured to integrate the output of the capacitively coupled amplifier 11 by charging and discharging the capacitors as the component switch (not shown) turns on and off at the reference frequency Fs.

[0033] When the switched capacitor of integrator 13 is charging and discharging to perform integration, operating the first common-mode feedback circuit CMFB1 and the second common-mode feedback circuit CMFB2 would fluctuate the output potential of the first operational amplifier OP1 and the second operational amplifier OP2, which is undesirable. Therefore, control circuit 12 controls so that at least the common-mode feedback circuits CMFB1 and CMFB2 do not operate during integration period Ts, when the output of capacitively coupled amplifier 11 is integrated by integrator 13. Specifically, for example, when operating integrator 13 using a clock signal with reference frequency Fs, control circuit 12 operates the common-mode feedback circuits CMFB1 and CMFB2 using a clock signal with a frequency Fs / 2, which is half the reference frequency Fs.

[0034] 6, during the integration period Ts, the first common control signal Φ1dcmfb and the second common control signal Φ2dcmfb do not change, and none of the switch groups Sf1y, Sf2x, Sf2y, and Sf1x are switching. As a result, the first common mode feedback circuit CMFB1 and the second common mode feedback circuit CMFB2 do not operate at the timing when the integrator 13 performs integration processing, so integration processing can be performed with as little fluctuation as possible in the output common potentials of the first operational amplifier OP1 and the second operational amplifier OP2.

[0035] The control circuit 12 allows the common-mode feedback circuits CMFB1 and CMFB2 to operate during periods other than the integration period Ts because, outside the integration period Ts, fluctuations in the output potential of the second operational amplifier OP2 do not affect the integration result.

[0036] A comparative example is shown in Fig. 7, and its operation is shown in Fig. 8. When the capacitive coupling amplifier 11, the integrator 13, and the common mode feedback circuits CMFB1 and CMFB2 are operated at the same frequency as shown in Fig. 7, the first common control signal Φ1dcmfb changes from on to off and the second common control signal Φ2dcmfb changes from off to on during the charge transfer for the integration period Ts that is accumulated by the integrator 13, as shown in Fig. 8 (see the arrows in Fig. 8).

[0037] In this case, the common mode feedback circuits CMFB1 and CMFB2 operate during the integration period Ts, which causes fluctuations in the output potentials of the first operational amplifier OP1 and the second operational amplifier OP2, potentially preventing accurate integration.In contrast, in this embodiment, the second common mode feedback circuit CMFB2 does not operate during the integration period Ts, which allows for more accurate charge transfer and accurate integration results.

[0038] For example, the control circuit 12 may operate the capacitive coupling amplifier 11 using a clock signal with a reference frequency Fs. Alternatively, the first common mode feedback circuit CMFB1 may operate at a frequency Fs / 2 that is half the reference frequency Fs, and the second common mode feedback circuit CMFB2 may operate at a frequency Fs / 2 that is half the reference frequency Fs.

[0039] (Third embodiment) The third embodiment will be described with reference to Figures 9 to 12. From the third embodiment onwards, more specific examples of the first or second embodiment will be described. The same functional parts as those in the first and second embodiments will be given the same reference numerals and their description will be omitted, and the description will focus on the different parts.

[0040] 9 shows a schematic configuration of the ΔΣ modulator 15. The ΔΣ modulator 15 is a switched capacitor circuit including a capacitively coupled amplifier 11, a control circuit 12, a first integrator 13, and a second integrator 14. A quantizer 16 is provided at the output stage of the second integrator 14, and the ΔΣ modulator 15 is configured to feed back the output of the quantizer 16 to the first integrator 13 via D / A converters 20a and 20b, and also to the second integrator 14 via D / A converters 220a and 220b.

[0041] Control circuit 12 outputs control signals to each of capacitively coupled amplifier 11, first integrator 13, second integrator 14, quantizer 16, and D / A converters 20a, 20b, 220a, and 220b. Differential input signals Vinp and Vinm are input to capacitively coupled amplifier 11 via input terminals Ina and Inb. As described in the previous embodiments, switches S1a, S1b, S2a, and S2b are configured as input chopping switch 170 at the input of capacitively coupled amplifier 11. As described in the first embodiment, capacitively coupled amplifier 11 amplifies differential input signals Vinp and Vinm. At this time, capacitively coupled amplifier 11 charges and discharges capacitors C1 and C3 by turning input chopping switch 170 on and off at a frequency Fs / 2 that is half the reference frequency Fs, thereby amplifying input signals Vinp and Vinm. Furthermore, the operational amplifier OP1 of the capacitive coupling amplifier 11 is connected to a first common mode feedback circuit CMFB1 that operates at a frequency Fs / 2 that is half the reference frequency Fs.

[0042] A first integrator 13 is configured in the subsequent stage of the capacitively coupled amplifier 11. A first output chopping switch 171 is connected between the capacitively coupled amplifier 11 and the integrator 13. A second output chopping switch 172 is connected between the first output chopping switch 171 and the input of the integrator 13. The first output chopping switch 171 and the second output chopping switch 172 are switches that switch the output polarity of the capacitively coupled amplifier 11 between normal and inverted.

[0043] The first integrator 13 is configured as a correlated double sampling (CDS) type including a second fully differential operational amplifier OP2, a series circuit of feedback capacitors C5a and C5b and feedback switches S10a and S10b connected between the input and output of the second operational amplifier OP2, and reset switches S9a and S9b connecting the input and output of the second operational amplifier OP2. The capacitors C5a and C5b can be switched between charging and discharging using the switches S10a and S10b.

[0044] 10, the first integrator 13 includes a second common-mode feedback circuit CMFB2 at the output of the second operational amplifier OP2. The second common-mode feedback circuit CMFB2 includes fourth capacitors Cda and Cdb connected between the output of the second operational amplifier OP2 and a bias current potential Vbias of the second operational amplifier OP2, and fifth capacitors Cea and Ceb connected in parallel to the fourth capacitors Cda and Cdb via a fifth switch group Sf3y.

[0045] The second common mode feedback circuit CMFB2 includes sixth capacitors Cfa and Cfb connected in parallel to the fourth capacitors Cda and Cdb via a sixth switch group Sf4x. The second common mode feedback circuit CMFB2 includes a seventh switch group Sf4y and an eighth switch group Sf3x that apply the output common mode reference potential Vref and the reference potential Vbias_ref for the bias current of the second operational amplifier OP2 to the fifth capacitors Cea and Ceb and the sixth capacitors Cfa and Cfb, respectively.

[0046] When the control circuit 12 operates the first integrator 13 using a clock signal of the reference frequency Fs, it operates the second common mode feedback circuit CMFB2 of the first integrator 13 using a clock signal of a frequency Fs / 2 that is half the reference frequency Fs. Here, the second common mode feedback circuit CMFB2 of the first integrator 13 is operated using a clock signal of a frequency Fs / 2 that is half the reference frequency Fs, but it may also be operated using a clock signal of the reference frequency Fs.

[0047] The output of the first integrator 13 is input to the second integrator 14. The second integrator 14 is also mainly composed of a fully differential third operational amplifier OP3. The output of the second operational amplifier OP2 is connected to the input of the third operational amplifier OP3 via capacitors C6a and C6b. In addition, switches S11a, S11b, S12a, S12b, S13a, S13b, S14a, and S14b are connected as shown in the figure between the output of the second operational amplifier OP2 and the input of the third operational amplifier OP3.

[0048] These switches S11 to S14 are switches that are switched when charging the capacitor C6 of the second integrator 14 from the feedback capacitor C5 of the first integrator 13, or when discharging the capacitor C6.

[0049] A feedback capacitor C7 is connected between the input and output of the third operational amplifier OP3. Switches S14a and S14b are switches that are switched when charging from capacitor C6 to feedback capacitor C7. The output of the third operational amplifier OP3 is connected to the input of the quantizer 16.

[0050] The quantizer 16 converts the level of the output of the second integrator 14 to generate a digital signal Dout. The digital signal Dout from the quantizer 16 is input to D / A converters 20a, 20b and 220a, 220b. The D / A converters 20a, 20b of this embodiment provide feedback to the first integrator 13 based on the digital signal Dout output by the quantizer 16. The D / A converters 20a, 20b are circuits that output a potential based on the digital signal Dout.

[0051] Switches S7a, S7b and capacitors C2a, C2b are connected in series between the D / A converters 20a, 20b and the input of the second operational amplifier OP2 that constitutes the first integrator 13, and when the control circuit 12 turns on the switches S7a, S7b, the D / A converters 20a, 20b are fed back to the first integrator 13.

[0052] Furthermore, the D / A converters 220a and 220b provide feedback to the second integrator 14 based on the digital signal Dout output by the quantizer 16. The D / A converters 220a and 220b are circuits that output a potential based on the digital signal Dout.

[0053] Switches S8a, S8b and capacitors C22a, C22b are connected in series between the D / A converters 220a, 220b and the inputs of the capacitors C6a, C6b that constitute the second integrator 14, and when the control circuit 12 turns on the switches S8a, S8b, the D / A converters 220a, 220b are fed back to the second integrator 14.

[0054] Next, we will explain the control signals generated by the control circuit 12 in this embodiment. The control circuit 12 is composed of a master clock generator using, for example, a crystal oscillator, a frequency divider, a synchronization circuit, an on / off edge generator, a clock generator, etc.

[0055] FIG. 11 shows the control signals Φ1, Φ2, Φ1din, Φ1dout, Φ2din, and Φ2dout to be applied to each of the switches mentioned above, and FIG. 12 shows which switches the control signals Φ1, Φ2, Φ1din, Φ1dout, Φ2din, and Φ2dout are applied to.

[0056] The control signals Φ1 and Φ2 are control signals that are turned on and off in a complementary manner, and the control signals Φ1d and Φ2d are also control signals that are turned on and off in a complementary manner. That is, there is no overlap between the control signals Φ1 and Φ2, and there is also no overlap between the control signals Φ1d and Φ2d. The control signals Φ1d and Φ2d are also control signals that are output with a slight delay compared to the control signals Φ1 and Φ2.

[0057] Moreover, the control signals Φ1din, Φ1dout, Φ2din, and Φ2dout are control signals having a half cycle with respect to the control signals Φ1d and Φ2d.

[0058] As shown in Figures 11 and 12, the control circuit 12 outputs control signals Φ1, Φ2, Φ1d, Φ1din, Φ1dout, Φ2d, Φ2din, and Φ2dout to the target switches S1a, S1b to S15a, and S15b to turn on and off the switches S1a, S1b to S15a, and S15b.

[0059] 11, when the frequencies of the control signals Φ1, Φ2, Φ1d, and Φ2d are defined as a reference frequency Fs, the control signals Φ1din, Φ2din, Φ2dout, and Φ2dout have a frequency Fs / 2, which is half the reference frequency Fs. Therefore, when the control circuit 12 drives the first integrator 13 using the first control signal Φ1 with a predetermined phase timing of the reference frequency Fs, the control circuit 12 causes the first integrator 13 to perform chopping operation at the predetermined timing of the reference frequency Fs, which is the same as the timing at which the second output chopping switch 172 at the input of the first integrator 13 is driven. In addition, the control circuit 12 causes the input chopping switch 170 and the first output chopping switch 171 to perform chopping operation at a frequency Fs / 2, which is half the frequency of the first control signal Φ1 with the reference frequency Fs.

[0060] The control circuit 12 modulates the input signals Vinp and Vinm by chopping them at the input of the capacitively coupled amplifier 11 using the input chopping switch 170, demodulates them by chopping them at the output of the capacitively coupled amplifier 11 using the first output chopping switch 171, and furthermore, causes the demodulated output signal of the capacitively coupled amplifier 11 to be taken into the first integrator 13 by the second output chopping switch 172.

[0061] This circuit operation causes the output signal to repeatedly change between positive and negative, so that the DC value converges to an average value, and the effect of the offset of the first operational amplifier OP1 in the capacitively coupled amplifier 11 can be canceled out by the output of the capacitively coupled amplifier 11. As a result, even if the first integrator 13 has sensitivity to an error dependent on the input voltage of the first integrator 13, it will not be affected by this, and the effect of the offset can be reduced for the entire circuit.

[0062] Furthermore, the chopping frequency Fs / 2 of the input chopping switch 170 and the first output chopping switch 171 before and after the capacitive coupling amplifier 11 is set lower than the reference frequency Fs of the chopping operation of the first integrator 13 and the second integrator 14. This makes it possible to lower the drive frequency of the input chopping switch 170 and the first output chopping switch 171. An anti-aliasing filter may be provided in the stage preceding the input terminals Ina and Inb. The anti-aliasing filter is configured by an RC low-pass filter including a resistor and a capacitor.

[0063] Since the drive frequencies of the input chopping switch 170 and the first output chopping switch 171 are reduced, the amount of current flowing through the resistors that make up the anti-aliasing filter can be reduced. This reduces detection errors due to voltage drops across the resistors. Furthermore, according to this embodiment, the control signals Φ1din, Φ1dout are made to have the same phase, and the control signals Φ2din, Φ2dout are made to have the same phase, making it easier to generate the control signals Φ1din, Φ1dout, Φ2din, and Φ2dout.

[0064] (Fourth embodiment) The fourth embodiment will be described with reference to Fig. 13 to Fig. 15. Differences from the third embodiment will be described. The difference from the third embodiment is that the configuration equivalent to the first output chopping switch 171 is omitted.

[0065] 13, the functions of the switches S3a and S5a shown in FIG. 9 are combined into a switch S5a, and the functions of the switches S3b and S5b are combined into a switch S5b. Furthermore, the functions of the switches S4b and S6a shown in FIG. 9 are combined into a switch S6a, and the functions of the switches S4a and S6b are combined into a switch S6b. That is, only one output chopping switch 172z is provided between the capacitive coupling amplifier 11 and the first integrator 13.

[0066] In this embodiment, the wiring of each component is changed as shown in FIG. 13, and the control signals of each switch shown in FIG. 11 are changed as shown in FIG. 15 and applied to each switch as shown in FIG.

[0067] When the control circuit 12 drives the first integrator 13 by the first control signal Φ1 having a predetermined phase timing of the reference frequency Fs, the control circuit 12 causes the input chopping switch 170 to perform chopping at a frequency Fs / 2 that is half the reference frequency Fs. The control circuit 12 also causes the output chopping switch 172z to perform chopping at a frequency Fs / 2 that is half the reference frequency Fs and at a timing that is 90° out of phase with the drive timing of the input chopping switch 170.

[0068] According to this embodiment, the input signals Vinp and Vinm are modulated by chopping at the input of the capacitively coupled amplifier 11 using the input chopping switch 170, and are demodulated by chopping at the output of the capacitively coupled amplifier 11 using the output chopping switch 172z, and the demodulated output signal of the capacitively coupled amplifier 11 is taken into the first integrator 13. With this configuration, it is possible to obtain the same effects as those of the third embodiment.

[0069] 13 of this embodiment, the functions of the switches S3a and S5a shown in FIG. 9 of the above-described embodiment can be combined into a single switch S5a, and the functions of the switches S3b and S5b shown in FIG. 9 can be combined into a single switch S5b. Furthermore, the functions of the switches S4b and S6a shown in FIG. 9 can be combined into a switch S6a, and the functions of the switches S4a and S6b shown in FIG. 9 can be combined into a switch S6b. Therefore, in this embodiment, as shown in FIG. 14, the output chopping switch 172z made up of switches S5 and S6 is switched by control signals Φ1dout and Φ2dout, so that the first integrator 13 can take in the demodulated output signal of the capacitively coupled amplifier 11.

[0070] In this embodiment, the number of switches S3a, S3b, S4a, and S4b can be reduced compared to the third embodiment. The switches S3a, S3b, S4a, and S4b shown in the third embodiment are configured using MOS transistors, and therefore, an error factor due to the on-resistance of the MOS transistors may occur when the transistors are on. In this embodiment, the number of switches S3a, S3b, S4a, and S4b can be reduced, and the influence of variations in the on-resistance of the MOS transistors can be minimized.

[0071] (Fifth embodiment) The fifth embodiment will be described with reference to Figs. 16 to 18. In this embodiment, a first integrator 13z is configured from the initial stage, and the capacitively coupled amplifier 11 is omitted. As shown in Fig. 16, the first integrator 13z, as a main circuit, includes a first operational amplifier OP1z and a feedback capacitor C5 (C5a, C5b) connected between the input and output of the first operational amplifier OP1z. A second integrator 14 is configured downstream of the first integrator 13z, and a quantizer 16 is configured downstream of the second integrator 14.

[0072] More specifically, the first integrator 13z is configured as a correlated double sampling integrator including a series circuit of a feedback capacitor C5 (C5a, C5b) and a feedback switch S10 (S10a, S10b) connected between the input and output of the first operational amplifier OP1z, and a reset switch S9 (S9a, S9b) connecting the input and output of the first operational amplifier OP1z. The output of the first operational amplifier OP1z constituting the first integrator 13z is provided with a first common mode feedback circuit CMFB1 shown in FIG. 1, but this is the same as in the above embodiment and therefore will not be described here.

[0073] In this configuration, when the first integrator 13z operates at the reference frequency Fs, the first common-mode feedback circuit CMFB1 of the first integrator 13z may be operated at a frequency Fs / 2 that is half the reference frequency Fs. The control signals Φ1, Φ2, Φ1d, Φ2d, Φ1din, and Φ2din applied to the switches are shown in Figure 17, and the relationship between the control signals Φ1, Φ2, Φ1d, and Φ2d and the control signals Φ1dcmfb and Φ2dcmfb applied to the first common-mode feedback circuit CMFB1 is further shown in Figure 18.

[0074] By turning the first common mode feedback circuit CMFB1 on and off using the control signals Φ1dcmfb and Φ2dcmfb shown in Figure 18, it can be operated at a frequency Fs / 2 that is half the reference frequency Fs, and the same effects as in the first embodiment can be obtained.

[0075] (Sixth embodiment) The sixth embodiment will be described with reference to FIG. 19. In the sixth embodiment, a case where a circuit configuration similar to that of the fifth embodiment is applied will be described. During the period when the ΔΣ modulator 15 shown in FIG. 17 is operating normally, the operation frequency of the first common mode feedback circuit CMFB1 is switched at a frequency Fs / 2 that is half the reference frequency Fs, thereby operating in the same manner as the fifth embodiment, and charge transfer between the first integrator 13z and the second integrator 14 can be performed accurately.

[0076] During the period in which the normal operation is reset, the control circuit 12 holds the control signals Φ1 and Φ1d ON and holds the control signals Φ2 and Φ2d OFF, as shown in Fig. 19. This stops the integration operation of the first integrator 13z and cuts off the charge transfer to the second integrator 14, thereby resetting the normal operation.

[0077] At this time, the control circuit 12 preferably switches the first common-mode feedback circuit CMFB1 at the reference frequency Fs. Operating the first common-mode feedback circuit CMFB1 at the reference frequency Fs during reset allows the first common-mode feedback circuit CMFB1 to operate at high speed, allowing the bias Vbias to be quickly returned to the ideal common-mode value.

[0078] (Other embodiments) The present invention is not limited to the above-described embodiments, and the following modifications or extensions are possible, for example. The configurations and functions of the above-described embodiments may be combined. Aspects in which part of the above-described embodiments is omitted as long as the problem can be solved can also be considered to be embodiments. Furthermore, any conceivable aspect can also be considered to be an embodiment, as long as it does not deviate from the essence of the invention as specified by the wording of the claims.

[0079] In addition to the content set forth in the claims, the present disclosure also includes the following disclosure content. [1] The input chopping switch is turned on by a first control signal (Φ1din) and a second control signal (Φ2din) which are different from each other, and the main circuit unit (11; 13z) includes a sampling capacitor for sampling the input signal and a first operational amplifier (OP1; OP1z), the main circuit unit includes a first capacitor connected between the output of the first operational amplifier and a bias current potential (Vbias) of the first operational amplifier, a second capacitor connected in parallel to the first capacitor via a first switch group, a third capacitor connected in parallel to the first capacitor via a second switch group, and a common mode feedback circuit (CMFB1) including a third switch group and a fourth switch group that apply an output common mode reference potential (Vref) and a bias current reference potential (Vbias_ref) of the first operational amplifier to the second capacitor and the third capacitor, respectively; a control circuit (12) that turns on the first switch group and the fourth switch group in synchronization with a first common control signal (Φ1dcmfb) that is set depending on the first control signal, and turns on the second switch group and the third switch group in synchronization with a second common control signal (Φ2dcmfb) that is set depending on the second control signal; A switched capacitor circuit configured so that the total connected capacitance value connecting the output of the first operational amplifier and any one of the first capacitor, the second capacitor, and the third capacitor of the common mode feedback circuit is equal when the first common control signal is on and when the second common control signal is on.

[0080] [2] The main circuit section is a capacitively coupled amplifier that includes a feedback capacitor connected between the input and output of the first operational amplifier and amplifies an input signal. [1] A switched capacitor circuit.

[0081] [3] an integrator (13) connected to a subsequent stage of the capacitive coupling amplifier; The control circuit controls the common mode feedback circuit so as not to operate at least during an integration period in which the output of the capacitive coupling amplifier is integrated by the integrator as an input signal, and allows the common mode feedback circuit to operate during other periods. [2] A switched capacitor circuit.

[0082] [4] The control circuit is a switched capacitor circuit according to [2] or [3], wherein when the integrator is operated using a clock signal of a reference frequency, the control circuit operates the common mode feedback circuit using a clock signal of a frequency half the reference frequency (Fs / 2).

[0083] [5] The switched capacitor circuit according to any one of [2] to [4], wherein the control circuit operates the capacitive coupling amplifier by a clock signal having a frequency (Fs / 2) that is half the reference frequency.

[0084] [6] The switched capacitor circuit according to any one of [2] to [5], wherein the integrator is configured as a correlated double sampling (CDS) type having a second operational amplifier, a series circuit of a feedback capacitor and a feedback switch connected between the input and output of the second operational amplifier, and a reset switch connecting the input and output of the second operational amplifier.

[0085] [7] the integrator comprises a second operational amplifier (OP2); a second common mode feedback circuit (CMFB2) including: a fourth capacitor connected between the output of the second operational amplifier and the bias current potential (Vbias) of the second operational amplifier; a fifth capacitor connected in parallel to the fourth capacitor via a fifth switch group; a sixth capacitor connected in parallel to the fourth capacitor via a sixth switch group; and seventh and eighth switch groups that apply the output common mode reference potential (Vref) and the bias current reference potential (Vbias_ref) of the second operational amplifier to the fifth capacitor and the sixth capacitor, respectively; The switched capacitor circuit according to any one of [3] to [6], wherein when the control circuit operates the integrator using a clock signal of a reference frequency, the control circuit operates the second common mode feedback circuit of the integrator using a clock signal of a frequency half the reference frequency (Fs / 2).

[0086] [8] an output chopping switch (172z) is provided between the capacitive coupling amplifier and the integrator; The control circuit When the integrator is driven by a first control signal (Φ1) having a predetermined phase timing of the reference frequency (Fs), The input chopping switch is caused to perform chopping at a frequency (Fs / 2) that is 1 / 2 the reference frequency (Fs), and the output chopping switch is caused to perform chopping at a frequency (Fs / 2) that is 1 / 2 the reference frequency and at a timing that is 90° out of phase with respect to the drive timing of the input chopping switch, A switched capacitor circuit according to [6] or [7], wherein modulation is performed by chopping the input of the capacitive coupling amplifier using the input chopping switch, and demodulation is performed by chopping the output of the capacitive coupling amplifier using the output chopping switch, and the demodulated output signal of the capacitive coupling amplifier is input to the integrator.

[0087] [9] a first output chopping switch (171) connected between the capacitively coupled amplifier and the integrator; a second output chopping switch (172) connected between the first output chopping switch and the input of the integrator; The control circuit When the integrator is driven by a first control signal having a predetermined phase timing of the reference frequency (Fs), the integrator is chopped at the predetermined timing of the reference frequency (Fs) which is the same as the timing at which the second output chopping switch of the input of the integrator is driven, and the input chopping switch and the first output chopping switch are chopped at a frequency (Fs / 2) which is half the frequency of the first control signal of the reference frequency, A switched capacitor circuit according to [6] or [7], wherein the input chopping switch modulates the input of the capacitively coupled amplifier by chopping, and the first output chopping switch demodulates the output of the capacitively coupled amplifier by chopping, and the second output chopping switch inputs the demodulated output signal of the capacitively coupled amplifier into the integrator.

[0088]

[10] The main circuit section is a switched capacitor circuit [1] configured by an integrator (13z) having feedback capacitors (C5a, C5b) connected between the input and output of the first operational amplifier (OP1z).

[0089]

[11] A switched capacitor circuit according to

[10] , wherein when the integrator operates at a reference frequency (Fs), the common mode feedback circuit of the integrator operates at a frequency (Fs / 2) that is half the reference frequency.

[0090]

[12] The switched capacitor circuit of

[10] or

[11] , wherein the integrator is composed of a correlated double sampling integrator having the first operational amplifier (OP1z), a series circuit of a feedback capacitor and a feedback switch connected between the input and output of the first operational amplifier, and a reset switch connecting the input and output of the first operational amplifier.

[0091]

[13] During a period in which the normal operation is reset, the control circuit switches the common mode feedback circuit at the reference frequency (Fs), The switched capacitor circuit according to any one of [6] to [9] or

[12] , wherein during the normal operation period, the operating frequency of the common mode feedback circuit is switched at a frequency (Fs / 2) that is half the reference frequency.

[0092] Although the present disclosure has been described based on the above-described embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including one, more, or less than one element, are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0093] In the drawing, 11 denotes a capacitive coupling amplifier (main circuit section), 13 denotes a first integrator, 13z denotes a first integrator (main circuit section), 14 denotes a second integrator, 20a, 20b, 220a, and 220b denote D / A converters, and 16 denotes a quantizer.

Claims

1. a main circuit unit (11; 13z) including a sampling capacitor that samples an input signal by turning on an input chopping switch in response to a first control signal (Φ1din) and a second control signal (Φ2din) that are different from each other, and a first operational amplifier (OP1; OP1z); the main circuit unit includes a common mode feedback circuit (CMFB1) including: a first capacitor connected between the output of the first operational amplifier and a bias current potential (Vbias) of the first operational amplifier; a second capacitor connected in parallel to the first capacitor via a first switch group; a third capacitor connected in parallel to the first capacitor via a second switch group; and a third switch group and a fourth switch group that apply an output common mode reference potential (Vref) and a bias current reference potential (Vbias_ref) of the first operational amplifier to the second capacitor and the third capacitor, respectively; a control circuit (12) that turns on the first switch group and the fourth switch group in synchronization with a first common control signal (Φ1dcmfb) that is set depending on the first control signal, and turns on the second switch group and the third switch group in synchronization with a second common control signal (Φ2dcmfb) that is set depending on the second control signal; A switched capacitor circuit configured so that the total connected capacitance value connecting the output of the first operational amplifier and any one of the first capacitor, the second capacitor, and the third capacitor of the common mode feedback circuit is equal when the first common control signal is on and when the second common control signal is on.

2. 2. The switched capacitor circuit according to claim 1, wherein the main circuit section is a capacitively coupled amplifier that includes a feedback capacitor connected between the input and output of the first operational amplifier and amplifies an input signal.

3. an integrator (13) connected to a subsequent stage of the capacitive coupling amplifier; 3. The switched capacitor circuit according to claim 2, wherein the control circuit controls the common mode feedback circuit so as not to operate at least during an integration period in which the integrator is caused to integrate the output of the capacitive coupling amplifier as an input signal, and allows the common mode feedback circuit to operate during other periods.

4. 4. The switched capacitor circuit according to claim 3, wherein when the control circuit operates the integrator using a clock signal of a reference frequency, the control circuit operates the common mode feedback circuit using a clock signal of a frequency that is half the reference frequency (Fs / 2).

5. 5. The switched capacitor circuit according to claim 4, wherein the control circuit operates the capacitive coupling amplifier with a clock signal having a frequency (Fs / 2) that is half the reference frequency.

6. 6. The switched capacitor circuit according to claim 5, wherein the integrator is configured as a correlated double sampling (CDS) type including a second operational amplifier, a series circuit of a feedback capacitor and a feedback switch connected between the input and output of the second operational amplifier, and a reset switch connecting the input and output of the second operational amplifier.

7. the integrator comprises a second operational amplifier (OP2); a second common mode feedback circuit (CMFB2) including: a fourth capacitor connected between the output of the second operational amplifier and the bias current potential (Vbias) of the second operational amplifier; a fifth capacitor connected in parallel to the fourth capacitor via a fifth switch group; a sixth capacitor connected in parallel to the fourth capacitor via a sixth switch group; and a seventh switch group and an eighth switch group that apply the output common mode reference potential (Vref) and the bias current reference potential (Vbias_ref) of the second operational amplifier to the fifth capacitor and the sixth capacitor, respectively; The control circuit the fifth switch group and the eighth switch group are turned on in synchronization with the first common control signal (Φ1dcmfb) provided depending on the first control signal, and the sixth switch group and the seventh switch group are turned on in synchronization with the second common control signal (Φ2dcmfb) provided depending on the second control signal, 4. The switched capacitor circuit according to claim 3, wherein when the integrator is operated using a clock signal of a reference frequency, the second common mode feedback circuit of the integrator is operated by a clock signal of a frequency (Fs / 2) that is 1 / 2 times the reference frequency.

8. an output chopping switch (172z) between the capacitive coupling amplifier and the integrator; The control circuit When the integrator is driven by a first control signal having a predetermined phase timing of the reference frequency (Fs), The input chopping switch is caused to perform chopping operation at a frequency (Fs / 2) that is 1 / 2 the reference frequency (Fs), and the output chopping switch is caused to perform chopping operation at a frequency (Fs / 2) that is 1 / 2 the reference frequency and at a timing that is 90° out of phase with respect to the drive timing of the input chopping switch, 7. The switched capacitor circuit according to claim 6, wherein modulation is performed by chopping the input of the capacitively coupled amplifier using the input chopping switch, and demodulation is performed by chopping the output of the capacitively coupled amplifier using the output chopping switch, and the demodulated output signal of the capacitively coupled amplifier is input to the integrator.

9. a first output chopping switch (171) connected between the capacitively coupled amplifier and the integrator; a second output chopping switch (172) connected between the first output chopping switch and the input of the integrator; The control circuit When the integrator is driven by a first control signal having a predetermined phase timing of the reference frequency (Fs), a chopping operation is performed at the predetermined timing of the reference frequency (Fs) which is the same as the timing at which the second output chopping switch of the input of the integrator is driven, and the input chopping switch and the first output chopping switch are chopped at a frequency (Fs / 2) which is 1 / 2 of the first control signal (Φ1) of the reference frequency, 7. The switched capacitor circuit according to claim 6, wherein modulation is performed by chopping the input of the capacitively coupled amplifier using the input chopping switch, and demodulation is performed by chopping the output of the capacitively coupled amplifier using the first output chopping switch, and the demodulated output signal of the capacitively coupled amplifier is taken into the integrator by the second output chopping switch.

10. 2. The switched-capacitor circuit according to claim 1, wherein the main circuit section is configured by an integrator (13z) having feedback capacitors (C5a, C5b) connected between the input and output of the first operational amplifier (OP1z).

11. 11. The switched capacitor circuit of claim 10, wherein when the integrator operates at a reference frequency (Fs), the common mode feedback circuit of the integrator operates at a frequency (Fs / 2) that is half the reference frequency.

12. 12. The switched capacitor circuit according to claim 11, wherein the integrator is configured by a correlated double sampling integrator including the first operational amplifier (OP1z), a series circuit of a feedback capacitor and a feedback switch connected between the input and output of the first operational amplifier, and a reset switch connecting the input and output of the first operational amplifier.

13. During a period in which the normal operation is reset, the control circuit causes the common mode feedback circuit to perform a switching operation at the reference frequency (Fs), 13. The switched capacitor circuit according to claim 6, wherein during the normal operation period, the common mode feedback circuit is switched at an operating frequency (Fs / 2) that is half the reference frequency.

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