Leakage current reduction methods

Abstract

Procedure (600) comprising the following: Providing (602) a substrate (720) having a first active region (702) and a second active region (704) adjacent to the first active region (702) at a boundary (711); Forming a first rib (710) within the first active region (702), a second rib (712) within the second active region (702), and a dummy rib (714) along the border (711); Deposition of a photoresist layer (715) and structuring of the photoresist layer to expose the dummy rib (714) while the first rib (710) and the second rib (712) remain covered by the structured photoresist layer (715); Performing a threshold voltage implantation (722) through the structured photoresist layer (715) into the dummy rib to provide an ion-implanted dummy rib (714A); and Forming a gate stack (716) over the first rib (710), the second rib (712) and the ion-implanted dummy rib (714A).

Description

BACKGROUND

[0001] The electronics industry faces a steadily growing demand for smaller and faster electronic components that are also capable of supporting a greater number of increasingly complex and demanding functions. Accordingly, there is an ongoing trend in the semiconductor industry to produce cost-effective, high-performance, and energy-efficient integrated circuits (ICs). So far, this goal has largely been achieved by scaling down the dimensions of semiconductor ICs (for example, in terms of the smallest structural element size), thereby improving production efficiency and reducing associated costs. However, such scaling has also increased the complexity of the semiconductor manufacturing process.Therefore, realizing ongoing advances in semiconductor ICs and components requires similar advances in semiconductor manufacturing processes and semiconductor manufacturing technology.

[0002] Multi-gate devices were introduced some time ago to improve gate control by enhancing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs). One such multi-gate device that has reached the market is the finned field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure that extends from the substrate on which it is formed and is used to create the FET channel. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their three-dimensional structure allows them to scale significantly while maintaining gate control and mitigating SCEs. Furthermore, at least one aspect of IC scaling involves reducing cell size (for example, as part of a layout process).In some examples, reducing the FinFET cell size involves aligning active regions, such as active FinFET regions, in adjacent cells. In some cases, aligning active regions across adjacent cells can be referred to as a "continuous active region." In various examples, a continuous active region can lead to significant leakage current. Attempts have been made to reduce such leakage current by adding filler layers to enlarge the lithography window. However, using such filler layers presents space constraints (for example, the area needs to be increased). Thus, existing techniques have not proven entirely satisfactory in every respect.

[0003] US 2016 / 0254261 A1 relates to an integrated circuit (IC) device comprising a first active transistor of a first type in a first type range and a second active transistor of a second type.

[0004] US patent 2013 / 0309838 A1 concerns methods for manufacturing integrated FinFET circuits on bulk semiconductor substrates.

[0005] US 2017 / 0033101 A1 relates to an integrated circuit with at least one cell, wherein the at least one cell has first and second spaced-apart active areas.

[0006] US 2017 / 0053996 A1 concerns methods for manufacturing semiconductor devices with a first and a second dielectric layer in first and second trenches.

[0007] US 2014 / 0001564 A1 concerns a design method for an integrated semiconductor circuit that is capable of minimizing parasitic capacitance generated by overhead in conductive lines, especially a gate line.

[0008] US 2015 / 0171164 A1 relates to a method for manufacturing a field-effect transistor (FET) device, comprising forming a plurality of semiconductor fins on a substrate.

[0009] US Patent 9,768,072 B1 relates to a method for manufacturing a ribbed field-effect transistor with tins with reduced dimensional changes, comprising forming a dummy rib trench and forming a dummy rib filling in the dummy rib trench.

[0010] US 2016 / 0141387 A1 relates to a process comprising forming a rib structure on a substrate; and performing a threshold stress implantation process into the rib structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Aspects of this disclosure are best understood with the help of the following detailed description, when read together with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be enlarged or reduced as desired to enhance clarity. Fig. Figure 1 is a perspective view of an embodiment of a FinFET device; Fig. 2A illustrates a layout design of at least one section of the two adjacent FinFET cells; Fig. Figure 2B illustrates a cross-sectional view of a FinFET device, essentially section CC' of Fig. 2A corresponds to; Fig. 3A, Fig. 3B and Fig. Figure 3C illustrates mask layout designs that can be used to set a metal gate exit function for different pairs of adjacent N-type cells having a continuous active region, according to examples not pertaining to the invention; Fig. 4A, Fig. 4B and Fig. Figure 4C illustrates mask layout designs that can be used to set a metal gate exit function for different pairs of adjacent P-type cells having a continuous active region, according to examples not pertaining to the invention; Fig. Figure 5 is a flowchart of a process for manufacturing a FinFET device; Fig. Figure 6 is a flowchart of an alternative method for manufacturing a FinFET device according to one or more aspects of the present invention; Fig. 7, Fig. 8, Fig. 9, Fig. 10 and Fig. Figure 11 illustrates cross-sectional views of an embodiment of a FinFET device according to one or more steps of the method of Fig. 6; Fig. Figure 12 illustrates a layout design of at least one section of the two adjacent FinFET cells, including a SiGe region, according to some embodiments; Fig. Figure 13 is a flowchart of a further method for manufacturing a FinFET device according to one or more aspects of the present invention; and Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18 and Fig. Figure 19 illustrates cross-sectional views of an embodiment of a FinFET device according to one or more steps of the method of Fig. 13. DETAILED DESCRIPTION

[0012] The invention is defined according to the independent claims. The dependent claims relate to corresponding embodiments. The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples. For instance, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which further structural elements may be formed between the first and second structural elements, so that the first and second structural elements may not be in direct contact.Furthermore, this disclosure may repeat reference numbers and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not automatically establish a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0014] It should also be noted that the present disclosure introduces embodiments in the form of multi-gate transistors or rib-multi-gate transistors, referred to herein as FinFET devices. Such a device may comprise a P-type metal-oxide-semiconductor FinFET device or an N-type metal-oxide-semiconductor FinFET device. The FinFET device may be a dual-gate device, a tri-gate device, a bulk device, a silicon-on-insulator (SOI) device, and / or any other configuration. The person skilled in the art will recognize further embodiments of semiconductor devices that may benefit from aspects of the present disclosure. For example, some of the embodiments described herein may also be applied to gate-all-around (GAA) devices, omega-gate (Ω-gate) devices, or pi-gate (Π-gate) devices.

[0015] In Fig. Figure 1 illustrates a FinFET device 100. The FinFET device 100 contains one or more fin-multi-gate field-effect transistors (FETs). The FinFET device 100 includes a substrate 102, at least one fin element 104 extending from the substrate 102, insulating regions 106, and a gate structure 108 arranged on and around the fin element 104. The substrate 102 can be a semiconductor substrate, such as a silicon substrate. The substrate can contain various layers, including conductive or insulating layers, formed on the semiconductor substrate. Depending on the design requirements, the substrate can contain various doping configurations, as is known in the prior art. The substrate can also contain other semiconductors, such as germanium, silicon carbide (SiC), silicon-germanium (SiGe), or diamond.Alternatively, the substrate can contain a composite semiconductor and / or an alloy semiconductor. Furthermore, in some embodiments, the substrate can contain an epitaxial layer (epi-layer), the substrate can be stretched to increase performance, the substrate can contain a silicon-on-insulator (SOI) structure, and / or the substrate can have other suitable optimization features.

[0016] The rib element 104, like the substrate 102, can comprise silicon or another elemental semiconductor, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. The ribs 104 can be fabricated using suitable processes, including photolithography and etching. The photolithography process can include: forming a photoresist layer (resist) over the substrate (for example, on a silicon layer), exposing the resist to create a structure, performing firing processes after exposure, and developing the resist to form a masking element containing the resist.In some embodiments, the structuring of the resist to form the masking element can be performed using an electron beam (E-beam) lithography process, an EUV lithography process, a dip lithography process, or any other suitable lithography process. The masking element can then be used to protect regions of the substrate while an etching process forms recesses in the substrate 102, leaving behind an extending rib 104. The recesses can be etched using a dry etching process, a wet etching process, or a combination thereof. Numerous other embodiments of the method for forming the ribs 104 on the substrate 102 can also be used.

[0017] Each of the multiple ribs 104 also contains a source region 105 and a drain region 107, wherein the source / drain regions 105, 107 are formed in, on, and / or around the rib 104. The source / drain regions 105, 107 can be grown epitaxially over the ribs 104. In some embodiments, one or more layers of a low Schottky barrier height (SBH) material are formed over the source / drain regions 105, 107 to reduce source / drain contact resistance. In some examples, the low SBH material is a III-V material, such as GaAs, In x Ga 1-x As, Ni-InAs and / or other suitable materials. A channel region of a transistor is arranged within rib 104, which lies below gate structure 108, along a plane substantially parallel to a plane defined by the intersection line BB' of Fig. 1 is defined. In some examples, the channel region of the fin contains silicon, a high-mobility material such as germanium, silicon-germanium, one of the compound or alloy semiconductors discussed above, and / or combinations thereof. High-mobility materials include those with an electron mobility greater than that of silicon, for example, greater than that of Si, which has an intrinsic electron mobility at room temperature (300 K) of about 1350 cm² / (V·s) and a hole mobility of about 480 cm² / (V·s). In some embodiments, the channel region contains a stretched channel material. For example, the stretched channel material can be formed using a different material for the fin element 104 and the substrate 102, such that there is a lattice mismatch between the fin element 104 and the substrate 102.The lattice mismatch between the rib element 104 and the substrate 102 can thus cause strain (for example, tension or compression) within the channel region. In various embodiments, such a strained channel material generates higher carrier mobility (for example, electron or hole mobility) and higher transistor performance. Therefore, in some embodiments, the high-mobility material discussed above can, in some cases, incorporate a strained channel material.

[0018] The insulating regions 106 can be shallow trench insulation (STI) structural elements. Alternatively, a field oxide, a LOCOS structural element, and / or other suitable insulating structural elements can be implemented on and / or in the substrate 102. The insulating regions 106 can consist of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a dielectric with a low k-value, combinations thereof, and / or other suitable materials known in the prior art. In one embodiment, the insulating structures are STI structural elements and are formed by etching trenches in the substrate 102. The trenches can then be filled with an insulating material (such as a dielectric material), followed by a chemical-mechanical polishing (CMP) process. However, other embodiments are also possible.In some embodiments, the insulating regions 106 may contain a multilayer structure, which, for example, has one or more lining layers.

[0019] The gate structure 108 comprises a gate stack with an interface layer 110 formed over the channel region of the rib 104, a gate dielectric layer 112 formed over the interface layer 110, and a metal layer 114 formed over the gate dielectric layer 112. The interface layer 110 can contain a dielectric material, such as a silicon oxide layer (SiO2) or silicon oxynitride (SiON). The interface layer 110 can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable processes. The gate dielectric layer 112 can contain a dielectric layer with a high k-value, such as hafnium oxide (HfO2).Alternatively, the high k-value dielectric layer can also contain other high k-value dielectrics, such as TiO₂, HfZrO, Ta₂O₃, HfSiO₄, ZrO₂, ZrSiO₂, La₂O₃, combinations thereof, or other suitable materials. In other embodiments, the gate dielectric layer can contain silicon dioxide or other suitable dielectrics. The dielectric layer can be formed by ALD, physical vapor deposition (PVD), oxidation, and / or other suitable methods. The metal layer 114 can contain a conductive layer, such as W, TiN, TaN, WN, Re, Ir, Ru, Mo, Al, Cu, Co, Ni, combinations thereof, and / or other suitable compositions. In some embodiments, the metal layer 114 can contain a first metal material for N-type FinFETs and a second metal material for P-type FinFETs. Thus, the FinFET device 100 can contain a dual working exit metal gate configuration.For example, the first metal material (for example, for N-type devices) can contain metals exhibiting a work function that is substantially matched to the work function of the substrate's conduction band, or at least substantially matched to the work function of the conduction band of the channel region of rib 104. Similarly, for example, the second metal material (for example, for P-type devices) can contain metals exhibiting a work function that is substantially matched to the work function of the substrate's valence band, or at least substantially matched to the work function of the valence band of the channel region of rib 104. Thus, the metal layer 114 can provide a gate electrode for the FinFET device 100, which contains both N-type and P-type devices 100. In some embodiments, the metal layer 114 can alternatively contain a polysilicon layer.The metal layer 114 can be formed by PVD, CVD, electron beam (E-beam) evaporation, and / or other suitable processes. In some embodiments, sidewall spacers are formed on the sidewalls of the gate structure 108. The sidewall spacers can contain a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof.

[0020] Traditionally, advances in semiconductor fabrication and integrated circuit (IC) performance have largely been achieved by downscaling the dimensions of semiconductor ICs (for example, with respect to the smallest feature size). At least one aspect of IC scaling has been the reduction of cell size (for example, as part of a layout process). In some examples, reducing FinFET cell size has involved the adjoining of active regions, such as active FinFET regions, in adjacent cells. For the purposes of this disclosure, the adjoining of active regions across adjacent cells can be referred to as a “continuous active region.” In various examples, a continuous active region can lead to significant leakage current.In some cases, attempts have been made to reduce such leakage by adding layers of filler material to enlarge the lithographic window. However, using such filler layers presents space problems (for example, the area needs to be increased).

[0021] For the discussion of adjacent FinFET cells, we now turn to the Fig. 2A and Fig. 2B to. Fig. Figure 2A illustrates a layout design 200 of at least one section of the two adjacent FinFET cells. As shown, the layout design 200 contains a first cell 202 and a second cell 204, which are adjacent along a cell boundary 211. Furthermore, an active region 206 of the first cell 202 and an active region 208 of the second cell 204 are also adjacent along the cell boundary 211. Thus, the layout design 200 represents an example of a continuous active region, as described above. The layout design 200 also contains active ribs 210 and active ribs 212 in the first cell 202 and in the second cell 204, respectively. For the purposes of this discussion, the term "active rib" can be used to refer to a rib region that contains a FinFET channel. In various examples, each of the active regions 206, 208 can contain an active region of N type or an active region of P type.Thus, in some embodiments, the active ribs 210, 212 can contain N-type or P-type active ribs. To avoid misunderstandings, it should be noted that the embodiments disclosed in this text are not limited to a specific doping configuration; rather, the examples given in this text serve only for illustrative purposes. In some embodiments, a dummy rib 214 is also formed between the first cell 202 and the second cell 204 along the cell boundary 211.A “dummy” structure, as used in this text, such as a dummy rib, refers, for example, to a structure used to imitate a physical property of another structure (such as imitating the physical dimensions of adjacent active ribs 210, 212) and which is circuit-inoperable in the finished manufactured device (for example, not intended to be part of a circuit current flow path, although unwanted leakage current may flow). A gate 216 spanning the first cell 202 and the second cell 204 is also illustrated.

[0022] In Fig. Figure 2B illustrates a cross-sectional view of a FinFET device 250, which essentially follows the section line CC' of Fig. 2A corresponds to this. Fig. Figure 2B further illustrates the first cell 202 and the second cell 204, which are adjacent to each other along the cell boundary 211. The FinFET device 250 comprises the active ribs 210, 212, the dummy rib 214, the gate 216, a shallow trench insulation (STI) region 218, and a substrate 220. In some embodiments, the active ribs 210, 212, and the dummy rib 214 can be arranged as above with reference to Fig. 1 described above. In some cases, the active ribs 210, 212 and the dummy rib 214 can contain one or more epitaxial layers formed over the substrate 220, these epitaxial layers being deposited, patterned, and etched to form the active ribs 210, 212, and the dummy rib 214. The STI region 218 can resemble the insulating regions 106, the substrate 220 can resemble the substrate 102, and the gate 216 can resemble the gate structure 108, each described above. In various embodiments, the active ribs 210, 212 can contain N-type or P-type active ribs, and the gate 216 can contain one or more metallic and / or dielectric layers providing an appropriate work function for the device type in question (for example, N-type or P-type).Although leakage current can generally exist in devices containing a continuous active region, in some cases such leakage current can be more severe if adjacent active regions are of the same type (for example, N-type or P-type). Therefore, for the purposes of this discussion, we will assume that both active regions 206, 208 contain an N-type active region (for example, such that both active ribs 210, 212 are N-type active ribs), or that both active regions 206, 208 contain a P-type active region (for example, such that both active ribs 210, 212 are P-type active ribs). In some cases, the leakage current in devices with adjacent active regions of the same type can be more severe because such devices may, for example, have similar threshold voltages.Controlling the leakage current can therefore be particularly challenging, especially near the cell boundary 211 when adjacent active regions are of the same type (for example, N-type or P-type). In various scenarios, such a leakage current can lead to device failure and / or a degradation of the device's performance.

[0023] Embodiments of the present disclosure offer advantages over the prior art, although it is understood that other embodiments offer other advantages, that not all advantages are necessarily discussed in this text, and that no particular advantage is required for all embodiments. For example, embodiments discussed in this text include methods and structures for reducing leakage current in devices containing a continuous active region. As noted above, the leakage current can be more severe in devices with adjacent active regions of the same type because, for example, such devices may have similar threshold voltages.Therefore, in various embodiments, the isolation between adjacent cells, and thus the isolation between adjoining active regions, is improved by increasing a threshold voltage at the cell boundary (for example, with a position of the dummy rib 214). In some cases, the threshold voltage is increased with respect to the adjacent active regions. For better understanding of the discussion, it should be noted that the transistor threshold voltage (V. t ) and the flat belt tension (V fb ) can be expressed generally as: Vt=Vfb+2q∈NA2φBCox Vfb=φms+2φB−QfCox

[0024] From these two expressions for V t and V fb It becomes clear that the threshold voltage (V t ) - among other factors - by a gate-metal work function (for example, φ ms as a difference between the metal work function φm and the semiconductor work function φ s defined), by substrate doping and substrate type (for example, N A, φ B , ε) and by the composition of the gate dielectric (for example, C ox) is influenced. Thus, in some embodiments, the threshold voltage at the cell boundary is increased by modifying a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary (for example, from N-type to P-type or from P-type to N-type). In some examples, such a threshold voltage reversal—or adjustment in general—can be achieved by adjusting the exit work metal and / or a gate dielectric layer. Alternatively, in some cases according to the invention, the threshold voltage at the cell boundary is increased by performing a threshold voltage implantation (for example, an ion implantation) at the cell boundary and into the dummy rib located at the cell boundary. Furthermore, in some embodiments according to the invention, the threshold voltage at the cell boundary is increased by using a silicon-germanium (SiGe) channel at the cell boundary.In some cases, the SiGe can be located within the substrate at the cell boundary, and / or the SiGe can be part of the dummy rib located at the cell boundary. Therefore, embodiments of the present disclosure provide improved insulation and thus a reduced leakage current between adjacent cells that have adjoining active regions.

[0025] Examples of various embodiments, including different ways of improving the insulation between adjacent cells by increasing a threshold voltage at the cell boundary, are now discussed. In some embodiments, the threshold voltage at the cell boundary is increased by changing a photomask LOP to reverse a cell boundary threshold voltage type, for example, by adjusting the exit work metal and / or a gate dielectric layer. In some cases, changing the photomask LOP can reduce the cell boundary leakage current by one to two orders of magnitude. Fig. 3A, Fig. 3B and Fig. Section 3C illustrates layout designs that can be used to set the work function of a metal gate for various pairs of adjacent N-type cells that have a continuous active region. In some examples, the layout designs shown and described can be used to set the work function of a metal gate, such as gate 216 or gate structure 108, which were described above. It is also understood that the various structural elements (for example, ribs, active regions, openings, etc.) that are related to the layout designs of the Fig. 3A, Fig. 3B and Fig. 3C will be illustrated and discussed, and can be structured using a set of masks. However, for the purposes of this discussion, aspects of the layout designs relating to setting the work function of a metal layer will be highlighted and noted accordingly. Furthermore, in some cases, aspects of the layout designs relating to setting the work function of a metal layer can be structured using several separate and individual masks, as discussed below. We will first turn to Fig. Figure 3A illustrates layout designs 300, 302, 304, and 306. Each of the layout designs 300, 302, 304, and 306 contains a first cell 308 and a second cell 310 adjacent to each other along a cell boundary 311. In some examples, the first cell 308 can be an N-type standard threshold voltage (NSVT) cell, and the second cell 310 can be an N-type low threshold voltage (NLVT) cell. As shown, an active region 312 of the first cell 308 and an active region 314 of the second cell 310 can also be adjacent to each other along the cell boundary 311. In some examples, the first cell 308 contains active ribs 316, the second cell 310 contains active ribs 318, and a dummy rib 320 is arranged between the first cell 308 and the second cell 310 along the cell boundary 311.For the sake of clarity, certain structural elements in layout designs 302, 304, and 306, which are essentially the same as structural elements shown and identified in layout design 300, are not again assigned a reference number, but can be referred to in the following discussion using the reference numbers given above.

[0026] With regard to setting the work function of a metal layer, a set of separate and individual masks can be used to achieve a target threshold voltage of the dummy rib 320 at the cell boundary 311. For example, as part of forming the one or more metallic and / or dielectric layers that provide a suitable work function (for example, for the gate 216 or the gate structure 108), each of the one or more layers (for example, gate layers) can be deposited, patterned, and etched as described in the process of Fig. 5 will be discussed in more detail. For example, a first gate layer can be deposited, and a first mask containing a structure of an aperture 322 (shown, for example, in layout design 300) can be used to structure or define a section of the first gate layer to be removed (for example, by means of an etching process). For the purposes of this discussion, the “aperture” described in this text may refer to an aperture in a photoresist layer. For example, a photoresist layer can be deposited and structured (for example, by an exposure process using a mask having a layout as described in this text, followed by a development process), the resulting structured photoresist layer containing the aperture.In some cases, an underlying layer (exposed, for example, by the opening) can then be removed (for example, by an etching process). In some embodiments, the first gate layer can contain a dielectric layer, such as SiO2 or SiON, or a dielectric layer with a high k-value, such as HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, and La2O3. Thus, according to layout design 300, the first gate layer can be removed from the region defined by opening 322 (for example, from above active ribs 316 and dummy rib 320). A second gate layer can then be deposited, and a second mask containing the structure of opening 324 and opening 326 (shown, for example, in layout design 302) can be used to structure or define a section of the second gate layer to be removed.In some embodiments, the second gate layer may contain a P-type exit work metal (PWFM) layer. In some cases, the second gate layer may contain a TiN layer. In at least some examples, the second gate layer may have a thickness of approximately 1.2 nm (12 angstroms). Thus, according to layout design 302, the second gate layer can be removed from the region defined by opening 324 (for example, from above active ribs 316) and opening 326 (for example, from above active ribs 318), while remaining above dummy rib 320. At least some prior art processes, in contrast to the present embodiment, can additionally remove the second gate layer from above dummy rib 320.A third gate layer can then be deposited, and a third mask without opening structures in the first cell 308 or the second cell 310 (for example, as shown in layout design 304) can be used to ensure that the third gate layer remains above the first cell 308 and the second cell 310. In some embodiments, the third gate layer can also include a PWFM layer. For example, the third gate layer can include a first layer deposited over a second layer, such as TiN deposited over TaN, or TaN deposited over TiN. In some examples, the deposited third gate layer can include a TiN layer approximately 1 nm (10 angstroms) thick and a TaN layer approximately 1.5 nm (15 angstroms) thick.Thus, according to layout design 304, the third gate layer does not need to be removed from the first or second cells 308, 310 (for example, from above the active ribs 316, 318 and above the dummy rib 320). To avoid misunderstandings, it should be noted that in some cases, the third mask may also contain structures or openings in other areas of the mask not shown in layout design 304. In some embodiments, a fourth gate layer may then be deposited, and a fourth mask containing a structure of an opening 328 and an opening 330 (for example, shown in layout design 306) may be used to structure or define a section of the fourth gate layer that is to be removed. In some embodiments, the fourth gate layer may contain a PWFM layer. In some cases, the fourth gate layer may contain a TiN layer.In at least some examples, the fourth gate layer can have a thickness of approximately 1 nm (10 angstroms). Thus, according to layout design 306, the fourth gate layer can be removed from the region defined by opening 328 (for example, from above the active ribs 316) and opening 330 (for example, from above the active ribs 318), while remaining above the dummy rib 320. At least some prior art processes, in contrast to the present embodiment, can additionally remove the fourth gate layer from above the dummy rib 320.

[0027] Thus, it Fig. 3A Layout designs for multiple masks are provided that can be used to set the work function of a metal gate for an NSVT cell and an adjacent NLVT cell, wherein the two adjacent cells have a continuous active region. Furthermore, although the various gate layer depositions, the corresponding mask structuring, and the layer ablations (if necessary) have been described in their execution according to a specific sequence, it is understood that other sequences may also be used, and the present disclosure is not intended to be limited to any particular sequence. Moreover, some of the described steps may be omitted or replaced. Furthermore, by performing the above in Fig. In the process described in 3A, the threshold voltage at cell boundary 311 is increased by changing a photomask LOP to reverse a threshold voltage type at cell boundary 311 (for example, at dummy rib 320).

[0028] In Fig. Figure 3B illustrates layout designs 332, 334, 336, and 338. Each of these layout designs contains a first cell 340 and a second cell 342 adjacent to each other along a cell boundary 341. In some examples, the first cell 340 may be an N-type standard threshold voltage (NSVT) cell, and the second cell 342 may be an N-type ultra-low threshold voltage (NULVT) cell. An active region 344 of the first cell 340 and an active region 346 of the second cell 342 may also be adjacent to each other along the cell boundary 341. In some examples, the first cell 340 contains active ribs 348, the second cell 342 contains active ribs 350, and a dummy rib 352 is arranged between the first cell 340 and the second cell 342 along the cell boundary 341.For the sake of clarity, certain structural elements in layout designs 334, 336, and 338, which are essentially the same as structural elements shown and identified in layout design 332, are not again assigned a reference number, but can be referred to in the following discussion using the reference numbers given above.

[0029] Similar to the example described above, a set of separate and individual masks can be used to adjust the work function of a metal layer to achieve a target threshold voltage of the dummy rib 352 at the cell boundary 341. Furthermore, in some embodiments, each of the first gate layer, second gate layer, third gate layer, and fourth gate layer can be essentially the same as described above. Fig. 3A discussed. However, the example of Fig. 3B Layout designs for multiple masks that can be used to set an exit work of a metal gate for an NSVT cell and an adjacent NULVT cell, wherein the two adjacent cells have a continuous active region.

[0030] For example, and with reference to Fig. 3B, the first gate layer can be deposited, and a first mask containing a structure of an opening 354 (shown, for example, in layout design 332) can be used to structure or define a section of the first gate layer to be removed (for example, by means of an etching process). Thus, according to layout design 332, the first gate layer can be removed from the region defined by opening 354 (for example, from above active ribs 348, active ribs 350, and dummy rib 352). Afterward, the second gate layer can be deposited, and a second mask containing a structure of opening 356 and opening 358 (shown, for example, in layout design 334) can be used to structure or define a section of the second gate layer to be removed.Thus, according to layout design 334, the second gate layer can be removed from the region defined by opening 356 (for example, from above the active ribs 348) and opening 358 (for example, from above the active ribs 350), while remaining above the dummy rib 352. At least some prior art processes—in contrast to the present embodiment—can additionally remove the second gate layer from above the dummy rib 352. The third gate layer can then be deposited, and a third mask containing an opening 360 structure (for example, as shown in layout design 336) can be used to structure or define a section of the third gate layer to be removed.Thus, according to layout design 336, the third gate layer can be removed from the region defined by opening 360 (for example, from above the active ribs 350), while remaining above the dummy rib 352 and above the active ribs 348. In some embodiments, the fourth gate layer can then be deposited, and a fourth mask containing a structure of opening 362 (for example, shown in layout design 338) can be used to structure or define a section of the fourth gate layer to be removed. Thus, according to layout design 338, the fourth gate layer can be removed from the region defined by opening 362 (for example, from above the active ribs 348), while remaining above the dummy rib 352 and above the active ribs 350.At least some prior art processes can—in contrast to the present embodiment—additionally remove the fourth gate layer from above the dummy rib 352. Although the various gate layer depositions, the corresponding mask structuring, and the layer removal (if necessary) have been described in their execution according to a specific sequence, it is understood that other sequences may also be used, and the present disclosure is not intended to be limited to any particular sequence. Furthermore, some of the described steps may be omitted or replaced. Moreover, by carrying out the process described above with reference to... Fig. As described in 3B, the threshold voltage at cell boundary 341 is increased by changing a photomask LOP to reverse a threshold voltage type at cell boundary 341 (for example, at dummy rib 352).

[0031] In Fig. 3C illustrates layout design 364, layout design 366, layout design 368, and layout design 370. Each of the layout designs 364, 366, 368, and 370 contains a first cell 372 and a second cell 374 adjacent to each other along a cell boundary 371. In some examples, the first cell 372 can be an N-type low-threshold voltage (NLVT) cell, and the second cell 374 can be an N-type ultra-low-threshold voltage (NULVT) cell. An active region 376 of the first cell 372 and an active region 378 of the second cell 374 can also be adjacent to each other along the cell boundary 371. In some examples, the first cell 372 contains active ribs 380, the second cell 374 contains active ribs 382, ​​and a dummy rib 384 is arranged between the first cell 372 and the second cell 374 along the cell boundary 371.For the sake of clarity, certain structural elements in layout designs 366, 368, and 370, which are essentially the same as structural elements shown and identified in layout design 364, are not again assigned a reference number, but can be referred to in the following discussion using the reference numbers given above.

[0032] Similar to the previous examples, a set of separate and individual masks can be used to adjust the work function of a metal layer to achieve a target threshold voltage of the dummy rib 384 at the cell boundary 371. Furthermore, in some embodiments, each of the first gate layer, second gate layer, third gate layer, and fourth gate layer can be essentially the same as shown above. Fig. 3A discussed. However, the example of Fig. 3C Layout designs for multiple masks that can be used to set an exit work of a metal gate for an NLVT cell and an adjacent NLVT cell, where the two adjacent cells have a continuous active region.

[0033] As in Fig. As shown in 3C, the first gate layer can be deposited, and a first mask containing a structure of an opening 386 (shown, for example, in layout design 364) can be used to structure or define a section of the first gate layer to be removed (for example, by means of an etching process). Thus, according to layout design 364, the first gate layer can be removed from the region defined by opening 386 (for example, from above the active ribs 382 and the dummy rib 382). Afterward, the second gate layer can be deposited, and a second mask containing a structure of opening 388 and opening 390 (shown, for example, in layout design 366) can be used to structure or define a section of the second gate layer to be removed.Thus, according to layout design 366, the second gate layer can be removed from the region defined by opening 388 (for example, from above the active ribs 380) and opening 390 (for example, from above the active ribs 382), while remaining above the dummy rib 384. At least some prior art processes—in contrast to the present embodiment—can additionally remove the second gate layer from above the dummy rib 384. The third gate layer can then be deposited, and a third mask containing a structure of an opening 392 (for example, as shown in layout design 368) can be used to structure or define a section of the third gate layer to be removed.Thus, according to layout design 368, the third gate layer can be removed from the region defined by the opening 392 (for example, from above the active ribs 382), while it remains above the dummy rib 384 and above the active ribs 380. In some embodiments, the fourth gate layer can then be deposited, and a fourth mask containing a structure of an opening 394 (for example, shown in layout design 370) can be used to structure or define a section of the fourth gate layer to be removed. Thus, according to layout design 370, the fourth gate layer can be removed from the region defined by the opening 394 (for example, from above the active ribs 380), while it remains above the dummy rib 384 and above the active ribs 382.At least some prior art processes can—in contrast to the present embodiment—additionally remove the fourth gate layer from above the dummy rib 384. Although the various gate layer depositions, the corresponding mask structuring, and the layer removal (if necessary) have been described in a specific sequence, it is understood that other sequences may also be used, and the present disclosure is not intended to be limited to any particular sequence. Furthermore, some of the described steps may be omitted or replaced. Moreover, by performing the above in . Fig. The process described in 3C increases the threshold voltage at cell boundary 371 by changing a photomask LOP to reverse a threshold voltage type at cell boundary 371 (for example, at dummy rib 384).

[0034] We continue with embodiments in which the threshold voltage at the cell boundary is increased by changing a photomask LOP to reverse a threshold voltage type at the cell boundary (for example, by adjusting the exit work metal and / or a gate dielectric layer). For this, we now turn to the Fig. 4A, Fig. 4B and Fig. 4C to. Various aspects of the Fig. 4A, Fig. 4B and Fig. 4C are similar to the examples discussed above. Fig. 3A, Fig. 3B and Fig. 3C. For example, each of the first gate layer, the second gate layer, the third gate layer, and the fourth gate layer, which are related to the Fig. 4A, Fig. 4B and Fig. 4C will be discussed, essentially the same as above. Fig. 3A was discussed. For clarity, certain structural elements, essentially the same as those shown and described above, will now be briefly discussed, while we focus on the differences that exist in the Fig. 4A, Fig. 4B and Fig. 4C can be seen. In particular, the Fig. 4A, Fig. 4B and Fig. 4C layout designs that can be used to set an exit work of a metal gate for different pairs of adjacent P-type cells that have a continuous active region.

[0035] We turn first Fig. Figure 4A illustrates layout designs 400, 402, 404, and 406. Each of the layout designs 400, 402, 404, and 406 contains a first cell 408 and a second cell 410 adjacent to each other along a cell boundary 411. In some examples, the first cell 408 may be a P-type standard threshold voltage (PSVT) cell, and the second cell 410 may be a P-type low threshold voltage (PLVT) cell. An active region 412 of the first cell 408 and an active region 414 of the second cell 410 may also be adjacent to each other along the cell boundary 411. In some examples, the first cell 408 contains active ribs 416, the second cell 410 contains active ribs 418, and a dummy rib 420 is arranged between the first cell 408 and the second cell 410 along the cell boundary 411.For the sake of clarity, certain structural elements in layout designs 402, 404, and 406, which are essentially the same as structural elements shown and identified in layout design 400, are not again assigned a reference number, but can be referred to in the following discussion using the reference numbers given above.

[0036] As also in Fig. As shown in Figure 4A, the first gate layer can be deposited, and a first mask containing the structure of an opening 422 (for example, as shown in layout design 400) can be used to structure or define a section of the first gate layer to be removed. Thus, according to layout design 400, the first gate layer can be removed from the region defined by the opening 422 (for example, from above the active ribs 416) while remaining above the dummy rib 420. At least some prior art processes—in contrast to the present embodiment—can additionally remove the first gate layer from above the dummy rib 420.The second gate layer can then be deposited, and a second mask containing the structure of an opening 424 (shown, for example, in layout design 402) can be used to structure or define a section of the second gate layer to be removed. Thus, according to layout design 402, the second gate layer can be removed from the region defined by opening 424 (for example, from above active ribs 416 and from above dummy rib 420). The third gate layer can then be deposited, and a third mask containing the structure of an opening 426 (shown, for example, in layout design 404) can be used to structure or define a section of the third gate layer to be removed.Thus, according to layout design 404, the third gate layer can be removed from the region defined by the opening 426 (for example, from above the dummy rib 420), while remaining over the active ribs 416, 418. At least some prior art processes—in contrast to the present embodiment—do not require the third gate layer to be removed from above the dummy rib 420. In some embodiments, the fourth gate layer can then be deposited, and a fourth mask containing a structure of an opening 428 (for example, as shown in layout design 406) can be used to structure or define a section of the fourth gate layer to be removed.Thus, according to layout design 406, the fourth gate layer can be removed from the region defined by opening 428 (for example, from above dummy rib 420), while remaining above active ribs 416, 418. At least some prior art processes—in contrast to the present embodiment—do not require removing the fourth gate layer from above dummy rib 420. Although the various gate layer depositions, the corresponding mask structuring, and the layer removal (if necessary) have been described in a specific sequence, it is understood that other sequences may also be used, and the present disclosure is not intended to be limited to any particular sequence. Furthermore, some of the described steps may be omitted or replaced. Moreover, by performing the steps described in 406, the process can be further refined. Fig. 4A In the process described above, the threshold voltage at cell boundary 411 is increased by changing a photomask LOP to reverse a threshold voltage type at cell boundary 411 (for example, at dummy rib 420).

[0037] We now turn Fig. Figure 4B illustrates layout designs 432, 434, 436, and 438. Each of the layout designs 432, 434, 436, and 438 contains a first cell 440 and a second cell 442 adjacent to each other along a cell boundary 441. In some examples, the first cell 440 may be a P-type standard threshold voltage (PSVT) cell, and the second cell 442 may be a P-type ultra-low threshold voltage (PULVT) cell. An active region 444 of the first cell 440 and an active region 446 of the second cell 442 may also be adjacent to each other along the cell boundary 441. In some examples, the first cell 440 contains active ribs 448, the second cell 442 contains active ribs 450, and a dummy rib 452 is arranged between the first cell 440 and the second cell 442 along the cell boundary 441.For the sake of clarity, certain structural elements in layout designs 434, 436, and 438, which are essentially the same as structural elements shown and identified in layout design 432, are not again assigned a reference number, but can be referred to in the following discussion using the reference numbers given above.

[0038] As further explained in Fig. As shown in Figure 4B, the first gate layer can be deposited, and a first mask containing a structure of an opening 453 and an opening 454 (for example, shown in layout design 432) can be used to structure or define a section of the first gate layer to be removed. Thus, according to layout design 432, the first gate layer can be removed from the region defined by opening 453 (for example, from above the active ribs 448) and by opening 454 (for example, from above the active ribs 450), while remaining above the dummy rib 452. At least some prior art processes can—in contrast to the present embodiment—additionally remove the first gate layer from above the dummy rib 452.The second gate layer can then be deposited, and a second mask containing the structure of an opening 456 (shown, for example, in layout design 434) can be used to structure or define a section of the second gate layer to be removed. Thus, according to layout design 434, the second gate layer can be removed from the region defined by opening 456 (for example, from above the active ribs 448 and from above the dummy rib 452). The third gate layer can then be deposited, and a third mask containing the structure of an opening 460 (shown, for example, in layout design 436) can be used to structure or define a section of the third gate layer to be removed.Thus, according to layout design 436, the third gate layer can be removed from the region defined by the opening 460 (for example, from above the dummy rib 452), while remaining above the active ribs 448, 450. At least some prior art processes—in contrast to the present embodiment—do not require the third gate layer to be removed from above the dummy rib 452. In some embodiments, the fourth gate layer can then be deposited, and a fourth mask containing a structure of an opening 462 (for example, as shown in layout design 438) can be used to structure or define a section of the fourth gate layer to be removed.Thus, according to the layout design 438, the fourth gate layer can be removed from the region defined by the opening 462 (for example, from above the dummy rib 452), while remaining above the active ribs 448, 450. At least some prior art processes—in contrast to the present embodiment—do not require the fourth gate layer to be removed from above the dummy rib 452. Although the various gate layer depositions, the corresponding mask structuring, and the layer removal (if necessary) have been described in a specific sequence, it is understood that other sequences may also be used, and the present disclosure is not intended to be limited to any particular sequence. Furthermore, some of the described steps may be omitted or replaced. Moreover, by performing the above in . Fig. In the process described in 4B, the threshold voltage at cell boundary 441 is increased by changing a photomask LOP to reverse a threshold voltage type at cell boundary 441 (for example, at dummy rib 452).

[0039] In Fig. Figures 4C illustrate layout designs 464, 466, 468, and 470. Each of these layout designs contains a first cell 472 and a second cell 474 adjacent to each other along a cell boundary 471. In some examples, the first cell 472 may be a P-type low-threshold voltage (PLVT) cell, and the second cell 474 may be a P-type ultra-low-threshold voltage (PULVT) cell. An active region 476 of the first cell 472 and an active region 478 of the second cell 474 may also be adjacent to each other along the cell boundary 471. In some examples, the first cell 472 contains active ribs 480, the second cell 474 contains active ribs 482, and a dummy rib 484 is arranged between the first cell 472 and the second cell 474 along the cell boundary 471.For the sake of clarity, certain structural elements in layout designs 466, 468, and 470, which are essentially the same as structural elements shown and identified in layout design 464, are not again assigned a reference number, but can be referred to in the following discussion using the reference numbers given above.

[0040] As also in Fig. As shown in diagram 4C, the first gate layer can be deposited, and a first mask containing a structure of an opening 486 (shown, for example, in layout design 464) can be used to structure or define a section of the first gate layer to be removed. Thus, according to layout design 464, the first gate layer can be removed from the region defined by the opening 486 (for example, from above the active ribs 482), while remaining above the dummy rib 484 and above the active ribs 480. Afterward, the second gate layer can be deposited, and a second mask containing a structure of an opening 488 (shown, for example, in layout design 466) can be used to structure or define a section of the second gate layer to be removed.Thus, according to layout design 466, the second gate layer can be removed from the region defined by the opening 488 (for example, from above the dummy rib 484), while remaining over the active ribs 480, 482. At least some prior art processes—in contrast to the present embodiment—do not require removing the second gate layer from above the dummy rib 484. The third gate layer can then be deposited, and a third mask containing a structure of an opening 490 (for example, as shown in layout design 468) can be used to structure or define a section of the third gate layer to be removed. Thus, according to layout design 468, the third gate layer can be removed from the region defined by the opening 490 (for example, from above the dummy rib 484), while remaining over the active ribs 480, 482.At least some prior art processes—unlike the present embodiment—do not require the removal of the third gate layer from above the dummy rib 484. In some embodiments, the fourth gate layer can then be deposited, and a fourth mask containing an opening 492 structure (shown, for example, in layout design 470) can be used to structure or define a section of the fourth gate layer to be removed. Thus, according to layout design 470, the fourth gate layer can be removed from the region defined by the opening 492 (for example, from above the dummy rib 484) while remaining above the active ribs 480 and 482. At least some prior art processes—unlike the present embodiment—do not require the removal of the fourth gate layer from above the dummy rib 484.Although the various gate layer depositions, the corresponding mask structuring, and the layer removal (if necessary) have been described in a specific order, it is understood that other orders may also be used, and the present disclosure is not intended to be limited to any particular order. Furthermore, some of the described steps may be omitted or replaced. Moreover, by performing the above in . Fig. In the process described in 4C, the threshold voltage at cell boundary 471 is increased by changing a photomask LOP to reverse a threshold voltage type at cell boundary 474 (for example, at dummy rib 484).

[0041] Fig. Figure 5 illustrates a Method 500 for fabricating a semiconductor device containing a FinFET device. Method 500 can be used to modify a photomask LOP to introduce a threshold voltage type at a cell boundary, for example, using one or more of the masks and mask sequences described above with reference to the Fig. 3A, Fig. 3B, Fig. 3C, Fig. 4A, Fig. 4B and Fig. 4C described, to reverse. In some embodiments, method 500 can be used to manufacture component 100 or component 250 as described above. Thus, one or more of the aspects discussed above may also apply to method 500.

[0042] Procedure 500 begins at block 502, where a substrate containing ribs and recessed insulating regions is provided. In various examples, the substrate, ribs, and recessed insulating regions may be essentially the same as those shown above. Fig. 1 and Fig. 2B described. The process proceeds to block 504, where a gate layer is deposited. In some embodiments, the deposited gate layer may include a layer deposited during the formation of gate 216 or gate structure 108, as described above. In some embodiments, the deposited gate layer includes the first gate layer, the second gate layer, the third gate layer, or the fourth gate layer, as described above with reference to the Fig. 3A, Fig. 3B, Fig. 3C, Fig. 4A, Fig. 4B and Fig. 4C described. The method proceeds to block 506, where a photoresist layer is deposited over the gate layer and the photoresist layer is structured using a mask. In some embodiments, the photoresist layer can be structured (for example, by a photolithography process) using a mask that has a structure defining an opening (for example, in the photoresist layer), wherein the opening defines a section of the deposited gate layer to be removed. The method proceeds to block 508, where a section of the deposited gate layer is removed from a region exposed by the structured opening in the photoresist layer to form a structured deposited gate layer.In some examples, the portion of the deposited gate layer can be removed by an etching process (for example, a wet etching process, a dry etching process, or a combination thereof). In some cases, after the etching process, the structured photoresist layer can be removed (for example, by means of a solvent). In some embodiments, after the removal of the portion of the deposited gate layer (block 508), the process 500 can be continued at block 504, as indicated by a dashed line 510, depositing another gate layer. The process of depositing another gate layer, structuring a photoresist layer formed over the gate layer using a mask, and removing a portion of the layer can be continued until a target work function and thus a target threshold voltage is achieved.Additional process steps may be implemented before, during and after Method 500, and some of the process steps described above may be substituted or omitted according to different embodiments of Method 500.

[0043] In some embodiments, the insulation between adjacent cells can be improved by increasing a threshold voltage at the cell boundary, for example by performing a threshold voltage implantation (e.g., an ion implantation) at the cell boundary and into the dummy rib located at the cell boundary. Fig. Figure 6 illustrates a method 600 for fabricating a semiconductor device containing a FinFET device. Method 600 can be used to increase a threshold voltage at the cell boundary, for example, by performing a threshold voltage implantation at the cell boundary. In some embodiments, method 600 can be used to fabricate device 100 or device 250, as described above. Thus, one or more of the aspects discussed above may also apply to method 600. Furthermore, Figure 6 shows Fig. 7-11 Cross-sectional views of an exemplary component 700, manufactured according to one or more steps of the method 600 of Fig. 6 is produced.

[0044] Procedure 600 begins at block 602, where a substrate containing ribs and recessed insulating regions is provided. Referring to the example of Fig. Figure 7 includes the component 700 in one embodiment of block 602, active ribs 710, 712, a dummy rib 714, a recessed STI region 718, and a substrate 720. In various examples, the substrate 720, the active ribs 710, 712, the dummy rib 714, and the recessed STI region 718 can be substantially the same as those shown above. Fig. 1 and Fig. 2B described. Fig. Figure 7 also illustrates a first cell 702 and a second cell 704, which are adjacent to each other along a cell boundary 711. The process proceeds to block 604, where a photoresist layer is deposited and structured. Referring to the example of Fig. In one embodiment of block 604, a structured photoresist layer 715 is formed over the substrate 720. In some examples, a photoresist layer is first deposited (for example, by spin deposition, evaporation, or another suitable method). After deposition, the photoresist layer can be exposed with a structure, a post-exposure firing process can be performed, and the exposed photoresist layer is developed to form the structured photoresist layer 715. In some embodiments, the photoresist layer can be exposed using an electron beam (E-beam) lithography process, an EUV lithography process, an immersion lithography process, or another suitable process. As in Fig. As shown in Figure 8, the structured photoresist layer 715 was structured to expose the dummy rib 714 along the cell boundary 711, while the active ribs 710, 712 remain covered by the structured photoresist layer 715. The procedure proceeds to block 606, where a threshold voltage implantation is performed. Referring to the example of Fig. In one embodiment of block 606, a threshold voltage (V) is used. t )-implantation 722 is performed to provide an ion-implanted dummy rib 714A. In various embodiments, the V t-Implantation 722, for example, can be carried out using an ion implantation process and employing a suitable N-type or P-type dopant. In some embodiments, the N-type dopant contains arsenic, phosphorus, antimony, or other N-type donor material. In some embodiments, the P-type dopant contains boron, BF2, aluminum, gallium, indium, or other P-type acceptor material. In some cases, an N-type dopant can be used as a PV t -Implant can be used, meaning that the N-type dotand can be implanted into dummy rib 714 if the active ribs 710 and 712 are P-type. Likewise, and in some cases, a P-type dotand can be used as a V t -Implant can be used, which means that the P-type dot and can be implanted into dummy rib 714 if the active ribs 710 and 712 are N-type ribs. In some embodiments, the V t-Implantation of 722 using BF2 with a dosage of more than approximately 3.3 x 10 13 executed. In some examples, the V t -Implantation 722 using phosphorus with a dosage of more than approximately 4.5 x 10 13 executed. In some cases, the V t -Implantation 722 increases the threshold voltage of the dummy rib 714 by more than approximately 70 mV. In some cases, the V t -Implantation 722 reduces the leakage current at the cell boundary 711 by more than an order of magnitude. In various embodiments, the V t-Implantation 722 can be performed during a channel implantation step, an LDD implantation step, or any other suitable implantation step. In some cases, after the ion implantation process, the semiconductor device 700 may be subjected to high-temperature curing to remove defects and activate dopants (i.e., to place dopants at substitution sites). The process proceeds to block 608, where the structured photoresist layer is removed. Referring to the example of the Fig. 9 and Fig. In one embodiment of block 608, the structured photoresist layer 715 was removed, for example, using a solvent. The process proceeds to block 610, where a gate stack is formed. Referring to the example of Fig. 10 and Fig. In one embodiment of block 610, a gate stack 716 is formed over the active ribs 710, 712 and over the ion-implanted dummy rib 714A. In some embodiments, the gate stack 716 may resemble the gate 216 or the gate structure 108 as described above. Furthermore, in some cases, the gate stack 716 may contain one or more metallic and / or dielectric layers that provide a suitable work function for the specific device type (for example, N-type or P-type). Thus, although the device 700 may contain adjacent active regions of the same type (for example, N-type or P-type), the leakage current at the cell boundary 711 is significantly reduced due to the increased threshold voltage of the ion-implanted dummy rib 714A. Or to put it another way: The ion-implanted dummy rib 714A serves to improve the insulation between the adjacent first and second cells 702, 704.

[0045] The semiconductor device 700 can undergo further processing to form various structural elements and regions known in the prior art. For example, subsequent processing can form a gate stack, sidewall spacers, source / drain regions, various contacts, vias or traces, and multilayer interconnect structural elements (for example, metal layers and interlayer dielectrics) on the substrate 720, configured to connect the various structural elements to form a functional circuit that can contain one or more FinFET devices. Continuing with this example, a multilayer interconnect can include vertical interconnect connections, such as vias or contacts, and horizontal interconnect connections, such as metal traces.The various interconnect structural elements can utilize different conductive materials, including copper, tungsten, and / or silicide. In one example, a damascene and / or dual-damascene process is used to form a copper-based multilayer interconnect structure. Furthermore, additional process steps can be implemented before, during, and after Process 600, and some of the process steps described above can be substituted or omitted according to different embodiments of Process 600.

[0046] In some examples, the insulation between adjacent cells can be improved by increasing a threshold voltage at the cell boundary, for example, by using a silicon-germanium (SiGe) channel at the cell boundary. In some cases, the SiGe can be located within the substrate at the cell boundary, and / or the SiGe can be part of the dummy rib located at the cell boundary. For example, [illustrates] Fig. 12 a layout design 1200 of the two adjacent FinFET cells. In particular, a first cell 1202 and a second cell 1204 are adjacent to each other along a cell boundary 1211. The layout design 1200 is similar to the layout design 200 of Fig. 2A, as discussed above. However, as in Fig. As shown in Figure 12, a SiGe region 1215 is formed between an active region 1206 of the first cell 1202 and an active region 1208 of the second cell 1204. The layout design 1200 also includes active ribs 1210 and active ribs 1212 in each of the first cell 1202 and the second cell 1204, respectively. Additionally, a dummy rib 1214 is formed between the first cell 1202 and the second cell 1204 along the cell boundary 1211. In some embodiments, the dummy rib 1214—or at least a portion of the dummy rib containing the FinFET channel—can contain SiGe from the SiGe region 1215. Alternatively, in some examples, the dummy rib 1214 can contain a different material than the SiGe substrate portion over which it is arranged. A gate 1216 extending over the first cell 1202 and the second cell 1204 is also illustrated. In some embodiments, the SiGe region 1215 can be made of Si (1-x) Ge xare formed where “x” is a percentage of Ge and where “x” is greater than 0% and less than 100%. For example, and in at least some embodiments, the SiGe region 1215 can be 30% Ge (Si 0,7 Ge 0,3) which increases the threshold voltage of the dummy rib 1214 by approximately 52 mV. In some cases, the use of SiGe at the cell boundary can reduce the leakage current at the cell boundary 1211 by approximately 0.36X. For the avoidance of misunderstandings, it should be noted that the embodiments disclosed herein are not intended to be limited to a specific percentage of Ge content in the SiGe region 1215, and the examples given herein are for illustrative purposes only. In various examples, the Ge content in the SiGe region 1215 can be adjusted to achieve a desired threshold voltage (for example, of the dummy rib 1214) and a desired leakage current at the cell boundary 1211. In some examples, the SiGe region 1215 can be implemented at the cell boundary 1211 of adjacent N-type cells.In some embodiments, the SiGe region 1215 has a width of approximately 48 nm, which in some cases may be approximately equal to a single poly center-to-center distance.

[0047] In Fig. Figure 13 illustrates a method 1300 for fabricating a semiconductor device containing a FinFET device. Method 1300 can be used to increase a threshold voltage at the cell boundary, for example, by using a silicon-germanium (SiGe) channel at the cell boundary. In some embodiments, method 1300 can be used to fabricate device 100 or device 250, as described above. Thus, one or more of the aspects discussed above may also apply to method 1300. Furthermore, the Fig. 14-19 Cross-sectional views of an exemplary device 1400, which essentially follows the section line DD' of Fig. 12 corresponds to which, according to one or more steps of procedure 1300 of Fig. 13 is produced.

[0048] Procedure 1300 begins at block 1302, where a substrate is provided. Referring to the example of Fig. In one embodiment of block 1302, a substrate 1402 is provided. In some embodiments, the substrate 1402 may be essentially the same as described above. Fig. 1 and Fig. 2B described. In various examples, the substrate 1402 can contain a first cell region 1404 and a second cell region 1406, which are adjacent to each other along a cell boundary 1411. The process proceeds to block 1304, where a recess is formed within the substrate at a cell boundary. Referring to the example of Fig. In one embodiment of block 1304, a recess 1502 is formed within the substrate 1402 at the cell boundary 1411. In some embodiments, the recess 1502 can be formed by a photolithography and etching process. In some cases, the recess 1502 defines a SiGe region, as discussed in more detail below. The process proceeds to block 1306, where a SiGe layer is formed within the recess. Referring to the example of Fig. In one embodiment of block 1306, a SiGe layer 1602 is formed within the recess 1502 at the cell boundary 1411. In various embodiments, the SiGe layer 1602 can be grown epitaxially within the recess 1502. In some embodiments, the SiGe layer 1602 can be composed of Si (1-x) Ge xare formed as described above. The process progresses to block 1308, where ribs are formed within the substrate. Referring to the example of the Fig. 16 and Fig. In one embodiment of block 1308, active ribs 1702 are formed within the substrate 1402 and within the first cell region 1404, active ribs 1704 are formed within the substrate 1402 and within the second cell region 1406, and a dummy rib 1706 is formed within the SiGe layer 1602 along the cell boundary 1411. In some embodiments, the active ribs 1702, 1704, and the dummy rib 1706 can be arranged as above with reference to the Fig. 1 described. In some cases, the etching process used to form recesses in the SiGe layer 1602 to form the SiGe dummy rib 1706 may etch down to a base 1604 of the recess 1502. The process proceeds to block 1310, where an STI region is formed. Referring to the example of the Fig. 17 and Fig. In one embodiment of block 1310, an STI region 1802 is formed. In some cases, the STI region 1802 contains a recessed STI region. Furthermore, in some embodiments, the recessed STI region 1802 may be substantially the same as that shown above. Fig. 1 and Fig. 2B described. The process progresses to block 1312, where a gate stack is formed. Referring to the example of the Fig. 18 and Fig.In one embodiment of block 1312, a gate stack 1902 is formed over the active ribs 1702, 1704 and over the SiGe dummy rib 1706. In some embodiments, the gate stack 1902 may resemble the gate 216 or the gate structure 108, as described above. Furthermore, in some cases, the gate stack 1902 may contain one or more metallic and / or dielectric layers that provide a suitable work function for the device type in question (for example, N-type or P-type). Thus, although adjacent active regions (for example, the first and second cell regions 1404, 1406) of the same type (for example, N-type or P-type) may be present upstream of device 1400, the leakage current at the cell boundary 1411 is significantly reduced due to the increased threshold voltage of the SiGe layer 1602 and the SiGe dummy rib 1706.Or to put it another way: The SiGe layer 1602 and the SiGe dummy rib 1706 serve to improve the insulation between the adjacent first and second cell regions 1404, 1406.

[0049] The semiconductor device 1400 can undergo further processing to form various structural elements and regions known in the prior art. For example, in subsequent processing, a gate stack, sidewall spacers, source / drain regions, various contacts, vias or traces, and multilayer interconnect structural elements (e.g., metal layers and interlayer dielectrics) can be formed on the substrate 1402. These elements are configured to connect the various structural elements to form a functional circuit that can contain one or more FinFET devices. Continuing with this example, a multilayer interconnect can include vertical interconnect connections, such as vias or contacts, and horizontal interconnect connections, such as metal traces.The various interconnect structural elements can utilize different conductive materials, including copper, tungsten, and / or silicide. In one example, a damascene and / or dual-damascene process is used to form a copper-based multilayer interconnect structure. Furthermore, additional process steps can be implemented before, during, and after Process 1300, and some of the process steps described above can be substituted or omitted according to different embodiments of Process 1300.

[0050] The various embodiments described in this text offer several advantages over the prior art. It is understood that not all advantages have necessarily been discussed in this text, that no particular advantage is required for all embodiments, and that other embodiments may offer different advantages. For example, embodiments discussed in this text include methods and structures for reducing leakage current in devices containing a continuous active region. In various embodiments, the insulation between adjacent cells, and thus the insulation between adjacent active regions, is improved by increasing a threshold voltage at the cell boundary.In some embodiments, the threshold voltage at the cell boundary is increased by modifying a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary (for example, from N-type to P-type or from P-type to N-type). In some examples, such a threshold voltage reversal or adjustment can generally be achieved by adjusting the exit work metal and / or a gate dielectric layer. Alternatively, in some cases according to the invention, the threshold voltage at the cell boundary is increased by performing a threshold voltage implantation (for example, an ion implantation) at the cell boundary and into the dummy rib located at the cell boundary. Furthermore, in some embodiments according to the invention, the threshold voltage at the cell boundary is increased by using a silicon-germanium (SiGe) channel at the cell boundary.In some cases, the SiGe can be located within the substrate at the cell boundary, and / or the SiGe can be part of the dummy rib located at the cell boundary. Therefore, embodiments of the present disclosure provide improved insulation and thus a reduced leakage current between adjacent cells that have adjoining active regions.

[0051] In another embodiment, a method is discussed that includes providing a substrate containing a first active region and a second active region adjacent to the first active region at a boundary. In some embodiments, a first rib is formed within the first active region, a second rib is formed within the second active region, and a dummy rib is formed along the boundary. In various examples, a photoresist layer is deposited and structured to expose the dummy rib, while the first and second ribs remain covered by the structured photoresist layer. In some cases, threshold voltage implantation is performed through the structured photoresist layer into the dummy rib to provide an ion-implanted dummy rib.In some embodiments, a gate stack is formed over the first rib, the second rib, and the ion-implanted dummy rib.

[0052] In another embodiment, a method is discussed that includes providing a substrate containing a first cell region and a second cell region adjacent to the first cell region at a cell boundary. In some embodiments, a recess is formed within the substrate at the cell boundary. In some examples, a silicon-germanium (SiGe) layer is deposited within the recess at the cell boundary. In various cases, a first active rib is formed within the substrate and within the first cell region, a second active rib is formed within the substrate and within the second cell region, and a dummy rib is formed within the SiGe layer along the cell boundary. In some embodiments, a gate stack is formed over the first active rib, the second active rib, and a channel region of the dummy rib.

Claims

[1] Method (600) comprising the following: Providing (602) a substrate (720) having a first active region (702) and a second active region (704) adjacent to the first active region (702) at a boundary (711); Forming a first rib (710) within the first active region (702), a second rib (712) within the second active region (702), and a dummy rib (714) along the border (711); Deposition of a photoresist layer (715) and structuring of the photoresist layer to expose the dummy rib (714) while the first rib (710) and the second rib (712) remain covered by the structured photoresist layer (715); Performing a threshold voltage implantation (722) through the structured photoresist layer (715) into the dummy rib to provide an ion-implanted dummy rib (714A); and Forming a gate stack (716) over the first rib (710), the second rib (712) and the ion-implanted dummy rib (714A). [2] Method according to claim 1, wherein the first active region (702) and the second active region (704) both contain an N-type active region, or wherein the first active region (702) and the second active region (704) both contain a P-type active region. [3] Method according to claim 1, wherein performing the threshold voltage implantation (722) includes the implantation of an N-type dopant containing at least one of arsenic, phosphorus and antimony. [4] Method according to claim 1, wherein performing the threshold voltage implantation (722) includes the implantation of a P-type dopant containing at least one of boron, BF2, aluminium, gallium and indium. [5] Method according to any one of claims 1 to 4, wherein the threshold voltage implantation (722) increases the threshold voltage of the dummy rib (714) by more than about 70 mV. [6] Method according to any one of claims 1 to 5, further comprising: following threshold voltage implantation (722), perform high-temperature curing. [7] Procedure (1300) comprising the following: Providing (1302) a substrate (1402) comprising a first cell region (1404) and a second cell region (1406) adjacent to the first cell region at a cell boundary (1411); Forming (1304) a recess (1502) within the substrate (1402) at the cell boundary (1411); Deposition (1306) of a silicon germanium (SiGe) layer (1602) within the recess (1502) at the cell boundary (1411); Forming (1308) a first active rib (1702) within the substrate (1402) and within the first cell region (1404), a second active rib (1704) within the substrate (1402) and within the second cell region (1406), and a dummy rib (1706) within the SiGe layer (1602) along the cell boundary (1411); and Forming (1312) a gate stack (1902) over the first active rib (1702), the second active rib (1704) and a canal region of the dummy rib (1706). [8] Method according to claim 7, wherein the SiGe layer (1602) contains about 30% Ge (Si 0,7 Ge 0,3 ) contains. [9] Method according to claim 70 or 8, wherein the first cell region (1404) and the second cell region (1406) both contain an N-type region. [10] Method according to any one of claims 7 to 9, wherein the formation of the dummy rib (1706) within the SiGe layer (1602) along the cell boundary (1411) serves to improve the insulation between the first cell region (1404) and the second cell region (1406) by increasing the threshold voltage there. [11] Method according to any one of claims 7 to 10, further comprising: prior to the formation of a gate stack (1902), the formation of an STI region (1802) on the substrate (1402).

Images