Semiconductor device and method of forming the same

Abstract

Embodiments of the present invention provide a semiconductor device and a method for forming the same. The semiconductor device includes first, second, third, fourth, and fifth active regions extending longitudinally along a first direction. The first and fifth active regions extend completely across a first cell and an adjacent second cell. The second, third, and fourth active regions partially extend across the first and second cells and are disposed between the first and fifth active regions along a second direction. The device includes a first gate stack connected to the first and second active regions, and second and third gate stacks connected to the fourth and fifth active regions. The second gate stack extends along the second direction between the first and third gate stacks. The spacing between the first and second gate stacks spans a first distance, and the spacing between the second and third gate stacks spans a second distance, with the second distance being greater than the first distance.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of semiconductors, and more specifically, to semiconductor devices and methods of forming the same. Background Technology

[0002] The electronics industry's demand for increasingly smaller and faster electronic devices capable of supporting a growing number of complex and sophisticated functions is constantly evolving. To meet these demands, the manufacture of low-cost, high-performance, and low-power integrated circuits (ICs) has been a persistent trend in the semiconductor industry. To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., the smallest feature size), thereby improving production efficiency and reducing associated costs. However, the miniaturization of component dimensions also increases the complexity of the IC manufacturing process. Therefore, continued advancements in IC devices and their performance require similar advancements in IC manufacturing processes and technologies.

[0003] One advancement is the use of nanostructure designs in memory devices. However, as transistor pitch decreases, memory devices may encounter reliability and performance issues. For example, smaller pitch at smaller technology nodes can lead to reduced structural integrity, poorer epitaxial growth, and increased gate-to-gate leakage.

[0004] Therefore, although existing memory device structures and layouts can generally meet their intended uses, they are not satisfactory in every respect. Summary of the Invention

[0005] An embodiment of the present invention provides a semiconductor device, comprising: a first active region, a second active region, a third active region, a fourth active region, and a fifth active region, extending longitudinally along a first direction, wherein the first active region and the fifth active region completely extend across a first unit and an adjacent second unit, wherein the second active region, the third active region, and the fourth active region partially extend across the first unit and the second unit, and are disposed between the first active region and the fifth active region along a second direction different from the first direction; a first gate stack, connected to the first active region and the second active region, the first gate stack extending longitudinally above the first unit along the second direction; a second gate stack, connected to the fifth active region, extending longitudinally above the first unit along the second direction; and a third gate stack, connected to the first active region, extending longitudinally above the first unit along the second direction. A quad gate stack is connected to the fourth and fifth active regions, the fourth gate stack extending longitudinally over the first unit along the second direction; a fifth gate stack is connected to the first active region, the fifth gate stack extending longitudinally over the second unit along the second direction; and a sixth gate stack is connected to the fourth and fifth active regions, the sixth gate stack extending longitudinally over the second unit along the second direction, wherein an isolation dielectric member is connected to the end portions of one or more of the second, third, and fourth active regions; wherein the fourth gate stack extends between the first and sixth gate stacks, wherein, along the first direction, the spacing between the first and fourth gate stacks spans a first distance, the spacing between the fourth and sixth gate stacks spans a second distance, and the second distance is greater than the first distance.

[0006] Another embodiment of the present invention provides a semiconductor device, comprising: a first unit having: a first active region and a second active region extending longitudinally along a first direction, wherein the second active region extends a greater length than the first active region; a first gate stack extending along a second direction different from the first direction, the first gate stack being connected to a first channel region of the first active region and the first channel region of the second active region; a second gate stack extending along the second direction, the second gate stack being connected to a second channel region of the second active region; and a third gate stack extending along the second direction, the third gate stack having a gate end portion adjacent to a first edge of the first active region; and a second unit having: the first active region and the second active region extending longitudinally along the first direction. Extending in the second direction, in the second unit, the second active region extends a greater length than the first active region; a fourth gate stack extends along the second direction, the fourth gate stack being connected to the second channel region of the first active region and the third channel region of the second active region; a fifth gate stack extends along the second direction, the fifth gate stack being connected to the fourth channel region of the second active region; and a sixth gate stack extends along the second direction, the sixth gate stack having a gate end portion adjacent to the second edge of the first active region, wherein the first active region between the first gate stack and the third gate stack spans a first distance, the first active region between the first gate stack and the fourth gate stack spans a second distance, and the second distance is greater than the first distance.

[0007] Another embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a plurality of active regions above a substrate, the plurality of active regions extending longitudinally along a first direction; forming a plurality of gates above a plurality of channel regions of the plurality of active regions, the plurality of gates extending longitudinally along a second direction different from the first direction, wherein each of the plurality of gates includes a protruding portion, the protruding portion causing an asymmetric gate spacing along the first direction; forming a gate dicing member cutting across the plurality of gates along the first direction and at the end portion of the protruding portion at one or more interfaces; and forming a plurality of source / drain contacts and a plurality of vias above a plurality of source / drain members of the plurality of active regions, wherein the plurality of source / drain members have an asymmetric width corresponding to the asymmetric gate spacing. Attached Figure Description

[0008] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0009] Figure 1 The diagram shows a circuit diagram of a static random access memory array according to an embodiment of the present invention.

[0010] Figure 2 A flowchart is shown of a method 1000 for forming a portion or the entirety of a memory device having asymmetric gate spacing according to an embodiment of the present invention.

[0011] Figure 3 , Figure 4 , Figure 5 , Figure 6 This illustrates an embodiment of the invention, during an intermediate stage of manufacturing and corresponding to... Figure 2 The flowchart shows the top-view device layout of the static random access memory array.

[0012] Figure 7A and Figure 7B This illustrates an embodiment of the invention, showing the following along... Figure 6 A cross-sectional diagram of a static random access memory array, showing the cuts along lines A-A' and B-B'.

[0013] Figure 8A and Figure 8B This illustrates an embodiment of the invention, along... Figure 6 A cross-sectional diagram of a static random access memory array, taken from line A-A'.

[0014] Figure 9 , Figure 10 , Figure 11 , Figure 12 Top-view device layouts of various static random access memory arrays having asymmetric gate spacing according to various embodiments of the present invention are shown. Detailed Implementation

[0015] This invention provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] Furthermore, when using terms such as "approximately," "about," "roughly," and similar terms to describe numbers or ranges of numbers, the purpose of these terms is to cover numbers within a reasonable range that includes the described number, such as within + / - 10% of the described number, or other values ​​understood by those skilled in the art. For example, the term "approximately 5 nm" may cover 4.5 nm to 5.5 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 10%. Furthermore, when comparing the dimensions or sizes of one component and another, the terms "substantially the same," "essentially the same," "similar in size," and similar terms may be understood to mean within + / - 10% of the dimensions of the compared components. It should be noted that those skilled in the art will understand that other values ​​may exist and may depend on the process. Furthermore, the disclosed dimensions of different components may implicitly reveal the size ratios between the different components.

[0018] Memory devices, such as static random-access memory (SRAM) devices, have become popular storage units in high-speed communications, image processing, and system-on-chip (SoC) products. To meet the demands of continuously miniaturizing component sizes and optimizing power consumption, SRAM devices have begun to employ nanostructured transistors, such as gate-all-around (GAA) transistors. However, due to the inherent layout of SRAM cell structures, the metal gate may fall in areas directly adjacent to the edges of p-type active regions. These p-type active regions form the pull-up transistors of the SRAM device. The close proximity of the metal gate to these active region edges... Proximity can lead to uneven landing due to variations in surface topography. This, in turn, causes bending of the respective metal gates, resulting in reduced space between adjacent metal gates at the Vcc node (the source end of adjacent pull-up transistors). This results in smaller spacing for forming source epitaxial components at the Vcc node, potentially leading to performance degradation. In some all-around gate designs, smaller spacing can cause oxide residue at the bottom of the source / drain trenches when forming a disposable oxide interposer. Oxide residue can cause poor epitaxial growth and may further lead to inter-gate short circuits during metal gate replacement of the disposable oxide interposer.

[0019] For this and other reasons, embodiments of the present invention provide a static random access memory (SRAM) layout with asymmetric gate spacing. Asymmetric gate spacing increases the distance between adjacent metal gates at the source / drain nodes for the Vcc node by proportionally reducing the distance between adjacent metal gates at adjacent source / drain nodes. Increasing the spacing at the Vcc source / drain nodes mitigates problems caused by gate bending, which helps prevent poor epitaxial growth and inter-gate leakage. Various gate jogs can be formed to achieve asymmetric gate spacing. These gate jogs are large enough to prevent inter-gate leakage, yet small enough to form continuous gates without breakage. Embodiments of the present invention further introduce gate extensions in regions adjacent to the edge of the active region to further mitigate gate bending and improve gate landing smoothness. Through various combinations of gate asymmetry, gate jogs, and gate extensions, the process margin of the SRAM is improved when forming epitaxial components (e.g., when forming undoped L0 epitaxial components at the Vcc of the p-type active region).

[0020] This document illustrates embodiments of the invention using a gate-all-around (GAA) field-effect transistor (FET), but the invention is not limited thereto. A gate-all-around FET refers to a transistor having a gate stack (gate electrode and gate dielectric layer) surrounding a transistor channel (e.g., a metal-oxide-semiconductor FET device with vertically stacked gate-all-around horizontal nanowires or nanosheets). Those skilled in the art will understand that they can readily use the embodiments of this invention as a basis to design or modify other structures to achieve the same purpose and / or the same advantages as the embodiments described herein.

[0021] This document describes embodiments of the invention implemented using memory devices, such as static random access memory (SRAM) devices in a static random access memory (SRAM) cell layout. However, the embodiments of the invention are not limited thereto. The embodiments of the invention are generally applicable to all semiconductor devices susceptible to gate bending caused by uneven gate landings, which can occur, for example, when the gate is placed near the edge of an active region. Therefore, those skilled in the art will understand that they can readily use the embodiments of the invention as a basis for designing or modifying other semiconductor devices, such as other types of memory devices with different logic devices or cell layouts than the exemplary embodiments. For example, in a further embodiment, asymmetric gate spacing may be applied to logic cells above an n-type or p-type active region.

[0022] Figure 1This diagram illustrates a circuit diagram of a Static Random Access Memory (SRAM) array as part of a memory device 102 according to an embodiment of the present invention. The circuit diagram corresponds to a SRAM array of two memory cells (or SRAM cells 104) in the memory cell region of the memory device 102. These two SRAM cells 104 are labeled as SRAM cell 104a and SRAM cell 104b. Each SRAM cell 104a and 104b is formed by six transistors (two pull-down transistors, two pull-up transistors, and two pass-gate transistors). Each transistor is defined by a source, a drain, and a gate. Each SRAM cell 104 stores a bit of memory via the pull-down and pull-up transistors, while the SRAM cells are addressed by word lines and bit lines via the pass-gate transistors.

[0023] Static Random Access Memory (SRAM) cell 104a includes pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2, and pass-gate transistors PG1 and PG2. The sources of pull-up transistors PU1 and PU2 are coupled together and connected to a high voltage Vcc. The sources of pull-down transistors PD1 and PD2 are coupled together and connected to a low supply voltage Vss or ground. The gates of pull-up transistors PU1 and PD1 are coupled together and connected to the common drain of pull-up transistors PU2, PD2, and pass-gate transistor PG2. The gates of pull-up transistors PU2 and PD2 are coupled together and connected to the common drain of pull-up transistors PU1, PD1, and PG1. Pull-up transistors PU1 and PU2, along with pull-down transistors PD1 and PD2, form a first set of cross-coupled inverters to store data bits. The source of the transfer gate transistor PG1 is connected to the first bit line BL1 (or the first bit line BL), while the source of the transfer gate transistor PG2 is connected to the first anti-phase line BLB1 (or the first anti-phase line BLB). The gates of the transfer gate transistors PG1 and PG2 are connected to the first word line WL_A.

[0024] Static Random Access Memory (SRAM) cell 104b includes pull-up transistors PU3 and PU4, pull-down transistors PD3 and PD4, and pass-gate transistors PG3 and PG4. The sources of pull-up transistors PU3 and PU4 are coupled together and connected to a high voltage Vcc. The sources of pull-down transistors PD3 and PD4 are coupled together and connected to a low supply voltage Vss or ground. The gates of pull-up transistors PU3 and PD3 are coupled together and connected to the common drain of pull-up transistors PU4, PD4, and PG4. The gates of pull-up transistors PU4 and PD4 are coupled together and connected to the common drain of pull-up transistors PU3, PD3, and PG3. Pull-up transistors PU3 and PU4, along with pull-down transistors PD3 and PD4, form a first set of cross-coupled inverters to store data bits. The source of pass-gate transistor PG3 is connected to the same first bit line BL1, while the source of pass-gate transistor PG4 is connected to the same first anti-phase line BLB1. The gates of the transmission gate transistors PG3 and PG4 are connected to the second word line WL_B.

[0025] It should be noted that, Figure 1 An exemplary embodiment of a static random access memory (SRAM) array is shown, but other configurations are possible. For example, in other embodiments, the source and drain nodes of different pull-up and pull-down transistors can be toggled. Furthermore, the Vcc and Vss nodes can also be toggled. In other words, in some embodiments, the high voltage Vcc can be connected to the source or drain of the pull-up and pull-down transistors in the SRAM array. In other embodiments, the low supply voltage Vss or ground can be connected to the source or drain of the pull-up and pull-down transistors in the SRAM array. Thus, the electrical connections to Vcc and Vss can be referred to as power lines, power signal lines, or power line connections providing paths to the pull-up and pull-down transistors in the memory device.

[0026] Memory device 102 can be integrated with logic components. For example, memory device 102 may also include peripheral logic circuitry adjacent to static random access memory cell 104 for implementing various functions, such as write and / or read address decoders, word / bit selectors, data drivers, memory self-tests, etc. The logic circuitry may include logic cell regions, which may contain arrays of standard logic cells for implementing input / output (I / O) blocks. Each memory and logic circuit can be implemented using various P-type and N-type metal-oxide-semiconductor transistors, such as planar transistors, fin field-effect transistors, gate-all-around (GAA) nanosheet transistors, gate-all-around nanowire transistors, or other types of transistors. Furthermore, the memory and logic circuitry may include various contact elements (or contacts), vias, and metal lines for connecting the source, drain, and gate electrodes (or terminals) of transistors to form an integrated circuit.

[0027] Figure 2 A flowchart illustrating a method 1000 for forming a portion or all of a memory device 102 having an asymmetric gate spacing according to an embodiment of the present invention is shown. The memory device 102 may generally be referred to as a semiconductor device having a corresponding semiconductor layout and structure. Reference is made below. Figures 3 to 6 Description method 1000. Figures 3 to 6 This illustrates an embodiment of the invention, during an intermediate stage of manufacturing and corresponding to... Figure 1 The circuit diagram is shown as a top view of the device layout of the static random access memory array (as part of memory device 102). For clarity, these device layouts have been simplified to better understand the inventive concept of this embodiment. Figures 3 to 6 Some components not shown are referenced. Figure 7A and Figure 7B describe, Figure 7A and Figure 7B A cross-sectional schematic diagram of the device layout is shown. Additional components may be added to the memory device 102, and in other embodiments of the memory device 102, some of the components described below may be replaced, modified, or eliminated.

[0028] Please refer to Figure 3 In method 1000, during operation 1002, an active region 106 is formed above the substrate. Figure 3 The substrate is not shown, but it can be correlated to... Figure 7A and Figure 7BSubstrate 101 is present in the substrate. The substrate may be a silicon (Si) substrate, or a substrate having other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. The substrate may be doped with a p-type dopant (e.g., boron) or an n-type dopant (e.g., arsenic or phosphorus). Active region 106 protrudes above the substrate and may contain the same or similar material as the substrate. Active region 106 may be formed by patterning a pedestal semiconductor layer (or pedestal substrate) to form a fin-shaped active region protruding above the bottom surface of the substrate. For example, active region 106 may be formed by a patterning process including photolithography and etching. In some embodiments, the photolithography process forms a patterned mask layer covering the area of ​​the pedestal semiconductor layer used to form active region 106, and the etching process uses the patterned mask layer as an etching mask to etch the exposed portions of the patterned mask layer. The etching process forms recesses that space and define active region 106. Active region 106 extends longitudinally in the x-direction and may be referred to as a fin active region or semiconductor fin.

[0029] As shown in the figure, the active region 106 can be an n-type active region for forming an N-type metal-oxide-semiconductor (NMOS) transistor, or a p-type active region for forming a P-type metal-oxide-semiconductor (PMOS) transistor. The n-type active region can be formed above a p-type well (e.g., a portion of the substrate doped with a p-type dopant (e.g., boron), while the p-type active region can be formed above an n-type well (e.g., a portion of the substrate doped with an n-type dopant (e.g., arsenic or phosphorus)). The active region 106 for forming the NMOS transistor can extend continuously across multiple static random access memory (SRAM) cells 104, while the active region 106 for forming the PMOS transistor can be broken down into shorter, isolated segments with shorter widths. The segmentation of the active region 106 of the PMOS transistor can be formed as part of an initial patterning to form all active regions 106. Alternatively, all active regions 106 are first formed such that they extend continuously across the static random access memory cell 104a. Then, a fin-cutting patterning process is performed to form cut-through isolation regions, and a portion of the active regions 106 is removed to form a P-type metal-oxide-semiconductor (PMOS) transistor. As described in more detail below, the active regions 106 of the PMOS are used to form pull-up transistors, while the active regions 106 of the NMOS are used to form pull-down transistors and pass-gate transistors. In this way, different active regions 106 can be configured differently depending on the design appearance. For example, although not shown, the active regions 106 of the PMOS may have a smaller width along the Y direction than the active regions 106 of the NMOS.

[0030] As part of forming the active region 106, method 1000 further includes forming an isolation structure above the substrate and between the active regions. Figure 3 The isolation structure is not shown, but it can be mapped to... Figure 7A , Figure 8A , Figure 8B The isolation structure 107 is provided. The isolation structure 107 may be a shallow trench isolation (STI) layer and provides isolation between adjacent active regions 106 along the Y direction. When there is an isolation segment of the active region 106 of the P-type metal-oxide-semiconductor PMOS, the isolation structure can also provide isolation between the active regions 106 of adjacent P-type metal-oxide-semiconductor PMOS along the X direction.

[0031] The isolation structure can be formed by first depositing an isolation layer over the substrate and the active region 106. The isolation layer is located on the top surface of the substrate, filling the grooves between the active regions 106, and situated on the top surface of the active regions 106. In other words, the isolation layer is overfilled to surround all exposed surfaces of the active regions 106. The isolation layer can be deposited using any suitable deposition process, and the isolation layer can comprise silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-dielectric-constant dielectric, a combination of the foregoing, and / or other suitable materials.

[0032] Subsequently, the isolation layer can be recessed to form an isolation structure surrounding the bottom (i.e., the lower protrusion) of the active region 106. The isolation structure can be formed by first performing chemical mechanical polishing (CMP) to remove excess portions of the isolation layer on the top surface of the active region 106. The remaining portion of the isolation layer forms an isolation region transversely between the active regions 106. Next, the isolation region is recessed in an etching step such that the exposed fin portions of the active region 106 (e.g., the upper protrusion) are above the top surface of the isolation region. The final isolation region forms the isolation structure. In this embodiment, the isolation structure is a shallow trench isolation (STI) structure forming a stepped height profile of the active region 106 (see reference). Figure 7A An isolation structure 107 with a stepped height profile of active region 106 is formed in the middle. The shallow trench isolation structure can be connected to the end portion of one or more active regions 106 along the X direction.

[0033] Please refer to Figure 3 In method 1000, in operation 1004, a gate 108 is formed above the channel region of the active region 106. The channel region refers to the portion of the active region 106 directly below the gate 108. The gate 108 is connected to the channel of the channel region. The gate 108 can be formed by first depositing a dummy gate (not shown) above the channel region of the active region 106, followed by forming source / drain epitaxial components and internal spacers (e.g., ...) in the source / drain and channel regions of the active region 106. Figure 7A and Figure 7BThe source / drain epitaxial component 106b and internal spacer 111 are then used. The dummy gate is then replaced with a metal gate (e.g., gate 108). Gate 108 is connected to the channel region (e.g., the channel of the channel region). Figure 7A and Figure 7B The channel 106a) is joined together. The channel connects the source / drain epitaxial components of adjacent source / drain regions together. The source / drain region refers to the portion of the active region adjacent to the channel region and not covered by the gate. As shown, the gate 108 extends longitudinally in the Y direction across one or more channel regions of one or more active regions 106. The gate 108 surrounds the top and side surfaces of the channel region. The gate further extends to sit on an isolation structure. Each gate 108 may include a gate stack and gate spacers on the sidewalls of the gate stack. The gate stack and gate spacers are not shown in the figure. Figure 3 In the middle, but it can correspond to Figure 7A and Figure 7B The gate stack 208a and gate spacer 208c are shown in the figure. (Refer to the following...) Figure 7A and Figure 7B Further structural details of gate 108 are described.

[0034] It should be noted that the gate 108 is formed continuously along the Y direction and may include a jog that results in asymmetric gate spacing along the X direction. This jog is large enough to create sufficient spacing separation in a given source / drain region, yet small enough to allow the gate to be formed continuously without breakage. Advantageously, since the proportionally proportioned jog increases the spacing on one side and decreases the spacing on the other, the jog does not affect the overall cell layout pattern. Further details of these jogs that result in asymmetric gate spacing are described below with reference to the static random access memory cell layout.

[0035] like Figure 3 As shown, memory device 102 includes a static random access memory (SRAM) array (or SRAM cells 104a and 104b) with two memory cells. Each SRAM cell 104 has a cell width CW along the x-direction and a cell height CH along the y-direction. SRAM cells 104a and 104b can correspond to... Figure 1 Static random access memory (SRAM) cells 104a and 104b are adjacent to each other in the X direction, and the vertical cell boundaries between SRAM cells 104a and 104b are mirror images of each other. Although not shown, memory device 102 may include additional SRAM cells that are adjacent to and mirror images of SRAM cells 104a and 104b.

[0036] Figure 3The locations where pull-up transistors PU1, PU2, PU3, PU4, pull-down transistors PD1, PD2, PD3, PD4, and transfer gate transistors PG1, PG2, PG3, PG4 will be formed are shown (marked on the gate 108 of each transistor). [The last part, "already shown," appears to be an error and is left untranslated.] Figure 2 The details of how each transistor is interconnected have been described in the previous section, and for the sake of brevity, they will not be repeated here.

[0037] As shown in the figure, the two static random access memory (SRAM) cells 104a and 104b include active regions 106 extending along the X direction. The active regions 106 can be configured for planar, fin-type, or full-ring gate semiconductor structures. In one embodiment, as previously described, the active region 106 is a fin structure projecting from the base substrate in the positive Z direction. Some active regions 106 may extend longitudinally across the vertical cell boundary, such that identical active regions share the span across the SRAM cell 104. The active regions 106 may include n-type active regions for forming pull-down and pass-gate transistors (e.g., active regions 106 of an N-type metal-oxide-semiconductor (NMOS) forming pull-down transistors PD1, PD2, PD3, PD4, and pass-gate transistors PG1, PG2, PG3, PG4) and p-type active regions for forming pull-up transistors (e.g., active regions 106 of a P-type metal-oxide-semiconductor (PMOS) forming pull-up transistors PU1, PU2, PU3, PU4). The p-type active region is shorter in the X direction than the n-type active region. As shown, the p-type active region is discontinuous and spans at most less than the cell width CW of two static random access memory (SRAM) cells 104 in the X direction. On the other hand, the n-type active region can continuously span the entire memory cell region in the X direction (shown here as spanning the entire SRAM layout). Gates 108 are disposed above the channel region of the active region 106 and extend longitudinally in the Y direction. Although not shown, some gates 108 may extend across horizontal cell boundaries to span the active regions 106 of different SRAM cells 104 in the Y direction.

[0038] Each gate 108 has a base portion 158 and a protrusion 160. The gate spacing between adjacent base portions 158 is defined by a gate spacing GS1. The gate spacing between protrusions 160 differs from the gate spacing GS1, resulting in an asymmetric gate spacing. For example, the gate spacing between protrusions 160 may be GS1-j or GS1+j, where "j" is the protrusion distance along the X direction. As shown, to maintain the same cell width CW, increasing the gate spacing between the first pair of adjacent protrusions 160 (e.g., increasing the protrusion distance j) requires decreasing the gate spacing between the second pair of adjacent protrusions 160 (e.g., decreasing the protrusion distance j). Each protrusion 160 is offset from the sidewall of the base portion by its sidewall width 0.5j. This results in the gate spacing of any two adjacent pairs of protrusions 160 increasing or decreasing by the protrusion distance j in total. Each base portion 158 has a gate width G1 along the X direction, which may be a consistent gate width from one gate to another. In this paper, "consistent" means that each gate has an average or approximately the same gate width; however, in real structures, due to manufacturing variations, the gates may have curved or non-ideal sidewalls. The cell width CW is defined by twice the gate spacing GS1 plus twice the gate width G1 (i.e., CW = 2GS1 + 2G1). The cell height CH is defined by four times the spacing between the active regions 106 along the Y direction plus four times the width of the active regions 106 along the Y direction (not explicitly stated).

[0039] Gate dicing regions (GCRs) are shown at various locations within static random access memory cells 104a and 104b. The GCR defines the region where the gate 108 will be diced to form a spaced gate 108 for subsequent transistor devices, such as a spaced gate 108 for forming a pass gate and a pull-up transistor. In this embodiment, the GCR extends laterally in the X direction at one or more junctions between the base portion 158 and the protrusion 160. The gate dicing region can be defined by any patterning process suitable for forming a patterned mask that exposes the gate dicing region GCR.

[0040] Please refer to Figure 4 In method 1000, in operation 1006, a gate dicing feature GCF is formed in the gate dicing region GCR. Operation 1006 may include etching through an opening in a patterned mask to remove a portion of the gate 108 in the gate dicing region GCR. This etching forms an exposed underlying isolation structure (e.g., Figure 7AThe corresponding trenches of the isolation structure 107 in the figure are then filled with a dielectric material in operation 1006, followed by a planarization process, such as chemical mechanical polishing. The dielectric material may comprise silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low dielectric constant dielectrics, combinations thereof, and / or other suitable materials. The dielectric material provides isolation between the newly diced gates 108. As shown, the gate dicing component GCF can define a gate 108 shared by pull-up and pull-down transistors and a gate 108 used only for the transmission gate transistor. The gate dicing component GCF is connected to the end portions of the spaced gates 108.

[0041] Please refer to Figure 5 In method 1000, during operation 1008, a source / drain contact 112 is formed above the source / drain (S / D) region of the active region 106. The source / drain contact 112 is disposed on and located within the source / drain epitaxial component (e.g., [missing information]) of the source / drain region. Figure 7A and 7BOn the source / drain epitaxial component 106b) in the figure. As shown, some source / drain contacts 112 are slot contacts extending in the Y direction to couple the source / drain regions of different transistors together. For example, a single source / drain contact 112 wires the drain regions of pull-down transistor PD1, pull-up transistor PU1, and transfer gate transistor PG1 together. Operation 1008 further forms a source / drain via 116 at a location above and on the source / drain contacts. The source / drain via 116 allows the source / drain contacts 112 to be electrically coupled to a higher material layer in the Z direction. As part of operation 1008, method 1000 also forms multiple mating contacts 130 for gate-to-drain electrical connections. As shown, the mating contacts 130 couple various gates 108 to various source / drain contacts 112. In one embodiment, the interconnect between the drain (or source) and gate 108 is achieved using local interconnect (LI) technology. For example, a local interconnect is formed using a gate material (e.g., polysilicon, metal, or other conductive material for gate 108). In this case, polysilicon (metal or other conductive material) is used not only to form the gate stack but also to form the interconnect structure. More specifically, gate 108 may extend to and be directly situated on the target drain (or source) region. As another example, the mating contact 130 is an elongated contact oriented in the X direction and is formed simultaneously with other contacts in the same process including dielectric deposition, patterning, and metal deposition. The source / drain contact 112, source / drain via 116, and mating contact 130 can be formed using any suitable patterning and metal deposition process. These processes may include single-damascene or double-damascene processes that individually (or simultaneously) form various layers of embedded conductive components in a dielectric structure (e.g., an intermetallic dielectric structure). For example, these processes may include depositing an intermetallic dielectric layer over an intermediate structure, forming trenches in the intermetallic dielectric layer, and then filling the trenches with a conductive material, such as Al, W, and / or Cu.

[0042] Figure 5 The diagram shows that the nodes (or terminals) of the low supply voltage Vss, high voltage Vcc, bit line BL, first word line WL_A, and second word line WL_B are located at their corresponding source / drain contacts 112 and source / drain vias 116. These locations and their connections to the lower gate and source / drain terminals... Figure 1 The circuit shown Figure 1As shown in the figure, at nodes with low supply voltage Vcc, the spacing between the gates of the pull-up transistors is increased. This is because the gate ends of both the pull-up and pull-down transistors are directly adjacent and close to the p-type active region 106. This close proximity is to provide a landing to form the mating contact 130. However, this close proximity can lead to the gate bending problem described earlier, where adjacent gates may bend towards each other, thereby reducing the spacing between the gates. This reduced spacing can adversely affect device performance, resulting in poor epitaxial growth and / or gate leakage between pull-up transistors. Therefore, the gate spacing at nodes with low supply voltage Vcc (i.e., the source / drain regions between adjacent pull-up transistors) is intentionally increased to gate spacing GS1+j to alleviate the gate bending problem. To maintain a consistent cell width CW, the gate spacing at adjacent interconnect nodes (i.e., nodes with mating contacts 130) is intentionally reduced to gate spacing GS1-j. In this way, the sum of the spacings between the first pair of protrusions 160 and the adjacent pairs of protrusions 160 (i.e., (GS1+j)+(GS1-j)) is equal to the sum of the spacings between the first pair of base portions 158 and the adjacent pairs of base portions 158 (i.e., GS1+GS1). It should be noted that the reduced gate spacing GS1-j at adjacent interconnect nodes does not negatively impact device performance because edge gates have less impact on source / drain epitaxial growth and inter-gate leakage. Furthermore, gate bending may have a greater impact on the central source / drain region of the active region 106 than on the edge source / drain region of the active region 106.

[0043] Please refer to Figure 6 In method 1000, operation 1010 forms a metal line 140 extending longitudinally in the X direction. The metal line 140 is disposed on and situated on source / drain vias 116. As shown, some metal lines 140 extend across multiple source / drain vias 116 to route connections across the same nodes of multiple static random access memory cells 104, for example, connecting multiple source / drain vias 116 for Vcc nodes, BL nodes, etc. These metal lines 140 can connect the source / drain components of multiple pull-up transistors together, or connect the source / drain components of multiple pass-gate transistors together. Some metal lines 140 extend only across a single source / drain via 116 to route connections from a single source / drain via 116, for example, connecting Vss nodes, WL_A nodes, WL_B nodes, etc. The metal lines 140 can be formed by any suitable patterning and metal deposition process. These processes may include depositing an intermetallic dielectric layer over the intermediate structure, forming trenches in the intermetallic dielectric layer to expose the underlying source / drain vias 116, and then filling the trenches with a conductive material (e.g., Al, W, and / or Cu).

[0044] Method 1000 may be further operated to complete the fabrication of memory device 102. For example, although not shown, method 1000 may form an additional layer of interconnect vias and metal lines above metal lines 140 to collectively form an interconnect structure. The interconnect structure electrically couples various devices (e.g., p-type transistors and / or n-type full-ring gate transistors of memory device 102, other transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate structures of p-type transistors and / or n-type transistors and / or epitaxial source / drain components) such that the various devices and / or components can operate according to the design requirements of memory device 102. The interconnect structure includes a combination of dielectric and conductive layers (e.g., metal layers) configured to form various interconnect components. Conductive layers are configured to form vertical interconnect components (e.g., source / drain vias 116) and / or horizontal interconnect components (e.g., metal lines 140). Vertical interconnect components generally connect horizontal interconnect components in different layers (or different planes) of the interconnect structure. During operation, the interconnect structure is configured to route signals between memory device 102 and / or components of memory device 102 and / or distribute signals (e.g., clock signals, voltage signals and / or ground signals) to the device and / or components of memory device 102.

[0045] Figure 7A and Figure 7B This illustrates an embodiment of the invention, showing the following along... Figure 6 A cross-sectional schematic diagram of the static random access memory array of memory device 102, showing cuts along lines A-A' and B-B'. (As described with reference to method 1000) Figure 7A and Figure 7B For the sake of brevity, some of the various components will not be described in detail.

[0046] Figure 7AA cross-sectional schematic diagram of the active region 106 of a P-type metal-oxide-semiconductor (PMOS) extending across three gates 108 in the X direction above substrate 101 is shown. As shown, the active region 106 of the PMOS includes source / drain epitaxial members 106b and a channel 106a located between and connecting the source / drain epitaxial members 106b. An isolation structure 107 laterally surrounds the active region 106 of the PMOS, providing isolation between adjacent active regions 106 in the X and Y directions (not shown in this figure). The active region 106 of the PMOS protrudes above the isolation structure 107. The isolation structure 107 is situated on the top surface of substrate 101 and laterally adjacent to the protrusion of substrate 101 and the ends of the elongated active region 106. This protruding portion of substrate 101 may also be referred to as the lower portion of the active region 106 of a P-type metal-oxide-semiconductor (PMOS), on which the source / drain epitaxial member 106b is grown. As shown, the isolation structure 107 may be in contact with the sidewall surface of the active region 106, for example, the sidewall surface of the source / drain epitaxial member 106b at the end portion of the active region 106.

[0047] Please refer to this together. Figure 7A and Figure 7B The source / drain epitaxial component 106b can be formed by etching source / drain trenches in the source / drain regions of the active region 106, followed by epitaxial growth of the source / drain epitaxial component 106b in the source / drain trenches. Epitaxial growth may include performing an epitaxial process using deposition techniques such as chemical vapor deposition (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum chemical vapor deposition (UHV-CVD)), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The epitaxial process may use gas-phase and / or liquid-phase precursors that react with the composition of the substrate 101. The source / drain epitaxial component 106b is doped with n-type dopant and / or p-type dopant. In some embodiments, for p-type full-ring gate transistors (e.g., in…), Figure 7A In the middle), the source / drain epitaxial component 106b comprises silicon germanium or germanium, and may be doped with boron, other p-type dopants, or combinations thereof (e.g., forming a Si:Ge:B epitaxial source / drain component). In some embodiments, for an n-type full-ring gate transistor (e.g., in...), Figure 7B (As shown in the figure), the source / drain epitaxial component 106b contains silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants or combinations thereof (e.g. forming a Si:C epitaxial source / drain component, a Si:P epitaxial source / drain component or a Si:C:P epitaxial source / drain component).

[0048] The epitaxial process may include forming various epitaxial layers with different doping concentrations. For example, the epitaxial component may include a saddle epitaxial layer (L0) formed above the initial exposed surface of the source / drain trench (including the surface of the substrate 101 and the channel 106a). The L0 epitaxial layer is largely undoped or contains only a minimal concentration of dopant. The epitaxial component may also include an L1 epitaxial layer, which has a higher doping concentration than the L0 epitaxial layer. The L1 epitaxial layer may be located in the region adjacent to the L0 epitaxial layer and extend along the sidewall of the internal spacer 111. In addition, the epitaxial component may include a bulk L2 epitaxial layer, which has a higher doping concentration than the L1 epitaxial layer. The L2 epitaxial layer is laterally surrounded by the L1 epitaxial layer and is buried within the L1 epitaxial layer. Gate bending caused by the gate being close to the periphery of the active region 106 may result in suboptimal growth of the L0 epitaxial layer. This is due to the reduced bottom spacing between adjacent gates. In this embodiment, the gate bending problem exists in the active region 106 of the P-type metal-oxide-semiconductor (PMOS) but not in the active region 106 of the N-type metal-oxide-semiconductor (NMOS). This is because the gate landing point is closer to the edge of the active region 106 of the PMOS. Therefore, the protruding design described herein aims to address the challenges associated with the active region 106 of the PMOS. In alternative embodiments, such as in different cell layouts, the protruding design may target the active region 106 of the NMOS.

[0049] Please refer to Figure 7A and Figure 7BThe gate 108 comprises a gate stack 208a and a gate spacer 208c adjacent to the gate stack 208a. The gate stack 208a may include a gate dielectric layer 208b and a gate electrode disposed on the gate dielectric layer 208b. In some embodiments, the gate dielectric layer 208b includes an interface layer and a high-dielectric-constant dielectric layer disposed on the interface layer. The gate electrode may include one or more conductive materials, such as a capping layer, a work function metal layer, a barrier layer, a metal fill layer, and / or other suitable conductive material layers. The work function metal layer (if present) may be the same or different, and depending on the corresponding all-around gate transistor, may be an n-type work function metal layer or a p-type work function metal layer. The gate dielectric layer contains a high-dielectric-constant dielectric material, for example, having a dielectric constant greater than that of silicon oxide (k ≈ 3.9). The gate electrode may be formed by a chemical vapor deposition process or a physical vapor deposition process to deposit filling of the remaining portion of the gate trench and the metal fill layer above the gate dielectric layer. The metal filler layer comprises a suitable conductive material, such as Al, W, and / or Cu. The metal filler layer may additionally or collectively comprise other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof. Alternatively, the metal filler layer is formed using other suitable deposition processes, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, distal plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, spin coating, plating, other deposition processes, or combinations thereof.

[0050] Please refer to Figure 7AA gate 108, situated on the active region 106 of a P-type metal-oxide-semiconductor, vertically surrounds a channel 106a. An inner spacer 111 laterally surrounds the portion of the gate stack 208a below the topmost channel 106a, while a gate spacer 208c laterally surrounds the portion of the gate stack 208a above the topmost channel 106a. The inner spacer 111 provides isolation between the gate and adjacent source / drain components. The inner spacer 111 may contain the same or different dielectric material as the gate spacer 208c. The dielectric material may be made of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide, metal nitride, or a suitable dielectric material. The gate spacer 208c and the inner spacer 111 may be vertically aligned in the Z-direction. The gate 108, adjacent to the edge of the active region 106 (or its edge source / drain region) of the P-type metal-oxide-semiconductor, sits on an isolation structure 107. This gate is not located in or surrounds the channel 106a of the active region 106 of the P-type metal-oxide-semiconductor. This gate is a gate end extension serving as a landing surface for mating contact connections. However, when viewed along the Y direction, other portions of this gate may be located on and engaged with the channels 106a of other active regions 106. As shown, the gate end extension has gate spacers 208c and gate stacks 208a that extend continuously downward to sit on the isolation structure 107.

[0051] Please refer to Figure 7A An inter-metal dielectric (IMD) structure 145 is disposed above the active region 106 and gate 108 of a P-type metal-oxide-semiconductor. The IMD structure 145 may include one or more interlayer dielectric (ILD) layers 141 and one or more etch stop layers 142 defining the top and bottom surfaces of various buried conductive components (e.g., the top and bottom surfaces of buried source / drain contacts 112 and mating contacts 130). Source / drain contacts 112 pass through one or more IMD layers 141 and one or more etch stop layers 142 to sit on the source / drain epitaxial component 106b. Mating contacts 130 pass through one or more IMD layers 141 and one or more etch stop layers 142 to sit on the corresponding source / drain contact 112 and the gate end portion of the corresponding gate 108. As shown, mating contacts 130 provide gate-to-source / drain interconnects. The etch stop layer 142 comprises a dielectric material different from that of the interlayer dielectric layer 141 to provide etchant selectivity. For example, the etch stop layer 142 comprises a nitride-based dielectric, while the interlayer dielectric layer 141 comprises an oxide-based dielectric. The etch stop layer 142 has a smaller thickness than the interlayer dielectric layer 141.

[0052] Figure 7BA schematic cross-sectional view of the active region 106 of an N-type metal-oxide-semiconductor (NMOS) extending across the three gates 108 above the substrate 101 and along the X direction is shown. Figure 7B Similar to Figure 7A Except for the absence of mating contacts 130, the active region 106 of the N-type metal-oxide-semiconductor (NMOS) extends continuously and uninterruptedly in the X direction. In this way, each of the three gates 108 is engaged with the channel 106a of the active region 106 of the NMOS.

[0053] Compare Figure 7A and Figure 7B The gate spacing associated with the active region 106 of the P-type metal-oxide-semiconductor is asymmetric, having gate spacings GS1-j and GS1+j. This asymmetry originates from the inclusion of a protrusion distance j. However, Figure 7B The active region 106 of the N-type metal-oxide-semiconductor (NMOS) is shown to have symmetrical gate spacing, each with a gate spacing GS1. These gate spacings refer to the source / drain regions between adjacent gates 108. Due to their protrusion, Figure 7A The three gates of the active region 106 of the P-type metal-oxide-semiconductor in the middle edge are connected to... Figure 7B The three gates along the active region 106 of the N-type metal-oxide-semiconductor NMOS are misaligned.

[0054] Figure 8A and Figure 8B An additional embodiment of the invention is shown, along Figure 6 A cross-sectional schematic diagram of the static random access memory array of memory device 102, taken from line A-A'. Figure 8A and Figure 8B Similar to Figure 7A For the sake of brevity, similar components will not be described in detail. Please refer to the previous section. Figure 7A In one embodiment, the edge gate 108 has a gate end portion that is fully situated on the isolation structure 107, which is adjacent to the active region 106 of the P-type metal-oxide-semiconductor. However, in Figure 8A In one embodiment, the edge gate 108 has a gate end portion partially located on the active region 106 of the P-type metal-oxide semiconductor and partially located on the isolation structure 107. For example... Figure 8A As shown, a portion of the gate stack 208a and one of the gate spacers 208c may be located on the top surface of the source / drain epitaxial member 106b at the edge, while the other portion of the gate stack 208a and the other of the gate spacers 208c may be located on the top surface of the isolation structure 107. In this case, Figure 8A The edge source / drain epitaxial component 106b is comparable Figure 7AThe source / drain epitaxial component 106b at the edge extends a greater length along the X direction. Figure 8B In one embodiment, the edge gate 108 has a gate end portion that is entirely situated on the active region 106 of the P-type metal-oxide semiconductor. For example... Figure 8B As shown, all gate stacks 208a and gate spacers 208c can be located on the top surface of the source / drain epitaxial member 106b at the edge. In this case, Figure 8B The edge source / drain epitaxial component 106b is comparable Figure 8A The source / drain epitaxial component 106b at the edge extends a greater length along the X direction.

[0055] Still refer to Figure 8A and Figure 8B Since the edge gate 108 is partially or completely situated on the active region 106 of the P-type metal-oxide-semiconductor, the edge source / drain epitaxial portion 106b can extend a longer length in the X direction than the gate spacing GS1-j. This mitigates any impact of having a shorter gate spacing GS1-j, which is necessary to compensate for the larger gate spacing at the Vcc node. In other words, the source / drain region used to form this edge source / drain epitaxial portion 106b is not limited by the gate spacing GS1-j. The partial or complete placement of the edge gate 108 does not cause a short-circuit problem because the edge gate 108 is already used for electrical connection to the underlying source / drain epitaxial portion 106b, as shown by the covered mating contact 130.

[0056] Figures 9 to 12 The diagram shows top-view device layouts of various static random access memory arrays having asymmetric gate spacing according to various embodiments of the present invention. Each of the static random access memory arrays may be part of memory device 102.

[0057] Figure 9 Show reference Figures 3 to 6The described embodiment. For the sake of brevity, some components are not described in detail. As shown in the figure, the memory device 102 includes static random access memory cells 104a and 104b. Static random access memory cell 104a includes a first gate 108a, a second gate 108b, a third gate 108c, and a fourth gate 108d. Static random access memory cell 104b includes a fifth gate 108a', a sixth gate 108b', a seventh gate 108c', and an eighth gate 108d'. The first gate 108a is connected to the channel region of the active region 212a of the P-type metal-oxide-semiconductor PMOS and the channel region of the active region 214a of the N-type metal-oxide-semiconductor NMOS to form a pull-up transistor PU1 and a pull-down transistor PD1. The second gate 108b is bonded to the channel region of the active region 212b of the P-type metal-oxide-semiconductor (PMOS) and the channel region of the active region 214b of the N-type metal-oxide-semiconductor (NMOS) to form a pull-up transistor PU2 and a pull-down transistor PD2. The third gate 108c is bonded to the channel region of the active region 214a of the NMOS to form a transfer gate transistor PG1. The fourth gate 108d is bonded to the channel region of the active region 214b of the NMOS to form a transfer gate transistor PG2. The fifth gate 108a' is bonded to the channel regions of the active regions 212a and 214a of the PMOS to form a pull-up transistor PU3 and a pull-down transistor PD3. The sixth gate 108b' is bonded to the channel region of the active region 212c of the P-type metal-oxide-semiconductor (PMOS) and the channel region of the active region 214b of the N-type metal-oxide-semiconductor (NMOS) to form a pull-up transistor PU4 and a pull-down transistor PD4. The seventh gate 108c' is bonded to the channel region of the active region 214a of the NMOS to form a transfer gate transistor PG3. The eighth gate 108d' is bonded to the channel region of the active region 214b of the NMOS to form a transfer gate transistor PG4.

[0058] Each of static random access memory (SRAM) cells 104a and 104b includes two columns of gates extending in the Y direction and four rows of active regions extending in the X direction. SRAM cell 104a includes a first column having a second gate 108b and a third gate 108c aligned generally (or at least partially) along the Y direction. SRAM cell 104a further includes a second column having a fourth gate 108d aligned generally (or at least partially) along the Y direction and a first gate 108a. SRAM cell 104b includes a third column having an eighth gate 108d' aligned generally (or at least partially) along the Y direction and a fifth gate 108a'. SRAM cell 104b further includes a fourth column having a sixth gate 108b' aligned generally (or at least partially) along the Y direction and a seventh gate 108c'. Static random access memory (SRAM) cell 104a includes a first row of active regions 214b with N-type metal-oxide-semiconductor (NMOS) semiconductors, a second row of active regions 212b with P-type metal-oxide-semiconductor (PMOS) semiconductors, a third row of active regions 212a with P-type metal-oxide-semiconductor (PMOS) semiconductors, and a fourth row of active regions 214a with N-type metal-oxide-semiconductor (NMOS) semiconductors. Static random access memory (SRAM) cell 104b includes a first row of active regions 214b with N-type metal-oxide-semiconductor (NMOS) semiconductors, a second row of active regions 212c with P-type metal-oxide-semiconductor (PMOS) semiconductors, a third row of active regions 212a with P-type metal-oxide-semiconductor (PMOS) semiconductors, and a fourth row of active regions 214a with N-type metal-oxide-semiconductor (NMOS) semiconductors.

[0059] All gates (first gate 108a, second gate 108b, third gate 108c, fourth gate 108d, fifth gate 108a', sixth gate 108b', seventh gate 108c', and eighth gate 108d') have a base portion 158, and the first gate 108a, second gate 108b, fifth gate 108a', and sixth gate 108b' each further include a protrusion 160. The protrusion 160 protrudes from the sidewall of the corresponding base portion 158 toward or away from an adjacent protrusion 160. The protrusion 160 is situated on and connected to the channel region of a pull-up transistor (e.g., pull-up transistors PU1, PU2, PU3, PU4). Each protrusion protrudes from its corresponding sidewall by half a protrusion distance j. In one embodiment, the protrusion distance j is in the range of approximately 0.3 nm to approximately 1 nm. The protrusion distance j is chosen to be large enough to increase the gate spacing (e.g., greater than 0.3 nm) in the desired region, while being small enough to have a transition region that allows for the formation of a continuous gate (e.g., less than 1 nm). In this embodiment, the transition region is located between the active regions of the N-type metal-oxide-semiconductor (NMOS) and the P-type metal-oxide-semiconductor (PMOS) along the Y direction. The base portion 158 and the protrusion portion 160 each have a gate width G1 along the X direction. In one embodiment, the gate width G1 is in the range of about 2.5 nm to about 3.5 nm. Each spacing between adjacent base portions 158 has a gate spacing GS1. In one embodiment, the gate spacing GS1 is in the range of about 43 nm to about 47 nm. Each spacing between adjacent protrusion portions 160 has a gate spacing GS1-j or a gate spacing GS1+j. In one embodiment, the ratio of the protrusion distance j to the gate width G1 is in the range of 0.01 to 0.35, for example, between 0.1 and 0.3. The spacing between the protruding portion 160 of the first gate 108a and the protruding portion 160 of the fifth gate 108a' is gate spacing GS1+j. In this embodiment, this spacing may correspond to the length of the shared source / drain region between adjacent pull-up transistors. The spacing between the protruding portions of the first gate 108a and the second gate 108b, and the spacing between the protruding portions of the fifth gate 108a' and the sixth gate 108b', is gate spacing GS1-j. In this embodiment, this spacing may correspond to the gate spacing adjacent to gate spacing GS1+j.

[0060] Figure 10 Another embodiment of a static random access memory array with asymmetric gate spacing is shown. Figure 10 Similar to Figure 9In addition to the protruding portion 160, the system also includes a gate extension 160a in the region adjacent to the edges of the active regions 212a, 212b, and 212c. This further reduces gate bending and makes the gate landing smoother. In this embodiment, the gate extension 160a has a width of 0.5j. The gate extension 160a extends away from the edge of the active region such that the sidewall of the gate extension 160a is aligned with the sidewall of the base portion 158 in the Y direction. In this way, the protruding portion 160 with the gate extension 160a can have a gate width G1+0.5j. The gate extension 160a can span half the length of the protruding portion 160 in the Y direction, for example, extending to the middle of the cell boundary in the Y direction. When the gate extension 160a is included, the spacing between the protruding portions 160 at the edges of the active regions 212b and 212c corresponds to the gate spacing GS1. In contrast, the spacing between the protruding portions 160, excluding the gate extension 160a, remains unchanged.

[0061] Figure 11 Another embodiment of a static random access memory array with asymmetric gate spacing is shown. Figure 11 Similar to Figure 10 In addition to the addition of a gate extension 160a, this embodiment further includes a gate extension 160a. In this embodiment, the gate extension 160a has a width of 0.5j + 0.5b, where the distance b may be equal to or less than the protrusion distance j. In one embodiment, the distance b is in the range of approximately 0.3 nm to approximately 0.5 nm. In one embodiment, the gate extension 160a extends away from the edge of the active region, such that the sidewall of the gate extension 160a extends beyond the sidewall of the base portion 158. Thus, the protrusion 160 with the gate extension 160a may have a gate width G1 + 0.5j + 0.5b. The gate extension 160a may span half the length of the protrusion 160 in the Y direction. Due to the inclusion of the gate extension 160a, the spacing between the protrusions 160 at the edges of the active regions 212b and 212c corresponds to the gate spacing GS1 - b. In contrast, the spacing between the protrusions 160 without the gate extension 160a remains unchanged. The added gate extension 160a provides greater structural integrity to the corresponding gate base portion 158, thereby further reducing gate bending and improving source / drain epitaxial growth margin.

[0062] Figure 12 Another embodiment of a static random access memory array with asymmetric gate spacing is shown. Figure 12 Similar to Figure 9In addition to the base portion 158, which is also a protruding portion 160, each gate 108 protrudes uniformly (overall) along the X direction. In this embodiment, the gate spacing between adjacent pull-down transistors may also be the same as the gate spacing GS1+j between adjacent pull-up transistors. Furthermore, the gate spacing between the pull-down transistor and the transmission gate transistor may also be the same as the gate spacing GS1-j between the edge gate and the pull-up transistor. Uniform protrusion reduces manufacturing difficulties by avoiding the need for patterning and forming transition regions protruding between different gate portions.

[0063] It should be noted that, due to the various gate spacings described herein (e.g., gate spacings GS1, GS1+j, GS1-j, etc.), the source / drain epitaxial components 106b formed in these gate spacings can also have corresponding dimensions (e.g., similar or proportional dimensions). For example, in Figure 7A In this embodiment, one source / drain epitaxial member 106b (e.g., formed in gate spacing GS1-j) may have a width smaller than that of another source / drain epitaxial member 106b (e.g., formed in gate spacing GS1+j). In this way, the asymmetric gate spacing can result in corresponding asymmetric source / drain epitaxial member sizes. However, in some of the foregoing embodiments, the source / drain epitaxial members 106b at certain edges may not be limited by the gate spacing (e.g., see [reference]). Figure 8A and Figure 8B (and related descriptions).

[0064] Although not shown, embodiments of the present invention provide advantages for memory device cell layout. One exemplary advantage is the formation of asymmetric gate spacing to improve process margin while maintaining a consistent cell layout. Another exemplary advantage is the introduction of gate extensions in regions adjacent to the edges of active regions to reduce gate bending and ensure smooth gate landing. Another exemplary advantage is the introduction of various protrusions to adjust device layout. Yet another exemplary advantage is allowing gate end extensions to sit on the edges of active regions.

[0065] One aspect of this invention relates to a semiconductor device comprising a first active region, a second active region, a third active region, a fourth active region, and a fifth active region extending longitudinally along a first direction. The first and fifth active regions completely extend across a first unit and an adjacent second unit. The second, third, and fourth active regions partially extend across the first and second units and are disposed between the first and fifth active regions along a second direction different from the first direction. A first gate stack is connected to the first and second active regions and extends longitudinally above the first unit along the second direction. A second gate stack is also included. A first active region is connected to a second active region; a second gate stack extends longitudinally along a second direction above a first cell; a third gate stack is connected to a first active region and extends longitudinally along a second direction above a first cell; a fourth gate stack is connected to both the fourth and fifth active regions and extends longitudinally along a second direction above a first cell; a fifth gate stack is connected to the first active region and extends longitudinally along a second direction above a second cell; and a sixth gate stack is connected to both the fourth and fifth active regions and extends longitudinally along a second direction above a second cell. An isolation dielectric member is connected to the end portions of one or more of the second, third, and fourth active regions. The fourth gate stack extends between the first and sixth gate stacks, wherein along a first direction, the spacing between the first and fourth gate stacks spans a first distance, and the spacing between the fourth and sixth gate stacks spans a second distance, and the second distance is greater than the first distance.

[0066] In one embodiment, a second active region extends longitudinally within a first unit, and a third active region extends longitudinally within a second unit. A fourth active region extends longitudinally across the first and second units. The first and fifth active regions form an n-type active region, and the second, third, and fourth active regions form a p-type active region.

[0067] In one embodiment, the spacing between the first gate stack and the third gate stack, and the spacing between the second gate stack and the fourth gate stack, each span a third distance, wherein the third distance is greater than the first distance and less than the second distance.

[0068] In one embodiment, the spacing between the first gate stack and the third gate stack, and the spacing between the second gate stack and the fourth gate stack, each span a first distance, wherein the spacing between the third gate stack and the fifth gate stack, and the spacing between the fourth gate stack and the sixth gate stack, each span a second distance.

[0069] In one embodiment, the first gate stack, the fourth gate stack, and the sixth gate stack each include a base portion and a protruding portion, wherein the protruding portions of the first gate stack and the fourth gate stack bend from the base portions of the first gate stack and the fourth gate stack toward each other, thereby reducing the protruding distance between the first gate stack and the fourth gate stack, and wherein the protruding portions of the fourth gate stack and the sixth gate stack bend away from the base portions of the fourth gate stack and the sixth gate stack, thereby increasing the protruding distance between the fourth gate stack and the sixth gate stack.

[0070] In a further embodiment, the base portion of the first gate stack is connected to the first active region, and the protruding portion of the first gate stack is connected to the second active region.

[0071] In a further embodiment, the spacing between the third gate stack and the fifth gate stack spans a third distance, wherein the first distance is equal to the third distance minus the protrusion distance, and the second distance is equal to the third distance plus the protrusion distance.

[0072] In a further embodiment, the first gate stack, the fourth gate stack, and the sixth gate stack each further include an extension, wherein each extension extends the corresponding protrusion by half a protrusion distance, wherein the extension extends from the gate end protrusion, the gate end protrusion being adjacent to one of the second, third, and fourth active regions. In a further embodiment, the spacing between the third gate stack and the fifth gate stack spans a third distance, and the spacing between two adjacent gate end protrusions also spans a third distance.

[0073] In a further embodiment, the semiconductor device further includes a first source / drain component spanning a first distance over one of the first active region, the second active region, the third active region, the fourth active region, and the fifth active region; and a second source / drain component spanning a second distance over one of the first active region, the second active region, the third active region, the fourth active region, and the fifth active region.

[0074] Another aspect of the present invention relates to a semiconductor device comprising a first unit having: a first active region and a second active region extending longitudinally along a first direction, wherein the second active region extends a greater length than the first active region in the first unit; a first gate stack extending along a second direction different from the first direction, wherein the first gate stack is connected to a first channel region of the first active region and a first channel region of the second active region; a second gate stack extending along a second direction, wherein the second gate stack is connected to a second channel region of the second active region; and a third gate stack extending along the second direction, wherein the third gate stack has a gate end portion adjacent to a first edge of the first active region. This device includes a second unit having: a first active region and a second active region extending longitudinally along a first direction, wherein the second active region extends a greater length than the first active region in the second unit; a fourth gate stack extending along a second direction, the fourth gate stack being connected to a second channel region and a third channel region of the first active region; a fifth gate stack extending along the second direction, the fifth gate stack being connected to the fourth channel region of the second active region; and a sixth gate stack extending along the second direction, the sixth gate stack having a gate end portion adjacent to a second edge of the first active region. The first active region between the first gate stack and the third gate stack spans a first distance, and the first active region between the first gate stack and the fourth gate stack spans a second distance, the second distance being greater than the first distance.

[0075] In one embodiment, a second active region between the first gate stack and the second gate stack spans a third distance, and a second active region between the first gate stack and the fourth gate stack also spans a third distance. The third distance is greater than the first distance and less than the second distance. In one embodiment, the first distance is equal to the third distance minus the protrusion distance, and the second distance is equal to the third distance plus the protrusion distance.

[0076] In a further embodiment, the second gate stack has a uniform gate width, and the first and second cells each have a cell width equal to twice the third distance plus twice the uniform gate width. In a further embodiment, the sum of the first and second distances plus twice the uniform gate width equals the cell width.

[0077] In one embodiment, the second gate stack has a uniform gate width, and the gate end portion of the third gate stack has a uniform gate width.

[0078] In one embodiment, the second gate stack has a uniform gate width, and the gate end portion of the third gate stack has a width greater than the uniform gate width. In a further embodiment, along a second direction, the gate end portion of the third gate stack has sidewalls aligned with the sidewalls of the second gate stack.

[0079] Another aspect of the present invention relates to a method for forming a semiconductor device, the method comprising forming a plurality of active regions above a substrate, the plurality of active regions extending longitudinally along a first direction; forming a plurality of gates above a plurality of channel regions of the plurality of active regions, the plurality of gates extending longitudinally along a second direction different from the first direction, each of the plurality of gates including a protrusion, the protrusion causing an asymmetric gate spacing along the first direction; forming a gate dicing member cutting across the plurality of gates along the first direction and at the end portion of the protrusion at one or more interfaces; and forming a plurality of source / drain contacts and a plurality of vias above a plurality of source / drain members of the plurality of active regions, wherein the plurality of source / drain members have an asymmetric width corresponding to the asymmetric gate spacing.

[0080] In one embodiment, the multiple gates have protrusions that are continuously formed without breaking.

[0081] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: The first active region, the second active region, the third active region, the fourth active region, and the fifth active region extend longitudinally along the first direction, wherein, The first active region and the fifth active region extend completely across the first unit and the adjacent second unit, wherein the second active region, the third active region and the fourth active region partially extend across the first unit and the second unit, and are disposed between the first active region and the fifth active region along a second direction different from the first direction. A first gate stack is connected to the first active region and the second active region, and the first gate stack extends longitudinally above the first cell along the second direction; The second gate stack is connected to the fifth active region, and the second gate stack extends longitudinally above the first unit along the second direction; A third gate stack is connected to the first active region, and the third gate stack extends longitudinally above the first unit along the second direction; A fourth gate stack is connected to the fourth active region and the fifth active region, and the fourth gate stack extends longitudinally above the first unit along the second direction; A fifth gate stack is connected to the first active region, and the fifth gate stack extends longitudinally along the second direction above the second cell; and A sixth gate stack is connected to the fourth active region and the fifth active region, and the sixth gate stack extends longitudinally above the second cell along the second direction. The isolation dielectric component is connected to the end portions of one or more of the second active region, the third active region, and the fourth active region; The fourth gate stack extends between the first gate stack and the sixth gate stack, wherein, along the first direction, the interval between the first gate stack and the fourth gate stack spans a first distance, the interval between the fourth gate stack and the sixth gate stack spans a second distance, and the second distance is greater than the first distance.

2. The semiconductor device according to claim 1, wherein, The second active region extends longitudinally within the first unit, and the third active region extends longitudinally within the second unit. The fourth active region extends longitudinally across the first unit and the second unit. The first active region and the fifth active region form an n-type active region, and the second active region, the third active region, and the fourth active region form a p-type active region.

3. The semiconductor device according to claim 1, wherein, The spacing between the first gate stack and the third gate stack, and the spacing between the second gate stack and the fourth gate stack, each span a third distance, wherein the third distance is greater than the first distance and less than the second distance.

4. The semiconductor device according to claim 1, wherein, The spacing between the first gate stack and the third gate stack, and the spacing between the second gate stack and the fourth gate stack, each span the first distance, wherein the spacing between the third gate stack and the fifth gate stack, and the spacing between the fourth gate stack and the sixth gate stack, each span the second distance.

5. The semiconductor device according to claim 1, wherein, The first gate stack, the fourth gate stack, and the sixth gate stack each include a base portion and a protruding portion, wherein the respective protruding portions of the first gate stack and the fourth gate stack bend toward each other from their respective base portions, such that the spacing between the first gate stack and the fourth gate stack reduces the protruding distance, and wherein the respective protruding portions of the fourth gate stack and the sixth gate stack bend away from their respective base portions, such that the spacing between the fourth gate stack and the sixth gate stack increases the protruding distance.

6. The semiconductor device according to claim 5, wherein, The base portion of the first gate stack is connected to the first active region, and the protruding portion of the first gate stack is connected to the second active region.

7. A semiconductor device comprising a first unit and a second unit, wherein: The first unit has: The first active region and the second active region extend longitudinally along the first direction. In the first unit, the second active region extends a longer length than the first active region. A first gate stack extends along a second direction different from the first direction, and the first gate stack is connected to the first channel region of the first active region and the first channel region of the second active region. The second gate stack extends along the second direction and is connected to the second channel region of the second active region; and A third gate stack extends along the second direction, the third gate stack having a gate end portion adjacent to a first edge of the first active region; as well as The second unit has: The first active region and the second active region extend longitudinally along the first direction. In the second unit, the second active region extends a greater length than the first active region. A fourth gate stack extends along the second direction, and the fourth gate stack is connected to the second channel region of the first active region and the third channel region of the second active region; A fifth gate stack extends along the second direction and is connected to the fourth channel region of the second active region; and A sixth gate stack extends along the second direction, the sixth gate stack having a gate end portion adjacent to a second edge of the first active region, wherein the first active region between the first gate stack and the third gate stack spans a first distance, the first active region between the first gate stack and the fourth gate stack spans a second distance, and the second distance is greater than the first distance.

8. The semiconductor device according to claim 7, wherein, The second active region between the first gate stack and the second gate stack spans a third distance, and the second active region between the first gate stack and the fourth gate stack spans the third distance, wherein the third distance is greater than the first distance and less than the second distance.

9. A method for forming a semiconductor device, comprising: Multiple active regions are formed above the substrate, and the multiple active regions extend longitudinally along a first direction; A plurality of gates are formed above a plurality of channel regions of the plurality of active regions, the plurality of gates extending longitudinally along a second direction different from the first direction, wherein each of the plurality of gates includes a protrusion portion that results in an asymmetric gate spacing along the first direction; A gate cutting member is formed along the first direction and at one or more interfaces at the end portion of the protrusion, cutting across the plurality of gates; and Multiple source / drain contacts and multiple vias are formed above multiple source / drain components in the multiple active regions, wherein the multiple source / drain components have an asymmetric width corresponding to the asymmetric gate spacing.

10. The method for forming a semiconductor device according to claim 9, wherein, The plurality of gates have the protruding portions formed continuously without breakage.

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