Method for manufacturing a semiconductor package

Abstract

Procedure, comprehensive: Encapsulation of an integrated circuit chip (114) in a molded composite material (130), wherein the integrated circuit chip (114) has a chip connector; Deposition of a first dielectric layer (133) over the mold composite material (130); Structuring a first opening (140) through the first dielectric layer (133); Forming a first conductive column (702) in the first opening (140) on the chip connector of the integrated circuit chip (114); Deposition of a second dielectric layer (146) over the first dielectric layer (133); Structuring a second opening (148) in the second dielectric layer (146), wherein the second opening (148) exposes the first opening (140); and Forming a first conductive via (704) around the first conductive pillar (702) in the first opening (140) and the second opening (148).

Description

GENERAL STATE OF THE ART

[0001] The semiconductor industry has experienced rapid growth thanks to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, these improvements in integration density have resulted from repeated reductions in the minimum feature size, enabling the integration of more components into a given area. As the demand for ever smaller electronic components has grown, so has the need for smaller and more innovative packaging techniques for semiconductor chips. One example of such a packaging system is package-on-package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to achieve a high degree of integration and component density.PoP technology generally enables the production of semiconductor devices with extended functionalities and small footprints on a printed circuit board (PCB).

[0002] Prior art relating to the subject matter of the invention can be found, for example, in US 2014 / 0 252 647 A1, DE 10 2015 113 085 A1 and DE 10 2015 116 822 A1.

[0003] The invention is defined by the main claim. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The embodiments described in this disclosure are best understood with reference to the detailed description below, when read together with the accompanying figures. It should be noted that, in accordance with common industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be enlarged or reduced as desired for clarity. The Fig. Figures 1 to 23 show cross-sectional views of intermediate steps in a process for forming a package according to some embodiments. The Fig. Figures 24 to 26 show cross-sectional views of intermediate steps in a process for forming a package arrangement according to some embodiments. The Fig. Figures 27 to 42 show the formation of a stacked via arrangement according to some other embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples of the realization of various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which additional features can be formed between the first and second features such that the first and second features cannot be in direct contact. Furthermore, reference numerals and / or symbols may be repeated in the various examples in the present disclosure.This repetition serves to simplify and clarify matters and does not in itself imply any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatial relational terms such as "below," "below," "lower," "above," "upper," and the like can be used here for the sake of simplicity to describe the relationship of one element or feature to another element or feature (other elements or features), as illustrated in the figures. These spatial relational terms are intended to encompass various orientations of the component in use or operation, in addition to the orientation shown in the figures. The device can be oriented differently (rotated by 90 degrees or in other orientations), and the spatial designations used here can be interpreted accordingly.

[0007] The embodiments discussed here can be considered in the context of a package assembly (e.g., a package-on-package (PoP) assembly) that incorporates vias in a redistribution arrangement, and methods for forming these vias. Stacked vias are used here to describe multiple conductive vias (a "stack") that connect different metallization structures, each of the multiple conductive vias being vertically oriented (e.g., a conductor extends perpendicular to a main face of the redistribution arrangement through each of the multiple vias). The various embodiments can provide methods for forming the stacked conductive vias with reduced defects, such as...This results in reduced stress at the interfaces between vias during thermal cycling, reduced void formation within the vias, and / or reduced formation of metal oxide (e.g., copper oxide) intermediate layers between adjacent stacked vias, and the like. For example, in various embodiments, a seed layer can be provided as a diffusion-blocking layer (e.g., copper diffusion) between adjacent stacked vias. In some embodiments, the seed layer can be a multilayer arrangement, including, for example, a titanium layer and a copper layer. Furthermore, the intermediate surfaces between the stacked vias can be non-planar (e.g., staggered) to increase the overall strength of the stacked via arrangement.These embodiments can be provided in various ways without a significant increase in manufacturing costs.

[0008] The findings of this disclosure can be applied to any package arrangement comprising stacked conductive vias. Other embodiments consider other applications, such as different package types or configurations, which are readily apparent to those skilled in the art upon reading this disclosure. It should be noted that the embodiments discussed here do not necessarily require the illustration of every component or feature that may be present in an arrangement. For example, components that are present multiple times may be omitted from a figure, such as when the discussion of one of the components may be sufficient to illustrate the aspects of the embodiment.Furthermore, the method implementations discussed here can be presented as if they were being carried out in a specific order; however, other embodiments of the method can be carried out in any logical order.

[0009] The Fig. Figures 1 to 23 show cross-sectional views of intermediate steps during a process for forming a first package 200 according to some embodiments. The first package 200 can also be referred to as an integrated fan-out package (InFO package). Fig. Figures 1 to 23 are cross-sectional views showing a first package area 600 for the formation of the first package 200. It should be clear that multiple packages can be formed simultaneously in multiple package areas.

[0010] In Fig. In this embodiment, a support substrate 100 is provided, and a release layer 102 is formed on the support substrate 100. The support substrate 100 can be a glass support substrate, a ceramic support substrate, or the like. The support substrate 100 can be a wafer such that several packages can be formed simultaneously on the support substrate 100. The release layer 102, which can be released together with the support substrate 100 from the overlying arrangements formed in subsequent steps, can be formed from a polymer-based material. In some embodiments, the release layer 102 is a heat-release epoxy-based material that loses its adhesive properties upon heating, such as a light-to-heat conversion (LTHC) release coating.In other embodiments, the release layer 102 can be an ultraviolet (UV) adhesive that loses its adhesive properties when exposed to UV radiation. The release layer 102 can be applied and cured as a liquid, it can be a laminate film layered onto the support substrate 100, or it can be similar. The top surface of the release layer 102 can be smoothed and exhibit a high degree of coplanarity.

[0011] In Fig. 2. A dielectric layer 104 and a metallization structure 106 (sometimes referred to as a redistribution layer or redistribution line) are formed. The dielectric layer 104 is formed on the release layer 102. The bottom surface of the dielectric layer 104 can contact the top surface of the release layer 102. In some embodiments, the dielectric layer 104 is formed from a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 104 is formed from a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or similar materials. The dielectric layer 104 can be formed by any permissible deposition process, such as…Rotational coating, chemical vapor deposition (CVD), lamination, the like or a combination thereof, may be used.

[0012] The metallization structure 106 is formed on the dielectric layer 104. As an example of the formation of the metallization structure 106, a seed layer (not shown) is formed over the dielectric layer 104. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising several sublayers made of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer can be formed, for example, using PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by rotational coating or the like and exposed for patterning. The structure of the photoresist corresponds to the metallization structure 106.During structuring, openings are created through the photoresist to expose the seed layer. A conductive material is then formed in these openings and on the exposed portions of the seed layer. This conductive material can be created by plating, such as electroplating or electroless plating. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or similar. The photoresist and the portions of the seed layer where the conductive material is not present are then removed. The photoresist can be removed by an acceptable ashing or peeling process, such as using oxygen plasma. Once the photoresist is removed, the exposed portions of the seed layer are removed, for example, by an acceptable etching process, such as wet or dry etching.The remaining sub-areas of the seed layer and the conductive material form the metallization structure 106.

[0013] In Fig. 3. A dielectric layer 108 is formed on the metallization structure 106 and the dielectric layer 104. In some embodiments, the dielectric layer 108 is formed from a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, which can be patterned using a lithographic mask. In other embodiments, the dielectric layer 108 is formed from a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer 108 can be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 108 is then patterned to form openings for exposing portions of the metallization structure 106. The patterning can be performed using an acceptable process, such as…by exposing the dielectric layer 108, if the dielectric layer is a photosensitive material, or by etching, for example using anisotropic etching.

[0014] The dielectric layers 104 and 108 and the metallization structures 106 can be referred to as a backside redistribution arrangement 110. In the illustrated embodiment, the backside redistribution arrangement 110 comprises the two dielectric layers 104 and 108 and one metallization structure 106. In other embodiments, the backside redistribution arrangement 110 can comprise any number of dielectric layers, metallization structures, and vias. One or more additional metallization structures and dielectric layers can be formed in the backside redistribution arrangement 110 by repeating the processes for forming a metallization structure 106 and a dielectric layer 108.During the formation of a metallization structure, vias (not shown) can be formed by the formation of the seed layer and the conductive material of the metallization structure in the opening of the underlying dielectric layer. These vias can thus connect and electrically link the different metallization structures.

[0015] Then the vias 112 are formed. As an example of forming the vias 112, a seed layer is formed over the backside redistribution arrangement 110, e.g., the dielectric layer 108 and the exposed portions of the metallization structure 106, as shown. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer having several sublayers made of different materials. In some embodiments, the seed layer has a titanium layer and a copper layer over the titanium layer. The seed layer can be formed, for example, using PVD or the like. Then a photoresist is formed and patterned on the seed layer. The photoresist can be formed by rotational coating or the like and exposed for patterning.The photoresist structure corresponds to the vias. During structuring, openings are formed through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating, or similar processes. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or similar. The photoresist and portions of the seed layer where the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or peeling process, such as using oxygen plasma or similar methods. Once the photoresist is removed, the exposed portions of the seed layer are removed, for example, using an acceptable etching process.Wet or dry etching. The remaining portions of the seed layer and the conductive material form the vias 112.

[0016] In Fig. 4. An integrated circuit chip 114 is bonded to the dielectric layer 108 using an adhesive 116. In the illustrated embodiment, one integrated circuit chip 114 is bonded in the first package area 600; in other embodiments, more or fewer integrated circuit chips 114 can be bonded in each area. For example, in one embodiment, several integrated circuit chips 114 can be bonded in the first package area 600. The integrated circuit chips 114 can be logic chips (e.g., central processing unit, microcontroller, etc.), memory chips (e.g., dynamic random access memory (DRAM) chip, static random access memory (SRAM) chip, etc.), power management chips (e.g., integrated power management chip (PMIC)), radio frequency (RF) chips, sensor chips, microelectromechanical systems (MEMS) chips, signal processing chips (e.g., digital signal processing (DSP) chip), front-end chips (e.g.,...)B. Analog front-end (AFE) chips), the like, or a combination thereof. Furthermore, in some embodiments, the integrated circuit chips 114 may have different sizes (e.g., different heights and / or surface areas), and in other embodiments, the integrated circuit chips 114 may be of the same size (e.g., the same heights and / or surface areas).

[0017] Before being bonded to the dielectric layer 108, the integrated circuit chips 114 can be processed according to the manufacturing processes applicable for forming integrated circuits in the integrated circuit chips 114. For example, the integrated circuit chips 114 each have a semiconductor substrate 118, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate can comprise other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used. Devices, such asTransistors, diodes, capacitors, resistors, etc., can be formed in and / or on the semiconductor substrate 118, and they can be interconnected by interconnection arrangements 120, which are realized, for example, by metallization structures in one or more dielectric layers on the semiconductor substrate 118, to form an integrated circuit.

[0018] The integrated circuit chips 114 also have contact points 122, such as aluminum contact points, where external connections are made. The contact points 122 are located at positions that can be referred to as the respective active sides of the integrated circuit chips 114. Passivation films 124 are located on the integrated circuit chips 114 and on portions of the contact points 122. Openings to the contact points 122 are formed through the passivation films 124. Chip connectors 126, such as conductive pillars (which, for example, have a metal such as copper), are located in the openings through the passivation films 124 and are mechanically and electrically connected to the respective contact points 122. The chip connectors 126 can be formed, for example, by plating or the like.The chip connectors 126 electrically connect the respective integrated circuits of the integrated circuit chips 114. Solder caps (not shown) can be formed on the chip connectors 126 during chip testing.

[0019] A dielectric material 128 is present on the active sides of the integrated circuit chips 114, such as on the passivation films 124 and the chip connectors 126. The dielectric material 128 laterally encapsulates the chip connectors 126, and the dielectric material 128 terminates laterally together with the corresponding integrated circuit chips 114. The dielectric material 128 can be a polymer, such as PBO, polyimide, BCB, or the like; a nitride, such as silicon nitride or the like; an oxide, such as silicon oxide, PSG, BSG, BPSG, or the like; something similar; or a combination thereof, and it can be formed, for example, by spin coating, lamination, CVD, or the like.

[0020] The adhesive 116 is located on the back sides of the integrated circuit chips 114 and adheres the integrated circuit chips 114 to the backside redistribution arrangement 110, such as the dielectric layer 108 in the figure. The adhesive 116 can be any suitable adhesive, an epoxy, a chip adhesion film (DAF), or the like. The adhesive 116 can be applied to a back side of the integrated circuit chips 114, such as a back side of the respective semiconductor wafer, or it can be applied over the surface of the support substrate 100. The integrated circuit chips 114 can be separated, for example by sawing or cutting, and adhered to the dielectric layer 108 by the adhesive 116, for example using a placement tool.

[0021] In the Fig. 5. An encapsulation 130 is formed on the various components. The encapsulation 130 can be a molding compound, an epoxy resin, or the like, and it can be applied by compression molding, injection molding, or the like. After curing, a grinding process can be performed on the encapsulation 130 to expose the vias 112 and the chip connectors 126. After the grinding process, the upper surfaces of the vias 112, the chip connectors 126, and the encapsulation 130 lie in one plane. In some embodiments, the grinding can be omitted, for example, if the vias 112 and the chip connectors 126 are already exposed.

[0022] In the Fig. 6A to 21B, a front-side redistribution arrangement 131 is formed. As shown, the front-side redistribution arrangement 131 has the dielectric layers 133, 146, 160 and 174 and the metallization structures 142, 156 and 170 (sometimes referred to as redistribution layers or redistribution lines). In the Fig. Figures 6A to 21B, those ending with an “A”, are cross-sectional views depicting the first package area 600, and those ending with a “B” are cross-sectional views showing more detail of an area 650 of the front-side redistribution assembly 131 above the integrated circuit chips 114. A stacked via arrangement 132 is formed in area 650 of the front-side redistribution assembly 131. The stacked via arrangement 132 has conductive vias that are vertically oriented (e.g., a conductor extends perpendicular to a major face of the encapsulation 130 through each of the multiple conductive vias). Fig. In Figures 6A to 21B, some features (such as the seedbeds discussed below) may only be shown in one of the figures “A” or “B”, and they may have been omitted from the corresponding figure “B” or “A” for the sake of simplicity.

[0023] In the Fig. 6A and Fig. In 6B, the dielectric layer 133 is deposited on the encapsulation 130, the vias 112, and the chip connectors 126. In some embodiments, the dielectric layer 133 is formed from a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, and which can be patterned using a lithography mask. In other embodiments, the dielectric layer 133 is formed from a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer 133 can be formed by spin coating, lamination, CVD, or a combination thereof.

[0024] The dielectric layer 133 is then patterned. During the patterning process, openings 134 are formed to expose portions of the vias 112 and the chip connectors 126. The patterning can be carried out by a permissible process, for example, by exposing the dielectric layer 133 if it is a photosensitive material, or by using an etching process, such as anisotropic etching. If the dielectric layer 133 is a photosensitive material, it can be developed after exposure.

[0025] A seed layer 136 is then formed over the dielectric layer 133 and in the openings 134 that extend through the dielectric layer 133. In some embodiments, the seed layer 136 is a metal layer, which can be a single layer or a composite layer comprising several sublayers formed from different materials. In some embodiments, the seed layer 136 comprises a titanium layer and a copper layer over the titanium layer. The seed layer 136 can be formed, for example, using PVD or the like.

[0026] In the Fig. 7A and Fig. In step 7B, a photoresist 138 is formed and structured on the seed layer 136. The photoresist 138 can be formed by a rotary coating or the like and can be exposed for structuring. The structure of the photoresist 138 corresponds to the metallization structure 142. During structuring, openings 140 are formed through the photoresist 138 to expose the seed layer 136.

[0027] In the Fig. 8A and Fig. In 8B, a conductive material is deposited in the openings 140 of the photoresist 138 and on the exposed portions of the seed layer 136. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, or the like. In one embodiment, the conductive material is formed by a shape-retaining plating process. The shape-retaining plating process can be a copper electroplating process carried out with a current density of less than approximately 2.2 A / dm². 2 , such as a current density of approximately 0.3 A / dm² 2 up to approximately 0.9 A / dm 2The plating solution may contain, for example, copper sulfate, and it may have additives such as an accelerator, an inhibitor, a smoothing agent, and / or the like. Such a plating solution and current density allow the plating process to be a shape-retaining plating process. Since the metallization structure 142 is formed by a shape-retaining plating process, the sub-regions of the metallization structure 142 that extend over the upper surface of the dielectric layer 133 can have approximately the same thickness as the sub-regions of the metallization structure 142 that extend along the sides and bottom of the openings 134.

[0028] The bond between the conductive material and underlying portions of the seed layer 136 forms the metallization structure 142. A portion of the metallization structure 142 forms a first layer of the stacked via arrangement 132. The metallization structure 142 features conductive vias 143. These conductive vias 143 are formed in the openings 134 through the dielectric layer 133, e.g., to the vias 112 and / or the chip connectors 126. Furthermore, as a result of the shape-retaining plating process, recesses 144 are formed in the conductive vias 143.

[0029] In the Fig. 9A and Fig. 9B, the photoresist 138 and portions of the seed layer 136 where no conductive material has formed are removed. The photoresist 138 can be removed by an acceptable ashing or peeling process, such as using an oxygen plasma or the like. Once the photoresist 138 is removed, the exposed portions of the seed layer 136 are removed, such as by using an acceptable etching process, such as wet or dry etching.

[0030] In the Fig. 10A and Fig. In 10B, the dielectric layer 146 is deposited on the dielectric layer 133 and the metallization structure 142. In some embodiments, the dielectric layer 146 is formed from a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, and which can be patterned using a lithographic mask. In other embodiments, the dielectric layer 146 is formed from a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer 146 can be formed by spin coating, lamination, CVD, the like, or a combination thereof.

[0031] The dielectric layer 146 is then structured. During structuring, openings 148 are formed to expose portions of the metallization structure 142. In particular, the openings 148 expose the grooves 144. The structuring can be carried out using a permissible process, such as by exposing the dielectric layer 146 if the dielectric layer is a photosensitive material, or by etching, for example, anisotropic etching. If the dielectric layer 146 is a photosensitive material, then the dielectric layer 146 can be developed after exposure.

[0032] A seed layer 150 is then formed over the dielectric layer 146 and in the openings 148. In some embodiments, the seed layer 150 is a metal layer, which can be a single layer or a composite layer comprising several sublayers formed from different materials. In some embodiments, the seed layer 150 comprises a titanium layer and a copper layer over the titanium layer. The seed layer 150 can be formed, for example, using PVD or the like.The seed layer 150 extends along an upper surface of the dielectric layer 146, along the sides of the openings 148, along an uppermost surface of the metallization structures 142 exposed through the openings 148, along portions of the conductive vias 143 defining the sides of the recesses 144, and along portions of the conductive vias 143 defining the bottom of the recesses 144.

[0033] In the Fig. 11A and Fig. In step 11B, a photoresist 152 is formed and structured on the seed layer 150. The photoresist 152 can be formed by a rotational coating or the like and can be exposed for structuring. The structure of the photoresist 152 corresponds to the metallization structure 156. During structuring, openings 154 are formed through the photoresist to expose the seed layer 150. The openings 154 expose the openings 148 of the dielectric layer 146.

[0034] In the Fig. 12A and Fig. In embodiment 12B, a conductive material is formed on the exposed portions of the seed layer 150 in the openings 154 of the photoresist 152. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, or the like. In one embodiment, the conductive material is formed by a shape-retaining plating process (similar to the metallization structure 142).

[0035] The bond between the conductive material and underlying portions of the seed layer 150 forms the metallization structure 156. A portion of the metallization structure 156 forms a second layer of the stacked via arrangement 132. The metallization structure 156 features conductive vias 157. The conductive vias 157 are formed in the openings 148 through the dielectric layer 146 to form the metallization structure 142. In particular, the conductive vias 157 extend into the recesses 144 of the conductive vias 143. Furthermore, recesses 158 are formed in the conductive vias 157 as a result of the shape-retaining plating process.

[0036] In the Fig. 13A and Fig. In step 13B, the photoresist 152 and portions of the seed layer 150 where the conductive material is not formed are removed. The photoresist 152 can be removed by an acceptable ashing or peeling process, such as using an oxygen plasma or the like. Once the photoresist 152 is removed, the exposed portions of the seed layer 150 are removed, such as by using an acceptable etching process, such as wet or dry etching.

[0037] The formation of conductive vias 143, which have recesses 144, can result in an uneven (e.g., stepped) interface between the metallization structures 142 and 156. Furthermore, the interface between the metallization structures 142 and 156 can occupy several planes that are offset from the interface between the dielectric layers 133 and 146 (e.g., located in a different plane). Package stress can concentrate at the interface between the dielectric layers 133 and 146. By offsetting the interface between the dielectric layers 133 and 146 from the multiple interface planes of the metallization structures 142 and 156, further package stress concentration can be avoided, thereby reducing the probability of crack formation at the interface between the metallization structures 142 and 156.

[0038] In the Fig. 14A and Fig. In 14B, the dielectric layer 160 is deposited on the dielectric layer 146 and the metallization structure 156. In some embodiments, the dielectric layer 160 is formed from a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, and which can be structured using a lithographic mask. In other embodiments, the dielectric layer 160 is formed from a nitride, such as silicon nitride, an oxide, such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 160 can be formed by spin coating, lamination, CVD, or a combination thereof.

[0039] The dielectric layer 160 is then structured. During structuring, openings 162 are formed to expose portions of the metallization structure 156. In particular, the openings 162 expose the grooves 158. The structuring can be carried out using a permissible process, such as by exposing the dielectric layer 160 if the dielectric layer is a photosensitive material, or by etching, for example, anisotropic etching. If the dielectric layer 160 is a photosensitive material, then the dielectric layer 160 can be developed after exposure.

[0040] A seed layer 164 is then formed over the dielectric layer 160 and in the openings 162. In some embodiments, the seed layer 164 is a metal layer, which can be a single layer or a composite layer comprising several sublayers formed from different materials. In some embodiments, the seed layer 164 comprises a titanium layer and a copper layer over the titanium layer. The seed layer 164 can be formed, for example, using PVD or the like.The seed layer 164 extends along an upper surface of the dielectric layer 160, along the sides of the openings 162, along an uppermost surface of the metallization structures 156 exposed through the openings 162, along portions of the conductive vias 157 defining the sides of the recesses 158, and along portions of the conductive vias 157 defining the bottom of the recesses 158.

[0041] In the Fig. 15A and Fig. In step 15B, a photoresist 166 is formed and structured on the seed layer 164. The photoresist 166 can be formed by a rotational coating process or the like and exposed for structuring. The structure of the photoresist 166 corresponds to the metallization structure 170. During structuring, openings 168 are formed through the photoresist to expose the seed layer 164. The openings 168 expose the openings 162 of the dielectric layer 160.

[0042] In the Fig. 16A and Fig. In embodiment 16B, a conductive material is formed on the exposed portions of the seed layer 164 in the openings 168 of the photoresist 166. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, or the like. In one embodiment, the conductive material is formed by a shape-retaining plating process (similar to the metallization structure 156).

[0043] The bond between the conductive material and underlying portions of the seed layer 164 forms the metallization structure 170. A portion of the metallization structure 170 forms a third layer of the stacked via arrangement 132. The metallization structure 170 features conductive vias 171. These conductive vias 171 are formed in the openings 162 through the dielectric layer 160 to form the metallization structure 156. In particular, the conductive vias 171 extend into the recesses 158 of the conductive vias 157. Furthermore, recesses 172 are formed in the conductive vias 171 as a result of the shape-retaining plating process.

[0044] In the Fig. 17A and Fig. In step 17B, the photoresist 166 and portions of the seed layer 164 where the conductive material is not formed are removed. The photoresist 166 can be removed by an acceptable ashing or peeling process, such as using an oxygen plasma or the like. Once the photoresist 166 is removed, the exposed portions of the seed layer 164 are removed, such as by using an acceptable etching process, such as wet or dry etching.

[0045] In the Fig. 18A and Fig. In 18B, the dielectric layer 174 is deposited on the dielectric layer 160 and the metallization structure 170. In some embodiments, the dielectric layer 174 is formed from a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, and which can be structured using a lithographic mask. In other embodiments, the dielectric layer 174 is formed from a nitride, such as silicon nitride, an oxide, such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 174 can be formed by spin coating, lamination, CVD, or a combination thereof.

[0046] The dielectric layer 174 is then structured. This structuring creates openings 176 for exposing portions of the metallization structure 170. In particular, the openings 176 expose the grooves 172. The structuring can be carried out using a permissible process, such as exposure of the dielectric layer 174 if the dielectric layer is a photosensitive material, or etching, for example, anisotropic etching. If the dielectric layer 174 is a photosensitive material, it can be developed after exposure.

[0047] A seed layer 178 is then formed over the dielectric layer 174 and in the openings 176. In some embodiments, the seed layer 178 is a metal layer, which can be a single layer or a composite layer comprising several sublayers formed from different materials. In some embodiments, the seed layer 178 comprises a titanium layer and a copper layer over the titanium layer. The seed layer 178 can be formed, for example, using PVD or the like.The seed layer 178 extends along an upper surface of the dielectric layer 174, along the sides of the openings 176, along an uppermost surface of the metallization structures 170 exposed through the openings 176, along portions of the conductive vias 171 defining the sides of the recesses 172, and along portions of the conductive vias 171 defining the bottom of the recesses 172.

[0048] In the Fig. 19A and Fig. In step 19B, a photoresist 180 is formed and structured on the seed layer 178. The photoresist 180 can be formed by a rotational coating process or the like and exposed for structuring. The structure of the photoresist 180 corresponds to the contact points 184. During structuring, openings 182 are formed through the photoresist to expose the seed layer 178. The openings 182 expose the openings 176 of the dielectric layer 174. The structure of the openings 182 in the photoresist 180 corresponds to the contact points that are subsequently formed on an outer surface of the front-side redistribution arrangement 131.

[0049] In the Fig. 20A and Fig. In embodiment 20B, a conductive material is deposited on the exposed portions of the seed layer 178 in the openings 182 of the photoresist 180. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, or the like. In one embodiment, the conductive material is formed by a gap-filling plating process, which has different plating process parameters than the shape-maintaining plating process. The gap-filling plating process can be a copper electroplating process carried out with a current density of approximately 2.0 A / dm². 2 up to approximately 6.0 A / dm 2 , such as greater than approximately 2.2 A / dm² 2The plating solution may contain copper sulfate and may include additives such as an accelerator, an inhibitor, a smoothing agent, and / or the like. Such a plating solution and current density allow the plating process to be a gap-filling plating process. The plating solution for the gap-filling plating process may be similar to or different from the plating solution used in the shape-maintaining plating process.

[0050] The bond between the conductive material and underlying portions of the seed layer 178 forms the contact points 184. A portion of the contact points 184 forms a fourth layer of the stacked via arrangement 132. The contact points 184 have conductive vias 185. The conductive vias 185 are formed in the openings 176 through the dielectric layer 174 to the metallization structure 170. In particular, the conductive vias 185 extend into the recesses 172 of the conductive vias 171. Furthermore, as a result of the gap-filling plating process, the contact points 184 do not have recesses 186 as deep as the other vias in the stacked via arrangement 132, and they can only have recesses 186 that conform to the underlying shape of the openings 176.The contact points 184 are used to connect subsequently formed conductive connectors, and they can be referred to as under-bump metallizations (UBMs).

[0051] In the Fig. 21A and Fig. 21B, the photoresist 180 and portions of the seed layer 178 where no conductive material has formed are removed. The photoresist 180 can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist 180 is removed, the exposed portions of the seed layer 178 are removed, such as using an acceptable etching process, such as wet or dry etching.

[0052] The front-side redistribution arrangement 131 and the stacked via arrangement 132 are shown as an example. More or fewer dielectric layers and metallization structures can be formed in the front-side redistribution arrangement 131. If fewer dielectric layers and metallization structures are to be formed, then the steps and processes discussed above can be omitted. If more dielectric layers and metallization structures are to be formed, then the steps and processes discussed above can be repeated. A person skilled in the art will easily recognize which steps and processes should be omitted or repeated.

[0053] In Fig. 22 Conductive connectors 187 are formed on the contact points 184. The conductive connectors 187 can be BGA connectors, solder balls, metal pillars, flip-chip mount contact bumps (C4 bumps), micro contact bumps, contact bumps formed using an electroless nickel-palladium-gold (ENEPIG) technique, or the like. The conductive connectors 187 can comprise a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 187 are formed by first forming a solder layer using such common methods as vapor deposition, electroplating, printing, solder transfer, ball placement, or the like. Once a solder layer has been applied to the assembly, remelting can be performed to form the material into the desired contact bump shapes.In another embodiment, the conductive connectors 187 are metal columns (such as a copper column) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal columns can be solder-free and have substantially vertical sidewalls. In such embodiments, a metal top layer (not shown) can be formed on top of the conductive connector 187. The metal top layer can contain nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and can be formed by a plating process.

[0054] Furthermore, an integrated passive device (IPD) 188 is attached to the front-side redistribution arrangement 131. The IPD 188 is electrically connected to the stacked via arrangement 132, and the stacked via arrangement 132 can be electrically connected to the integrated circuit chip 114. In one embodiment, the lowest via (e.g., the metallization structure 142) of the stacked via arrangement 132 is electrically and physically connected to one of the chip connectors 126 of the integrated circuit chip 114, and the uppermost via (e.g., the contact point 184) of the stacked via arrangement 132 is electrically and physically connected to the IPD 188.

[0055] Before being bonded to the front-side redistribution arrangement 131, the IPD 188 can be processed according to applicable manufacturing processes. For example, the IPD 188 can include one or more passive components within a framework of the IPD 188. The framework could include a substrate and / or an encapsulation. In embodiments that include a substrate, the substrate could be a semiconductor substrate, such as silicon, doped or undoped, or an active layer of an SOI substrate. The semiconductor substrate can include another semiconductor material, such as germanium, a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. Other substrates, such asMultilayer or gradient substrates are used. The passive components can include a capacitor, a resistor, an inductor, the like, or a combination thereof. The passive components can be formed in and / or on the semiconductor substrate and / or within the encapsulation, and they can be interconnected by intermediate connectors, which are realized, for example, by metallization structures in one or more dielectric layers on the substrate to form the IPD 188. The IPD 188 can be a surface-mount device (SMD), a two-terminal IPD, a multi-terminal IPD, or another type of passive component. The IPD 188 is electrically and physically connected to the contact point 184 of the stacked via assembly 132 by the conductive connectors 189, thereby connecting the front-side redistribution assembly 131 to the IPD 188.The conductive connectors 189 may be similar to or different from the conductive connectors 187.

[0056] In Fig. 23. A detachment of the support substrate is carried out to separate (detach) the support substrate 100 from the rear redistribution arrangement 110, e.g., the dielectric layer 104. According to some embodiments, the detachment includes projecting light, such as laser light or UV light, onto the detachment layer 102, so that the detachment layer 102 disintegrates under the heat of the light and the support substrate 100 can be detached. The arrangement is then turned over and placed on a belt 192.

[0057] Furthermore, openings 194 are formed through the dielectric layer 104 to expose parts of the metallization structure 106. The openings can be produced, for example, by laser drilling, etching, or similar processes.

[0058] The Fig. Figures 24 to 26 show cross-sectional views of intermediate steps during a process for forming a package assembly 500 according to some embodiments. The package assembly 500 can be described as a package-on-package (PoP) assembly.

[0059] In the Fig. Figure 24 shows that a second package 300 is attached to the first package 200. The second package 300 comprises a substrate 302 and one or more stacked chips 308 (308A and 308B) coupled to the substrate 302. Although a single chip stack 308 (308A and 308B) is shown, in other embodiments several stacked chips 308 (each comprising one or more stacked chips) can be arranged side by side, coupled to an equal area of ​​the substrate 302. The substrate 302 can be made of a semiconductor material, such as silicon, germanium, diamond, or the like. In some embodiments, composite materials such as silicon-germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon-germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Furthermore, substrate 302 may be a silicon-on-insulator (SOI) substrate.In general, an SOI substrate comprises a layer of a semiconductor material, such as epitaxial silicon, germanium, silicon-germanium, SOI, silicon-germanium-on-insulator (SGOI), or combinations thereof. In an alternative embodiment, the substrate 302 is based on an insulating core, such as a glass fiber-reinforced resin core. An example of a core material is glass fiber resin, such as FR4. Alternatives for the core material include bismaleimide triazine (BT) resin or, optionally, other printed circuit board (PCB) materials or films. Build-up films, such as the Ajinomoto build-up film (ABF), or other laminates can be used for the substrate 302.

[0060] The substrate 302 can incorporate (not shown) active and passive components. As a person skilled in the art will recognize, a wide variety of components, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to meet the structural and functional design requirements for the second package 300. The components can be formed using any suitable methods.

[0061] The substrate 302 can also include metallization layers (not shown) and vias 306. The metallization layers can be formed over the active and passive components and are designed to connect the various components to form functional circuits. The metallization layers can be formed from alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias connecting the conductive material layers, and they can be formed by any suitable process (such as deposition, damascene, dual-damascene, or the like). In some embodiments, the substrate 302 is essentially free of active and passive components.

[0062] The substrate 302 can have bond contact points 303 on a first side of the substrate 202 for connecting the stacked chips 308, and it can have contact points 304 on a second side of the substrate 302, the second side being opposite the first side of the substrate 302 for connecting the functional connectors 314. In some embodiments, the bond contact points 303 and 304 are formed by forming (not shown) recesses into the (not shown) dielectric layers on the first and second sides of the substrate 302. The recesses can be formed to allow the bond contact points 303 and 304 to be embedded in the dielectric layers. In other embodiments, the recesses are omitted because the bond contact points 303 and 304 can be formed on the dielectric layer.In some embodiments, the bond contact points 303 and 304 have a thin seed layer (not shown) consisting of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bond contact points 303 and 304 can be deposited over the thin seed layer. The conductive material can be formed by an electrochemical plating process, a currentless plating process, CVD, ALD, PVD, the like, or a combination thereof. In one embodiment, the conductive material of the bond contact points 303 and 304 is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

[0063] In one embodiment, the bond contact points 303 and 304 are UBMs comprising layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, a person skilled in the art will recognize that there are many suitable configurations of materials and layers, such as a chromium / chromium-copper alloy / copper / gold configuration, a titanium / titanium-tungsten / copper configuration, or a copper / nickel / gold configuration, that are suitable for making the bond contact points 303 and 304. It is fully intended that any suitable materials or material layers that can be used for the bond contact points 303 and 304 are included within the scope of this application. In some embodiments, the vias 306 extend through the substrate 302 and connect at least one bond contact point 303 to at least one bond contact point 304.

[0064] In the illustrated embodiment, the stacked chips 308 are connected to the substrate 302 by wire bonds 310, although other connections, such as conductive contact bumps, can be used. In one embodiment, the stacked chips 308 are stacked memory chips. For example, the stacked chips 308 can be memory chips such as low-power (LP) double-speed (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or similar memory modules.

[0065] The stacked chips 308 and the wire bonds 310 can be encapsulated by a molding material 312. The molding material 312 can be formed onto the stacked chips 308 and the wire bonds 310, for example, by compression molding. In some embodiments, the molding material 312 is a molding compound, a polymer, an epoxy, a silicon dioxide filler, the like, or a combination thereof. A curing step can be performed to cure the molding material 312, wherein the curing can be thermal curing, UV curing, the like, or a combination thereof.

[0066] In some embodiments, the stacked chips 308 and the wire bonds 310 are embedded in the mold material 312, and after the mold material 312 has hardened, a planarization step, such as grinding, is performed to remove excess portions of the mold material 312 and to provide a substantially flat surface for the second package 300.

[0067] After the formation of the second package 300, the second package 300 is mechanically and electrically bonded to the first package 200 using the functional connectors 314, the bond contact points 304, and the metallization structure 106. In some embodiments, the stacked chips 308 can be connected to the integrated circuit chips 114 via the wire bonds 310, the bond contact points 303 and 304, the vias 306, the functional connectors 314, and the vias 112.

[0068] The functional connectors 314 can be similar to the conductive connectors 187 described above, and the description is not repeated here, although the functional connectors 314 and the conductive connectors 187 need not be the same. The functional connectors 314 can be arranged in the openings 194 on a side of the substrate 302 opposite the stacked chips 308. In some embodiments, a solder resist 318 can also be formed on the side of the substrate 302 opposite the stacked chips 308. The functional connectors 314 can be arranged in openings in the solder resist 318 to be electrically and mechanically connected to the conductive features (e.g., the bond contact points 304) in the substrate 302. The solder resist 318 can be used to protect areas of the substrate 302 from external damage.

[0069] In some embodiments, the functional connectors 314 are coated with a flux (not shown), such as a residue-free flux, before bonding. The functional connectors 314 can be immersed in the flux, or the flux can be sprayed onto the functional connectors 314. In another embodiment, the flux can be applied to the surfaces of the metallization structures 106.

[0070] In some embodiments, the functional connectors 314 may have an optional epoxy flux (not shown) formed on them before they are melted, with at least some of the epoxy portion of the flux remaining after the second package 300 is attached to the first package 200. This remaining epoxy portion may act as a filler material to reduce stress and protect the joints resulting from the melting of the functional connectors 314.

[0071] A filler material (not shown) can be formed between the first package 200 and the second package 300 and can enclose the functional connectors 314. The filler material can be formed by a capillary flow process after the first package 200 is attached, or it can be formed by a suitable deposition process before the first package 200 is attached.

[0072] The bonding between the second package 300 and the first package 200 can be solder bonding. In one embodiment, the second package 300 is bonded to the first package 200 by a remelting process. During this remelting process, the functional connectors 314 are in contact with the bond contact points 304 and the metallization structures 106 to physically and electrically connect the second package 300 to the first package 200. After the bonding process, an intermetallic compound (IMC, not shown) can form at the interface between the metallization structures 106 and the functional connectors 314, and also at the interface between the functional connectors 314 and the bond contact points 304 (not shown).

[0073] In Fig. 25 A singulation process is carried out by sawing 190 along scoring line areas, e.g., between adjacent package areas. The sawing 190 singulates the first package area 600 from other (not shown) package areas. The resulting singulated first package 200 is from the first package area 600.

[0074] In Fig. 26 The first package 200 is attached to a package substrate 400 using the conductive connectors 187. The package substrate 400 can consist of a semiconductor material, such as silicon, germanium, diamond, or the like. Alternatively, composite materials such as silicon-germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon-germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like can be used. Furthermore, the package substrate 400 can be an SOI substrate. In general, an SOI substrate has a layer of a semiconductor material, such as epitaxial silicon, germanium, silicon-germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the package substrate 400 is based on an insulating core, such as a glass fiber-reinforced resin core. An example of a core material is fiberglass resin, such as FR4.Alternatives for the core material include bismaleimide triazine (BT) resin or, optionally, other printed circuit board (PCB) materials or films. Build-up films, such as ABF, or other laminates can be used for the Package Substrate 400.

[0075] The package substrate 400 can incorporate (not shown) active and passive components. As a person skilled in the art will recognize, a wide variety of components, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to meet the structural and functional design requirements for the package arrangement 500. The components can be formed using any suitable methods.

[0076] The package substrate 400 can also include (not shown) metallization layers and vias, as well as bond contact points 402 over the metallization layers and vias. The metallization layers can be formed over the active and passive components and are designed to connect the various components to form functional circuits. The metallization layers can be formed from alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias connecting the conductive material layers, and they can be formed by any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the package substrate 400 is essentially free of active and passive components.

[0077] In some embodiments, the conductive connectors 187 are melted to attach the first package 200 to the bond contact points 402. The conductive connectors 187 electrically and / or physically connect the package substrate 400, including the metallization layers in the package substrate 400, to the first package 200. In some embodiments, passive components (e.g., surface-mount devices (SMDs), not shown) can be attached to the package 200 before being attached to the package substrate 400 (e.g., bonded to the bond contact points 402). In such embodiments, the passive components can be bonded to the same area of ​​the first package 200 as the conductive connectors 187.

[0078] The conductive connectors 187 can have an epoxy flux (not shown) formed on them before they are melted, with at least some of the epoxy portion of the flux remaining after the first package 200 is attached to the first package 400. This remaining epoxy portion can act as a filler material to reduce stress and protect the joints resulting from the melting of the conductive connectors 187. In some embodiments, a filler material (not shown) can be formed between the first package 200 and the package substrate 400 and can surround the conductive connectors 187. The filler material can be formed by a capillary flow process after the first package 200 is attached, or it can be formed by a suitable deposition process before the first package 200 is attached.

[0079] The Fig. Figures 27 to 42 show the formation of the stacked via arrangement 132 according to some other embodiments. Fig. 27 to 42 represent the range 650. In the embodiment of the Fig. 27 to 42 the vias of the stacked via arrangement 132 are formed around conductive columns.

[0080] In Fig. 27 The dielectric layer 133 is deposited on the encapsulation 130, the vias 112, and the integrated circuit chips 114 (e.g., the chip connectors 126). The dielectric layer 133 is then structured to form the openings 134. The seed layer 136 is then formed over the dielectric layer 133 and in the openings 134 that extend through the dielectric layer 133.

[0081] In Fig. 28. The photoresist 138 is formed and structured on the seedbed 136. Then, the photoresist 138 is structured, forming openings 140 through it that expose the seedbed 136. The width of the openings 140 is less than the width of the openings 134.

[0082] In Fig. 29 A conductive material is formed on the exposed sections of the seedbed 136. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and the underlying sections of the seedbed 136 forms a conductive column 702.

[0083] In the Fig. 30. The photoresist 138 and parts of the seed layer 136, on which the conductive material is not formed, are removed.

[0084] In Fig. Step 31 deposits the dielectric layer 146 on the dielectric layer 133 and around the conductive column 702. The dielectric layer 146 is then structured. During structuring, the openings 148 are formed to expose the openings 134. Then the seed layer 150 is formed over the dielectric layer 146, in the openings 148 by dielectric layer 146, and in the openings 134 by dielectric layer 133. The seed layer 150 extends along the sides of the conductive column 702.

[0085] In Fig. In step 32, the photoresist 152 is formed and structured on the seedbed 150. During structuring, openings 154 are formed by the photoresist to expose the seedbed 150. The openings 154 surround the conductive column 702. Sections of the structured photoresist 152 are arranged above the conductive column 702.

[0086] In Fig. 33 A conductive material is formed on the exposed portions of the seed layer 150. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, or the like. The bond between the conductive material and the underlying portions of the seed layer 150 forms a conductive via 704 around the conductive pillar 702. The conductive via 704 extends through both dielectric layers 133 and 146.

[0087] In Fig. 34. The photoresist 152 and parts of the seed layer 150, on which the conductive material is not formed, are removed.

[0088] In Fig. In step 35, the dielectric layer 160 is deposited onto the dielectric layer 146 and the conductive via 704. The dielectric layer 160 is then patterned. During the patterning, openings 162 are formed to expose portions of the conductive via 704 and the conductive column 702. The seed layer 164 is then formed in the openings 162 through the dielectric layer 160, extending over the dielectric layer 160. The seed layer 164 extends along the side walls and the top surface of the conductive column 702.

[0089] In Fig. In step 36, the photoresist 166 is formed and structured on the seedbed 164. During structuring, the openings 168 are formed by the photoresist to expose the seedbed 164. The openings 168 lie above the conductive column 702 and can have a width approximately equal to the width of the conductive column 702.

[0090] In Fig. 37 A conductive material is formed on the exposed portions of the seedbed 164. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, or the like. The bond between the conductive material and the underlying portions of the seedbed 164 forms a conductive column 706 on top of the conductive column 702.

[0091] In Fig. 38. The photoresist 166 and parts of the seed layer 164 where the conductive material is not formed are removed. Parts of the seed layer 164 along the side walls and the upper surface of the conductive column 702 are not removed.

[0092] In Fig. In step 39, the dielectric layer 174 is deposited on the dielectric layer 160 and the conductive via 704 and around the conductive pillars 702 and 706. The dielectric layer 174 is patterned. During the patterning, openings 176 are formed to expose portions of the conductive via 704 and the conductive pillars 702 and 706. Then, the seed layer 178 is formed over the dielectric layer 174 and in the openings 176 through the dielectric layer 174. The seed layer 178 extends along the side walls of the conductive pillars 702 and 706 and along the upper surface of the conductive pillar 706.

[0093] In Fig. In step 40, the photoresist 180 is formed and structured on the seedbed 178. During structuring, openings 182 are formed through the photoresist 180 to expose the seedbed 178. The openings 182 are located above the conductive columns 702 and 706.

[0094] In Fig. 41 A conductive material is formed on the exposed portions of the seed layer 178. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, or the like. The bond between the conductive material and the underlying portions of the seed layer 178 forms the contact point 184, which has a conductive via 708 around the conductive pillars 702 and 706. The conductive via 708 extends through both dielectric layers 160 and 174. The conductive via 708 can extend over the conductive pillars 702 and 706.

[0095] In Fig. 42. The photoresist 180 and parts of the seed layer 178, on which the conductive material had not formed, are removed.

[0096] Advantages can be achieved with these embodiments. By offsetting the intermediate surface of the dielectric layers 133 and 146 from the multiple intermediate surface planes of the metallization structures 142 and 156, further package stress concentration can be avoided, thereby reducing the probability of crack formation at the intermediate surface of the metallization structures 142 and 156. Furthermore, the seed layers 136, 150, 164, and 178 can act as a diffusion-blocking layer between adjacent stacked vias. In embodiments where conductive pillars 702 and 706 are formed, they can serve as a core framework that reinforces the stacked via arrangement 132.

[0097] In one embodiment, a component comprises: a molded composite material; an integrated circuit chip encapsulated in the molded composite material; a via adjacent to the integrated circuit chip; and a redistribution arrangement over the integrated circuit chip, the molded composite material, and the via, wherein the redistribution arrangement is electrically connected to the integrated circuit chip and the via, and wherein the redistribution arrangement comprises: a first dielectric layer arranged over the molded composite material; a first conductive via extending through the first dielectric layer; and a second dielectric layer arranged over the first dielectric layer and the first conductive via.and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, wherein an intermediate surface between the first conductive via and the second conductive via is not planar.

[0098] In some embodiments, an intermediate surface between the first conductive via and the second conductive via has a first sub-area located in a first plane and a second sub-area located in a second plane, wherein the first plane is close to the integrated circuit chip, the second plane is far from the integrated circuit chip, and an intermediate surface between the first dielectric layer and the second dielectric layer is located in a third plane between the first plane and the second plane.In some embodiments, the redistribution arrangement further comprises: a third dielectric layer above the second dielectric layer and the second conductive via; and a third conductive via extending through the third dielectric layer and into a portion of the second conductive via, wherein an intermediate surface between the second and third conductive vias is not planar. In some embodiments, the device further comprises: an integrated passive device (IPD) attached to the third conductive via.

[0099] In one embodiment, a method comprises: encapsulating an integrated circuit chip in a molded composite material, wherein the integrated circuit chip has a chip connector; depositing a first dielectric layer over the molded composite material; structuring a first opening through the first dielectric layer, exposing the chip connector of the integrated circuit chip; depositing a first seed layer over the first dielectric layer and in the first opening; plating a first conductive via extending through the first dielectric layer on the first seed layer, wherein the first conductive via has a first recess in portions of the first conductive via extending through the first dielectric layer; depositing a second dielectric layer over the first dielectric layer and the first conductive via;Structuring a second opening in the second dielectric layer, wherein the second opening exposes the first notch of the first conductive via; depositing a second seed layer over the second dielectric layer, in the second opening and in the first notch; and plating a second conductive via on the second seed layer, wherein the second conductive via extends into the first notch of the first conductive via and through the second dielectric layer, wherein the second conductive via has a second notch in portions of the second conductive via that extends through the second dielectric layer.

[0100] In some embodiments, the second seed layer has a first sub-region lying in a first plane and a second sub-region lying in a second plane, wherein a second intermediate surface lies in a third plane between the first dielectric layer and the second dielectric layer, and wherein the first plane is close to the integrated circuit chip, the second plane is far from the integrated circuit chip, and the third plane is between the first plane and the second plane. In some embodiments, the second seed layer extends along a top surface of the second dielectric layer, the sides of the second opening, a top surface of the conductive via, the sub-regions of the first conductive via that define the sides of the first recess, and the sub-regions of the first conductive via that define a bottom of the first recess.In some embodiments, an intermediate surface between the second dielectric layer and the second seed layer is not planar. In some embodiments, the method further comprises: depositing a third dielectric layer over the second dielectric layer and the second conductive via; structuring a third opening in the third dielectric layer, wherein the third opening exposes the second recess of the second conductive via; depositing a third seed layer over the third dielectric layer, in the third opening and in the second recess; and plating a third conductive via onto the third seed layer, wherein the third conductive via extends into the second recess of the second conductive via and through the third dielectric layer.In some embodiments, the second conductive via extends through the second dielectric layer and at least partially into the dielectric layer and the third dielectric layer. In some embodiments, the method further comprises: attaching an integrated passive device (IPD) to the third conductive via. In some embodiments, the plating of the third conductive via on the second seed layer is performed using a gap-filling plating process. In some embodiments, the gap-filling plating process includes a plating process performed at a plating current density of 2.0 A / dm². 2 up to 6.0 A / dm 2is carried out, and a plating solution containing copper sulfate is used. In some embodiments, the plating of the second conductive via on the second seed layer is carried out using a shape-retaining plating process. In some embodiments, the shape-retaining plating process includes a plating process carried out with a plating current density of 0.3 A / dm². 2 up to 0.9 A / dm 2 is carried out, and a plating solution containing copper sulfate is used.

[0101] In one embodiment, a method comprises: encapsulating an integrated circuit chip in a molded composite material, wherein the integrated circuit chip has a chip connector; depositing a first dielectric layer over the molded composite material; structuring a first opening through the first dielectric layer; forming a first conductive pillar in the first opening on the chip connector of the integrated circuit chip; depositing a second dielectric layer over the first dielectric layer; structuring a second opening in the second dielectric layer, wherein the second opening exposes the first opening; and forming a first conductive via around the first conductive pillar in the first opening and the second opening.

[0102] In some embodiments, the method further comprises: depositing a third dielectric layer over the second dielectric layer; structuring a third opening in the third dielectric layer, wherein the third opening exposes the first conductive via; forming a second conductive pillar in the third opening on top of the first conductive pillar; depositing a fourth dielectric layer over the third dielectric layer; structuring a fourth opening in the fourth dielectric layer, wherein the fourth opening exposes the third opening; and forming a second conductive via around the second conductive pillar in the third and fourth openings. In some embodiments, the method further comprises: attaching an integrated passive device (IPD) to the second conductive via.In some embodiments, the first conductive via extends through the first dielectric layer, through the second dielectric layer, and partially into the third dielectric layer after the deposition of the third dielectric layer. In some embodiments, the second conductive via is also formed around the first conductive pillar.

Claims

[1] Method comprising: Encapsulating an integrated circuit chip (114) in a molding compound (130), the integrated circuit chip (114) having a chip connector; Depositing a first dielectric layer (133) over the molding compound (130); Structuring a first opening (140) through the first dielectric layer (133); Forming a first conductive pillar (702) in the first opening (140) on the chip connector of the integrated circuit chip (114); depositing a second dielectric layer (146) over the first dielectric layer (133); Structuring a second opening (148) in the second dielectric layer (146), wherein the second opening (148) exposes the first opening (140); and Forming a first conductive via (704) around the first conductive pillar (702) in the first opening (140) and the second opening (148). [2] The method of claim 1, further comprising: depositing a third dielectric layer (160) over the second dielectric layer (146); Patterning a third opening (176) in the third dielectric layer (160), the third opening (176) exposing the first conductive via (704); Forming a second conductive column (706) in the third opening (176) on the first conductive column (702); depositing a fourth dielectric layer (174) over the third dielectric layer (160); Structuring a fourth opening (176) in the fourth dielectric layer (174), the fourth opening (176) exposing the third opening (176); and Forming a second conductive via (708) around the second conductive pillar (706) in the third opening (176) and fourth opening (176). [3] The method of claim 2, further comprising: Attaching an integrated passive component, IPD, to the second conductive via (708). [4] The method of claim 2 or 3, wherein the first conductive via (704) extends through the first dielectric layer (133), through the second dielectric layer (146) and partially into the third dielectric layer (160) after the third dielectric layer (160) has been deposited. [5] The method of any one of the preceding claims 2 to 4, wherein the second conductive via (708) is further formed around the first conductive pillar (702).

Images