METHOD FOR MANUFACTURING FINNE FIELD DEFECT TRANSITOR DEVICES

Abstract

Method for forming a semiconductor device (30), the method comprising: forming a first dummy gate structure (75) and a second dummy gate structure (75) over a fin (64) projecting over a substrate (50); forming a dielectric layer (90) around the first dummy gate structure (75) and the second dummy gate structure (75); removing the first dummy gate structure (75) and the second dummy gate structure (75) to form a first well (69) and a second well (69) in the dielectric layer (90); successively forming a gate dielectric layer (82), an N-type exit layer (84), and a cover layer (85) in the first well (69) and in the second well (69); forming a structured mask layer (87) over the cover layer (85), wherein an opening (89) of the structured mask layer (87) exposes the top layer (85) in the first depression (69);Selective removal of the cover layer (85) in the first well (69) to expose the N-type exit working layer (84) in the first well (69) using a first wet etching process, wherein the first wet etching process is carried out using a fluoride-containing chemical; and selective removal of the N-type exit working layer (84) in the first well (69) to expose the gate dielectric layer (82) in the first well (69) using a second wet etching process, which differs from the first wet etching process, wherein the second wet etching process is carried out using a chemical comprising an acid and an oxidizing agent or using a chemical comprising a base and an oxidizing agent.

Description

GENERAL STATE OF THE ART The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a wide variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density has largely resulted from repeated reductions in the minimum feature size, allowing more components to be integrated into a given area. Fin-based field-effect transistors (FinFETs) are increasingly used in integrated circuits. FinFETs have a three-dimensional structure comprising a semiconductor fin projecting from a substrate. A gate structure, configured to control the flow of charge carriers within a conductive channel of the FinFET, is formed around the semiconductor fin. In a three-gate FinFET, for example, the gate structure is wrapped around three sides of the semiconductor fin, forming conductive channels on three sides of the fin. A method for forming a semiconductor device is known from US 2019 / 0 088 555 A1. Another method for forming a semiconductor structure is known from US 2013 / 0 299 922 A1. A semiconductor device is known from US 2015 / 0 061 042 A1.Other methods and devices are also known from US 2013 / 0 292 744 A1, US 2019 / 0 148 514 A1, US 2019 / 0 165 123 A1, US 2019 / 0 214 343 A1 and US 2018 / 0 350 955 A1. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood with reference to the following detailed description, when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Indeed, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity of discussion. Fig. 1 shows a perspective view of a fin field-effect transistor (FinFET) device in accordance with some embodiments. Figs. 2-6 and 7A show cross-sectional views of a FinFET device at various stages of fabrication in accordance with one embodiment. Figs. 7B and 7C show various cross-sectional views of the semiconductor device depicted in Fig. 7A in some embodiments. Figs. 8-19 show cross-sectional views of the FinFET device of Fig.Figure 7A shows cross-sectional views of a semiconductor device at various stages of manufacturing according to one embodiment. Figures 20-26 show cross-sectional views of a semiconductor device at various stages of manufacturing according to one embodiment. Figures 27-29 show cross-sectional views of a semiconductor device at various stages of manufacturing according to one embodiment. Figure 30 shows a cross-sectional view of a semiconductor device in one embodiment. Figure 31 shows a flowchart of a method for manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on top of a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact with each other, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features are not arranged in direct contact with each other. Furthermore, terms of spatial relationships, such as "below," "bottom," "lower," "above," "upper," and the like, may be used herein for a simpler description of the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These expressions of spatial relationships serve to encompass various orientations of the component in use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the expressions of spatial relationships used herein may be interpreted accordingly.Unless otherwise stated, throughout this discussion the same or similar reference numerals in different figures refer to the same or a similar component formed by the same or a similar formation process. Embodiments of the present disclosure are discussed in connection with the fabrication of a FinFET device and, in particular, in connection with the formation of exit work layers of a FinFET device. Although the disclosed embodiments are discussed using FinFET devices as examples, the disclosed method can also be used in other types of devices, such as planar devices. Fig. 1 shows an example of a FinFET 30 in a perspective view. The FinFET 30 has a substrate 50 and a fin 64 projecting beyond the substrate 50. Insulation regions 62 are formed on opposite sides of the fin 64, with the fin 64 projecting beyond the insulation regions 62. A gate dielectric 66 is arranged along the side walls and over a top surface of the fin 64, and a gate 68 is arranged above the gate dielectric 66. Source / drain regions 80 are arranged in the fin 64 and on opposite sides of the gate dielectric 66 and the gate 68. Fig. 1 also shows reference cross-sections used in later figures. The cross-section BB extends along a longitudinal axis of the gate 68 of the FinFET 30. The cross-section AA is perpendicular to the cross-section BB and is arranged along a longitudinal axis of the fin 64 and, for example, in a direction of current flow between the source / drain regions 80.Cross-section CC is arranged parallel to cross-section BB and transversely across the source / drain area 80. Subsequent figures refer to these reference cross-sections for clarification. Figures 2-6, 7A, and 8-19 are cross-sectional views of a FinFET device 100 at various stages of fabrication, consistent with one embodiment. The FinFET device 100 is similar to the FinFET 30 in Figure 1, but with multiple fins and multiple gate structures. Figures 2-5 show cross-sectional views of the FinFET device 100 along cross-section BB. Figures 6, 7A, and 8-19 show cross-sectional views of the FinFET device 100 along cross-section AA. Figures 7B and 7C show different embodiments in cross-sectional views of the FinFET device 100 from Figure 7A, but along cross-section CC. Fig. 2 shows a cross-sectional view of the substrate 50. The substrate 50 can be a semiconductor substrate, such as a basic semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a P-type or N-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate has a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is created on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may comprise silicon, germanium, a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, an alloy semiconductor comprising SiGe, GaAsP, AlInAs, Al-GaAs, GaInAs, GaInP and / or GaInAsP, or combinations thereof. Referring to Fig. 3, the substrate 50 shown in Fig. 2 is structured, for example, using photolithography and etching techniques. For example, a mask layer, such as a contact oxide layer 52 and an overlying contact nitride layer 56, can be formed over the substrate 50. The contact oxide layer 52 can be a thin film containing silicon oxide, formed, for example, using a thermal oxidation process. The contact oxide layer 52 can act as an adhesive layer between the substrate 50 and the overlying contact nitride layer 56.In some embodiments, the contact point nitride layer 56 will be formed from silicon nitride, silicon oxynitride, silicon carbonitride, the like or a combination thereof, and can be formed, for example, by using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). The mask layer can be structured using photolithographic techniques. Generally, photolithographic techniques use a photoresist material that is applied, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. In this example, the photoresist material is used to structure the contact oxide layer 52 and the contact nitride layer 56 to form a structured mask 58, as shown in Fig. 3. The structured mask 58 is subsequently used to structure exposed sections of the substrate 50 to form trenches 61, thereby defining semiconductor fins 64 (e.g., 64A and 64B) between adjacent trenches 61, as shown in Fig. 3. In some embodiments, the semiconductor fins 64 are formed by etching trenches into the substrate 50, for example, using reactive ion etching (RIE), neutral beam etching (NBE), the like, or combinations thereof. The etching can be anisotropic. In some embodiments, the trenches 61 can be strips (viewed from above) arranged parallel and closely spaced. In some embodiments, the trenches 61 can be continuous and surround the semiconductor fins 64. The semiconductor fins 64 may also be referred to as fins 64 in the following. The fins 64 can be structured by any suitable method. For example, the fins 64 can be structured using one or more photolithographic processes, including dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-aligning processes, which makes it possible to create structures that, for example, have smaller divisions than can otherwise be achieved using a single, direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed together with the structured sacrificial layer using a self-aligning process.Then the sacrificial layer is removed, and the remaining spacers, or mold cores, can then be used to structure the fins. Fig. 4 shows the formation of an insulating material between adjacent semiconductor fins 64 to form insulating regions 62. The insulating material can be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and can be formed by high-density plasma-cured vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., deposition of CVD-based material in a remote plasma system and post-curing to achieve conversion to another material, for example, an oxide), the like, or a combination thereof. Other insulating materials and / or formation processes can also be used. In the illustrated embodiment, the insulating material is a silicon oxide formed by an FCVD process. An annealing process can be carried out after the insulating material has been formed.A planarization process, such as a chemical-mechanical polishing (CMP) process, can remove excess insulating material and form coplanar top surfaces of the insulating areas 62 and the semiconductor fins 64 (not shown). The structured mask 58 (see Fig. 3) can also be removed by the planarization process. In some embodiments, the insulating regions 62 have a separating layer, for example an oxide separating layer (not shown), at the interface between the insulating region 62 and the substrate 50 / the semiconductor fins 64. In some embodiments, the oxide separating layer is formed to reduce crystalline defects at the interface between the substrate 50 and the insulating region 62. Likewise, the oxide separating layer can also be used to reduce crystalline defects at the interface between the semiconductor fins 64 and the insulating region 62. The oxide separating layer (e.g., silicon oxide) can be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 50, although other suitable methods can also be used to form the oxide separating layer. Next, the insulation regions 62 are recessed to form trench insulation (STI) regions 62. The insulation regions 62 are recessed such that the upper portions of the semiconductor fins 64 protrude between adjacent STI regions 62. The upper surfaces of the STI regions 62 can have a flat surface, a convex surface, a concave surface (such as a crown), or a combination thereof (as shown). The upper surfaces of the STI regions 62 can be formed flat, convex, and / or concave by appropriate etching. The insulation regions 62 can be recessed using an acceptable etching process, such as one that is selective for the material of the insulation regions 62. For example, dry etching or wet etching using dilute hydrofluoric acid (dHF) can be used to recess the insulation regions 62. Figures 2, 3 to 4 show one embodiment of the formation of the fins 64, although fins can be formed in a wide variety of different processes. For example, an upper section of the substrate 50 can be replaced by a suitable material, such as an epitaxial material, which is suitable for a specific type (e.g., type N or type P) of semiconductor devices to be formed. The substrate is then structured with the epitaxial material applied to it to form semiconductor fins 64 that encompass the epitaxial material. As another example, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; homoepitaxial structures can be grown epitaxially in the trenches; and the dielectric layer can be deepened such that the homoepitaxial structures protrude from the dielectric layer to form fins. In yet another example, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; heteroepitaxial structures can be grown epitaxially in the trenches using a material different from the substrate; and the dielectric layer can be deepened such that the heteroepitaxial structures protrude from the dielectric layer to form fins. In embodiments where epitaxial material(s) or epitaxial structures (e.g., heteroepitaxial or homoepitaxial structures) are grown, the grown materials or structures can be doped in situ during growth, which can eliminate the need for prior and subsequent implantations. However, in situ doping and doping by implantation can also be used together. Furthermore, it can also be advantageous to epitaxially grow a material in an NMOS region that differs from the material in a PMOS region. In various embodiments, the fins can comprise silicon-germanium (SixGe1-x, where x can be between 0 and 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like.For example, the available materials for forming a III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP and the like. Fig. 5 shows the formation of a dummy gate structure 75 over the semiconductor fins 64. In some embodiments, the dummy gate structure 75 includes a gate dielectric 66 and a gate 68. A mask 70 can be formed over the dummy gate structure 75. To form the dummy gate structure 75, a dielectric layer is formed on the semiconductor fins 64. The dielectric layer can be, for example, silicon oxide, silicon nitride, multiple layers thereof, or the like, and can be deposited or thermally grown. A gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer can be deposited over the dielectric layer and then planarized, for example, by CMP. The mask layer can be deposited over the gate layer. The gate layer can be made of polysilicon, for example, but other materials can also be used. The mask layer can be made of silicon nitride or a similar material, for example. After the layers (e.g., the dielectric layer, the gate layer, and the mask layer) have been formed, the mask layer can be patterned using acceptable photolithography and etching techniques to form the mask 70. The pattern of the mask 70 can then be transferred to the gate layer and the dielectric layer using an acceptable etching technique to form the gate 68 and / or the gate dielectric 66. The gate 68 and the gate dielectric 66 cover corresponding channel regions of the semiconductor fins 64. The gate 68 can also have a longitudinal direction that extends substantially perpendicular to the longitudinal direction of the respective semiconductor fins 64. In the example shown in Fig. 5, the gate dielectric 66 is formed over the fins 64 (e.g., over the upper surfaces and side walls of the fins 64) and over the STI areas 62. In other embodiments, the gate dielectric 66 can be formed, for example, by thermal oxidation of a material of the fins 64, and can therefore be formed over the fins 64 but not over the STI areas 62. These and other variations are considered to be entirely within the scope of this disclosure. Figures 6, 7A, and 8-19 show cross-sectional views of the further processing of the FinFET device 100 along cross-section AA (along the longitudinal axis of the fin 64). Figures 7B and 7C show various embodiments in cross-sectional views of the FinFET device 100 from Figure 7A, but along cross-section CC. Note that in Figures 6, 7A, and 8, four dummy gate structures 75 (e.g., 75A, 75B, 75C, and 75D) are formed over the fins 64. Those skilled in the art will recognize that more or fewer than four gate structures can be formed over the fin 64, and these and other variations are considered to be entirely within the scope of the present invention. As shown in Fig. 6, weakly doped drain (LDD) regions 65 are formed in the fins 64. The LDD regions 65 can be formed by a plasma doping process. The plasma doping process can include the formation and structuring of masks, such as a photoresist, to cover the areas of the FinFET that need to be protected before the plasma doping process. The plasma doping process can implant N-type or P-type impurities into the fins 64 to form the LDD regions 65. For example, P-type impurities, such as boron, can be implanted into the fin 64 to form the LDD regions 65 for a P-type device. As another example, N-type impurities, such as phosphorus, can be implanted into the fin 64 to form the LDD regions 65 for an N-type device. In some embodiments, the LDD areas 65 border the channel area of ​​the FinFET device 100.Sections of the LDD regions 65 can extend below the gate 68 and into the channel region of the FinFET device 100. Fig. 6 shows a non-limiting example of the LDD regions 65. Other configurations, shapes, and methods for forming the LDD regions 65 are also possible and are considered to be fully contained within the scope of this disclosure. For example, LDD regions 65 can be formed after gate spacers 76 have been formed. In some embodiments, the LDD regions 65 are omitted. Referring further to Fig. 6, a gate spacer 76 is formed on the gate structure after the LDD regions 65 have been formed. The gate spacers 76 can comprise a first gate spacer 72 and a second gate spacer 74. For example, the first gate spacer 72 can be a gate sealing spacer and is formed on opposite side walls of the gate 68 and on opposite side walls of the gate dielectric 66. The second gate spacer 74 is formed on top of the first gate spacer 72. The first gate spacer 72 can be formed from silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof, and can be formed, for example, using thermal oxidation, chemical vapor deposition (CVD), or another suitable deposition process.The second gate spacer element 74 can be formed from silicon nitride, silicon carbonitride, a combination thereof or the like using a suitable deposition method. In one exemplary embodiment, the gate spacer 76 is formed by first depositing a first gate spacer layer conformally over the FinFET device 100, before depositing a second gate spacer layer conformally over the deposited first gate spacer layer. Next, an anisotropic etching process, such as a dry etching process, is performed to remove a first portion of the second gate spacer layer located on the upper surfaces of the FinFET device 100 (e.g., the upper surface of the mask 70), while a second portion of the second gate spacer layer remains located along the sidewalls of the dummy gate structures 75. The second portion of the second gate spacer layer remaining after the anisotropic etching process forms the second gate spacer 74.The anisotropic etching process also removes a section of the first gate spacer layer located outside the side walls of the second gate spacer 74, and the remaining section of the first gate spacer layer forms the first gate spacer 72. The shapes and methods for forming the gate spacer element 76 shown in Fig. 6 are merely non-limiting examples, and other shapes and methods of formation are possible. These and other variations are considered to be fully contained within the scope of the present disclosure. Next, the source / drain regions 80 are formed, as shown in Fig. 7A. The source / drain regions 80 are formed by etching the fins 64 (e.g., in the LDD region 65) to create wells, followed by epitaxial growth of a material in the well using suitable methods, such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), vapor-phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or combinations thereof. As shown in Fig. 7A, the epitaxial source / drain regions 80 can have surfaces raised from the respective surfaces of the fins 64 (e.g., raised above the non-recessed sections of the fins 64) and can have facets. The source / drain regions 80 of adjacent fins 64 can merge to form a continuous epitaxial source / drain region 80 (see Fig. 7B). In some embodiments, the source / drain regions 80 for adjacent fins 64 do not merge and remain separate source / drain regions 80 (see Fig. 7C). Figures 7A and 7B also show spacer elements 76' along opposite side walls of the fins 64, wherein these spacer elements 76' can have the same or a similar structure as the gate spacer elements 76, and can be formed in the same process step(s) as the gate spacer elements 76. Dopants can be implanted into the epitaxial source / drain regions 80 to form these regions, followed by a annealing process. The implantation process can include the formation and structuring of masks, such as a photoresist, to cover the areas of the FinFET that need to be protected before the implantation process. The source / drain regions 80 can have an impurity (e.g., dopant) concentration of between approximately 1 × 10⁻¹⁹ cm⁻³ and approximately 1 × 10⁻¹⁹ cm⁻³. P-type impurities, such as boron or indium, can be implanted into the source / drain region 80 of a P-type transistor. N-type impurities, such as phosphorus or arsenide, can be implanted into the source / drain region 80 of an N-type transistor. In some embodiments, the epitaxial source / drain regions can be doped in situ during growth. Next, a first interlayer dielectric (ILD) 90 is formed over the substrate 50 and over the dummy gate structures 75 (e.g., 75A, 75B, 75C, and 75D) as shown in Fig. 8. In some embodiments, the first ILD 90 is formed from a dielectric material such as silicon dioxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and can be applied by any suitable method, such as CVD, PECVD, or FCVD. A planarization process, such as a CMP process, can be performed to remove the mask 70 (see Fig. 7A). After the planarization process, the top surface of the first ILD 90 is flush with the top surface of the gate 68. A gate-loading process (sometimes referred to as a replacement gate process) is subsequently performed to replace the gate 68 and the gate dielectric 66 with an active gate (which may also be referred to as a replacement gate or a metal gate) and an active dielectric gate material. In some embodiments, the active gate may be a metal gate. Therefore, in a gate-loading process, the gate 68 and the gate dielectric 66 are considered dummy gate structures. Referring to Fig. 9, the dummy gate structures 75A, 75B, 75C, and 75D are removed to form depressions 69A, 69B, 69C, and / or 69D in the first ILD 90. In accordance with some embodiments, the gates 68 and the gate dielectric 66 directly beneath the gates 68 are removed in one etching step(s), so that the depressions 69 (e.g., 69A, 69B, 69C, and 69D) are formed between the gate spacer elements 76. Each of the depressions 69 exposes the channel area of ​​a respective fin 64. During dummy gate removal, the dielectric dummy gate 66 can be used as an etch stop layer when the dummy gate 68 is etched. The dummy gate dielectric 66 can then be removed after the dummy gate 68 has been removed. Since the replacement gates are formed in the recesses 69, the recesses 69 are also referred to as gate grooves 69. Next, as shown in Fig. 10, a gate dielectric layer 82 is conformally applied in the recesses 69, such as on the upper surfaces and side walls of the fins 64, on the side walls of the gate spacers 76, and on an upper surface of the first ILD 90. In some embodiments, the gate dielectric layer 82 comprises silicon oxide, silicon nitride, or multiple layers thereof. In other embodiments, the gate dielectric layer 82 comprises a high-k dielectric material (or high-K dielectric material), and in these embodiments, the gate dielectric layers 82 may have a k-value greater than approximately 7.0 and may comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The methods for forming the gate dielectric layer 82 can include molecular beam deposition (MBD), atomic layer deposition (ALD), CVD, PECVD and the like. In the example of Fig. 10, the fin 64 has a region 200 (e.g., an N-type device region) and a region 300 (e.g., a P-type device region) for forming different types of devices (e.g., N-type transistors or P-type transistors). As shown in Fig. 10, after the gate dielectric layer 82 has been conformally formed in regions 200 and 300, a first P-type exit layer 83A and a second P-type exit layer 83B are formed in region 300. In particular, the first P-type exit layer 83A is conformally formed in the depression 69C and over sections of the upper surface of the first ILD 90 adjacent to (or adjoining) the depression 69C. The second P-type exit working layer 83B is conformally formed in the depression 69D and over sections of the upper surface of the first ILD 90 adjacent to (or bordering on) the depression 69D.In the discussion herein, a P-type exit working layer may also be referred to as a P-type exit working metal, and an N-type exit working layer may also be referred to as an N-type exit working metal. The second P-type exit working layer 83B is formed from a material (e.g., a P-type exit working metal) which, in the illustrated embodiment, differs from that of the first P-type exit working layer 83A. Example P-type exit work materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type exit work materials, or combinations thereof. Example N-type exit work materials include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type exit work materials, or combinations thereof. An exit work value is related to the material composition of the exit work layer, and thus the exit work layer material can be selected to match its exit work value to achieve a target threshold voltage Vt in the device to be formed. The exit work layer(s) can be deposited by CVD, physical vapor deposition (PVD), and / or other suitable processes. Both the first P-type exit working layer 83A and the second P-type exit working layer 83B in Fig. 10 can be formed by depositing the exit working metal and structuring the deposited exit working metal. For example, the first P-type exit working layer 83A can be formed by conformally depositing a P-type exit working metal over the gate dielectric layer 82 (e.g., in regions 200 and 300), forming a structured mask layer to expose portions of the P-type exit working metal to be removed, performing an etching process to remove the exposed P-type exit working metal, and removing the structured mask layer. After removal of the structured mask layer, the remaining P-type exit working metal forms the first P-type exit working layer 83A. Similar processes can be performed to form the second P-type exit working layer 83B. Next, an N-type exit working layer 84 is formed in regions 200 and 300 in Fig. 11 (e.g., conformal). The N-type exit working layer 84 can be formed from any suitable N-type exit working material, such as titanium aluminum carbon (TiAlC). Any suitable forming process, such as CVD, PVD, ALD, the like, or combinations thereof, can be used to form the N-type exit working layer 84. In Fig. 11, the N-type exit working layer 84 extends along the gate dielectric layer 82 in region 200 and physically contacts it, and extends along the first P-type exit working layer 83A and the second P-type exit working layer 83B in region 300 and physically contacts them. The upper surface of the N-type exit working layer 84 in the area 200 can be lower (e.g.closer to the substrate 50) than the upper surface of the N-type exit working layer 84 in the area 300, due to the underlying first P-type exit working layer 83A and the second P-type exit working layer 83B in the area 300. Next, a cover layer 85 is conformally formed over the N-type exit work layer 84 in regions 200 and 300. In some embodiments, the cover layer 85 is formed from titanium nitride, silicon, silicon oxide, silicon oxynitride, or combinations thereof using a suitable formation process, such as PVD, CVD, ALD, combinations thereof, or the like. The cover layer 85 protects the underlying exit work layers (e.g., 84, 83A, 83B) from oxidation by ambient oxygen. Furthermore, in a subsequent thermal insertion process, the cover layer 85 assists in driving the exit work metals into the gate dielectric layer 82, thus improving the efficiency of the thermal insertion process. Next, a three-layer photoresist, comprising a bottom antireflective coating (BARC) 86, a middle layer 87 (e.g., a mask layer), and a top photoresist 88, is formed over the FinFET device 100 of Fig. 11, as shown in Fig. 12. After being formed over the top layer 85, the three-layer photoresist can also fill the recesses 69. The top photoresist 88 of the three-layer photoresist is then structured to form an opening 89, the opening 89 being located above (e.g., directly above) the recess 69B (see Fig. 11) in the region 200. In one embodiment, the top photoresist 88 is structured by exposing it, for example, through a reticle, to a structured energy source (e.g., light).The energy input causes a chemical reaction in those parts of the photosensitive material that have been affected by the structured energy source. This modifies the physical properties of the exposed sections of the photoresist such that they differ from the unexposed sections. The photoresist can then be developed, for example, with a developer to separate the exposed section from the unexposed section. Next, in Fig. 13, the opening 89 in the top photoresist 88 is enlarged by the middle layer 87 and the BARC layer 86, for example, using an etching process. The etching process can use the structured top photoresist 88 as an etching mask. A suitable etching process, such as dry etching, can be used to transfer the structure of the top photoresist 88 to the middle layer 87 and the BARC layer 86. The etchant used in the etching process can be selective for the materials of the middle layer 87 and the BARC layer 86 (e.g., have a higher etch rate for them) so that the sections of the middle layer 87 and the BARC layer 86 located below the opening 89 are removed, essentially without attacking the top layer 85. After the etching process, sections of the top layer 85 located in the recess 69B (see Fig. 13) are removed.11) and are arranged over sections of the upper surface of the first ILD 90 adjacent to (or adjacent to) the recess 69B, exposed. The top photoresist 88 can be removed, for example, by an ashing process after the etching process. Next, a first etching process is carried out in Fig. 14 to selectively remove sections of the cover layer 85 exposed through the opening 89. In some embodiments, the first etching process is a wet etching process using a chemical that is selective for the cover layer 85 material (e.g., has a higher etch rate for it), such that the cover layer 85 is removed essentially without attacking the underlying N-type exit working layer 84. In some embodiments, the N-type exit working layer 84 is exposed after the first etching process. In one exemplary embodiment, the cover layer 85 is removed by the first wet etching process using a fluoride-containing chemical. In some embodiments, the fluoride-containing chemical is a mixture of hydrofluoric acid (HF) and water (e.g., deionized water (DIW)).For example, the mixing ratio between one volume of HF acid and one volume of DIW of the fluoride-containing chemical is between approximately 1 : 00 and approximately 1 : 500. In some embodiments, the first wet etching process is carried out at a temperature between approximately 20°C and approximately 25°C, for example, at room temperature, and for a predetermined period, which, depending on the thickness of the cover layer 85, may be, for example, between approximately 1 minute and approximately 3 minutes. An etching temperature above the range disclosed above can cause over-etching of the cover layer 85 (e.g., etching away portions of the N-type exit layer 84) and can lead to a failure of the control of the selective etching process. An etching temperature below the range disclosed above might not remove a target amount (e.g., a target thickness) of the cover layer 85 within the predetermined period. Next, a second etching process is carried out in Fig. 15 to selectively remove sections of the N-type exit working layer 84 exposed through the opening 89. In some embodiments, the second etching process is a second wet etching process performed using a chemical selective for the material of the N-type exit working layer 84, such that the N-type exit working layer 84 is removed essentially without attacking the underlying gate dielectric layer 82. The gate dielectric layer 82 is exposed in some embodiments after the second etching process. In one embodiment, the N-type exit layer 84 is removed by the second wet etching process using a chemical comprising an acid (e.g., hydrogen chloride (HCl)) and an oxidizing agent (e.g., hydrogen peroxide (H₂O₂) or ozone (O₃)). For example, the chemical can be a mixture of the acid (e.g., HCl), the oxidizing agent (e.g., H₂O₂ or O₃), and DIW. The volume percentage of the acid in the mixture can be between approximately 1% and approximately 10%, the volume percentage of the oxidizing agent in the mixture can be between approximately 1% and approximately 10%, and the volume percentage of the DIW in the mixture can be between approximately 80% and approximately 98%. In a further embodiment, the N-type exit layer 84 is removed by the second wet etching process using a chemical comprising a base (e.g., ammonia (e.g., NH4OH)) and an oxidizing agent (e.g., hydrogen peroxide (H2O2) or ozone (O3)). For example, the chemical can be a mixture of the base (e.g., NH4OH), the oxidizing agent (e.g., H2O2 or O3), and DIW. The volume percentage of the base in the mixture can be between approximately 1% and approximately 10%, the volume percentage of the oxidizing agent in the mixture can be between approximately 1% and approximately 10%, and the volume percentage of the DIW in the mixture can be between approximately 80% and approximately 98%. In some embodiments, the second wet etching process is carried out at a temperature between approximately 50°C and approximately 70°C for a predetermined period, which, depending on the thickness of the N-type exit layer 84, may be, for example, between approximately 3 minutes and approximately 5 minutes. An etching temperature above the range disclosed above can cause over-etching of the N-type exit layer 84 and can damage the underlying gate dielectric layer 82. An etching temperature below the range disclosed above might not remove a target amount (e.g., a target thickness) of the exposed N-type exit layer 84 within the predetermined period. The middle layer 87 of the three-layer photoresist can be removed after the second wet etching process by a suitable method, such as CMP and / or selective etching, which is selective for the material of the middle layer 87. In the example shown in Figures 14 and 15, the top layer 85 is removed by performing the first wet etching process once, and the N-type exit working layer 84 is subsequently removed by performing the second wet etching process once. In other embodiments, the top layer 85 and the N-type exit working layer 84 are removed by performing a plurality of etching cycles, each cycle comprising the first wet etching process followed by the second wet etching process, the first and second wet etching processes being discussed above with reference to Figures 14 and / or 15. Figures 20-26 show an embodiment in which the top layer 85 and the N-type exit working layer 84 are removed by performing, for example, three etching cycles. Reference is made temporarily to Figures 20-26, which show cross-sectional views of a section of the semiconductor device 100 in one embodiment at various stages of the etching cycles. For the sake of simplicity, Figures 20-26 show only a section of the semiconductor device 100 around the gate groove 69B, and not all components of the semiconductor device 100 are depicted. For example, Figures 20-26 show only the gate dielectric layer 82, the N-type exit layer 84, and the cover layer 85 during the process steps corresponding to Figures 13-15 (e.g., the first etching process and the second etching process). In other words, the processing shown in Figures 20-26 can, in one embodiment, replace the processing shown in Figures 13-15. Fig. 20 shows a section of the top layer 85 exposed through the opening 89 (see Fig. 13) in the photoresist and the layers (e.g., 84, 82) directly beneath the section of top layer 85. Next, a first wet etching process is carried out in a first etching cycle, as shown in Fig. 21, to selectively remove the top layer 85. As shown in Fig. 21, the thickness of the top layer 85 is reduced after the first wet etching process. Fig. 21 also shows a non-uniform thickness for remaining sections of the top layer located along the side walls of the gate groove 69B. The non-uniform thickness of the top layer 85 may have been caused by the reduced efficiency of the first wet etching process in small crevices (e.g., the gate groove 69B), as the etching chemicals have difficulty penetrating the narrow crevices. As shown in Fig. 21, lower sections of the cover layer 85 in the gate trench 69B have a greater thickness than upper sections of the cover layer 85.Note that in the example of Fig. 21, sections of the top layer 85 remain after the first wet etching process of the first etching cycle. Next, the second wet etching process of the first etching cycle is carried out in Fig. 22. However, since the chemical of the second wet etching process is selective for the material of the N-type exit working layer 84, and since remaining sections of the cover layer 85 are arranged above the N-type exit working layer 84 (e.g., covering it), the second wet etching process removes little or nothing of the remaining sections of the cover layer 85. Next, in Fig. 23, the first wet etching process of a second etching cycle is carried out, which removes the remaining sections of the cover layer 85. Next, in Fig. 24, the second wet etching process of the second etching cycle is carried out. As shown in Fig. 24, the thickness of the N-type exit working layer 84 is reduced, and the remaining sections of the N-type exit working layer 84 in gate trench 69B have a non-uniform thickness. Next, the first wet etching process of a third etching cycle is performed in Fig. 25, which removes little or none of the remaining portions of the N-type exit working layer 84. Next, the second wet etching process of the third etching cycle is performed in Fig. 26, which removes the remaining portions of the N-type exit working layer 84 and exposes the underlying gate dielectric layer 82. Although three etching cycles are used in the example shown, any number of etching cycles can be used to remove the top layer 85 and the N-type exit working layer 84. The first and second wet etching processes disclosed herein achieve precise control and excellent selectivity for the etching processes. For example, the first wet etching process selectively removes exposed top layer 85, essentially without attacking the underlying N-type exit working layer, and the second wet etching process selectively removes exposed N-type exit working layer 84, essentially without attacking the underlying gate dielectric layer 82. Compared to a reference method in which dry etching processes (e.g.,By using plasma etching processes to remove the top layer 85 and the N-type exit working layer 84, difficulties associated with dry etching processes, such as damage to the gate dielectric layer 82, damage to the side wall profile of the openings, and damage to the fins 64 and / or loss of the critical dimension (CD) of the fins 64, are avoided or reduced. Next, with further reference to Fig. 16, the BARC layer 86 is removed, for example by a suitable removal process such as ashing. After the BARC layer 86 has been removed, the remaining sections of the cover layer 85 (e.g., in regions 200 and 300) are exposed, as are sections of the gate dielectric layer 82 in / around the well 69B. Referring again to Fig. 17, an adhesive layer 91 is formed, for example conformally over the FinFET device 100 of Fig. 16 in region 200. A structured mask layer can be formed to cover region 300 while the adhesive layer 91 is formed in region 200. After the adhesive layer 91 has been formed, the structured mask layer is removed. As shown in Fig. 17, the adhesive layer 91 is formed over and in physical contact with the cover layer 85 in / around the well 69A (see Fig. 16), and is formed over and in physical contact with the gate dielectric layer 82 in / around the well 69B (see Fig. 16). The adhesive layer 91 can serve as an adhesive layer between the underlying layers (e.g. 85, 82) and a subsequently formed conductive material (e.g. 93), and can be formed from a suitable material, such as titanium nitride.The adhesive layer 91 can also serve as an exit working layer for the metal gate (see 97B in Fig. 18), which is to be formed in the recess 69B, in which case the adhesive layer 91 can comprise a material suitable as an N-type exit working material. A suitable formation process, such as CVD, PVD, ALD, combinations thereof, or the like, can be used to form the adhesive layer 91. After the adhesive layer 91 has been formed, an electrically conductive material 93 (also referred to as filler metal) is formed over the adhesive layer in region 200 and over (e.g., in physical contact with) the cover layer 85 in region 300. The electrically conductive material 93 fills the remaining sections of the recesses 69 and forms the gate electrodes of the metal gates (see 97A, 97B, 97C, and 97D in Fig. 18). In one embodiment, the electrically conductive material 93 is tungsten, although other suitable electrically conductive materials, such as cobalt, gold, copper, aluminum, combinations thereof, or the like, may also be used. A suitable formation process, such as CVD, PVD, ALD, or the like, may be used to form the electrically conductive material 93. Referring to Fig. 18, a planarization process, such as CMP, can be performed to remove excess sections of the various layers (e.g., 82, 83A, 83B, 84, 85, 91, and 93) located above the top surface of the first ILD 90. Following the planarization process, metal gates 97 (e.g., 97A, 97B, 97C, and 97D) are formed. A thermal insertion process can then be performed at a temperature between approximately 300°C and approximately 500°C to drive the exit-work layer materials into the gate dielectric layer 82 of the metal gates 97. In the embodiment of Fig. 18, each of the metal gates 97 has a different structure. For example, metal gate 97A comprises the gate dielectric layer 82 arranged along the side walls of corresponding gate spacers 76 and along the side walls and upper surface of the fin 64. The N-type exit working layer 84, the cover layer 85, the adhesive layer 91, and the filler metal 93 are formed sequentially over the gate dielectric layer 82 of metal gate 97A. Metal gate 97B comprises the gate dielectric layer 82 arranged along the side walls of corresponding gate spacers 76 and along the side walls and upper surface of the fin 64. The adhesive layer 91 and the filler metal 93 are formed sequentially over the gate dielectric layer 82 of metal gate 97B.The metal gate 97C comprises the gate dielectric layer 82 arranged along the side walls of corresponding gate spacers 76 and along the side walls and upper surface of the fin 64. The first P-type exit working layer 83A, the N-type exit working layer 84, the cover layer 85, and the filler metal 93 are formed sequentially over the gate dielectric layer 82 of the metal gate 97C. The metal gate 97D comprises the gate dielectric layer 82 arranged along the side walls of corresponding gate spacers 76 and along the side walls and upper surface of the fin 64. The second P-type exit working layer 83B, the N-type exit working layer 84, the cover layer 85, and the filler metal 93 are formed sequentially over the gate dielectric layer 82 of the metal gate 97D. In the example shown in Fig. 18, each of the metal gates 97 has a different gate structure with different exit working layers. This allows for great flexibility in tuning the threshold voltages of the metal gates 97, thereby improving the performance, functionality, and application of the resulting FinFET device 100. Referring to Fig. 19, a second ILD 92 is formed above the first ILD 90. Contact openings are formed by the second ILD 92 to expose the metal gates 97 (e.g., 97A, 97B, 97C, and 97D). Furthermore, contact openings are formed by the first ILD 90 and the second ILD 92 to expose the source / drain regions 80. In one embodiment, the second ILD 92 is a flowable film formed by a flowable CVD process. In some embodiments, the second ILD 92 is formed from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and can be applied by any suitable method, such as CVD and PECVD. The contact openings can be formed using photolithography and etching. After the contact openings are formed, silicide regions 95 are formed over the source / drain regions 80. In some embodiments, the silicide regions 95 are first formed by applying a metal capable of reacting with semiconductor materials (e.g., silicon, germanium) to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other high-melting-point metals, rare-earth metals, or their alloys, over the exposed portions of the source / drain regions 80, and subsequently performing a thermal annealing process to form the silicide regions 95. The unreacted portions of the applied metal are then removed, for example, by an etching process. Although the regions 95 are referred to here as silicide regions, they can also be germanide regions or silicon germanide regions (e.g., regions comprising both silicide and germanide). Next, contacts 102 (e.g., 102A or 102B, also referred to as contact terminals) are formed in the contact openings. In the illustrated embodiment, each of the contacts 102 has a barrier layer 101, an inoculation layer 103, and an electrically conductive material 105, and is electrically connected to the underlying conductive feature (e.g., the metal gate 97 or the silicide area 95). The contacts 102A, which are electrically connected to the metal gates 97, can be referred to as gate contacts, and the contacts 102B, which are electrically connected to the silicide areas 95, can be referred to as source / drain contacts. In some embodiments, the barrier layer 101 is conformally formed along the sidewalls and bottom of the contact openings. The barrier layer 101 can comprise an electrically conductive material, such as titanium nitride, but other materials, such as tantalum nitride, titanium, tantalum, or the like, can also be used alternatively. The barrier layer 101 can be formed using a CVD process, such as PECVD. However, alternatively, other processes, such as sputtering, metal-organic chemical vapor deposition (MOCVD), or ALD, can also be used. Next, the inoculation layer 103 is conformally formed over the barrier layer 101. The inoculation layer 103 can comprise copper, titanium, tantalum, titanium nitride, tantalum nitride, the like, or combinations thereof, and can be applied by ALD, sputtering, PVD, or the like. In some embodiments, the inoculation layer is a metal layer, which can be a single layer or a composite layer comprising a plurality of sublayers formed from different materials. For example, the inoculation layer 103 can comprise a titanium layer and a copper layer over the titanium layer. Next, the electrically conductive material 105 is applied over the inoculation layer 103, filling the remaining portions of the contact openings. The electrically conductive material 105 can be formed from a metallic material, such as gold, aluminum, tungsten, combinations thereof, or multiple layers thereof, and can be formed, for example, by electroplating, electroless plating, or another suitable method. After the formation of the electrically conductive material 105, a planarization process, such as CMP, can be performed to remove the excess portions of the barrier layer 101, the inoculation layer 103, and the electrically conductive material 105, such that these excess portions protrude beyond the top surface of the second ILD 92.The remaining sections of the barrier layer 101, the inoculation layer 103 and the electrically conductive material 105 therefore form the contacts 102 of the resulting FinFET device 100. The gate grooves 69 of the FinFET device 100 are shown as an example with U-shaped cross-sections. The gate grooves 69 can also have other cross-sectional shapes. Figures 27-29 show cross-sectional views of a section of a semiconductor device 100A with Y-shaped gate grooves (e.g., 69B) at various stages of fabrication in accordance with one embodiment. The semiconductor device 100A is similar to the FinFET device 100, but with Y-shaped cross-sections for the gate grooves 69. For simplicity, Figures 27-29 show only a section of the semiconductor device 100A around the gate groove 69B, and not all of the components of the semiconductor device 100A are shown. For example, Figs. 27-29 show only the gate dielectric layer 82, the N-type exit working layer 84 and the cover layer 85 during the processing steps corresponding to Figs. 13-15 (e.g. the first etching process and the second etching process).In other words, the machining operations shown in Figures 27-29 correspond to those shown in Figures 13-15. Those skilled in the art will readily recognize that by replacing the gate grooves 69 of the FinFET device 100 with the Y-shaped gate grooves, the machining steps shown in Figures 1-19 represent the successive machining steps for forming the semiconductor device 100A, wherein the semiconductor device 100A has metal gates 97 with Y-shaped cross-sections. The Y-shaped gate grooves can be formed, for example, by forming gate spacer elements 77 that do not have straight sidewalls, corresponding to the shape of the outer sidewalls of the gate dielectric layer 82 shown in Fig. 27. The gate spacer elements 76 with the non-straight sidewalls can be formed, for example, by forming dummy gate structures 75 that do not have straight sidewalls and forming gate spacer elements along the sidewalls of the dummy gate structures 75. As shown in Figs. 28 and / or 29, the top layer 85 is selectively removed by the first etching process (e.g., the first wet etching process), and the N-type exit working layer 84 is selectively removed by the second etching process (e.g., the second wet etching process), the first and second etching processes being discussed above with reference to Figs. 14 and / or 15. Due to the narrow lower section of the gate trenches, it can be very difficult to precisely remove the cover layer 85 and the N-type exit working layer 84 from the Y-shaped gate trenches without the method disclosed herein. However, the method disclosed herein achieves selective removal of the cover layer 85 and the N-type exit working layer 84 with precision and ease. Damage to the gate dielectric layer 82 is avoided or reduced, and a substantially uniform thickness of the gate dielectric layer 82 is achieved. Fig. 30 shows a cross-sectional view of a semiconductor device 100B at a stage of manufacture in accordance with one embodiment. The semiconductor device 100B in Fig. 30 is similar to the semiconductor device 100 in Fig. 13, but with some modifications. For example, the two metal gates 97A / 97B on the left side of Fig. 30 are arranged in a P-type device area 300, and the two metal gates 97C / 97D on the right side of Fig. 30 are arranged in an N-type device area 200. Consequently, a first N-type exit layer 84A and a second N-type exit layer 84B are formed over the gate dielectric layer 82 in the gate grooves of the metal gates 97C and / or 97D. Fig. 30 also shows the P-type exit working layer 83 and the cover layer 85, which are arranged in both the N-type component area 200 and the P-type component area 300. Fig. 30 further shows the structured photoresist (e.g. 86 and 87) with the opening 89.In some embodiments, a two-stage etching process similar to that shown in Figures 14 and 15 is performed to remove the cover layer 85 and the P-type exit working layer 83 beneath the opening 89. For example, a first etching process is performed using a first chemical selective for the material of the cover layer 85 to selectively remove the cover layer 85. Next, a second etching process is performed using a chemical selective for the material of the P-type exit working layer 83 to selectively remove the P-type exit working layer 83 and expose the gate dielectric layer 82. In other embodiments, a plurality of etching cycles are performed to remove the cover layer 85 and the P-type exit working layer 83, each cycle comprising a first etching process followed by a second etching process.After the gate dielectric layer 82 of the metal gate 97B has been exposed, processing steps similar to those shown in Figs. 16-19 can be carried out to form the semiconductor device 100B. Variations of the disclosed embodiments are possible and are considered to be fully contained within the scope of this disclosure. For example, the number of fins and / or the number of gate structures in the FinFET device shown in the examples may change without deviating from the spirit of the disclosure. As another example, depending on the design of the FinFET device, each of the gate grooves 69 may be arranged over a different fin and along a different cross-section, although the gate grooves 69 (e.g., 69A, 69B, 69C, and 69d) are shown arranged over the same fin along the same cross-section. Fig. 31 shows a flowchart of a method for manufacturing a semiconductor device in accordance with several embodiments. It should be noted that the embodiment of the method shown in Fig. 31 is only one example of many possible embodiments of the method. An average person skilled in the art would recognize many variations, alternatives, and modifications. For example, various steps shown in Fig. 31 can be added, removed, replaced, rearranged, and repeated. Referring to Fig. 31, in step 1010 a first dummy gate structure and a second dummy gate structure are formed over a fin projecting beyond a substrate. In step 1020, a dielectric layer is formed around the first dummy gate structure and the second dummy gate structure. In step 1030, the first dummy gate structure and the second dummy gate structure are removed to form a first well and / or a second well in the dielectric layer. In step 1040, a gate dielectric layer, an N-type exit working layer, and a cover layer are successively formed in the first well and the second well. In step 1050, a structured mask layer is formed over the cover layer, with an opening in the structured mask layer exposing the cover layer in the first well.In step 1060, the top layer in the first well is selectively removed to expose the N-type exit working layer in the first well using a first wet etching process. In step 1070, the N-type exit working layer in the first well is selectively removed to expose the gate dielectric layer in the first well using a second wet etching process, which differs from the first wet etching process. Embodiments can offer advantages. The first and second wet etching processes disclosed herein achieve precise control and excellent selectivity for the etching processes. For example, the first wet etching process selectively removes exposed top layer 85, essentially without attacking the underlying N-type exit working layer 84, and the second wet etching process selectively removes exposed N-type exit working layer 84, essentially without attacking the underlying gate dielectric layer 82. By using the disclosed methods, difficulties such as damage to the gate dielectric layer 82, damage to the sidewall profile of the openings, and damage to the fins 64 and / or loss of the critical dimension (CD) of the fins 64 are avoided or reduced.Furthermore, the disclosed methods allow for greater flexibility in the structure of the metal gates, such as the ability to select and match different working functional layers (and thus different threshold voltages) in different metal gates, which improves the performance, functionality and application of the semiconductor device formed. The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims.

Claims

Method for forming a semiconductor device (30), the method comprising: forming a first dummy gate structure (75) and a second dummy gate structure (75) over a fin (64) projecting over a substrate (50); forming a dielectric layer (90) around the first dummy gate structure (75) and the second dummy gate structure (75); removing the first dummy gate structure (75) and the second dummy gate structure (75) to form a first well (69) and a second well (69) in the dielectric layer (90); successively forming a gate dielectric layer (82), an N-type exit working layer (84), and a cover layer (85) in the first well (69) and in the second well (69); forming a structured mask layer (87) over the cover layer (85), wherein an opening (89) of the structured mask layer (87) exposes the top layer (85) in the first depression (69);Selective removal of the cover layer (85) in the first well (69) to expose the N-type exit working layer (84) in the first well (69) using a first wet etching process, wherein the first wet etching process is carried out using a fluoride-containing chemical; and selective removal of the N-type exit working layer (84) in the first well (69) to expose the gate dielectric layer (82) in the first well (69) using a second wet etching process, which differs from the first wet etching process, wherein the second wet etching process is carried out using a chemical comprising an acid and an oxidizing agent or using a chemical comprising a base and an oxidizing agent. The method of claim 1, wherein the gate dielectric layer (82) is formed from a high K dielectric material, the N-type exit working layer (84) is formed from titanium aluminum carbon, and the cover layer (85) is formed using titanium nitride, silicon, silicon oxide, silicon oxynitride or a combination thereof. Method according to claim 1 or 2, wherein the fluoride-containing chemical is a mixture of hydrofluoric acid and water. Method according to one of the preceding claims, wherein the first wet etching process is carried out at a temperature between 20°C and 25°C, for example at room temperature, and for a period of time between 1 minute and 3 minutes. Method according to any of the preceding claims, wherein the acid is hydrogen chloride and the oxidizing agent is ozone or hydrogen peroxide. The method according to claim 5, wherein the volume percentage of the acid in the mixture is between 1% and 10%, and the volume percentage of the oxidizing agent in the mixture is between 1% and 10%. Method according to any of the preceding claims, wherein the base is ammonium hydroxide and the oxidizing agent is ozone or hydrogen peroxide. The method according to claim 7, wherein the volume percentage of the base in the mixture is between 1% and 10%, and the volume percentage of the oxidizing agent in the mixture is between 1% and 10%. A method according to any one of the preceding claims, further comprising: removing the structured mask layer (87) after the second wet etching process to expose the cover layer (85) in the second well (69); forming an adhesive layer (91) in the first well (69) and in the second well (69), wherein the adhesive layer (91) in the first well (69) extends along and in physical contact with the gate dielectric layer (82), and the adhesive layer (91) in the second well (69) extends along and in physical contact with the cover layer (85); and filling the first well (69) and the second well (69) with an electrically conductive material (93) after forming the adhesive layer (91). Method according to one of the preceding claims, wherein the cover layer (85) is formed from titanium nitride. Method according to one of the preceding claims, wherein forming the structured mask layer (87) over the top layer (85) comprises forming a three-layer photoresist comprising a bottom antireflection coating (86), a middle layer (87) and a top photoresist (88). Method according to claim 11, wherein the antireflection coating (86) fills the first and the second well (69). Method according to claim 11 or 12, wherein forming the structured mask layer (87) over the top layer (85) further comprises structuring the top photoresist (88) by exposing the top photoresist (88) through a grid plate to a structured energy source, for example light. Method according to claim 13, wherein the top photoresist (88) is developed with a developer to separate an exposed section of the top photoresist (88) from an unexposed section of the top photoresist (88). A method according to any one of the preceding claims, further comprising: forming a third dummy gate structure (75) and a fourth dummy gate structure (75) over the fin (64), wherein the dielectric layer (90) surrounds the third dummy gate structure (75) and the fourth dummy gate structure (75); removing the third dummy gate structure (75) and the fourth dummy gate structure (75) to form a third well (69) and a fourth well (69) in the dielectric layer (90); successively forming a gate dielectric layer (82), a first P-type exit working layer (83A) and the cover layer (85) in the third well (69); successively forming the gate dielectric layer (82), a second P-type exit working layer (83B) and the cover layer (85) in the fourth well (69); and after removing the structured mask layer (87), filling the third well (69) and the fourth well (69) with the electrically conductive material (93). Method according to claim 15, wherein the electrically conductive material (93) in the third recess (69) and in the fourth recess (69) is in physical contact with the cover layer (85). Method for forming a semiconductor device (100), the method comprising: forming a first dummy gate structure (75) and a second dummy gate structure (75) over a fin (64) projecting over a substrate (50), wherein the first dummy gate structure (75) and the second dummy gate structure (75) are surrounded by a dielectric layer (90); and replacing the first dummy gate structure (75) and the second dummy gate structure (75) with a first metal gate (97) and a second metal gate (97), wherein the replacement comprises: - removing the first dummy gate structure (75) and the second dummy gate structure (75) to form a first well (69) and a second well (69) in the dielectric layer (90); - forming a gate dielectric layer (82) in the first well (69) and in the second well (69);- Forming an N-type exit working layer (84) and a cover layer (85) successively over the gate dielectric layer (82) in the second well (69) and not in the first well (69); and- filling the first well (69) and the second well (69) with an electrically conductive material; wherein forming the N-type exit working layer (84) and the cover layer (85) comprises: forming the N-type exit working layer (84) and the cover layer (85) successively in the second well (69) over the gate dielectric layer (82); forming a structured mask layer (87) over the cover layer (85), wherein the structured mask layer (87) has an opening (89) which exposes the cover layer (85) in the first well (69); selectively removing the cover layer (85) in the first well (69) using a first wet etching process, wherein the first wet etching process is carried out using a fluoride-containing chemical;and after the first wet etching process, selective removal of the N-type exit working layer (84) in the first well (69) using a second wet etching process which differs from the first wet etching process, wherein the second wet etching process is carried out using a mixture of an acid and an oxidizing agent or using a mixture of a base and an oxidizing agent. Method according to claim 17, further comprising: before filling the first well (69) and the second well (69), forming an adhesive layer (91) in the first well (69) on the gate dielectric layer (82) and in the second well (69) on the cover layer (85).

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