AD:JR:cs bending semiconductor chip for interconnection at different vertical planes and method for manufacturing a package

Abstract

A package (100) which contains: • a carrier (102); • a semiconductor chip (104) having a first interconnection area (106) on which the semiconductor chip (104) is mounted at a first vertical height (108) on or above the support (102); and • a connecting body (110); • wherein the semiconductor chip (104) is bent in order to be connected to the connecting body (110) at a second connection area (112) of the semiconductor chip (104) at a second vertical height (114) which differs from the first vertical height (108); • wherein the semiconductor chip (104) has a first planar section (138) mounted on or above the support (102), a second planar section (140) mounted on the connecting body (110), and an inclined and / or curved section (142) between the first planar section (138) and the second planar section (140); • comprising a further electronic component (116) which is arranged between the carrier (102) and the semiconductor chip (104); • comprising an encapsulation (124) which encapsulates at least a part of the semiconductor chip (104), at least a part of the carrier (102), and at least a part of the connecting body (110); • having a heat dissipation body (126) on the semiconductor chip (104) and exposed with respect to the encapsulation (124); • wherein the support (102) is exposed with respect to the encapsulation (124); • having a further connecting body (128); • wherein the heat dissipation body (126) electrically connects the further connecting body (128) to the semiconductor chip (104).

Description

Background Technical field

[0001] Different embodiments generally relate to a package and a method for manufacturing a package. Description of the state of the art

[0002] Packages can be described as encapsulated semiconductor chips with electrical connections extending from the encapsulation. For example, packages can be connected to electronic peripherals, such as being mounted on a printed circuit board or on a heat sink, and connected to a larger system via connectors.

[0003] Packaging costs are a key driver for the industry. Performance, dimensions, and reliability are directly linked to them. The various packaging solutions are diverse and must meet the requirements of a specific application.

[0004] US 9,607,968 B1 discloses a flexible package 100 comprising a first chip 110 and a second chip 120, which are connected to each other via pads 115b, 125b on their surfaces and solder balls 114, 124. Opposite ends of the chips 110, 120 are also provided with pads 115a, 125a, which are connected by wires 161, 162 to connectors 151, 152 of a support layer 170 of the package. The chips 110, 120 have a convex and concave shape, respectively. When a bending load is applied to the package 100, the chips 110, 120 can be bent so that they assume a substantially straight shape. US 2018 / 0 211 943 A1, US 2013 / 0 148 314 A1, JP 2018 - 200 205 A, US 2005 / 0 082 684 A1, US 2018 / 0 019 188 A1 and US 2018 / 0 190 589 A1 represent further prior art in the field of the present application. Summary

[0005] There may be a need to provide a way to package a semiconductor chip in a simple and compact manner.

[0006] According to an exemplary embodiment, a package is provided comprising a carrier, a semiconductor chip having a first connection area where the semiconductor chip is mounted on or above the carrier at a first vertical height, and a connecting body, wherein the semiconductor chip is bent (or curved) to be connected to the connecting body at a second connection area of ​​the semiconductor chip at a second vertical height that differs from the first vertical height. The semiconductor chip has a first planar section mounted on or above the carrier, a second planar section mounted on the connecting body, and an inclined and / or curved section between the first planar section and the second planar section.The package further comprises: another electronic component arranged between the substrate and the semiconductor chip; an encapsulation encapsulating at least a portion of the semiconductor chip, at least a portion of the substrate, and at least a portion of the interconnect; and a heat sink located on the semiconductor chip and exposed relative to the encapsulation, with the substrate also exposed relative to the encapsulation. Additionally, the package comprises another interconnect, the heat sink electrically connecting the interconnect to the semiconductor chip.

[0007] According to another exemplary embodiment, a method for manufacturing a package is provided, wherein the method comprises mounting a semiconductor chip, having a first connection area at a first vertical height, onto or over a carrier, and bending (or warping) the semiconductor chip to connect the semiconductor chip to a connecting body at a second connection area of ​​the semiconductor chip at a second vertical height which differs from the first vertical height, such that the semiconductor chip has a first planar section which is mounted on or over the carrier, a second planar section which is mounted on the connecting body, and an inclined and / or curved section between the first planar section and the second planar section.The package further comprises: another electronic component arranged between the substrate and the semiconductor chip; an encapsulation encapsulating at least a portion of the semiconductor chip, at least a portion of the substrate, and at least a portion of the interconnect; and a heat sink located on the semiconductor chip and exposed relative to the encapsulation, with the substrate also exposed relative to the encapsulation. Additionally, the package comprises another interconnect, the heat sink electrically connecting the interconnect to the semiconductor chip.

[0008] According to an exemplary embodiment, a package is provided in which a flexible or bendable semiconductor chip, due to its small thickness and / or its bendable or flexible material, is processed to create a curvature of the semiconductor chip in at least one bent section, so that different connection areas of the semiconductor chip can bridge a height difference via the at least one bent section. Consequently, the bent semiconductor chip can be connected at different height levels to a carrier on the one hand and to another connecting body on the other, and optionally to at least one further connecting body. By taking this measure, conventional measures for bridging a height difference between a semiconductor chip and an entity to be connected to it can be advantageously at least partially dispensed with (for example, a clip, a bond wire, or the like).In the past, such an approach was impossible with semiconductor chips due to the conventionally large thicknesses involved. However, with the advent of extremely thin semiconductor chips or similar devices, such bending or warping became possible and, according to one exemplary embodiment, can be used to easily and advantageously bridge a vertical height difference within a package. As a result, an extremely compact package can be achieved, which can be manufactured with minimal effort. Simultaneously, direct coupling using a curved semiconductor chip can shorten electrical paths, leading to lower losses and / or higher signal transmission quality. Thus, a package with improved performance can be obtained. Description of further exemplary embodiments

[0009] Further exemplary embodiments of the package and the method are explained below.

[0010] In the context of the present application, the term "package" can, in particular, refer to an electronic device which may comprise one or more semiconductor chips mounted on a substrate, wherein the substrate may comprise or consist of a single part, several parts connected via an encapsulation or other package components, or a subassembly of substrates. The components of the package may optionally be at least partially encapsulated by means of an encapsulation.

[0011] In the context of the present application, the term "semiconductor chip" may, in particular, comprise a body comprising a semiconductor material, for example, a power semiconductor chip, an active electronic device (for example, a transistor), a passive electronic device (for example, a capacitance, an inductor, or a resistor), a sensor (for example, a microphone, a light sensor, or a gas sensor), an actuator (for example, a loudspeaker), and a microelectromechanical system (MEMS). In particular, the semiconductor chip may have at least one integrated circuit element (for example, a diode or a transistor) in a surface region thereof. The semiconductor chip may be a bare wafer or may already be packaged or encapsulated.Semiconductor chips implemented according to exemplary embodiments can be formed using silicon technology, gallium nitride technology, silicon carbide technology, etc.

[0012] In the context of this application, the term "support" can, in particular, refer to a support structure (which is preferably, but not necessarily, electrically conductive) that serves as a mechanical support for one or more semiconductor chips and also contributes to the electrical connection between the semiconductor chip(s) and the periphery of the package. The support can fulfill both a mechanical support function and an electrical connection function. A support can comprise or consist of a single part, several parts connected via the encapsulation or other package components, or a subassembly of supports.

[0013] In the context of the present application, the term "connection area" can, in particular, refer to a surface area section of the semiconductor chip where the semiconductor chip is connected to another entity, in particular a substrate, another electronic component, or any other connecting body, for example, directly or via a connecting medium, such as a solderable material. For example, the connection area can correspond to an electrically conductive pad (or similar) of the semiconductor chip, where not only a mechanical connection but also an electrical connection can be established between the semiconductor chip on the one hand and the connecting body or the substrate on the other.

[0014] In the context of the present application, the term "vertical plane" can, in particular, refer to a height plane of the package, especially in accordance with a vertical direction oriented upwards from, for example, a substantially planar support. Stacking or assembling components of the package can be carried out from a bottom surface to a top surface of the package along a vertical direction that defines the vertical planes.

[0015] In the context of the present application, the term "connecting body" can, in particular, refer to any physical structure to which the semiconductor chip is directly or indirectly connected. For example, such a connecting body can be an electrically conductive conductor (which, for example, forms part of a conductor frame and, in particular, also includes the support), another electronic component, or any other body, for example, another support or a clip.

[0016] In the context of this application, the term "bent" or "bend" may refer in particular to bending or deformation of the semiconductor chip to produce a curvature of the semiconductor chip in one or more bent or flexed sections of the semiconductor chip. For example, the semiconductor chip may be planar in a force-free state and may be reshaped by applying a bending strain, thereby forcing a connection at its connection points. In particular, the bending of the semiconductor chip may be accomplished to bridge a vertical height difference between the first connection point and the second connection point. Such bending or flexing of the semiconductor chip may be carried out by producing an elastic or an inelastic deformation of the semiconductor chip.Thus, bending the semiconductor chip can be achieved by applying a mechanical stress to it. Under this stress, corresponding connection areas can then be attached to a connected entity (for example, the substrate or the connector body), for instance, by soldering. In particular, a semiconductor chip that is planar in its unstressed state can be bent at one or more points to connect the chip at two or more connection points.

[0017] One exemplary embodiment involves providing a package that utilizes the flexible properties of a semiconductor chip (particularly the secondary flexible properties of a very thin silicon wafer) to connect to a substrate (for example, a die pad of a conductor frame) or another interconnect (for example, another wafer) in a different geometric plane. Furthermore, it may be possible to utilize the flexible properties of a thin, wafer-like semiconductor chip to generate highly advantageous packaging geometries. More specifically, exemplary embodiments may reduce the package size and increase the package's power density. In particular, it may be possible to provide a low-on-resistance package, for example, in a half-bridge configuration.Furthermore, it may also be possible to create significantly shorter paths for connections between the semiconductor chips (for example, an integrated gate bipolar transistor (IGBT) and a diode), so that it may be possible to efficiently suppress a source of unwanted inductance.

[0018] In one embodiment, the package includes a further electronic component (for example, another semiconductor chip) which is arranged (particularly in a sandwich-like configuration) between the substrate and the semiconductor chip. More precisely, the further electronic component can be, for example, an active semiconductor component, in particular one consisting of a transistor, a diode, a bipolar transistor, and an insulated-gate bipolar transistor. In such an embodiment, the semiconductor chip and the further electronic component can be stacked vertically such that the semiconductor chip is vertically spaced from the substrate, onto which the further electronic component can be directly mounted (for example, soldered). As a result, a height difference occurs between the semiconductor chip and the substrate due to the further electronic component positioned between them.In order to nevertheless contact the spaced semiconductor chip with a connecting body, which may be arranged in the same height plane as the support (for example, because it forms part of the same planar structured metal plate, such as a conductor frame), bending the upper semiconductor chip to bridge the generated height difference can be carried out with little effort.

[0019] In one embodiment, the package features an electrically conductive connection structure, in particular a soldered structure, between the semiconductor chip and the other electronic component. In such an embodiment, the two aforementioned electronic components or semiconductor chips can be mechanically, and preferably also electrically, connected by means of the electrically conductive connection structure located directly between them. This can, for example, also establish a direct electrical path from a lower main surface of the upper semiconductor chip to an upper main surface of the lower electronic component.When electronic components / semiconductor chips work together functionally (for example, a processor and a memory chip, two interacting memory chips, or a sensor chip and a controller chip), such a direct connection between the opposing main surfaces of the electronic components / semiconductor chips can be extremely advantageous. This can result in short electrical signal paths, leading to low loss and high signal quality. Direct stacking combined with direct electrical coupling of the electronic components / semiconductor chips can be particularly beneficial when the electronic components / semiconductor chips experience a vertical current flow during package operation.As an alternative to soldering, the electrically conductive connection structure can also create a sintered connection, a welded connection or an adhesive connection between the stacked electronic components / semiconductor chips.

[0020] In particular, the electrically conductive connection structure can be configured to electrically couple opposing pads of the semiconductor chip and the other electronic component. This allows for direct vertical functional coupling between the main surfaces of the electronic components / semiconductor chips that are opposite each other.

[0021] In one embodiment, the semiconductor chip and the other electronic component are connected to form a half-bridge. In such a half-bridge configuration, the two electronic components / semiconductor chips can be field-effect transistor chips, which can be connected for power semiconductor applications, for example, switching applications. For example, such a half-bridge can be part of an inverter or a six-pack.

[0022] In one embodiment, the semiconductor chip and the other electronic component are transistor chips, in particular metal oxide semiconductor field-effect transistor (MOSFET) chips. When embodied as transistor chips, the electronic components / semiconductor chips can be, for example, MOSFET or IGBT (insulated-gate bipolar transistor) chips. Such transistor chips can be used as components of power semiconductor packages.

[0023] In one embodiment, one of the semiconductor chip and the other electronic component is a transistor chip, in particular an insulated-gate bipolar transistor (IGBT) chip, and the other of the semiconductor chip and the other electronic component is a diode chip. Such a combination of a transistor chip and a diode chip can also meet electronic requirements in power semiconductor technology.

[0024] In one embodiment, the connecting body has an electrically conductive structure, in particular one consisting of a conductor, a pad, and a section of a conductor frame. In such an embodiment, the connection between the bent semiconductor chip and the connecting body can establish a further electrically conductive connection. Preferably, the support can be a pad and the connecting body can be a conductor of a common conductor frame structure or any other structured planar metal plate.

[0025] In a further embodiment, the connecting body includes an additional electronic component. This allows for bridging a height difference between two electronic components / semiconductor chips by bending at least one of the electronic components / semiconductor chips to create a component-to-component connection. This can be achieved, in particular, by bridging a vertical gap between the lower main surface of one of the electronic components / semiconductor chips and the upper main surface of the other by bending one or both of the electronic components / semiconductor chips.

[0026] In one embodiment, the thickness of the bent or curved semiconductor chip is less than 100 µm, particularly less than 50 µm, and furthermore, particularly not greater than 20 µm. It has been found that, especially with the aforementioned thickness values, the semiconductor chips, and in particular silicon chips, exhibit sufficient elasticity and flexibility to create a permanently curved configuration of a fixed semiconductor chip in a package. In particular, when the thickness of the semiconductor chip is less than 50 µm, the flexibility can be so pronounced that a package with high mechanical and electrical reliability can be created with a curved semiconductor chip mounted with a permanent bending strain.

[0027] In one embodiment, the support and the connecting body are coplanar. In other words, the support and the connecting body can be arranged in the same plane and at the same vertical height plane, particularly with respect to their respective upper main surfaces. Such a scenario can occur, for example, when the support and the connecting body form part of a common planar structured metal plate, such as a conductor frame. Establishing an additional electrical connection between the bent semiconductor chip and the connecting body, in addition to the electrical connection between the support and the semiconductor chip, can be highly advantageous, especially when another element (for example, another electronic component) is sandwiched between the support and said semiconductor chip.

[0028] In one embodiment, the support and the connecting body are part of a common conductor frame. Such a conductor frame can include a die pad and a plurality of conductors. This conductor frame can be a layered metallic structure, which may be structured to form one or more die pads or mounting sections for mounting the one or more semiconductor chips of the package, and one or more conductor sections for electrically connecting the package to an electronic environment when the semiconductor chip(s) is / are mounted on the conductor frame. In one embodiment, the conductor frame can be a metal plate (particularly made of copper), which may be structured, for example, by stamping or etching.Forming the chip carrier as a conductor frame is a cost-effective and mechanically and electrically advantageous configuration, combining a low-resistance connection of the at least one semiconductor chip with the robust support provided by the conductor frame. Furthermore, a conductor frame can contribute to the thermal conductivity of the package and dissipate heat generated during the operation of the semiconductor chip(s) due to the high thermal conductivity of the metallic (especially copper) material of the conductor frame. A conductor frame can, for example, be made of aluminum and / or copper. Preferably, the described embodiment combines a conductor frame assembly technology with the ability to stack semiconductor chips within a package.

[0029] In a further embodiment, the carrier has a stack comprising a central electrically insulating and thermally conductive layer (for example, a ceramic layer) which is covered on both opposite main surfaces by a respective electrically conductive layer (for example, a copper layer or an aluminum layer, wherein the respective electrically conductive layer may be a continuous or a structured layer), a Direct Copper Bonding (DCB) substrate, and a Direct Aluminum Bonding (DAB) substrate.

[0030] In one embodiment, the package comprises an encapsulation that encapsulates at least one part of the semiconductor chip, at least one part of the substrate, and at least one part of the interconnect. In the context of the present application, the term "encapsulation" can, in particular, denote a substantially electrically insulating and preferably thermally conductive material that surrounds at least one part of a semiconductor chip and at least one part of a substrate and / or an interconnect to provide mechanical protection, electrical insulation, and optionally contribute to heat dissipation during operation. By encapsulating, in particular, the curved semiconductor chip (which thus remains under mechanical stress even when soldered at both or all connection points), a mechanically robust embedding of the curved semiconductor chip within the encapsulation can be achieved.Encapsulation, preferably by casting, offers certain advantages with regard to one or more bent semiconductor chips of the package, as it stabilizes the bent semiconductor chip within the encapsulation, ensuring it remains under permanent bending strain.

[0031] In one embodiment, the package includes a heat sink on the semiconductor chip, the heat sink being exposed relative to the encapsulation. Specifically, a primary surface of the semiconductor chip, opposite its other primary surface where the semiconductor chip is connected to both the substrate and the interconnect, can be equipped with a heat sink. Such a heat sink can be a bulk material with high thermal conductivity (particularly at least 50 W / mK) capable of dissipating heat generated by the bent semiconductor chip during package operation. This heat sink effectively suppresses thermal stress occurring during temperature cycling or package operation.Thus, internal stress on the bent semiconductor chip, which occurs when ohmic losses or similar factors heat the package, can be efficiently reduced by providing the aforementioned heat sink. Preferably, the heat sink is exposed with respect to the encapsulation, ideally with an entire main surface exposed. This can further enhance the heat sink's ability to dissipate heat from the interior of the package.

[0032] In one embodiment, at least one part of the carrier and the connecting body is exposed with respect to the encapsulation. By exposing part of the connecting body and / or part of the carrier with respect to the encapsulation (for example, a dielectric encapsulation such as a molding compound), the heat dissipation capability of the package can be further improved, and optionally, electrical coupling of the package with respect to an electronic periphery can also be achieved by taking this measure.

[0033] In one embodiment, the package includes an additional connecting element that is connected to the semiconductor chip. For example, this additional connecting element could be another electronic component or another conductor of a conductor frame.

[0034] Referring further to the embodiment described above, the package can include an electrically conductive connecting element, in particular a bonding wire or a clip, which connects the further connecting body to the semiconductor chip. Thus, a height difference between the bent semiconductor chip and the further connecting body can be bridged by means of wire bonding, clip assembly, or similar methods.

[0035] In a further embodiment, the semiconductor chip is additionally bent at a second bending section (in addition to a first bending section, which is used to connect the semiconductor chip to the aforementioned connecting body) in order to be connected to the further connecting body at a third connection area of ​​the semiconductor chip at a third vertical plane. It is highly advantageous for the semiconductor chip to be bent in such a way that it can be directly connected to three other entities at three vertical planes, i.e., the substrate, the connecting body, and the further connecting body. Thus, a more complex curvature of the bent semiconductor chip can generate a user-definable sequence of several concave and / or several convex sections thereof.Advantageously, such a complex curvature of a bent semiconductor chip, which allows the semiconductor chip to be coupled to two, three (or more) different vertical planes without the need to provide additional coupling elements, such as clips or bond wires, can significantly contribute to the compactness of the package and to low-loss operation.

[0036] In one embodiment, the third vertical plane is different from the first vertical plane and is different from the second vertical plane. In such a configuration, the elements at three different vertical planes can be directly connected to the semiconductor chip without any additional elements in between.

[0037] In another embodiment, the third vertical plane is different from the first and second vertical planes and identical to the first and second vertical planes. For example, a central vertical plane of a central section of the bent semiconductor chip can be different from (in particular higher than) two outer interconnect regions of the semiconductor chip, which are arranged in the same (in particular lower) vertical plane.

[0038] In one embodiment, the aforementioned heat dissipation body also connects, preferably electrically, the further connecting body to the semiconductor chip. In such a configuration, the heat dissipation body can be embodied as a clip or any other electrically and thermally conductive body. Thus, an electrical connection of a bent or warped semiconductor chip to a further connecting body can synergistically establish a thermally conductive connection with the bent semiconductor chip. The heat dissipation body can therefore perform a dual function of dissipating heat from the semiconductor chip out of the package and establishing an additional electrical connection path for the semiconductor chip.

[0039] In one embodiment, the semiconductor chip has a first planar section mounted on or above the substrate, a second planar section mounted on the interconnect, and an inclined and / or curved section between the first and second planar sections. Thus, the bent semiconductor chip can be shaped as a ramp between two planar sections. However, it is also possible for a bent semiconductor chip to have multiple inclined and / or curved sections, for example, two inclined and / or curved sections separated by a planar section. Particularly when thin silicon chips are used as semiconductor chips, their shape can be flexibly adapted by means of essentially any desired bending trajectory.For example, it may be possible to first connect a first interconnected area of ​​the semiconductor chip to a first connected entity, such as the substrate. The semiconductor chip can then be bent or deformed so that a second interconnected area is connected to a second connected entity, such as a conductor. Optionally, the bending of the semiconductor chip, which is already connected at two points, can then be refined to create more complex configurations.

[0040] In one embodiment, the semiconductor chip is bent to be permanently connected to a bending strain. In such a configuration, the bending strain can permanently act on the bent semiconductor chip of the package. The aforementioned connection areas of the semiconductor chip can be fixed in position on the respective connected entity. This can eliminate any effort involved in permanently bending semiconductor chips.

[0041] However, in an alternative embodiment, the semiconductor chip can also be three-dimensionally curved without permanent bending strain in order to be connected to the associated entities, for example the substrate and the connecting body, in a force-free bent state. This measure allows a force-free configuration to be created.

[0042] In one embodiment, the semiconductor chip is elastically deformed while connected to the substrate and the connecting body. Elastic deformation is characterized by the behavior of the bent semiconductor chip, whereby the bent semiconductor chip returns to a planar configuration when the bending or bending load or force is removed.

[0043] However, it is also possible that the bent semiconductor chip is plastically deformed, i.e., remains in the deformed configuration after the bending strain or force is released.

[0044] In one embodiment, the first interconnection area and the second interconnection area both form part of the same main surface of the semiconductor chip, specifically, both form part of a lower main surface of the semiconductor chip. In such a configuration, the different interconnection areas are formed on the same main surface of the semiconductor chip, i.e., on its lower main surface or its upper main surface. Alternatively, it is also possible for interconnection areas to be provided on both overlying main surfaces of the bent semiconductor chip, which further increases the design freedom of a package designer.

[0045] In one embodiment, all conductors or connections of the carrier can protrude laterally from the encapsulation (corresponding to a led package architecture). However, it is also possible for the package to be a leadless package.

[0046] In one embodiment, a connection between the semiconductor chip and the substrate and / or the connecting body(s) is formed by means of a connecting medium. For example, the connecting medium can be a soldered structure, a sintered structure, a welded structure, and / or an adhesive structure. Thus, the mounting of the semiconductor chip onto the substrate can be accomplished by soldering, sintering, or welding, or by bonding or adhesive bonding.

[0047] In one embodiment, the package comprises a plurality of semiconductor chips mounted on the substrate. Thus, the package can include one or more semiconductor chips (for example, at least one passive component, such as a capacitor, and at least one active component, such as a semiconductor chip).

[0048] In one embodiment, the at least one semiconductor chip comprises at least one from the group consisting of a controller circuit, a driver circuit, and a power semiconductor circuit. All these circuits can be integrated into a single semiconductor chip or separately into different chips. For example, a corresponding power semiconductor application can be implemented using the chip(s), wherein integrated circuit elements of such a power semiconductor chip can comprise at least one transistor (in particular a MOSFET, metal-oxide semiconductor field-effect transistor), at least one diode, etc. In particular, circuits can be manufactured that perform a half-bridge function, a full-bridge function, etc.

[0049] In one embodiment, the package is configured as a power converter, in particular one comprising an AC / DC power converter and a DC / DC power converter. However, other electronic applications are also possible, for example, inverters, etc.

[0050] A semiconductor substrate, i.e., a silicon substrate, can be used as the substrate or wafer for the semiconductor chips. Alternatively, a silicon oxide or another insulator substrate can be provided. It is also possible to implement a germanium substrate or a III-V semiconductor material. For example, exemplary embodiments can be implemented using GaN or SiC technology.

[0051] Furthermore, exemplary embodiments of standard semiconductor processing technologies can make use of, for example, suitable etching technologies (including isotropic and anisotropic etching technologies, in particular plasma etching, dry etching, wet etching), structuring technologies (which may involve lithographic masks), deposition technologies (for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputtering, etc.).

[0052] The above and other objectives, features and advantages will become apparent from the following description and the accompanying claims, in conjunction with the accompanying drawings, in which identical parts or elements are designated by the same reference numerals. Brief description of the drawings

[0053] The accompanying drawings, which are included to provide a deeper understanding of exemplary embodiments and which form part of the description, show exemplary embodiments.

[0054] In the drawings: Fig. Figure 1 shows a cross-sectional view of a package according to an exemplary embodiment. Fig. Figure 2 shows a flowchart of a process for manufacturing a package according to an exemplary embodiment. Fig. Figure 3 shows different views of a package according to a comparison example before encapsulation. Fig. Figure 4 shows the package of the comparison example according to Fig. 3 after encapsulation. Fig. Figure 5 shows different views of a package according to another exemplary embodiment before encapsulation. Fig. 6 shows the package according to Fig. 5 after encapsulation. Fig. Figure 7 shows different views of a package according to a comparison example before encapsulation. Fig. Figure 8 shows the package of the comparison example according to Fig. 7 after encapsulation. Detailed description

[0055] The representation in the drawing is schematic and not to scale.

[0056] Before exemplary embodiments are described in more detail with reference to the figures, some general considerations are summarized on which exemplary embodiments were based.

[0057] According to one exemplary embodiment, the flexible nature of a thin semiconductor chip (especially silicon chips) can be used to overcome a vertical gap between different interconnection areas of the semiconductor chip with respect to connected entities, for example, a substrate and another interconnect. By bending or warping the semiconductor chip, conventional measures, such as clips or bond wires, for bridging a gap between connected entities at different vertical planes can be partially or completely eliminated. As a result, a simpler package design can be achieved and the manufacturing effort can be significantly reduced.

[0058] According to one exemplary embodiment, a contact area of ​​the semiconductor chip can be arranged at a first vertical plane, and a second contact area of ​​the same semiconductor chip can be arranged at a second vertical plane. This can be achieved by bending the semiconductor chip to or between the aforementioned different vertical planes.

[0059] To promote the flexibility of the semiconductor chip, it can be made of a sufficiently thin semiconductor material, preferably silicon, and preferably of a constant thickness. For example, such a thickness can be less than 50 µm or, most preferably, 20 µm or less. Silicon or other semiconductors, for example, gallium nitride, can be particularly suitable for producing bent semiconductor chips if they are sufficiently thin. For example, such semiconductor chips can be connected under permanent elastic bending strain due to elastic deformation of the semiconductor chip.

[0060] Particularly when stacking multiple semiconductor chips on top of each other in a single package, the described manufacturing architecture can achieve significant space savings. Furthermore, shorter interconnect paths can be created within the package, which in turn leads to lower losses and improved signal quality.

[0061] There is a constant demand for semiconductor packages to have a smaller physical footprint, reducing the area occupied by printed circuit boards (PCBs) and enabling the realization of smaller, denser products. Other electrical requirements include a reduction in drain-source on-resistance (RDSON), collector-emitter on-voltage (VCEON), etc., for more efficient power delivery. Furthermore, low inductance can be advantageous for certain applications, such as operation in motor drives. Exemplary embodiments can help address these and / or other physical challenges and can, in particular, contribute to increasing power density.

[0062] According to an exemplary embodiment, a package is provided which is designed, for example, in a MOSFET half-bridge configuration. Such a package can comprise at least one sufficiently thin and therefore flexible semiconductor chip (in particular, a thin plate). More precisely, such a package can comprise a (for example, a conductor-frame-like) carrier, a first thin semiconductor chip (for example, a first thin plate) which is connected to the (for example, conductor-frame-like) carrier, and a second electronic component (for example, a second plate) which is aligned above the (in particular, top-side) first semiconductor chip. For example, a top-side pad (for example, a drain pad) can be added to the back side of the second electronic component to provide a top-side connection and a thermal path for the upper semiconductor chip.Furthermore, it may be possible to provide a gate on the top-side semiconductor chip, which is preferably connected (in particular soldered) to the conductor frame. In addition, another connection (in particular a gate connection) can be made to the second electronic component (for example, via a wire or a clip). Preferably, but not necessarily, the described assembly can be encapsulated (in particular potted).

[0063] One exemplary embodiment utilizes the flexible nature of a semiconductor chip, for example, a silicon wafer thinned to approximately 100 µm or less to improve the circuit's on-resistance. By flipping one electronic component (for example, a semiconductor wafer) and placing it on top of another (preferably similarly thinned) electronic component (for example, another semiconductor wafer), it may be possible to create an electrical configuration between the two electronic components / semiconductor chips (preferably wafers) with very low resistance and inductance. Since the electronic components / semiconductor chips can be stacked on top of each other, this also provides a possibility for a package with a smaller surface area on a mounting base (for example, a printed circuit board).Furthermore, it is also possible to establish double-sided cooling via the plate placed on top.

[0064] In the case of a MOSFET-like semiconductor chip, a half-bridge configuration can be achieved, in particular, by connecting the electronic components / semiconductor chips in the manner described, thereby utilizing the flexibility of at least one of the electronic components / semiconductor chips. To achieve a corresponding electronic implementation in an IGBT with a diode, the diode can bring its cathode (in particular corresponding to a base of a chip) connection out through the top of the chip (for example, by providing an inverted field-effect transistor).

[0065] To ensure that no electrical short circuit occurs between the plate edge termination structure, protection and insulation of this area can be advantageous. Additionally, the plate front metal (FSM) can be made thicker, and one or more metals suitable for soldering can be advantageously incorporated.

[0066] In one embodiment, a first plate can be connected to a conductor frame. A second plate can then be aligned over the top of the first plate. The thin upper plate can then be bent to achieve the same plane as the plate mounting and the conductor frame of the lower plate. An upper drain pad can also be added to the back of the second plate to provide a top-side connection and a heat path for the upper plate. The gate on the upper plate can also be soldered to an associated conductor frame pad. A gate connection can then be added to the lower plate (for example, a wire or clip can be used) before the assembly is potted. In particular, the use of bending a plate to form a connection on a different plane can be extremely advantageous in terms of package compactness and performance.

[0067] Fig. Figure 1 shows a cross-sectional view of a Package 100 according to an exemplary embodiment.

[0068] The package 100 shown has a carrier 102. Furthermore, the package 100 has a semiconductor chip 104, which has a first connection area 106. The semiconductor chip 104 is mounted on or above the carrier 102 at a first vertical plane 108. A connecting body 110 is also provided. The semiconductor chip 104 is bent to connect to the connecting body 110 at a second connection area 112 of the semiconductor chip 104 at a second vertical plane 114, which is different from the first vertical plane 108. As shown, the first connection area 106 and the second connection area 112 both form part of a lower main surface of the semiconductor chip 104.

[0069] As schematically in Fig. As shown in Figure 1, the connecting body 110 can have an electrically conductive structure 120 (for example, a conductor, a pad, or a section of a conductor frame) or another electronic component 122.

[0070] More precisely, the semiconductor chip 104 shown can have a first planar section 138 which is mounted on or above the carrier 102, a second planar section 140 which is mounted on the connecting body 110, and an inclined and curved section 142 between the first planar section 138 and the second planar section 140.

[0071] According to Fig. The package 100 has a height profile, as shown by its curved configuration along a vertical axis 150. A purely mechanical or an electrically conductive connection can be established between the carrier 102 and the semiconductor chip 104 at the first connection area 106, which is located at a first vertical plane 108, for example by means of an electrically conductive connection structure 118 (for example, an adhesive or a solder). Similarly, the second connection area 112 of the semiconductor chip 104, which is located at a lower second vertical plane 114, can be connected to the connecting body 110 purely mechanically or electrically. This can be accomplished by means of another electrically conductive connection structure 118, for example, an adhesive or a solder.

[0072] Fig. Figure 2 shows a flowchart 200 of a method for manufacturing a package 100 according to an exemplary embodiment. The reference numerals used in the following description of the method for manufacturing the package 100 refer to the embodiment of Fig. 1.

[0073] As shown by means of block 202, the method comprises mounting the semiconductor chip 104, which has a first connection area 106 at a first vertical plane 108, on or above the carrier 102. As shown by means of block 204, the method further comprises bending the semiconductor chip 104 in order to connect the semiconductor chip 104 to the connecting body 110 at a second connection area 112 of the semiconductor chip at a second vertical plane 114, which is different from the first vertical plane 108.

[0074] Referring to Fig. 3, Fig. 4, Fig. 7 and Fig. Section 8 provides comparative examples. Fig. 5 and Fig. Section 6 describes further exemplary embodiments of Package 100 according to exemplary embodiments. In each of Fig. 3 to Fig. Figure 8 shows a top view (shown on the lower left side) and two cross-sectional views (shown on the upper and lower right sides) of the respective Package 100.

[0075] Fig. Figure 3 shows different views of a Package 100 according to a comparison example before encapsulation.

[0076] Fig. Figure 4 shows package 100 according to Fig. 3 after encapsulation.

[0077] The package 100 shown includes a support 102, which can be embodied as a planar metal layer. The support 102 can form part of a structured planar metal plate, for example, a conductor frame. The support 102 can, for example, be a die pad. For example, the support 102 is made of copper and / or aluminum.

[0078] Furthermore, the package 100 includes a semiconductor chip 104, which can be a thin silicon wafer with a thickness of, for example, 20 µm. The semiconductor chip 104 can have a first interconnection area 106, in which the semiconductor chip 104 is mounted on a first vertical plane 108 above the carrier 102.

[0079] As in Fig. As shown in Figure 3, a further electronic component 116 (for example, another semiconductor wafer) can be arranged between the carrier 102 and the semiconductor chip 104, such that the components 104 and 116 form a stacked wafer configuration. An electrically conductive interconnect structure 118, for example, a solder structure, can be arranged between the semiconductor chip 104 and the further electronic component 116 for mechanical and electrical coupling of the components 104 and 116. Preferably, the semiconductor chip 104 and the further electronic component 116 are connected to form a half-bridge. For this purpose, the semiconductor chip 104 and the further electronic component 116 can both be metal-oxide semiconductor field-effect transistor (MOSFET) chips.

[0080] Furthermore, the package 100 includes an electrically conductive connecting body 110, for example, a pad or a pin. For example, the connecting body 110 can form part of the same structured planar metal plate (in particular, a conductor frame) as the support 102. Consequently, the connecting body 110 can be arranged in the same vertical plane as the support 102. In other words, the support 102 and the connecting body 110 can be coplanar and can belong to a common conductor frame.

[0081] Due to the presence of the electronic component 116 vertically between the carrier 102 and the semiconductor chip 104, the first connection area 106 is located on a lower main surface of the semiconductor chip 104 at a higher vertical plane compared to an upper main surface of the connector body 110. To bridge the vertical gap between the semiconductor chip 104 and the connector body 110, the semiconductor chip 104 is bent to assume a three-dimensionally curved configuration. This results in a second connection area 112 of the semiconductor chip 104 being directly connected to the connector body 110 at a second vertical plane 114, which differs from the first vertical plane 108. By bending or warping the thin semiconductor chip 104, the aforementioned vertical gap can be bridged by the semiconductor chip 104 itself, without the need for a clip, bond wire, or similar device.This may allow the Package 100 to be implemented according to . Fig. 3 and Fig. 4 in a compact and lightweight manner and with minimal effort. Furthermore, the described direct connection between the semiconductor chip 104 and the connecting body 110 can keep the signal paths short, resulting in low loss and high-quality signal transmission.

[0082] During the manufacturing of the package 100, the semiconductor chip 104 can be bent into a bent state and can be firmly connected to the electronic component 116 or the connecting body 110 with a permanent bending strain. During bending, the semiconductor chip 104 can be elastically deformed while it is connected (for example, by soldering) to the electronic component 116 and the connecting body 110. To promote the flexibility of the semiconductor chip 104, its thickness, d, can be sufficiently small, preferably less than 50 µm, and particularly preferably 20 µm or less.

[0083] As in Fig. As shown in Figure 4, the package 100 can have an encapsulation 124 which encapsulates the semiconductor chip 104, a part of the carrier 102, and a part of the connecting body 110. The encapsulation 124 can, for example, be a molding compound. The encapsulation can be carried out by overmolding. Since the semiconductor chip 104 can be connected to the top surface of the other electronic component 116 as well as to a top surface of the connecting body 110 by soldering or a similar process, the preferably elastically bent semiconductor chip 104 can be connected to both the other electronic component 116 and the connecting body 110 under permanent tension. Encapsulating the bent semiconductor chip 104 by means of a molding compound encapsulation 124 can be extremely advantageous for mechanically stabilizing the bent semiconductor chip 104 in the desired bent state shown.This can improve the mechanical and electrical reliability and therefore the performance of Package 100.

[0084] As in Fig. 3 and also in Fig. As shown in Figure 4, a heat sink 126 is mounted on top of the semiconductor chip 104. For example, the heat sink 126 can be a metal layer or sheet. In particular, the heat sink 126 can be a metal block, for example, a copper block. The heat sink 126 can be made of a material that has a high thermal conductivity (for example, at least 50 W / mK). As shown in Fig. As shown in Figure 4, an upper main surface of the heat dissipation body 126 is exposed relative to the encapsulation 124 on an upper main surface of the package 100 to promote top-side cooling. During operation of the package 100, the semiconductor chips 104, 116 can generate a considerable amount of heat, which can be at least partially dissipated from the package 100 at its upper surface by means of the heat dissipation body 126.

[0085] As shown, a lower main surface of the carrier 102 and a lower main surface of the connecting body 110 are also exposed with respect to the encapsulation 124. Thus, both the carrier 102 and the connecting body 110 can contribute to heat dissipation from the package 100 on one underside. This allows for double-sided cooling of the package 100 through the interaction of the heat dissipation body 126, the carrier 102, and the connecting body 110. Furthermore, the exposed surfaces of the carrier 102 and the connecting body 110 can function as electrical terminals of the package 100 for connecting the electronic components / semiconductor chips 104, 116 to an electronic periphery of the package 100 (for example, a printed circuit board on which the package 100 is mounted, for example, by soldering; not shown).

[0086] As in Fig. 3 and Fig. As shown in Figure 4, the package 100 has an additional interconnect 128, which is connected to the semiconductor chip 104 via solder. For example, the additional interconnect 128 can be another pad or pin. It is possible that the additional interconnect 128 forms part of the same structured planar metal plate (in particular, a conductor frame) as the carrier 102 and the interconnect 110. Consequently, the additional interconnect 128 can be arranged in the same vertical plane as the carrier 102 and the interconnect 110. In other words, the carrier 102, the interconnect 110, and the additional interconnect 128 are coplanar and can belong to a common conductor frame.

[0087] Referring further to the connecting body 128, an electrically conductive connecting element 130 (for example, a bond wire, which can be referred to as a gate wire) can be provided for connecting the further connecting body 128 to the semiconductor chip 104 via soldering material.

[0088] As already mentioned, Package 100, which is in Fig. 3 and Fig. Figure 4 shows two electronic components / semiconductor chips 104 and 116, which can be configured as thin MOSFET plates connected in a half-bridge configuration. The lower electronic component 116 and the upper semiconductor chip 104 can be soldered to a front-facing metal surface to create a plate-to-plate connection. The upper semiconductor chip 104 is a bent MOSFET plate that also contacts the interconnect 110, which is configured here as a conductor frame pad.

[0089] More precisely, the connecting body 110 can represent a source pad. Reference numeral 158 indicates Fig. 3. A gate pad is also located on the upper semiconductor chip 104. As indicated by the reference numeral 160, a drain pad may be soldered to the back side of the semiconductor chip 104. Accordingly, another drain pad 164 and another gate pad 166 are also indicated.

[0090] Fig. Figure 4 shows package 100 of Fig. 3 after encapsulation using a molding compound. In other words, the thin platelet MOSFETs in the half-bridge configuration can be overmolded with an encapsulation 124. Fig. Figure 4 also shows a top-side cooling connection in the form of the heat dissipation body 126, which is exposed beyond the encapsulation 124.

[0091] Fig. Figure 5 shows different views of a Package 100 according to another exemplary embodiment before encapsulation. Fig. Figure 6 shows package 100 according to Fig. 5 after encapsulation.

[0092] According to Fig. 5 and Fig. 6 The heat dissipation body 126 not only dissipates heat from the semiconductor chip 104, but also fulfills the additional function of electrically coupling the further connecting body 128 to a top-side connection of the semiconductor chip 104. For this purpose, the heat dissipation body 126 is made of Fig. 5 and Fig. 6 configured as a Clip 170, i.e. as a three-dimensionally bent metal plate.

[0093] Furthermore, the design differs from Fig. 5 and Fig. 6 from the comparative example of Fig. 3 and Fig. 4 in particular in that the thin plate MOSFETs, which are connected in the half-bridge configuration, represent an alternative drain pad connection architecture according to Fig. 5 and Fig. 6. The clip 170 mentioned can also have a drain pad connection function, see reference numeral 174, and can therefore be referred to as a drain pad clip. How best to in Fig. As can be seen in Figure 6, an upper main surface of the clip 170 is exposed beyond the encapsulation 124 after encapsulation, thereby forming a top-side cooling design.

[0094] Fig. Figure 7 shows different views of a Package 100 according to a comparison example before encapsulation. Fig. Figure 8 shows the package 100 according to Fig. 7 after encapsulation.

[0095] According to Fig. 7 and Fig. In Figure 8, the semiconductor chip 104 is bent at both opposite end sections relative to its central section, so that it can be connected to the further connecting body 128 at a third connection area 132 of the semiconductor chip 104 at a third vertical plane 134. In the comparative example shown, the third vertical plane 134 is different from (in particular lower than) the first vertical plane 108 and is identical to the second vertical plane 114 (alternatively, the third vertical plane 134 can also be different from the second vertical plane 114, not shown).

[0096] According to Fig. 7 and Fig. 8. One of the semiconductor chip 104 and the other electronic component 116 can be an insulated gate bipolar transistor chip (IGBT, see reference numeral 111), and the other of the semiconductor chip 104 and the other electronic component 116 can be a diode chip (see reference numeral 113). For more details, refer to the comparative example of Fig. 7 and Fig. 8. The IGBT 111, in the form of the electronic component 116, can initially be connected to a conductor frame collector or cathode pad. The diode chip 113 (corresponding to the semiconductor chip 104), which includes a front-facing output for the cathode connection, can then be placed over the top of the IGBT chip, so that the flexible nature of its thin silicon can then provide a connection to the conductor frame at the same vertical plane as the IGBT chip mounting. A gate connection can then be added to the IGBT 111, and the assembly can be encapsulated, for example, by forming. Thus, the configuration of Fig. 7 and Fig. 8 a thin plate-IGBT and FRED (fast-recovery epitaxial diode) configuration, wherein the FRED has its cathode provided through the top.

[0097] The comparative example of Fig. 7 and Fig. 8 differs from the comparative example of Fig. 3 to Fig. 6 not only by combining a bipolar transistor and a diode (instead of combining two MOSFETs), but also by the fact that according to Fig. 7 and Fig. 8 The upper semiconductor chip 104 has two bent sections. By means of these two bent, curved or bent sections, the package 100 provides three connections at different vertical planes, more precisely one raised vertical plane between two lower (and, for example, identical) vertical planes.

[0098] Show in more detail Fig. 7 and Fig.Figure 8 shows an electrically conductive connecting element 130 (for example, a bond wire, here represented as a gate wire) and an emitter / anode frame pad 180. Reference numeral 182 denotes an anode region on the diode. Reference numeral 184 indicates a collector / cathode frame pad, and reference numeral 186 indicates a cathode region on the pad. An IGBT gate pad is designated by reference numeral 188, and a gate frame pad by reference numeral 190. As shown, the upper semiconductor chip 104 is bent to contact the frame pads at both ends.

Claims

[1] A package (100) which contains: • a carrier (102); • a semiconductor chip (104) having a first interconnection area (106) on which the semiconductor chip (104) is mounted at a first vertical height (108) on or above the support (102); and • a connecting body (110); • wherein the semiconductor chip (104) is bent in order to be connected to the connecting body (110) at a second connection area (112) of the semiconductor chip (104) at a second vertical height (114) which differs from the first vertical height (108); • wherein the semiconductor chip (104) has a first planar section (138) mounted on or above the support (102), a second planar section (140) mounted on the connecting body (110), and an inclined and / or curved section (142) between the first planar section (138) and the second planar section (140); • comprising a further electronic component (116) which is arranged between the carrier (102) and the semiconductor chip (104); • comprising an encapsulation (124) which encapsulates at least a part of the semiconductor chip (104), at least a part of the carrier (102), and at least a part of the connecting body (110); • having a heat dissipation body (126) on the semiconductor chip (104) and exposed with respect to the encapsulation (124); • wherein the support (102) is exposed with respect to the encapsulation (124); • having a further connecting body (128); • wherein the heat dissipation body (126) electrically connects the further connecting body (128) to the semiconductor chip (104). [2] The package (100) according to claim 1, comprising at least one of the following features: the further electronic component (116) is an active semiconductor component, in particular one consisting of a transistor, a diode, a bipolar transistor, and an insulated gate bipolar transistor; The package (100) has an electrically conductive connection structure (118), in particular a solder structure, between the semiconductor chip (104) and the further electronic component (116), in particular for electrically coupling pads of the semiconductor chip (104) and the further electronic component (116); wherein the semiconductor chip (104) and the other electronic component (116) are connected to form a half-bridge; The semiconductor chip (104) and the further electronic component (116) are transistor chips, in particular metal oxide semiconductor field-effect transistor chips; or One of the semiconductor chip (104) and the other electronic component (116) is a transistor chip, in particular an insulated gate bipolar transistor chip, and the other of the semiconductor chip (104) and the other electronic component (116) is a diode chip. [3] The package (100) according to any one of claims 1 to 2, comprising one of the following features: wherein the connecting body (110) has an electrically conductive structure (120), in particular one consisting of a conductor, a pad, and a section of a conductor frame; wherein the connecting body (110) also includes a further electronic component (122). [4] The package (100) according to any one of claims 1 to 3, comprising at least one of the following features: wherein a thickness (d) of the bent semiconductor chip (104) is less than 20 µm; wherein the semiconductor chip (104) is one of a silicon chip, a silicon carbide chip, or a gallium nitride chip; wherein the semiconductor chip (104) is an active semiconductor component, in particular one consisting of a transistor, a diode, a bipolar transistor, and an insulated gate bipolar transistor. [5] The package (100) according to any one of claims 1 to 4, wherein the carrier (102) and the connecting body (110) are coplanar. [6] The package (100) according to any one of claims 1 to 5, wherein the support (102) and the connecting body (110) form a common conductor frame. [7] The package (100) according to any one of claims 1 to 6, wherein the connecting body (110) is exposed with respect to the encapsulation (124). [8] The package (100) according to any one of claims 1 to 7, comprising an electrically conductive connecting element (130), in particular a bond wire, a bond tape or a clip, which connects the further connecting body (128) to the semiconductor chip (104). [9] The package (100) according to any one of claims 1 to 8, wherein the semiconductor chip (104) is additionally bent in order to be connected to the further connecting body (128) at a third connection area (132) of the semiconductor chip (104) at a third vertical height (134). [10] The package (100) according to any one of claims 1 to 9, comprising at least one of the following features: the third vertical height (134) is different from the first vertical height (108) and is different from the second vertical height (114); the third vertical height (134) is different from the first vertical height (108) and the second vertical height (114) and is identical to the other of the first vertical height (108) and the second vertical height (114). [11] The package (100) according to any one of claims 1 to 10, wherein the semiconductor chip (104) is bent to be connected between the carrier (102) and the connecting body (110) with a permanent bending strain. [12] The package (100) according to any one of claims 1 to 11, wherein the semiconductor chip (104) is elastically deformed in its state connected to the carrier (102) and to the connecting body (110). [13] The package (100) according to any one of claims 1 to 12, wherein the first interconnection area (106) and the second interconnection area (112) both form part of the same main surface of the semiconductor chip (104), in particular both form part of a lower main surface of the semiconductor chip (104). [14] A method for producing a package (100), wherein the method comprises: • Mounting a semiconductor chip (104) which has a first interconnection area (106) at a first vertical height (108) on or above a support (102); and • Bending the semiconductor chip (104) in order to connect the semiconductor chip (104) to a connecting body (110) at a second connection area (112) of the semiconductor chip (104) at a second vertical height (114) which differs from the first vertical height (108), • such that the semiconductor chip (104) has a first planar section (138) mounted on or above the carrier (102), a second planar section (140) mounted on the connecting body (110), and an inclined and / or curved section (142) between the first planar section (138) and the second planar section (140); • the package (100) comprising a further electronic component (116) which is arranged between the carrier (102) and the semiconductor chip (104); • the package (100) comprising an encapsulation (124) which encapsulates at least a part of the semiconductor chip (104), at least a part of the carrier (102), and at least a part of the connecting body (110); • the package (100) having a heat dissipation body (126) on the semiconductor chip (104) and exposed with respect to the encapsulation (124); • wherein the support (102) is exposed with respect to the encapsulation (124); • the package (100) comprising a further connecting body (128); • wherein the heat dissipation body (126) electrically connects the further connecting body (128) to the semiconductor chip (104).

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