WAFER WITH CRYSTALLINE SILICON AND A POLYSILICON LAYER WITH HIGH IMPACT POLYSILICON LAYER

Abstract

Structure comprising a semiconductor-on-insulator, SOI, wafer (12) comprising a lower crystalline semiconductor layer (12a), a polysilicon layer (18) above the lower crystalline semiconductor layer (12a), an upper crystalline semiconductor layer (12b) above the polysilicon layer (18), a buried insulator layer (14, 20) above the upper crystalline semiconductor layer (12b), and an uppermost crystalline semiconductor layer (22) above the buried insulator layer (14, 20), wherein the polysilicon layer (18) comprises an extension region (18a) which is surrounded on its sides by the upper crystalline semiconductor layer (12b).

Description

AREA OF INVENTION

[0001] The present invention relates to semiconductor structures and in particular to a wafer with crystalline silicon and a trap-rich polysilicon region and to a manufacturing process. BACKGROUND

[0002] Bulk silicon substrates are less expensive than silicon-on-insulator (SOI) substrates. Generally, an SOI substrate comprises a thin silicon device layer, a handle substrate, and a thin buried oxide (BOX) layer that physically separates and electrically insulates the device layer from the handle substrate.

[0003] Devices manufactured using SOI technologies can exhibit certain performance improvements compared to similar devices manufactured in a bulk silicon substrate. For example, a bulk silicon substrate, unlike an SOI substrate, is characterized by poor device isolation against harmonic generation. Wafers with high resistivity are used for ~1 to 10 GHz RF applications to reduce substrate-to-RF losses.

[0004] In US 2018 / 0 337 043 A1, US 2017 / 0 084 478 A1 and US 2015 / 0 004 778 A1, SOI structures are taught, comprising a substrate, an adhesion-rich layer (for example, a polysilicon layer), a BOX layer, and an active layer above the BOX layer. The BOX layer is positioned directly above the adhesion-rich layer. BRIEF SUMMARY

[0005] According to the invention, a structure comprises: a semiconductor-on-insulator, SOI wafer comprising a lower crystalline semiconductor layer, a polysilicon layer above the lower crystalline semiconductor layer, an upper crystalline semiconductor layer above the polysilicon layer, a buried insulator layer above the upper crystalline semiconductor layer, and an uppermost crystalline semiconductor layer above the buried insulator layer, wherein the polysilicon layer comprises an extension area surrounded on its sides by the upper crystalline semiconductor layer.

[0006] According to a further aspect of the invention, a structure comprises: a wafer composed of a trap-rich polysilicon layer and a single-crystal semiconductor material over the trap-rich polysilicon layer; a buried oxide layer on a surface of the single-crystal semiconductor material; and a crystalline semiconductor layer over the buried oxide layer, wherein the polysilicon layer comprises an extent area surrounded on its sides by the single-crystal semiconductor material of the wafer.

[0007] According to a further aspect of the invention, a method comprises: forming a polysilicon layer with high adhesion in a wafer beneath a single-crystal semiconductor material; forming an insulating layer over the single-crystal semiconductor material, wherein the single-crystal semiconductor material provides a separation between the polysilicon layer with high adhesion and the insulating layer; and forming a crystalline semiconductor layer over the insulating layer, wherein the polysilicon layer with high adhesion comprises an extent area which is surrounded on its sides by the single-crystal semiconductor material of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is described in detail below with reference to the aforementioned multitude of drawings, using non-limiting examples of exemplary embodiments of the present disclosure. Fig. Figure 1 shows a wafer according to aspects of the present revelation. Fig. Figure 2 shows an amorphous region in the wafer, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. Figure 3 shows a recrystallized section of the wafer, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. Figure 4 shows the formation of a substrate-on-insulator technology, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. Figure 5 shows the substrate-on-insulator technology with a single-crystal substrate separated by a polysilicon layer, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. Figures 6-8 show a wafer and respective manufacturing processes according to additional aspects of the present disclosure. DETAILED DESCRIPTION

[0009] The present disclosure relates to semiconductor structures, and in particular to a wafer comprising crystalline silicon and a trap-rich polysilicon layer, and to a fabrication method. Specifically, the present disclosure provides a silicon-on-insulator (SOI) wafer comprising crystalline silicon, separating a trap-rich polysilicon layer from a buried oxide layer, and to a fabrication method. Advantageously, among other advantages, the present disclosure provides improved linearity for a field-effect transistor.

[0010] In embodiments, the wafer is a substrate-on-insulator (SOI) technology. The wafer comprises a thin silicon layer, a buried oxide layer, and a single-crystal silicon handle wafer with a high-adhesion polysilicon layer. The thin silicon layer can be a single-crystal material, e.g., monocrystalline silicon. The silicon layer and the monocrystalline silicon can also be composed of other single-crystal substrate materials. The high-adhesion polysilicon layer is located beneath and separated from the buried oxide layer. In further embodiments, the crystalline silicon can be located beneath the buried oxide layer for FET or NPN body contact, and the high-adhesion polysilicon layer provides improved linearity.

[0011] In more specific embodiments, the structure comprises a substrate and an adhesion-rich layer. A first crystalline layer is provided above the adhesion-rich layer, with a dielectric layer (e.g., a buried oxide layer) above the first crystalline layer. The first crystalline layer provides a separation between the adhesion-rich layer and the dielectric layer. A second crystalline layer is provided above the buried dielectric layer, forming an SOI wafer with the adhesion-rich layer separated from the buried oxide layer. In embodiments, the first and second crystalline layers can be monocrystalline silicon, and the buried dielectric layer can be an oxide material. In other embodiments, the adhesion-rich layer contains a crystalline polysilicon material.

[0012] The structures of this disclosure can be fabricated in several ways using several different tools. Generally, however, the methodologies and tools used are those for forming structures with dimensions on the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to fabricate the structures of this disclosure were adopted from integrated circuit (IC) technology. For example, the structures are fabricated on wafers and realized in material films that are patterned onto the top surface of a wafer by photolithographic processes. In particular, the fabrication of the structures uses three basic building blocks: (i) deposition of thin material films onto a substrate, (ii) application of a patterned mask to the top surface of the films by photolithographic imaging, and (iii) selective etching of the film with respect to the mask.

[0013] Fig. Figure 1 shows a wafer according to aspects of the present disclosure. In particular, the structure comprises 10 of Fig. 1. A handle wafer 12, used as a front-end module, which, in an exemplary embodiment, has a high resistivity for RF device applications. For example, the resistivity of the wafer 12 can be a high resistivity, such as, but not limited to, 1000 ohm-cm or greater. The wafer 12 can be composed of a single-crystal material 12a. For example, the single-crystal material 12a can be a single-crystal silicon material. In other embodiments, the single-crystal material 12a can be other single-crystal semiconductor materials, such as SiGe, SiC, Ge, etc., and can optionally be bonded to glass or sapphire (also represented by reference numeral 12a). An optional layer of oxide material 14 can be formed on the wafer 12.In embodiments, the optional oxide material 14, for example, may have a thickness of about 50 nm and may be formed by thermal oxidation, for example, by oxidation at 1000 °C in an oven.

[0014] Fig. Figure 2 shows an amorphous region 16 extending into the wafer 12. In embodiments, the amorphous region 16 is formed, for example, from amorphous silicon on a surface of the wafer 12 and extends to a certain depth. The amorphous region 16 is produced by amorphizing the substrate 12 using an implantation process at a critical dose that prevents recrystallization of the wafer 12, for example, of the single-crystal material 12a. In embodiments, the amorphous region 16 can be implanted by means of a coating, for example, the oxide material 14, or onto a bare surface of the wafer 12. In embodiments, the implantation process can be an argon implantation process at a dose level of 1E14 ions / cm². 2 up to 1.5 E15 ions / cm² 2 , and in more preferred embodiments, 1.25 E15 ions / cm² 2The implant can use argon or other implant elements, e.g., other inert gases such as other noble gases like xenon, germanium, nitrogen, or oxygen, etc. In embodiments, the amorphous region 16 has a crystalline silicon layer of a few tens of nm thickness on its surface, which, during subsequent aging steps, forms the seed crystal for the recrystallization of amorphous silicon.

[0015] In Fig. 3. The wafer 12 is subjected to a rapid thermal annealing process to recrystallize its surface, forming a single-crystal region 12b on the surface. The rapid thermal annealing process also leaves one or more polysilicon or adhesion-rich polysilicon layers 18 beneath the recrystallized region (layer) 12b. It should be clear to those skilled in the art that the adhesion-rich polysilicon layer 18 advantageously provides improved linearity and is capable of repinning a gate bias. The rapid thermal annealing process can be carried out at a temperature between 900 °C and 1150 °C for 0 to 10 seconds. In embodiments, the thermal annealing process is a spike anneal (e.g., 0 seconds) at 1000 °C.In embodiments, the polysilicon or adhesion-rich polysilicon layer is 10 nm to 500 nm thick, and in one embodiment, 50 nm thick.

[0016] As in Fig. Figure 4 shows a silicon wafer 120 with the wafer of Fig. Figure 3 shows the silicon wafer 120 comprising a silicon layer 180 with an oxidized lower surface layer 20, formed, for example, by thermal oxidation at 1000 °C to a thickness of 0.1 to 5 microns, and in one embodiment to a thickness of 0.4 microns (although other dimensions are considered herein). The wafer 120 comprises a hydrogen-implanted layer 100 located some tens or hundreds of nm below the lower surface, as is known in the art. As represented by the arrow, the wafer 120 is bonded to the wafer 12. The wafer 120 is then separated along the hydrogen-implanted region 100, for example, using a Smartcut™ process as is known in the art, followed by a planarization process as is known in the art, resulting in the structure shown representatively in Figure 3. Fig. 5 is shown. Processes for forming the wafer are also shown, for example, in US patent no. US 5 374 564 A.

[0017] With reference to the Fig. 5. It should be understood that the insulator layers 14 and 20 in the completed wafer form a buried oxide layer (BOX), as shown in Fig. Figure 5 shows that oxides 14 and 20, although drawn separately in the figures, merge to form a single oxide layer during the oxidation step of the layer. Alternatively, oxide layer 14 could be omitted, and the BOX layer could be formed using only oxide layer 20. If this is the case, then oxide layer 20 could be formed either on wafer 120 (e.g., donor wafer) or wafer 12 (acceptor wafer).

[0018] As in Fig. As shown in Figure 5, the wafer 120, after being separated along the hydrogen-implanted region 100, forms the substrate 22, which is now bonded, for example, to the insulator layers 14 and 20 and forms the upper section of the SOI technology. The substrate 22 can be single-crystal silicon or another suitable single-crystal semiconductor material, as described herein as examples. In this way, the wafer is now a silicon-on-insulator (SOI) substrate, with the bonding-rich polysilicon layer 18 below the recrystallized region 12b and separated from the oxide layer 14 / 20 by the recrystallized region 12b. That is, the recrystallized region 12b is an interposed layer that prevents direct contact between the bonding-rich polysilicon layer 18 and the insulator layer 20, e.g., BOX. There is also a crystalline bottom layer, e.g. a single-crystal Si layer 12a, beneath the adhesion-rich polysilicon layer 18.

[0019] Fig. Figures 6-8 show a wafer and respective manufacturing processes according to additional aspects of the present disclosure, wherein the adhesion-rich polysilicon layer 18, 18a extends in region 18a to the surface of the handle wafer 12. In particular, the Fig. Figure 6 shows structure 10a with a structured material 24 above the wafer. In embodiments, the structured material 24 is an oxide material that is deposited and structured prior to an implantation process (as represented by the arrows). The structuring is a conventional lithography and etching process. For example, after deposition of the oxide material 24, a resist formed above the oxide material 24 is exposed to energy (light) to form a structure (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), is used to remove oxide material through the opening, leaving behind the structure of oxide material 24, which is shown in Fig. Figure 6 is shown. The resist can then be removed by a conventional oxygen ashing process or other known stripping agents. Following the structuring process, the manufacturing process continues with the implantation process, as already described herein, with the difference that the oxide material 24 blocks some of the implants in the wafer 12.

[0020] In Fig. 7. The oxide material is removed by conventional etching processes using selective chemistry. The wafer 12 is subjected to a rapid thermal aging process to recrystallize the surface of the wafer 12, forming a single-crystal region 12b on the surface of the wafer 12 and an adhesion-rich polysilicon layer 18, 18a beneath and adjacent to the single-crystal region 12b.

[0021] According to the invention, the rapid thermal annealing process leaves behind an adhesion-rich polysilicon extension region 18a that extends to the surface of the recrystallized surface 12b, the structure of which corresponds to that of the structured oxide material. The adhesion-rich polysilicon extension region 18a is also surrounded by the single-crystal region 12b, a section of which contacts the buried oxide layer 20 (see figure). Fig. 8) and remaining sections are separated from the buried oxide layer 20 by the single-crystal region 12b. The rapid thermal annealing process can last from 0 to 10 seconds at a temperature between 900 °C and 1150 °C. In embodiments, the thermal annealing process is a spike (e.g., 0 seconds) at 1000 °C.

[0022] As in Fig. As shown in Figure 8, an insulator or dielectric layer (e.g., an oxide) 20 is deposited over the wafer 12, and in particular over the recrystallized region 12b and the adhesion-rich polysilicon layer 18a, which extends to the surface of the recrystallized region 12b. The layer 20 can be formed by any suitable conventional process, such as separation by implantation of oxygen (SIMOX), deposition, thermal oxidation, and / or any other suitable process.

[0023] Still with reference to Fig.8, the substrate 22 is deposited above the layer 20. The substrate 22 can be a single-crystal silicon or another suitable single-crystal substrate as described herein. In embodiments, the substrate 22 can be bonded directly to the oxide layer 20, e.g., BOX, or it can first be bonded to a separate oxide material, which in turn is bonded to the layer 20 using wafer bonding and / or other suitable methods as described herein. In this way, the wafer is now a silicon-on-insulator (SOI) substrate, with a highly adhesive polysilicon layer 18, 18a beneath and surrounded by the recrystallized region 12b and partially separated from the oxide layer 18 by the recrystallized region 12b.

[0024] The transistors and additional structures described herein can be used in system-on-chip (SoC) technology. It should be clear to those in the know that an SoC is an integrated circuit (also known as a "chip") that integrates all the components of an electronic system onto a single chip or substrate. Because the components are integrated onto a single substrate, SoCs consume far less power and occupy much less space than multi-chip designs with equivalent functionality. For this reason, SoCs are becoming the dominant force in mobile computing (such as in smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0025] The process(s) described above is / are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (that is, as a single wafer containing multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single-chip assembly (such as a plastic substrate with conductors attached to a motherboard or other higher-level support) or in a multi-chip assembly (such as a ceramic substrate having one or both surface interconnects or buried interconnects). In each case, the chip is then integrated with other chips, discrete switching elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) a final product.The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products that feature a display, a keyboard or other input device, and a central processor.

Claims

[1] Structure comprising a semiconductor-on-insulator, SOI, wafer (12) comprising a lower crystalline semiconductor layer (12a), a polysilicon layer (18) above the lower crystalline semiconductor layer (12a), an upper crystalline semiconductor layer (12b) above the polysilicon layer (18), a buried insulator layer (14, 20) above the upper crystalline semiconductor layer (12b), and an uppermost crystalline semiconductor layer (22) above the buried insulator layer (14, 20), wherein the polysilicon layer (18) comprises an extension region (18a) which is surrounded on its sides by the upper crystalline semiconductor layer (12b). [2] Structure according to claim 1, wherein the buried insulator layer (14, 20) is a buried oxide layer, the lower crystalline semiconductor layer (12a) is a single-crystal silicon and the upper crystalline semiconductor layer (12b) is a single-crystal silicon. [3] Structure according to claim 2, wherein the single-crystal silicon is silicon with a high specific resistance. [4] Structure according to claim 3, wherein the resistivity of the silicon is a high resistivity > 1000 Ohm-cm. [5] Structure according to any one of claims 1 to 4, wherein the polysilicon layer (18) is rich in adhesion sites. [6] Structure according to any one of claims 1 to 5, wherein the upper crystalline semiconductor layer (12b) separates the polysilicon layer (18) from the buried insulator layer (14, 20) in a region different from the extent region (18a). [7] Structure according to any one of claims 1 to 6, wherein the lower crystalline semiconductor layer (12a) and the upper crystalline semiconductor layer (12b) is a handle wafer (12) and the polysilicon layer (18) is embedded within the handle wafer (12) between the lower crystalline semiconductor layer (12a) and the upper crystalline semiconductor layer (12b). [8] Structure according to any one of claims 1 to 7, wherein the extension area (18a) extends to a surface of the upper crystalline semiconductor layer (12b) and contacts a section of the buried insulator layer (14, 20). [9] Structure encompassing: a wafer (12) composed of an adhesion-rich polysilicon layer (18) and a single-crystal semiconductor material (12b) over the adhesion-rich polysilicon layer (18); a buried oxide layer (14, 20) on a surface of the single-crystal semiconductor material (12b); and a crystalline semiconductor layer (22) over the buried oxide layer (14, 20), wherein the polysilicon layer (18) comprises an extension area (18a) which is surrounded on its sides by the single-crystal semiconductor material (12b) of the wafer (12). [10] Structure according to claim 9, wherein the single-crystal semiconductor material (12b) isolates the adhesion-rich polysilicon layer (18) from the buried oxide layer (14, 20) in a region different from the extent region (18a). [11] Structure according to claim 9 or claim 10, wherein the crystalline semiconductor layer (22) comprises single-crystal material. [12] Structure according to claim 11, wherein the single-crystal material is a single-crystal Si-based material. [13] Structure according to any one of claims 9 to 12, wherein the wafer (12), the buried oxide layer (14, 20) and the crystalline semiconductor layer (22) are a semiconductor-on-insulator, SOI, technology. [14] Structure according to any one of claims 9 to 13, wherein the wafer is a handle wafer (12) and the adhesion-rich polysilicon layer (18) is embedded within the handle wafer (12). [15] Structure according to any one of claims 9 to 14, wherein single-crystal semiconductor material (12a, 12b) is above and below the adhesion-rich polysilicon layer (18). [16] Structure according to any one of claims 9 to 15, wherein the extension area (18a) of the adhesion-rich polysilicon layer (18) extends to a surface of the single-crystal semiconductor material (12b) above the adhesion-rich polysilicon layer (18) and contacts a section of the buried oxide layer (14, 20). [17] Procedure encompassing: Forming a polysilicon layer with high adhesion sites (18) in a wafer (12) under a single-crystal semiconductor material (12b); Forming an insulating layer (14, 20) over the single-crystal semiconductor material (12b), wherein the single-crystal semiconductor material (12b) provides a separation between the adhesion-rich polysilicon layer (18) and the insulating layer (14, 20); and Formation of a crystalline semiconductor layer (22) over the insulating layer (14, 20), wherein the adhesion-rich polysilicon layer (18) comprises an extension area (18a) which is surrounded on its sides by the single-crystal semiconductor material (12b) of the wafer (12). [18] Method according to claim 17, wherein forming the adhesion-rich polysilicon layer (18) and the single-crystal semiconductor material (12b) over the adhesion-rich polysilicon layer (18) comprises: Amorphizing single-crystal semiconductor material of the wafer to create an amorphous region (16) that has a crystalline layer on its surface, and Performing a rapid thermal annealing process to form the single-crystal semiconductor material (12b) over the adhesion-rich polysilicon layer (18), the crystalline layer acting as a seed crystal for the recrystallization of the amorphous region (16) at the wafer surface. [19] Method according to claim 18, wherein the amorphization is an implant process using an inert gas at a critical dose that prevents recrystallization of the wafer (12), and the rapid thermal annealing process recrystallizes the wafer (12) to form the single-crystal semiconductor material (12b) over the adhesion-rich polysilicon layer (18).

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