MEMORY CELL AND METHOD FOR OPERATING THE SAME

Abstract

Memory cell (102), comprising: a write bit line; a write transistor (M1, M1') coupled between the write bit line and a first node (ND1); and a read transistor (M2, M2') which is coupled to the write transistor (M1, M1') via the first node (ND1); wherein the read transistor (M2, M2') has a ferroelectric layer (202, 520) and the write transistor (M1, M1') is designed to set a stored data value of the memory cell (102) by means of a write bit line signal which sets a polarization state of the read transistor, wherein the polarization state corresponds to the stored data value; where the write transistor (M1, M1') has: a first drain terminal that is coupled to the write bit line; a first source terminal coupled to the first node (ND1) and the read transistor (M2, M2'); and a first gate connection that is coupled to a write word line; where the read transistor (M2, M2') has: a second drain connection coupled to a second node; a second source port that is coupled to a third node; and a second gate terminal on the ferroelectric layer (202, 520) which is coupled to the first source terminal via the first node (ND1); wherein the memory cell (102) further comprises: a first transistor (M3, M3') coupled to the read transistor (M2, M2'), wherein the first transistor has: a third drain port that is coupled to the second source port via the third node; a third source port coupled with a read bit line; and a third gate connector; wherein the second drain terminal is coupled to a reference voltage supply via the second node; and the third gate connection is coupled with a read word line; and wherein the memory cell (102) further comprises: a second transistor (M4, M4') coupled via the first node (ND1) to the read transistor (M2, M2') and the write transistor (M1, M1'), the second transistor comprising: a fourth drain connection that is coupled to the read word line; a fourth source port coupled to a fourth node (ND2); and a fourth gate connection, which is coupled via the first node (ND1) to the first source connection and the second gate connection.

Description

BACKGROUND

[0001] The integrated circuit (IC) industry has produced a wide variety of digital devices to solve problems in a range of different fields. Some of these digital devices, such as memory macros, are designed for data storage. As ICs have become smaller and more complex, the resistance of the traces within these digital devices also changes, affecting the operating voltages of these digital devices and the overall performance of the ICs.

[0002] US 2013 / 0077397A1 describes a two-transistor DRAM with at least one memory cell. The memory cell contains a write transistor and a read transistor. The write transistor is connected to a bit line via one of its source / drain terminals, to the gate of the read transistor via the other source / drain terminal, and to a write word line (WWL) via the gate. The read transistor is a conventional MOSFET. Unlike the write transistor, the read transistor has a threshold-modulating layer in its gate structure. The threshold-modulating layer comprises a layer of ferroelectric material.

[0003] CN 110 415 744 A describes a non-volatile memory based on a ferroelectric transistor. A circuit unit consists of two or three transistors, and multiple units can be combined in an array layout with multiple rows and columns in an electrical interconnect mode. The memory's read / write operation utilizes the hysteresis characteristic of the drain-source current versus gate voltage of the ferroelectric transistor.

[0004] US 2018 / 0366476A1 describes a ferroelectric field-effect transistor. Within the ferroelectric field-effect transistor, a semiconductor substrate, a dielectric layer, a polarity-maintaining layer, and a conductive layer are sequentially fabricated. The polarity-maintaining layer comprises a ferroelectric and an antiferroelectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been enlarged or reduced arbitrarily for the sake of clarity. Fig. Figure 1 is a block diagram of a memory cell arrangement according to some embodiments. Fig. 2A is a circuit diagram of a memory cell according to some embodiments. Fig. 2B is a circuit diagram of a memory cell according to some embodiments. Fig. 2C is a circuit diagram of a memory cell according to some embodiments. Fig. 3A is a circuit diagram of a memory cell according to some embodiments. Fig. 3B is a circuit diagram of a memory cell according to some embodiments. Fig. 3C is a circuit diagram of a memory cell according to some embodiments. Fig. 4A is a circuit diagram of a memory cell according to some embodiments. Fig. 4B is a circuit diagram of a memory cell according to some embodiments. Fig. 4C is a circuit diagram of a memory cell according to some embodiments. Fig. Figure 5 is a cross-sectional view of an integrated circuit according to some embodiments. Fig. Figure 6 is a flowchart of a method for manufacturing an integrated circuit according to some embodiments. Fig. Figure 7 is a flowchart of a method for operating a circuit according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides various embodiments or examples for implementing the features of the invention. Specific examples of components, materials, values, steps, arrangements, or the like are described below to simplify the present disclosure. These are, of course, only examples. Other components, materials, values, steps, arrangements, or the like are also considered. For example, the formation of a first feature above or on top of a second feature in the description below may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which further features between the first and second features may be formed such that the first and second features may not be in direct contact.Furthermore, reference numbers and / or letters may be repeated in the various examples in this disclosure. This repetition is intended for the sake of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatial terms such as "under," "below," "lower," "above," "upper," and the like may be used here to facilitate description and to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatial terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatial descriptions in this patent specification may be interpreted accordingly.

[0008] According to some embodiments, a memory cell comprises a write bit line, a write transistor, and a read transistor. The write transistor is coupled between the write bit line and a first node. The read transistor is coupled to the write transistor via the first node. The write transistor is configured to set a stored data value of the memory cell by means of a write word line signal that establishes a polarization state of the read transistor. In some embodiments, the polarization state corresponds to the stored data value of the memory cell.

[0009] In some embodiments, the read transistor has a first gate terminal coupled to the write transistor via the first node, and a ferroelectric region with a polarization state corresponding to a stored data value of the memory cell.

[0010] In some embodiments, the memory cell exhibits less charge loss at the first node compared to other approaches due to the use of the ferroelectric region. In some embodiments, the ferroelectric region is able to maintain its polarization state even after the voltage at the first node has been removed, resulting in a longer data retention time and a larger memory window than other approaches. In some embodiments, the memory cell, due to its longer data retention time or larger memory window, requires less frequent refreshing than other approaches, leading to lower power consumption.

[0011] Fig. Figure 1 is a block diagram of a memory cell arrangement 100 according to some embodiments. In some embodiments, the memory cell arrangement 100 is part of an integrated circuit.

[0012] The memory cell arrangement 100 comprises an arrangement of memory cells 102[1,1], 102[1,2], ..., 102[2,2], ..., 102[M,N] (collectively referred to as "arrangement of memory cells 102A") with M rows and N columns, where N is a positive integer corresponding to the number of columns in the arrangement of memory cells 102A, and M is a positive integer corresponding to the number of rows in the arrangement of memory cells 102A. The rows of cells in the arrangement of memory cells 102A are arranged in a first direction X. The columns of cells in the arrangement of memory cells 102A are arranged in a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. Each memory cell 102[1,1], 102[1,2], ..., 102[2,2], ..., 102[M,N] in the arrangement of memory cells 102A is designed to store a corresponding bit of data.

[0013] The 102A array of memory cells is a dynamic random-access memory (DRAM) array with DRAM-like memory cells. In some embodiments, each memory cell in the 102A array corresponds to a memory cell with two transistors (2T) and one ferroelectric field-effect transistor (FeFET), as shown in Fig. 2A-2C shown. In some embodiments, each memory cell in the arrangement of memory cells 102A corresponds to a memory cell with three transistors (3T) with a FeFET, as shown in Fig. 3A-3C shown. In some embodiments, each memory cell in the arrangement of memory cells 102A corresponds to a memory cell with four transistors (4T) with one FeFET, as shown in Fig. 4A-4C shown.

[0014] Further embodiments include various types of memory cells in the arrangement of memory cells 102A. For example, in some embodiments, each memory cell in the arrangement of memory cells 102A is a static random access memory (SRAM). In some embodiments, each memory cell in the arrangement of memory cells 102A corresponds to a ferroelectric resistive random access memory cell (FeRAM cell). In some embodiments, each memory cell in the arrangement of memory cells 102A corresponds to a magneto-resistive random access memory cell (MRAM cell). In some embodiments, each memory cell in the arrangement of memory cells 102A corresponds to a resistive random access memory cell (RRAM cell). Further configurations of the arrangement of memory cells 102A are possible.

[0015] The memory cell arrangement 100 further comprises M write word lines WWL[1], ... WWL[M] (collectively referred to as "write word line WWL"). Each row 1, ..., M in the arrangement of memory cells 102A is linked to a corresponding write word line WWL[1], ..., WWL[M]. Each row of memory cells in the arrangement of memory cells 102A is coupled to a corresponding write word line WWL[1], ..., WWL[M]. For example, the memory cells 102[1,1], 102[1,2], ..., 102[1,N] in row 1 are coupled to the write word line WWL[1]. Each write word line WWL extends in the first direction X.

[0016] The memory cell arrangement 100 further comprises M read word lines RWL[1], ... RWL[M] (collectively referred to as "read word line RWL"). Each row 1, ..., M in the arrangement of memory cells 102A is linked to a corresponding read word line RWL[1], ..., RWL[M]. Each row of memory cells in the arrangement of memory cells 102A is coupled to a corresponding read word line RWL[1], ..., RWL[M]. For example, memory cells 102[1,1], 102[1,2], ..., 102[1,N] in row 1 are coupled to the read word line RWL[1]. Each read word line RWL extends in the first direction X.

[0017] The memory cell array 100 further comprises N write bit lines WBL[1], ... WBL[N] (collectively referred to as "write bit line WBL"). Each column 1, ..., N in the array of memory cells 102A is linked to a corresponding write bit line WBL[1], ..., WBL[N]. Each column of memory cells in the array of memory cells 102A is linked to a corresponding write bit line WBL[1], ..., WBL[N]. For example, memory cells 102[1,1], 102[2,1], ..., 102[M,1] in column 1 are linked to write bit line WBL[1]. Each write bit line WBL extends in the second direction Y.

[0018] The memory cell array 100 further comprises N read bit lines RBL[1], ... RBL[N] (collectively referred to as "read bit line RBL"). Each column 1, ..., N in the array of memory cells 102A is linked to a corresponding read bit line RBL[1], ..., RBL[N]. Each column of memory cells in the array of memory cells 102A is linked to a corresponding read bit line RBL[1], ..., RBL[N]. For example, memory cells 102[1,1], 102[2,1], ..., 102[M,1] in column 1 are linked to the read bit line RBL[1]. Each read bit line RBL extends in the second direction Y.

[0019] Further embodiments include further configurations of the memory cell arrangement 100. These further embodiments include various configurations of at least write bit lines WBL, write word lines WWL, read bit lines RBL, or read word lines RWL in the memory cell arrangement 100. In some embodiments, the memory cell arrangement 100 has additional write connections (write word lines WWL or write bit lines WBL) and / or read connections (read word lines RWL or read bit lines RBL). Furthermore, in some embodiments, the arrangement of memory cells 102A has several groups of different memory cell types.

[0020] As an illustrative example, a write operation is performed in memory cell 102[1,1], which is located in row 1 and column 1 of the array of memory cells 102A. Row 1 contains the memory cells 102[1,1], 102[1,2], ..., 102[1,N], which are selected by the write word line WWL[1]. Column 1 contains the memory cells 102[1,1], 102[2,1], ..., 102[M,1], which are selected by the write bit line WBL[1] to receive a data signal and store a binary data bit. Together, the write word line WWL[1] and the write bit line WBL[1] select a binary data bit and store it in memory cell 102[1,1].

[0021] As an illustrative example, a read operation is performed on memory cell 102[1,1], which is located in row 1 and column 1 of the array of memory cells 102A. Row 1 contains memory cells 102[1,1], 102[1,2], ..., 102[1,N], which are selected by the read word line RWL[1]. Column 1 contains memory cells 102[1,1], 102[2,1], ..., 102[M,1], which are selected by the read bit line RBL[1] to access the stored binary data bit. Together, the read word line RWL[1] and the read bit line RBL[1] select the binary data bit stored in memory cell 102[1,1].

[0022] Fig. 2A is a circuit diagram of a 200A memory cell according to some embodiments.

[0023] The memory cell 200A is an embodiment of a memory cell in the arrangement of memory cells 102A of Fig. 1 in a schematic representation, therefore a similarly detailed description is omitted.

[0024] Components that meet the criteria in one or more of the Fig. Components 2A-2C, 3A-3C, and 4A-4C (see below) that are identical or similar receive the same reference numbers, and a detailed description of these components is omitted. For better illustration, some of the labeled elements are shown in Fig. 2A-2C, 3A-3C, 4A-4C not in every one of the Fig. labelled 2A-2C, 3A-3C, 4A-4C. In some embodiments, the Fig. 2A-2C, 3A-3C, 4A-4C additional elements that are in Fig. 2A-2C, 3A-3C, 4A-4C are not shown.

[0025] The 200A memory cell is configured as one or more memory cells in the arrangement of 102A memory cells. Fig. 1 usable.

[0026] The memory cell 200A has a write transistor M1, a read transistor M2, a write word line WWL, a read word line RWL, a write bit line WBL and a read bit line RBL.

[0027] The write word line WWL corresponds to a write word line of the write word lines WWL[1], ..., WWL[[M], the read word line RWL corresponds to a read word line of the read word lines RWL[1], ..., RWL[[M], the write bit line WBL corresponds to a write bit line of the write bit lines WBL[1], ..., WBL[[N] and the read bit line RBL corresponds to a read bit line of the read bit lines RBL[1], ..., RBL[[N] of Fig. 1, therefore a similarly detailed description is omitted.

[0028] Write transistor M1 has: a gate terminal coupled to write word line WWL, a drain terminal coupled to write bit line WBL, and a source terminal coupled via node ND1 to at least one gate terminal of read transistor M2. Write transistor M1 is designed to write data to memory cell 200A. Write transistor M1 is activated (e.g., turned on) or deactivated (e.g., turned off) in response to a write bit line signal on write bit line WBL.

[0029] The writing transistor M1 is shown as a P-type metal-oxide-semiconductor transistor (PMOS transistor). In some embodiments, the writing transistor M1 is an N-type metal-oxide-semiconductor transistor (NMOS transistor).

[0030] The read transistor M2 has: a drain terminal coupled to read word line RWL, a source terminal coupled to read bit line RBL and a gate terminal coupled to the source terminal of write transistor M1.

[0031] The read transistor M2 is referred to as a ferroelectric field-effect transistor (FeFET) because it has a ferroelectric region 202 located within its gate terminal. This region is designed to exhibit different polarization states depending on the voltage applied to the gate. The polarization of this region determines the conductance (e.g., low-resistance or high-resistance) of read transistor M2, which represents the data stored within it.

[0032] The data is stored by programming the ferroelectric region 202 to different polarization states. The different polarization states generate two distinct threshold voltage states (e.g., Vth), corresponding to a logic "1" and a logic "0". Due to the threshold voltage difference, the ferroelectric region 202 in the read transistor M2 is configured to use specific gate voltages, based on its logic state, to turn on. In some embodiments, the difference between these gate voltages is referred to as the memory window.

[0033] The binary states of the stored data in memory cell 200A are encoded in the form of the polarization of the ferroelectric region 202. The direction or value of the polarization (e.g., +P or -P) of the ferroelectric region 202 determines the resistance state (e.g., low or high) of the read transistor M2. In some embodiments, a low-resistance state of the read transistor M2 corresponds to the on-switched or conducting state of the read transistor M2, and a high-resistance state of the read transistor M2 corresponds to the off-switched or non-conducting state of the read transistor M2. In some embodiments, a low-resistance state of the read transistor M2 corresponds to a first stored value (e.g., logic "0" or "1"), and a high-resistance state of the read transistor M2 corresponds to a second stored value (e.g., logic "1" or "0") that is opposite to the first stored value.A voltage from the gate of read transistor M2 or the node ND1 controls the polarization states and the corresponding electric field in the ferroelectric region 202 of read transistor M2.

[0034] The write transistor M1 is designed to write data by controlling the voltage of node ND1 or the gate of read transistor M2, thereby controlling the polarization states of the ferroelectric region 202 of read transistor M2. In some embodiments, when the write transistor M1 is activated or turned on, a voltage on the write bit line WBL is designed to control the voltage of node ND1 or the gate of read transistor M2. Thus, in some embodiments, the polarization state of the ferroelectric region 202 is controlled by the voltage on the write bit line WBL. In some embodiments, the voltage on the write bit line WBL corresponds to the data stored in memory cell 200A.In some embodiments, the polarization state of the ferroelectric region 202 is retained even after an electric field or corresponding voltage has been removed from node ND1, and the read transistor M2 is a non-volatile transistor device.

[0035] The read transistor M2 is designed to read data stored in memory cell 200A. In some embodiments, the read transistor M2 is designed to output data stored in memory cell 200A, based on whether the read transistor M2 is switched on or off. The polarization state of the ferroelectric region 202 determines whether the read transistor M2 is switched on or off.

[0036] In some embodiments, write transistor M1 and read transistor M2 each have channel regions formed from the same type of material. In some embodiments, write transistor M1 and read transistor M2 each have channel regions comprising a silicon body or mass.

[0037] The read transistor M2 is shown as a PMOS transistor. In some embodiments, the read transistor M2 is an NMOS transistor.

[0038] During a write operation of memory cell 200A, the voltage of the write bit line WBL (e.g., data to be stored in memory cell 200A) is set by a write driver circuit (not shown), and the write word line WWL is set to a logic low (low), thereby turning on the write transistor M1. In response to the turn-on of the write transistor M1, the voltage of the write bit line WBL is applied to the gate of read transistor M2 or node ND1. When the voltage of the write bit line WBL is applied to the gate of read transistor M2 or node ND1, the write bit line voltage controls the polarization state of the ferroelectric region 202 and the corresponding data stored by read transistor M2. In other words, the voltage of the write bit line WBL is used to switch the read transistor M2 into a low-impedance state (e.g., conducting) or a high-impedance state (e.g., switched off).to switch the non-conducting transistor. Afterwards, the write word line WWL is set to a logically high value (High), thus switching off the write transistor M1.

[0039] In response to the switching off of the write transistor M1, the stored data in memory cell 200A is held, and memory cell 200A is in a hold mode.

[0040] By using the ferroelectric region 202 in the memory cell 200A, the memory cell 200A exhibits no charge losses at node ND1 compared to other approaches (such as DRAM). Due to the non-volatile nature of the ferroelectric material, the ferroelectric region 202 in the memory cell 200A is able to maintain its polarization state even after the voltage at node ND1 is removed, resulting in a longer data retention time and a larger memory window than other approaches. Because it offers at least a longer data retention time or a larger memory window than other approaches, the memory cell 200A requires less frequent refreshing, leading to lower power consumption.

[0041] In some embodiments, the memory cell 200A and the memory cells 200B-200C ( Fig. 2B-2C) a 2T memory cell structure that is compatible with complementary metal oxide semiconductor processes (CMOS processes, Complementary Metal Oxide Semiconductor) and therefore scalable.

[0042] During a read operation of memory cell 200A, the voltage of the read bit line RBL is pre-discharged to a logic low (Low), and the read word line RWL is raised to a logic high (High). In some embodiments, when the read transistor M2 is in a low-impedance state, the read transistor M2 is turned on or conducting, and the current from the read word line RWL through the read transistor M2 to the read bit line RBL is detected by a read amplifier (not shown), and the data associated with the read transistor M2 in the low-impedance state (e.g., "1" or "0") is read.In some embodiments, when the read transistor M2 is in a high-impedance state, the read transistor M2 is switched off or non-conducting, and the current from the read word line RWL through the read transistor M2 to the read bit line RBL is detected by a read amplifier (not shown), and the data associated with the read transistor M2 in the high-impedance state (e.g., "0" or "1") is read. In this embodiment, the current through the read transistor M2 is negligible because the read transistor M2 is switched off. Subsequently, the read word line RWL is set to a logic low (low).

[0043] Further embodiments include additional transistor connections for each of the transistors M1, M2, M1', or M2' (described below) of the present patent application. For example, a reference to drains and sources of one and the same transistor in the present disclosure can be changed to source and drain of the same transistor. Thus, for the write transistor M1, the reference to drain and source of write transistor M1 can be changed to source and drain of write transistor M1, respectively. Similarly, for the read transistor M2, the reference to drain and source of read transistor M2 can be changed to source and drain of read transistor M2, respectively.

[0044] Other embodiments include further configurations or quantities of transistors in the 200A memory cell.

[0045] Fig. 2B is a circuit diagram of a 200B memory cell according to some embodiments.

[0046] The memory cell 200B is an embodiment of a memory cell in the arrangement of memory cells 102A of Fig. 1 in a schematic representation, therefore a similarly detailed description is omitted.

[0047] The memory cell 200B is configured as one or more memory cells in the arrangement of memory cells 102A of Fig. 1 usable. The memory cell 200B has a write transistor M1', a read transistor M2, a write word line WWL, a read word line RWL, a write bit line WBL and a read bit line RBL.

[0048] The 200B memory cell is a variant of the 200A memory cell from Fig. 2A, therefore a similarly detailed description is omitted. Compared to the 200A memory cell from Fig. 2A the write transistor M1' replaces the write transistor M1 from Fig. 2A, therefore a similarly detailed description is omitted.

[0049] The write transistor M1' is shown as a PMOS transistor. In some embodiments, the write transistor M1' is an NMOS transistor. In some embodiments, the write transistor M1' resembles the write transistor M1 of Fig. 2A, therefore a similarly detailed description is omitted. The operation of memory cell 200B is similar to the operation of memory cell 200A described above, therefore a similarly detailed description is omitted.

[0050] In comparison to the M1 write transistor from Fig. In 2A, the write transistor M1' has an oxide channel region 210; therefore, a similarly detailed description is omitted. In some embodiments, one or more transistors with oxide channel regions of the present disclosure comprise thin-film transistors (TFTs). In some embodiments, the oxide channel region 210 for the write transistor M1' comprises an oxide semiconductor material containing zinc oxide, cadmium oxide, indium oxide, IGZO, SnO2, TiO2, or combinations thereof, or the like. Further embodiments include other transistor types or oxide materials for the write transistor M1'.

[0051] In some embodiments, the memory cell 200B, by incorporating the write transistor M1' with an oxide channel region 210 and a FeFET read transistor M2, exhibits a lower leakage current than other approaches that lack an oxide channel region in the write transistor. In some embodiments, the reduced leakage current of the memory cell 200B results in a longer data retention time than other approaches. This longer data retention time means that the memory cell 200A is refreshed less frequently than in other approaches, leading to lower power consumption. In some embodiments, the reduced leakage current of the memory cell 200B also results in fewer write errors than other approaches.Furthermore, since memory cell 200B is similar to memory cell 200A, memory cell 200B also has the advantages described above with respect to memory cell 200A. In some embodiments, the oxide channel region 210, 220, 230 or 240 of memory cell 200B-200C, 300B-300C and 400B-400C ( Fig. 2B-2C, 3B-3C & 4B-4C) are integrated into a back-end-of-line process (BEOL process), thereby increasing the storage density of the 200B-200C, 300B-300C and 400B-400C memory cells.

[0052] Other embodiments include further configurations, connections or quantities of transistors in the 200B memory cell.

[0053] Fig. 2C is a circuit diagram of a 200C memory cell according to some embodiments.

[0054] The memory cell 200C is an embodiment of a memory cell in the arrangement of memory cells 102A of Fig. 1 in a schematic representation, therefore a similarly detailed description is omitted.

[0055] The memory cell 200C is configured as one or more memory cells in the arrangement of memory cells 102A of Fig. 1 usable. The memory cell 200C has a write transistor M1', a read transistor M2', a write word line WWL, a read word line RWL, a write bit line WBL and a read bit line RBL.

[0056] The 200C memory cell is a variant of the 200B memory cell from Fig. 2B, therefore a similarly detailed description is omitted. Compared to the 200B memory cell of Fig. 2B, the write transistor M2' replaces the write transistor M2 of Fig. 2B, therefore a similarly detailed description is omitted.

[0057] The read transistor M2' is shown as a PMOS transistor. In some embodiments, the read transistor M2' is an NMOS transistor. In some embodiments, the read transistor M2' resembles the read transistor M2 of Fig. 2A-2B, therefore a similarly detailed description is omitted. The operation of memory cell 200C is similar to the operation of memory cell 200A or memory cell 200B (described above), therefore a similarly detailed description is omitted.

[0058] In comparison to the write transistor M2 of Fig. In 2B, the write transistor M2' has an oxide channel region 220; therefore, a similarly detailed description is omitted. In some embodiments, the oxide channel region 220 for the read transistor M2' contains an oxide semiconductor material comprising zinc oxide, cadmium oxide, indium oxide, IGZO, SnO2, TiO2, or combinations thereof, or the like.

[0059] In some embodiments, the oxide channel region 220 of read transistor M2' contains the same oxide semiconductor material as the oxide channel region 210 of write transistor M1'. In other embodiments, the oxide channel region 220 of read transistor M2' contains a different oxide semiconductor material than the oxide channel region 210 of write transistor M1'. Further embodiments include additional transistor types or oxide materials for the read transistor M2'.

[0060] In some embodiments, the read transistor M2' has an oxide channel region 220, and the write transistor M1' has a silicon channel region with a silicon body or mass similar to the write transistor M1.

[0061] In some embodiments, the memory cell 200C exhibits a lower leakage current than other read transistor approaches because it incorporates the write transistor M1' with an oxide channel region 210 and the read transistor M2' with an oxide channel region 220 and as a FeFET. In some embodiments, the reduction in leakage current allows the memory cell 200C to offer the advantages discussed above with respect to the memory cell 200B. Furthermore, since the memory cell 200C is similar to the memory cell 200A, it also offers the advantages described above with respect to the memory cell 200A.

[0062] Other embodiments include further configurations, connections, or quantities of transistors in the 200C memory cell.

[0063] Fig. 3A is a circuit diagram of a 300A memory cell according to some embodiments.

[0064] The memory cell 300A is an embodiment of a memory cell in the arrangement of memory cells 102A of Fig. 1 in a schematic representation, therefore a similarly detailed description is omitted.

[0065] The 300A memory cell is available as one or more memory cells in the arrangement of 102A memory cells. Fig. 1 usable. The 300A memory cell has the write transistor M1, the read transistor M2, the write word line WWL, the read word line RWL, the write bit line WBL, the read bit line RBL and a transistor M3.

[0066] The 300A memory cell is a variant of the 200A memory cell from Fig. 2A, therefore a similarly detailed description is omitted. Compared to the 200A memory cell from Fig. The 2A memory cell 300A also features the write transistor M3, therefore a similarly detailed description is omitted.

[0067] Transistor M3 has: a source terminal coupled to the read bit line RBL, a drain terminal coupled to the source terminal of read transistor M2, and a gate terminal configured to receive a control signal CS. In some embodiments, transistor M3 is turned on or off in response to the control signal CS. In some embodiments, during a read operation of a selected memory cell, similar to memory cell 300A, contains a selected transistor M3, and unselected memory cells, similar to memory cell 300A, contain an unselected transistor M3. In these embodiments, the selected transistor M3 is turned on in response to a first value of the control signal CS, and the unselected transistors M3 in the corresponding unselected cells are turned off in response to a second value of the control signal CS.In these embodiments, the second value of the control signal CS is the inverse of the first value of the control signal CS. In these embodiments, the transistors M3 in unselected memory cells are switched off, thereby reducing the leakage current.

[0068] Compared to the 200A memory cell from Fig. 2A is the source terminal of read transistor M2 of Fig. 3A-3C is coupled to the drain terminal of transistor M3 and therefore not directly coupled to the read bit line RBL, as shown in Fig. 2A is shown.

[0069] The transistor M3 from Fig. 3A-3B is activated or deactivated in response to a control signal CS. Transistor M3 is designed to electrically couple or decouple read transistor M2 from the read bit line RBL in response to the control signal CS. For example, when the control signal CS is logic low, transistor M3 is activated, and transistor M3 electrically couples the source of read transistor M2 to the read bit line RBL. For example, when the control signal CS is logic high, transistor M3 is deactivated, and transistor M3 electrically decouples the source of read transistor M2 from the read bit line RBL.

[0070] The operation of the 300A memory cell is similar to the operation of the 200A memory cell described above; therefore, a similarly detailed description is omitted. For example, compared to the write operation of the 200A memory cell... Fig. During the write operation of memory cell 300A, transistor M3 is deactivated or switched off, and the operation of the other parts of memory cell 300A is similar to the write operation of memory cell 200A described above; therefore, a similarly detailed description is omitted. For example, compared to the read operation of memory cell 200A, Fig. During the read operation of memory cell 300A, transistor M3 is activated or switched on, and the operation of the other parts of memory cell 300A is similar to the read operation of memory cell 200A described above, therefore a similarly detailed description is omitted.

[0071] Transistor M3 is shown as a PMOS transistor. In some embodiments, transistor M3 is an NMOS transistor.

[0072] In some embodiments, transistor M3 and at least the write transistor M1 or the read transistor M2 have channel regions formed from the same type of material. In some embodiments, transistor M3 has a channel region comprising a silicon body or mass. In some embodiments, transistor M3 and at least the write transistor M1 or the read transistor M2 have channel regions comprising a silicon body or mass.

[0073] In some embodiments, the 300A memory cell resembles the 200A memory cell in that it includes the write transistor M1, the read transistor M2 (e.g., FeFET), and the transistor M3. In some embodiments, because the 300A memory cell is similar to the 200A memory cell, the 300A memory cell has the advantages described above in relation to the 200A memory cell.

[0074] In some embodiments, the memory cell 300A and the memory cells 300B-300C ( Fig. 3B-3C) a 3T memory cell structure that is compatible with CMOS processes and therefore scalable.

[0075] Further embodiments include additional transistor connections for each of the transistors M1, M2, M3, M1', M2' and M3' of the present patent application. For example, a reference to drains and sources of one and the same transistor in the present disclosure can be changed to source and drain of the same transistor.

[0076] Other embodiments include further configurations or quantities of transistors in the 300A memory cell.

[0077] Fig. 3B is a circuit diagram of a 300B memory cell according to some embodiments.

[0078] The memory cell 300B is an embodiment of a memory cell in the arrangement of memory cells 102A of Fig. 1 in a schematic representation, therefore a similarly detailed description is omitted.

[0079] The memory cell 300B is configured as one or more memory cells in the arrangement of memory cells 102A of Fig. 1 usable. The memory cell 300B has the write transistor M1', the read transistor M2, the write word line WWL, the read word line RWL, the write bit line WBL, the read bit line RBL and the transistor M3.

[0080] The 300B memory cell is a variant of the 300A memory cell from Fig. 3A and the memory cell 200B of Fig. 2B, therefore a similarly detailed description is omitted. For example, the 300B memory cell combines similar features to the 300A memory cell from Fig. 3A and the memory cell 200B of Fig. 2B.

[0081] Compared to the 300A memory cell from Fig. 3A replaces the write transistor M1' of Fig. 2B the write transistor M1 from Fig. 3A, therefore a similarly detailed description is omitted.

[0082] The write transistor M1' is located in memory cell 200B of Fig. The operation of memory cell 300B is described above, therefore a similarly detailed description is omitted. The write transistor M1' is shown as a PMOS transistor. In some embodiments, the write transistor M1' is an NMOS transistor. The operation of memory cell 300B is similar to the operation of memory cell 300A described above, therefore a similarly detailed description is omitted.

[0083] In some embodiments, the memory cell 300B achieves similar advantages to those discussed above with respect to memory cell 300A and memory cell 200B by having the write transistor M1' with an oxide channel region 210, the read transistor M2 (e.g. FeFET) and the transistor M3.

[0084] Furthermore, since the 300B memory cell is similar to the 200A memory cell, the 300B memory cell also has the advantages described above in relation to the 200A memory cell.

[0085] Other embodiments include further configurations, connections or quantities of transistors in the 300B memory cell.

[0086] Fig. 3C is a circuit diagram of a 300C memory cell according to some embodiments.

[0087] The memory cell 300C is an embodiment of a memory cell in the arrangement of memory cells 102A of Fig. 1 in a schematic representation, therefore a similarly detailed description is omitted.

[0088] The 300C memory cell is configured as one or more memory cells in the arrangement of 102A memory cells. Fig. 1 usable. The memory cell 300C has the write transistor M1', the read transistor M2', the write word line WWL, the read word line RWL, the write bit line WBL, the read bit line RBL and a transistor M3'.

[0089] The 300C memory cell is a variant of the 300B memory cell from Fig. 3B, therefore a similarly detailed description is omitted. Compared to the 300B memory cell of Fig. 3B, the read transistor M2' replaces the read transistor M2 of Fig. 3B and transistor M3' replaces transistor M3 from Fig. 3B, therefore a similarly detailed description is omitted.

[0090] The read transistor M2' is located in memory cell 200C of Fig. Section 2C describes this, therefore a similarly detailed description is omitted. The read transistor M2' is shown as a PMOS transistor. In some embodiments, the read transistor M2' is an NMOS transistor.

[0091] Transistor M3' is shown as a PMOS transistor. In some embodiments, transistor M3' is an NMOS transistor. In some embodiments, transistor M3' resembles transistor M3 of Fig. 3A-3B, therefore a similarly detailed description is omitted. The operation of the 300C memory cell is similar to the operation of the 300A or 300B memory cells (described above), therefore a similarly detailed description is omitted.

[0092] Compared to the transistor M3 from Fig. In 3B, transistor M3' has an oxide channel region 230; therefore, a similarly detailed description is omitted. In some embodiments, the oxide channel region 230 for transistor M3' contains an oxide semiconductor material comprising zinc oxide, cadmium oxide, indium oxide, IGZO, SnO2, TiO2, or combinations thereof, or the like.

[0093] In some embodiments, the oxide channel region 230 of transistor M3' contains the same oxide semiconductor material as the oxide channel regions 210, 220 of at least one write transistor M1' or one read transistor M2'. In some embodiments, the oxide channel region 230 of transistor M3' contains a different oxide semiconductor material than the oxide channel regions 210, 220 of at least one write transistor M1' or one read transistor M2'. Further embodiments include additional transistor types or oxide materials for transistor M3'.

[0094] In some embodiments, either the read transistor M2' or the transistor M3' has an oxide channel region 220 or 230, and the other of read transistor M2' and transistor M3' has a silicon channel region with a silicon body or mass similar to the read transistor M2 or transistor M3, respectively.

[0095] In some embodiments, the memory cell 300C achieves similar advantages to those discussed above with respect to memory cell 300A and memory cell 200C by incorporating the write transistor M1' with an oxide channel region 210, the read transistor M2' with an oxide channel region 220 and as a FeFET, and the transistor M3' with an oxide channel region 230. Furthermore, since the memory cell 300C is similar to the memory cell 200A, it also possesses the advantages described above with respect to the memory cell 200A.

[0096] Other embodiments include further configurations, connections, or quantities of transistors in the 300C memory cell.

[0097] Fig. 4A is a circuit diagram of a 400A memory cell according to some embodiments.

[0098] The memory cell 400A is an embodiment of a memory cell in the arrangement of memory cells 102A of Fig. 1 in a schematic representation, therefore a similarly detailed description is omitted.

[0099] The 400A memory cell is configured as one or more memory cells in the arrangement of 102A memory cells. Fig. 1 usable. The 400A memory cell has the write transistor M1, the read transistor M2, the write word line WWL, the read word line RWL, the write bit line WBL, the read bit line RBL, the transistor M3 and the transistor M4.

[0100] The 400A memory cell is a variant of the 300A memory cell from Fig. 3A, therefore a similarly detailed description is omitted. Compared to the 300A memory cell from Fig. The 400A memory cell also features transistor M4 (3A), therefore a similarly detailed description is omitted.

[0101] Transistor M4 has a drain terminal, a gate terminal, and a source terminal. The drain terminal of transistor M4 is coupled to the read / write line RWL. The gate terminal of transistor M4 is coupled to the drain terminal of write transistor M1, the gate terminal of read transistor M2, and node ND1. The source terminal of transistor M4 is coupled to node ND2. In some embodiments, node ND2 is electrically coupled to a reference voltage supply. In some embodiments, the reference voltage supply has a reference voltage VSS. In some embodiments, the reference voltage supply is ground.

[0102] The M4 transistor from Fig. 4A-4C is enabled or disabled in response to a voltage from node ND1. In some embodiments, the voltage of node ND1 corresponds to the write bit line signal, and thus transistor M4 is enabled by Fig. 4A-4C are enabled or disabled in response to the write bit line signal.

[0103] The M4 transistor from Fig. 4A-4C is designed to couple or decouple the read word line (RWL) with node ND2 in response to the write bit line signal on the write bit line (WBL). For example, when the write bit line signal is logic low (Low), transistor M4 is activated, and transistor M4 electrically couples the read word line (RWL) to node ND2. Conversely, when the write bit line signal is logic high (High), transistor M4 is deactivated, and transistor M4 electrically decouples the read word line (RWL) from node ND2.

[0104] Compared to the 300A memory cell from Fig. 3A is the drain terminal of read transistor M2 of Fig. 4A-4C is coupled to a reference voltage supply. In some embodiments, the reference voltage supply has a reference voltage VSS. In some embodiments, the reference voltage supply corresponds to ground.

[0105] Compared to the 300A memory cell from Fig. 3A is the gate terminal of transistor M3. Fig. 4A-4C is coupled to the read word line RWL. The transistor M3 of Fig. 4A-4C is activated or deactivated in response to a read word line signal on the read word line (RWL). Transistor M3 of Fig. The 4A-4C is designed to electrically couple or decouple the read transistor M2 from the read bit line RBL in response to the read word line signal on the read word line RWL. For example, when the read word line signal is logic low (Low), transistor M3 is activated, and transistor M3 electrically couples the source of read transistor M2 to the read bit line RBL. Conversely, when the read word line signal is logic high (High), transistor M3 is deactivated, and transistor M3 electrically decouples the source of read transistor M2 from the read bit line RBL.

[0106] The operation of the 400A memory cell is similar to the operation of the 200A memory cell described above; therefore, a similarly detailed description is omitted. For example, compared to the write operation of the 200A memory cell... Fig. 2A and the 300A storage cell from Fig. During the write operation of memory cell 400A, transistor M4 is activated or deactivated in response to the write bit line signal on the write bit line WBL, transistor M3 is activated or deactivated in response to the read word line signal on the read word line RWL, and the operation of the other parts of memory cell 400A is similar to the write operation of memory cell 200A described above, therefore a similarly detailed description is omitted.

[0107] During a read operation of memory cell 400A, the voltage of the read bit line RBL is precharged to a logic high value (high) and the read word line RWL is reduced to a logic low value (low), thereby activating or turning on transistor M3. In some embodiments, when the read transistor M2 moves from Fig. 4A-4C M2 is in a low-impedance state, the read transistor M2 is switched on or conducting, and the voltage of the read word line RBL is pulled through the read transistor M2 to VSS, and the voltage or current of the read bit line RBL is detected by a read amplifier (not shown), and the data associated with the read transistor M2 in the low-impedance state (e.g., "1" or "0") is read. In some embodiments, when the read transistor M2 is switched on or conducting, the voltage or current of the read bit line RBL is detected by a read amplifier (not shown), and the data associated with the read transistor M2 in the low-impedance state (e.g., "1" or "0") is read. Fig. 4A-4C M2 is in a high-impedance state, the read transistor M2 is switched off or non-conducting, and the voltage of the read word line RBL is not pulled to VSS by the read transistor M2, and the voltage or current of the read bit line RBL is not detected by a read amplifier (not shown), and the data associated with the read transistor M2 in the high-impedance state (e.g., "1" or "0") is read. In this embodiment, the voltage change of the read bit line RBL is negligible because the read transistor M2 is switched off. Subsequently, the read word line RWL is set to a logic high value (high), thus switching off the write transistor M3.

[0108] Transistor M4 is shown as a PMOS transistor. In some embodiments, transistor M4 is an NMOS transistor.

[0109] In some embodiments, transistor M4 and at least the write transistor M1, the read transistor M2, or transistor M3 have channel regions formed from the same type of material. In some embodiments, transistor M4 has a channel region comprising a silicon body or mass.

[0110] In some embodiments, the memory cell 400A resembles the memory cell 200A in that it includes the write transistor M1, the read transistor M2 (e.g., FeFET), the transistor M3, and the transistor M4. In some embodiments, because the memory cell 400A is similar to the memory cell 200A, it has the advantages described above in relation to the memory cell 200A.

[0111] In some embodiments, the memory cell 400A and the memory cells 400B-400C ( Fig. 4B-4C) a 4T memory cell structure that is compatible with CMOS processes and therefore scalable.

[0112] Further embodiments include additional transistor connections for each of the transistors M1, M2, M3, M4, M1', M2', M3' and M4' of the present patent application. For example, a reference to drains and sources of one and the same transistor in the present disclosure can be changed to source and drain of the same transistor.

[0113] Other embodiments include further configurations or quantities of transistors in the 400A memory cell.

[0114] Fig. 4B is a circuit diagram of a 400B memory cell according to some embodiments.

[0115] The memory cell 400B is an embodiment of a memory cell in the arrangement of memory cells 102A of Fig. 1 in a schematic representation, therefore a similarly detailed description is omitted.

[0116] The memory cell 400B is configured as one or more memory cells in the arrangement of memory cells 102A of Fig. 1 usable. The memory cell 400B has the write transistor M1', the read transistor M2, the write word line WWL, the read word line RWL, the write bit line WBL, the read bit line RBL, the transistor M3 and the transistor M4.

[0117] The 400B memory cell is a variant of the 400A memory cell from Fig. 4A and the memory cell 200B of Fig. 2B, therefore a similarly detailed description is omitted. For example, the 400B memory cell combines similar features to the 400A memory cell from Fig. 4A and the memory cell 200B of Fig. 2B.

[0118] Compared to the 400A memory cell from Fig. 4A replaces the write transistor M1' of Fig. 2B the write transistor M1 from Fig. 4A, therefore a similarly detailed description is omitted.

[0119] The write transistor M1' is located in memory cell 200B of Fig. The operation of memory cell 400B is described above, therefore a similarly detailed description is omitted. The write transistor M1' is shown as a PMOS transistor. In some embodiments, the write transistor M1' is an NMOS transistor. The operation of memory cell 400B is similar to the operation of memory cell 400A described above, therefore a similarly detailed description is omitted.

[0120] In some embodiments, the memory cell 400B achieves similar advantages to those discussed above with respect to memory cell 400A and memory cell 200B by having the write transistor M1' with an oxide channel region 210 and the read transistor M2 (e.g. FeFET), transistor M3 and transistor M4.

[0121] Furthermore, since the 400B memory cell is similar to the 200A memory cell, the 300B memory cell also has the advantages described above in relation to the 200A memory cell.

[0122] Other embodiments include further configurations, connections, or quantities of transistors in the 400B memory cell.

[0123] Fig. 4C is a circuit diagram of a 400C memory cell according to some embodiments.

[0124] The memory cell 400C is an embodiment of a memory cell in the arrangement of memory cells 102A of Fig. 1 in a schematic representation, therefore a similarly detailed description is omitted.

[0125] The 400C memory cell is configured as one or more memory cells in the arrangement of 102A memory cells. Fig. 1 usable. The memory cell 400C has the write transistor M1, the read transistor M2, the write word line WWL, the read word line RWL, the write bit line WBL, the read bit line RBL, the transistor M3' and the transistor M4'.

[0126] The 400C memory cell is a variant of the 400B memory cell from Fig. 4B, therefore a similarly detailed description is omitted. Compared to the 400B memory cell of Fig. 4B, the read transistor M2' replaces the read transistor M2 of Fig. 4B, the transistor M3' replaces the transistor M3 of Fig. 4B and transistor M4' replaces transistor M4 from Fig. 4B, therefore a similarly detailed description is omitted.

[0127] The read transistor M2' is located in memory cell 200C of Fig. Section 2C describes this, therefore a similarly detailed description is omitted. The read transistor M2' is shown as a PMOS transistor. In some embodiments, the read transistor M2' is an NMOS transistor.

[0128] The transistor M3' is located in the memory cell 300C of Fig. Section 3C describes this, therefore a similarly detailed description is omitted. The read transistor M3' is shown as a PMOS transistor. In some embodiments, transistor M3' is an NMOS transistor.

[0129] Transistor M4' is shown as a PMOS transistor. In some embodiments, transistor M4' is an NMOS transistor. In some embodiments, transistor M4' resembles transistor M4 of Fig. 4A-4B, therefore a similarly detailed description is omitted. The operation of the 400C memory cell is similar to the operation of the 400A or 400B memory cells (described above), therefore a similarly detailed description is omitted.

[0130] Compared to the transistor M4 of Fig. In 4B, transistor M4' has an oxide channel region 240; therefore, a similarly detailed description is omitted. In some embodiments, the oxide channel region 240 for transistor M4' contains an oxide semiconductor material comprising zinc oxide, cadmium oxide, indium oxide, IGZO, SnO2, TiO2, or combinations thereof, or the like.

[0131] In some embodiments, the oxide channel region 240 of transistor M4' contains the same oxide semiconductor material as the oxide channel region 210, 220, or 230 of at least one write transistor M1', one read transistor M2', or one read transistor M3'. In some embodiments, the oxide channel region 240 of transistor M4' contains a different oxide semiconductor material than the oxide channel region 210, 220, or 230 of at least one write transistor M1', one read transistor M2', or one read transistor M3', respectively. Further embodiments include additional transistor types or oxide materials for transistor M4'.

[0132] In some embodiments, either the read transistor M2', transistor M3' or transistor M4' has an oxide channel region 220, 230 or 240, and the other of read transistor M2', transistor M3' or transistor M4' has a silicon channel region with a silicon body or mass similar to read transistor M2, transistor M3 or transistor M4.

[0133] In some embodiments, the 400C memory cell achieves similar advantages to those discussed above with respect to the 400A and 200C memory cells by incorporating the write transistor M1' with an oxide channel region 210, the read transistor M2' with an oxide channel region 220, and, as a FeFET, the transistor M3' with an oxide channel region 230 and the transistor M4' with an oxide channel region 240. Furthermore, since the 400C memory cell is similar to the 200A memory cell, it also possesses the advantages described above with respect to the 200A memory cell.

[0134] Other embodiments include further configurations, connections, or quantities of transistors in the 400C memory cell.

[0135] Fig. Figure 5 is a cross-sectional view of an integrated circuit 500 according to some embodiments.

[0136] The integrated circuit 500 is an embodiment of the reading transistor M2 and M2' from Fig. 2A-2C, 3A-3C and 4A-4C, therefore a similarly detailed description is omitted. In some embodiments, the integrated circuit has 500 additional elements, which are not shown for the sake of clarity.

[0137] The integrated circuit 500 is depicted as a planar transistor; other embodiments include other transistors. In some embodiments, the integrated circuit 500 is a fin field-effect transistor (FinFET), a nanofilm transistor, a nanowire transistor, or the like. In some embodiments, the integrated circuit 500 is a FeFET or the like and is fabricated using a back-end-of-line (BEOL) process.

[0138] The integrated circuit 500 comprises a substrate 502. In some embodiments, the substrate 502 is a p-substrate. In some embodiments, the substrate 502 is an n-substrate. In some embodiments, the substrate 502 comprises an elementary semiconductor containing silicon or germanium in crystalline, polycrystalline, or amorphous form; a compound semiconductor containing silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor containing SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate has a SiGe gradient feature in which the Si and Ge composition changes from one ratio at one location to another ratio at another location of the SiGe gradient feature.In some embodiments, the SiGe alloy is formed over a silicon substrate. In some embodiments, the first substrate 502 is an extended SiGe substrate. In some embodiments, the semiconductor substrate has a semiconductor-on-insulator structure, for example, a silicon-on-insulator (SOI) structure. In some embodiments, the semiconductor substrate has a doped epilayer or a buried layer. In some embodiments, the compound semiconductor substrate has a multilayer structure, or the substrate has a multilayer compound semiconductor structure.

[0139] In some embodiments, the integrated circuit 500 is a silicon transistor (e.g., with a silicon channel region (unlabeled)), and the substrate 502 comprises a silicon body or mass. In some embodiments, the integrated circuit 500 is an oxide transistor (e.g., with an oxide channel region 210, 220, 230, or 240), and the substrate 502 comprises an oxide semiconductor material including zinc oxide, cadmium oxide, indium oxide, IGZO, SnO2, TiO2, or combinations thereof, or the like.

[0140] The integrated circuit 500 further comprises a drain region 504 and a source region 506 in the substrate 502. In some embodiments, at least a portion of the source region 506 or a portion of the drain region 504 extends over the substrate 502. In some embodiments, the source region 506 and the drain region 504 are embedded in the substrate 502.

[0141] Drain region 504 is an embodiment of the drain terminal of the read transistors M2 and M2' of Fig. 2A-2C, 3A-3C and 4A4C, therefore a similarly detailed description is omitted. Source region 506 is an embodiment of the source terminal of the read transistors M2 and M2' of Fig. 2A-2C, 3A-3C and 4A4C, therefore a similarly detailed description is omitted.

[0142] In some embodiments, the drain region 504 and the source region 506 are separated by Fig. 5 is designated as the oxide definition region (OD region), which is the source or drain diffusion region of the integrated circuit 500 or of read transistor M2 and M2' of Fig. 2A-2C, 3A-3C and 4A4C are defined, therefore a similarly detailed description is omitted.

[0143] In some embodiments, the integrated circuit 500 is a P-FeFET transistor; therefore, the substrate 502 is an N-region, the drain region 504 is an active P-region with P-doping implanted into the substrate 502, and the source region 506 is an active P-region with P-doping implanted into the substrate 502.

[0144] In some embodiments, the integrated circuit 500 is an N-FeFET transistor; therefore, the substrate 502 is an N-region, the drain region 504 is an active N-region with N-doping implanted into the substrate 502, and the source region 506 is an active N-region with N-doping implanted into the substrate 502.

[0145] In some embodiments, the nitrogen dopants include phosphorus, arsenic, or other suitable nitrogen dopants. In some embodiments, the phosphorus dopants include boron, aluminum, or other suitable phosphorus dopants.

[0146] The integrated circuit 500 further comprises an insulating layer 510 on the substrate 502. In some embodiments, the insulating layer 510 is located between the drain region 504 and the source region 506. In some embodiments, the insulating layer 510 is a gate dielectric layer. In some embodiments, the insulating layer contains an insulating material comprising SiO₂, SiO₂, or combinations thereof, or the like. In some embodiments, the insulating layer 510 comprises a gate oxide or the like.

[0147] The integrated circuit 500 further comprises a metal layer 512 over the insulating layer 510. In some embodiments, the metal layer 512 contains Cu, TiN, W, or a combination thereof, or the like. In some embodiments, the metal layer 512 is a conductive layer containing doped polysilicon. In some embodiments, the integrated circuit 500 does not have a metal layer 512.

[0148] The integrated circuit 500 further comprises a ferroelectric layer 520 over at least the conductive layer 512 or the insulating layer 510. In some embodiments in which the integrated circuit 500 does not have a metal layer 512, the ferroelectric layer 520 is located on the insulating layer 510. The ferroelectric layer 520 is an embodiment of the ferroelectric region 202 of Fig. 2A-2C, 3A-3C and 4A4C, therefore a similarly detailed description is omitted.

[0149] In some embodiments, the ferroelectric layer 520 contains ferroelectric material. In some embodiments, a ferroelectric material comprises HfO2, HfZrO, HfO, perovskite, SBT, PZT or combinations thereof or the like.

[0150] The ferroelectric layer 520 has the polarization states P1 or P2, which correspond to the polarization states P+ or P- in Fig. Since this corresponds to 2A, a similarly detailed description is omitted. The polarization state P1 points in a first direction Y. The polarization state P2 points in a second direction (e.g., negative Y), which is opposite to the first direction Y.

[0151] Fig. Figure 5 shows both polarization states P1 and P2. However, in some embodiments, the integrated circuit 500 exhibits, due to the non-volatile property of the ferroelectric layer 520, as soon as the polarization state P1 or P2 of the integrated circuit 500 is determined based on the gate voltage V. G is set to one of the polarization states P1 or P2.

[0152] The ferroelectric layer 520 creates a capacitance in the integrated circuit 500. Furthermore, the MOS transistor of the integrated circuit 500 also has a capacitance. In some embodiments, the capacitance of the ferroelectric layer 520 and the capacitance of the MOS transistor are matched to operate the integrated circuit 500 in a non-volatile mode. In some embodiments, the capacitance of the ferroelectric layer 520 is set based on a thickness T1 of the ferroelectric layer 520. In some embodiments, by changing the thickness T1, the integrated circuit 500 can be operated in a non-volatile mode or in a volatile mode.

[0153] In some embodiments, the thickness T1 of the ferroelectric layer 520 is in the range of about 3 nanometers (nm) to about 50 nm. In some embodiments, with increasing thickness T1, the ability of the ferroelectric layer 520 to preserve hysteresis and bistable polarization states (e.g., P1 or P2) increases, and the leakage current of the integrated circuit 500 decreases. In some embodiments, with decreasing thickness T1, the ability of the ferroelectric layer 520 to preserve hysteresis and bistable polarization states (e.g., P1 or P2) decreases, and the leakage current of the integrated circuit 500 increases. In some embodiments, the integrated circuit 500 lacks the insulating layer 510 and the metal layer 512, and the ferroelectric layer 520 is located directly on the substrate 502.In some embodiments, the integrated circuit 500 does not have the insulating layer 510, and the metal layer 512 is located directly on the substrate 502.

[0154] The integrated circuit 500 further comprises a gate structure 530 above the ferroelectric layer 520. The gate structure 530 contains a conductive material, such as a metal or doped polysilicon (here also referred to as "POLY").

[0155] In some embodiments, the integrated circuit 500 is an embodiment of the write transistor M1 and M1' of Fig. 2A-2C, 3A-3C and 4A-4C. In these embodiments, the integrated circuit 500 does not have the ferroelectric layer 520.

[0156] Because it is included in the memory cell arrangement 100 and the memory circuit 200A-200C, 300A-300C and 400A-400C, which are described above in relation to Fig. As discussed in sections 1, 2A-2C, 3A-3C and 4A-4C, the integrated circuit 500 is operational, achieving the advantages discussed above with respect to the memory cell arrangement 100 and the memory circuit 200A-200C, 300A-300C and 400A-400C.

[0157] Fig. Figure 6 is a flowchart of a method 600 for fabricating an integrated circuit (IC) according to some embodiments. It is understood that additional operations may be performed before, during, and / or after the process described in Figure 600. Fig. The processes described in Section 6 of the disclosed embodiments of Method 600 can be carried out in a variety of ways, and some other processes can only be briefly described here. In some embodiments, the sequence of operations of Method 600 differs. Method 600 includes exemplary operations, which, however, are not necessarily carried out in the sequence shown. Operations may be added, replaced, changed in order, and / or omitted according to the spirit and scope of the disclosed embodiments. In some embodiments, one or more of the operations of Method 600 are not carried out.

[0158] In some embodiments, method 600 can be used to at least the memory cell arrangement 100 ( Fig. 1) the memory cell 200A-200C, 300A-300C or 400A-400C ( Fig. 2A-2C, 3A-3C or 4A-4C) or the integrated circuit 500 ( Fig. 5) to produce or manufacture.

[0159] In operation 602 of method 600, the drain region 504 of a transistor is fabricated in the substrate 502. In some embodiments, the drain region of method 600 comprises at least the drain of read transistor M2 or M2'. In some embodiments, the transistor of method 600 comprises at least the read transistor M2 or M2'. In some embodiments, the drain region is fabricated in a first well in the substrate, and the first well has a doping that is opposite to the doping of the drain region.

[0160] In some embodiments, the transistor of method 600 comprises at least transistor M1, M1', M3, M3', M4 or M4'. In some embodiments, the drain region of method 600 comprises at least the drain of transistor M1, M1', M3, M3', M4 or M4'.

[0161] In operation 604 of method 600, the source region 504 of the transistor is fabricated in the substrate 502. In some embodiments, the source region of method 600 comprises at least the source of read transistor M2 or M2'. In some embodiments, the transistor of method 600 comprises at least the read transistor M2 or M2'. In some embodiments, the source region is fabricated in the first well. In some embodiments, the source region of method 600 comprises at least the source of transistor M1, M1', M3, M3', M4, or M4'.

[0162] In some embodiments, at least operation 602 or 604 comprises the formation of source / drain features in the substrate. In some embodiments, the formation of the source / drain features comprises removing a section of the substrate to form wells and subsequently performing a filling process by filling the wells in the substrate. In some embodiments, the wells are etched after the removal of a pad oxide layer or a sacrificial oxide layer, for example, by wet etching or dry etching. In some embodiments, the etching process is performed to remove an upper surface section of the active region. In some embodiments, the filling process is performed by means of an epitaxial process (epi-process).In some embodiments, the depressions are filled by means of a growth process that runs parallel to an etching process, wherein the growth rate of the growth process is greater than the etching rate. In some embodiments, the depressions are filled by means of a combination of growth and etching processes. For example, a layer of material is grown in the depression, and then the grown material is subjected to an etching process to remove some of the material. A subsequent growth process is then carried out on the etched material until a desired thickness of material is achieved in the depression. In some embodiments, the growth process continues until a top surface of the material is above the top surface of the substrate.In some embodiments, the growth process continues until the top surface of the material is level with the top surface of the substrate. In some embodiments, a section of the substrate 502 is removed by an isotropic or anisotropic etching process. The etching process selectively etches the substrate 502 without etching the gate structure 530. In some embodiments, the etching process is performed by reactive ion etching (RIE), wet etching, or other suitable methods. In some embodiments, a semiconductor material is deposited in the wells to form the source / drain features. In some embodiments, an epi-process is performed to deposit the semiconductor material in the wells.In some embodiments, the epi-process comprises a selective epitaxy growth (SEG) process, a continuous vapor deposition (CVD) process, molecular beam epitaxy (MBE), other suitable processes, and / or combinations thereof. The epi-process utilizes gaseous and / or liquid precursors that interact with a substrate composition. In some embodiments, the source / drain features include epitaxially grown silicon (epi-Si), silicon carbide, or silicon germanium. Source / drain features of the IC device, associated with the 530 gate structure, are in some cases doped or undoped in situ during the epi-process. If source / drain features are undoped during the epi-process, they are, in some cases, doped during a subsequent process.The subsequent doping process is achieved by ion implantation, plasma immersion ion implantation, gas and / or solid source diffusion, other suitable methods, and / or combinations thereof. In some embodiments, source / drain features are further subjected to tempering processes after their formation and / or after the subsequent doping process.

[0163] In some embodiments, the source / drain features include n-type dopants containing phosphorus, arsenic, or other suitable n-type dopants. In some embodiments, the concentration of the n-type dopants is in the range of approximately 1 x 10⁻⁶. 12 atoms / cm² 2 up to about 1 x 10 14 atoms / cm² 2 .

[0164] In some embodiments, the source / drain features include p-type dopants containing boron, aluminum, or other suitable p-type dopants. In some embodiments, the concentration of the p-type dopants is in the range of approximately 1 x 10⁻⁶. 12 atoms / cm² 2 up to about 1 x 10 14 atoms / cm² 2 .

[0165] In operation 606 of process 600, an insulating layer 510 is produced on the substrate 502. In some embodiments, at least the production of the insulating layer 510 in operation 610 comprises performing one or more deposition processes to form one or more layers of dielectric material. In some embodiments, a deposition process comprises chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or another process suitable for depositing one or more layers of material.

[0166] In operation 608 of process 600, a conductive layer is deposited onto the insulating layer 510. In some embodiments, the conductive layer of process 600 is the metal layer 512. In some embodiments, the conductive layer of operation 608 is formed by a combination of photolithography and a material removal process to create openings in an insulating layer (not shown) above the substrate. In some embodiments, the photolithography process includes structuring a photoresist, such as a positive or negative photoresist. In some embodiments, the photolithography process includes forming a hard mask, an antireflection structure, or another suitable photolithography structure. In some embodiments, the material removal process includes a wet etching process, a dry etching process, an RIE process, laser drilling, or another suitable etching process.The openings are then filled with conductive material, e.g., copper, aluminum, titanium, nickel, tungsten, or another suitable conductive material. In some embodiments, the openings are filled by CVD, PVD, sputtering, ALD, or another suitable formation process.

[0167] In operation 610 of method 600, a ferroelectric layer 520 is formed at least on the insulating layer 510 or the conductive layer (metal layer 512). In some embodiments, at least operation 606 or 608 is not performed. In some embodiments, operations 606 and 608 are not performed, and the ferroelectric layer 520 is formed directly on the substrate 502. In some embodiments, operation 606 is not performed, and the conductive layer (e.g., metal layer 512) is deposited on the substrate 502. In some embodiments, operation 608 is not performed, and the ferroelectric layer 520 is deposited on the insulating layer 510.

[0168] In operation 612 of process 600, a gate region 530 of the transistor is fabricated. In some embodiments, the fabrication of the gate region includes performing one or more deposition processes to form one or more layers of conductive material. In some embodiments, the fabrication of the gate regions includes the formation of gate electrodes. In some embodiments, gate regions are formed from doped or undoped polycrystalline silicon (or polysilicon). In some embodiments, the gate regions comprise a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0169] Fig. Figure 7 is a flowchart of a method 700 for operating a circuit according to some embodiments. In some embodiments, Fig. 7 a flowchart of the procedure 700 for operating a memory circuit, for example the memory cell arrangement 100 of Fig. 1 or the memory cell 200A-200C, 300A-300C or 400A-400C ( Fig. 2A-2C, 3A-3C or 4A-4C) or the integrated circuit 500 ( Fig. 5).

[0170] It is understood that additional operations may be necessary before, during and / or after the procedure. Fig. The processes described in Section 700 can be carried out in detail, and some other processes can only be briefly described here. In some embodiments, the sequence of operations in Process 700 differs. Process 700 includes exemplary operations, which, however, are not necessarily performed in the sequence shown. Operations may be added, replaced, reordered, and / or omitted according to the spirit and scope of the disclosed embodiments. In some embodiments, one or more of the operations of Process 700 are not performed.

[0171] In operation 702 of method 700, a write operation to a memory cell is performed. In some embodiments, the memory cell of method 700 comprises memory cell 200A-200C, 300A-300C, or 400A-400C. In some embodiments, the memory cell of method 700 comprises at least one memory cell of the memory cell arrangement 100. In some embodiments, operation 702 comprises at least operation 704, 706, 708, or 710.

[0172] In operation 704 of procedure 700, a write bit line signal is set on a write bit line WBL. In some embodiments, the write bit line signal of procedure 700 includes a write bit line signal of the write bit line WBL. In some embodiments, the write bit line signal corresponds to a stored data value in the memory cell.

[0173] In operation 706 of method 700, a write transistor is switched on in response to a write word line signal, thereby electrically coupling the write bit line WBL to a gate of a read transistor. In some embodiments, the write transistor of method 700 comprises at least the write transistor M1 or M1'. In some embodiments, the read transistor of method 700 comprises at least the read transistor M2 or M2'. In some embodiments, the gate of the read transistor of method 700 comprises at least the gate terminal of read transistor M2 or M2'. In some embodiments, the write word line signal of method 700 comprises a write word line signal of the write word line WWL. In some embodiments, the read transistor of method 700 comprises the integrated circuit 500.

[0174] In operation 708 of procedure 700, the stored data value of the memory cell is set by adjusting a polarization state of the read transistor, thereby turning the read transistor on or off.

[0175] In some embodiments, the polarization state of the read transistor of method 700 includes the polarization state P+ or P- of at least one read transistor M2 or M2'. In some embodiments, the polarization state of the read transistor of method 700 includes the polarization state P1 or P2 of the integrated circuit 500. In some embodiments, the polarization state corresponds to the stored data value of the memory cell.

[0176] In operation 710 of method 700, the write transistor is switched off in response to the write word line signal, thereby electrically decoupling the write bit line and the gate of the read transistor. In some embodiments, operation 710 further includes retaining the stored value in the memory cell.

[0177] In operation 712 of method 700, a read operation of the memory cell is performed. In some embodiments, operation 712 includes at least operation 714, 716, 718, or 720.

[0178] In operation 714 of method 700, a voltage of a read bit line RBL is pre-discharged to a first voltage (VSS), or the voltage of the read bit line RBL is pre-charged to a second voltage (VDD) different from the first voltage. In some embodiments, the first voltage of method 700 includes the reference voltage VSS. In some embodiments, the second voltage of method 700 includes the supply voltage VDD.

[0179] In operation 716 of method 700, the voltage of a read word line RWL is adjusted from a third voltage to a fourth voltage. In some embodiments, the voltage of the read word line RWL is the read word line signal. In some embodiments, the third voltage of method 700 includes a logic high (high) signal. In some embodiments, the third voltage of method 700 includes a supply voltage VDD. In some embodiments, the fourth voltage of method 700 includes a logic low (low) signal. In some embodiments, the fourth voltage of method 700 includes a reference voltage VSS.

[0180] In operation 718 of method 700, the voltage of the read word line is detected in response to the voltage of the read word line being set from the third voltage to the fourth voltage, thereby outputting the stored data value in the memory cell. In some embodiments, operation 718 comprises detecting the current of the read bit line in response to the voltage of the read word line being set from the third voltage to the fourth voltage, instead of detecting the voltage of the read word line, thereby outputting the stored data value in the memory cell.

[0181] In some embodiments, the stored data value of the memory cell has a first logic value corresponding to a first resistance state of the read transistor, or a second logic value corresponding to a second resistance state of the read transistor. In some embodiments, the second logic value is the opposite of the first logic value. In some embodiments, the second resistance value is the opposite of the first resistance value. In some embodiments, the first logic value is either logic 1 or logic 0, and the second logic value is the opposite of logic 0 or logic 1. In some embodiments, the first resistance state is either the low-resistance state or the high-resistance state, and the second resistance state is the opposite of the high-resistance state or the low-resistance state.

[0182] In some embodiments, adjusting the voltage of the read word line RWL from the third voltage to the fourth voltage includes switching on a first transistor in response to a first control signal or to the fact that the voltage of the read word line is the fourth voltage, thereby electrically coupling the read word line to a source of the read transistor. In some embodiments, the first transistor of Method 700 comprises at least transistor M3 or M3'. In some embodiments, the first control signal of Method 700 comprises the control signal CS. In some embodiments, the source of the read transistor of Method 700 comprises the source terminal of read transistor M2 or M2'.

[0183] In operation 720 of method 700, the voltage of the read word line is adjusted from the fourth voltage to the third voltage. In some embodiments, adjusting the voltage of the read word line from the fourth voltage to the third voltage in operation 720 includes turning off the first transistor in response to the first control signal or to the read word line voltage being the third voltage, thereby electrically decoupling the read word line and the source of the read transistor.

[0184] By performing procedure 700, the memory circuit is operational to perform the above with respect to the memory cell arrangement 100. Fig. 1 or the memory cell 200A-200C, 300A-300C or 400A-400C ( Fig. 2A-2C, 3A-3C or 4A-4C) or the integrated circuit 500 ( Fig. 5) to achieve the discussed advantages.

[0185] Although the method 700 above was described with reference to a single memory cell of the memory cell arrangement 100, it is understood that in some embodiments the method 700 is applied to each row and each column of the memory cell arrangement 100.

[0186] Furthermore, various PMOS or NMOS transistors are used in Fig. The transistors shown, 2A-2C, 3A-3C, or 4A-4C, are of a specific doping type (e.g., N or P) and serve for illustration purposes. Embodiments of the disclosure are not limited to a specific transistor type, and one or more of the transistors shown in the diagram may be used. Fig. The PMOS or NMOS transistors shown in 2A-2C, 3A-3C, or 4A-4C can be replaced by a corresponding transistor of a different transistor / doping type. Similarly, the low or high logic value of various signals used in the above description also serves for illustration. Embodiments of the disclosure are not limited to a specific logic value when a signal is enabled and / or disabled. Further embodiments include the choice of different logic values. Other embodiments include the choice of a different number of transistors in Fig. 2A-2C, 3A-3C or 4A-4C .

[0187] A person skilled in the art will readily recognize that one or more of the disclosed embodiments offer one or more of the advantages set out above. After reading the foregoing specification, a person skilled in the art will be able to consider various modifications, substitutions of equivalents, and various other embodiments as broadly disclosed herein.

[0188] The invention is defined by the main claim and the dependent claim. The subclaims describe further embodiments of the invention.

Claims

[1] Memory cell (102), comprising: a write bit line; a write transistor (M1, M1') coupled between the write bit line and a first node (ND1); and a read transistor (M2, M2') which is coupled to the write transistor (M1, M1') via the first node (ND1); wherein the read transistor (M2, M2') has a ferroelectric layer (202, 520) and the write transistor (M1, M1') is designed to set a stored data value of the memory cell (102) by means of a write bit line signal which sets a polarization state of the read transistor, wherein the polarization state corresponds to the stored data value; where the write transistor (M1, M1') has: a first drain terminal that is coupled to the write bit line; a first source terminal coupled to the first node (ND1) and the read transistor (M2, M2'); and a first gate connection that is coupled to a write word line; where the read transistor (M2, M2') has: a second drain connection coupled to a second node; a second source port that is coupled to a third node; and a second gate terminal on the ferroelectric layer (202, 520) which is coupled to the first source terminal via the first node (ND1); wherein the memory cell (102) further comprises: a first transistor (M3, M3') coupled to the read transistor (M2, M2'), wherein the first transistor has: a third drain port that is coupled to the second source port via the third node; a third source port coupled with a read bit line; and a third gate connector; wherein the second drain terminal is coupled to a reference voltage supply via the second node; and the third gate connection is coupled with a read word line; and wherein the memory cell (102) further comprises: a second transistor (M4, M4') coupled via the first node (ND1) to the read transistor (M2, M2') and the write transistor (M1, M1'), the second transistor comprising: a fourth drain connection that is coupled to the read word line; a fourth source port coupled to a fourth node (ND2); and a fourth gate connection, which is coupled via the first node (ND1) to the first source connection and the second gate connection. [2] Memory cell (102) according to claim 1, wherein the write transistor (M1') has an oxide channel region; and The read transistor (M2) has a silicon channel region. [3] Memory cell (102) according to claim 1, wherein the write transistor (M1') has an oxide channel region; and the reading transistor (M2') has another oxide channel region. [4] Memory cell (102) according to one of claims 1 to 3, wherein the read transistor (M2, M2') further comprises: a gate insulating layer (510) over a channel region of the read transistor (M2, M2'); and a gate layer (530) on the ferroelectric layer (202, 520); wherein the ferroelectric layer (202, 520) is located between the gate insulating layer (510) and the gate layer (530). [5] Memory cell (102) according to any one of claims 1 to 4, wherein the ferroelectric layer (202, 520) contains a ferroelectric material comprising HfO2, HfZrO, HfO or combinations thereof. [6] Memory cell (102), comprising: a write bit line; a spelling word guide; a write transistor (M1, M1') of a first type coupled to the write bit line, the write word line and a first node (ND1), wherein the write transistor is designed to be turned on or off in response to a write word line signal; and a read transistor (M2, M2') of the first type, wherein the read transistor has: a first gate connection that is coupled to the write transistor (M1, M1') via the first node (ND1); and a ferroelectric layer (202, 520) with a polarization state corresponding to a stored data value in the memory cell (102); wherein the write transistor (M1, M1') is designed to set the stored data value in the memory cell (102) by means of a write bit line signal that sets the polarization state of the ferroelectric layer (202, 520); and wherein the memory cell (102) further comprises a first transistor (M3, M3') coupled to the read transistor (M2, M2'), wherein the first transistor comprises: a drain terminal of the first transistor (M3, M3') which is coupled to a source terminal of the read transistor (M2, M2'); a source terminal of the first transistor (M3, M3') coupled to a read bit line; and a gate terminal of the first transistor (M3, M3') which is coupled to a read word line; wherein the memory cell (102) further comprises a second transistor (M4, M4') which is coupled via the first node (ND1) to the read transistor (M2, M2') and the write transistor (M1, M1'), wherein the second transistor comprises: a drain terminal of the second transistor (M4, M4') which is coupled to the read word line; a source terminal of the second transistor (M4, M4') which is coupled to a second node (ND2); and a gate terminal of the second transistor (M4, M4') which is coupled via the first node (ND1) to a source terminal of the write transistor (M1, M1') and the gate terminal of the read transistor (M2, M2'); and where a drain terminal of the read transistor (M2, M2') is coupled to a reference voltage supply. [7] Memory cell (102) according to claim 6, wherein the write transistor (M1') has an oxide channel region; and The read transistor (M2) has a silicon channel region. [8] Memory cell (102) according to claim 6, wherein the write transistor (M1') has an oxide channel region; and the reading transistor (M2') has another oxide channel region. [9] Memory cell (102) according to one of claims 6 to 8, wherein the read transistor (M2, M2') further comprises: a gate insulating layer (510) over a channel region of the read transistor (M2, M2'); and a gate layer (530) on the ferroelectric layer (202, 520); wherein the ferroelectric layer (202, 520) is located between the gate insulating layer (510) and the gate layer (530). [10] Memory cell (102) according to any one of claims 6 to 9, wherein the ferroelectric layer (202, 520) comprises a ferroelectric material comprising HfO2, HfZrO, HfO or combinations thereof. [11] Method for operating a memory cell (102) according to any one of the preceding claims, wherein the method comprises: Performing (702) a write operation of the memory cell (102), wherein performing the write operation of the memory cell includes: Setting (704) a write bit line signal on the write bit line of the memory cell, wherein the write bit line signal corresponds to a stored data value in the memory cell (102); Switching on (706) of the write transistor (M1, M1') of the memory cell in response to a write word line signal, thereby electrically coupling the write bit line to the gate of the read transistor (M2, M2') of the memory cell; Setting (708) the stored data value of the memory cell (102) by setting a polarization state of the read transistor (M2, M2'), thereby turning the read transistor on or off, the polarization state corresponding to the stored data value of the memory cell; and Switching off (710) of the write transistor (M1, M1') in response to the write word line signal, thereby electrically decoupling the write bit line and the gate of the read transistor (M2, M2'). [12] The method of claim 11, further comprising: Performing (712) a read operation of the memory cell (102), wherein performing the read operation of the memory cell comprises: Pre-discharging (714) of a voltage of the read bit line of the memory cell to a first voltage or pre-charging of the voltage of the read bit line to a second voltage different from the first voltage; Adjusting (716) a voltage of the read word line of the memory cell from a third voltage to a fourth voltage; Detection (718) of the voltage of the read word line in response to the adjustment of the voltage of the read word line from the third voltage to the fourth voltage, thereby outputting the stored data value in the memory cell (102); and Adjusting (720) the voltage of the reading word line from the fourth voltage to the third voltage. [13] Method according to claim 12, wherein adjusting (716) the voltage of the read word line comprises: Switching on of the first transistor (M3, M3') of the memory cell in response to the voltage of the read word line being the fourth voltage, thus electrically coupling the read bit line to the source of the read transistor (M2, M2'). [14] Method according to claim 12, wherein adjusting (720) the voltage of the read word line comprises: Switching off the first transistor (M3, M3') of the memory cell in response to the fact that the voltage of the read word line is the third voltage, thereby electrically decoupling the read bit line and the source of the read transistor (M2, M2'). [15] Method according to any one of claims 11 to 14, wherein the stored data value of the memory cell (102) has a first logical value corresponding to a first resistance state of the read transistor (M2, M2') or a second logical value corresponding to a second resistance state of the read transistor, wherein the second logical value is opposite to the first logical value and the second resistance state is opposite to the first resistance state.

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