Semiconductor component and method for manufacturing a semiconductor component

A dual-architecture compatible layout diagram addresses the limitations of single-architecture semiconductor design rules by allowing selective structure removal, enabling seamless adaptation to both non-buried and buried power rail architectures, enhancing manufacturing flexibility and efficiency.

DE102021107950B4Active Publication Date: 2026-07-09TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
DE102021107950
Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
Priority Date
2021-03-09
Filing Date
2021-03-30
Publication Date
2026-07-09
Estimated Expiration
2041-03-30

AI Technical Summary

Technical Problem

Existing semiconductor design rules are specific to a single architecture type, limiting the adaptability of semiconductor devices to different manufacturing processes and architectures, and there is a need for a layout diagram that can be easily adapted to multiple architecture types without adding or extending structures.

Method used

A dual-architecture compatible layout diagram that allows selective pruning of structures, enabling adaptation to either non-buried or buried power rail architectures by selectively removing structures, without adding new elements, thus facilitating porting to both non-BPR and BPR architectures.

Benefits of technology

The dual-architecture compatible layout diagram enhances the adaptability of semiconductor devices to various manufacturing processes, ensuring compatibility and performance across different architectures without requiring additional structures, thereby optimizing manufacturing efficiency and flexibility.

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Abstract

Method for manufacturing a semiconductor device (100, 208A) based on a dual architecture compatible design, the method comprising: Forming (1202) one or more components of one or more transistors in a transistor layer, TR layer, of the semiconductor device (100, 208A); and Performing one of: A) Manufacturing (1206) further components according to a buried busbar architecture type, BPR architecture type, for the semiconductor device (100, 208A), wherein the BPR architecture type comprises sub-transistor layer layers, sub-TR layers, and supra-transistor layer layers; or B) Manufacturing (1236) further components according to an architecture type with a non-buried busbar, non-BPR architecture type, for the semiconductor device (100, 208A), wherein the non-BPR architecture type includes supra-TR layers; and where: The dual-architecture compatible design is essentially equally suitable for adaptation to the BPR architecture type and for adaptation to the non-BPR architecture type; A) Manufacturing (1206) further components according to a BPR architecture type includes: in corresponding sub-TR layers, forming (1208) various non-dummy structures, non-dummy sub-TR structures that are coupled accordingly to the transistor components; and, in corresponding supra-TR layers, forming (1210) various dummy structures, dummy supra-TR structures, which are corresponding artifacts resulting from the dual-architecture compatible design suitable for adaptation to the non-BPR architecture type; and B) Manufacturing (1236) further components according to a non-BPR architecture type includes: in corresponding supra-TR layers: Forming (1238) various non-dummy structures, non-dummy supra-TR structures, which are coupled accordingly with the transistor components; and Forming (1240) various dummy structures, dummy supra-TR structures, which are corresponding artifacts resulting from the dual architecture compatible design suitable for adaptation to the BPR architecture type.
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