Semiconductor device

Abstract

A semiconductor device according to one aspect of the present disclosure comprises a semiconductor substrate; wiring provided on the semiconductor substrate; and a protective layer covering at least a portion of the wiring; wherein the wiring comprises a first metal layer and a second metal layer provided on the first metal layer, the second metal layer comprising a metal having a higher resistance to moisture or acid than the first metal layer, and a contact portion between the first metal layer and the second metal layer in the wiring is not exposed to a component provided on the protective layer.

Description

background Area The present disclosure relates to a semiconductor device. background WO2021 / 064944 A1 discloses a semiconductor device that can improve insulation reliability. The semiconductor device comprises a semiconductor substrate having a drift layer of a first conductivity type and a termination well region formed on a surface layer of the drift layer and having a second conductivity type different from the first. A surface electrode, consisting mainly of aluminum, is formed on the surface of the semiconductor substrate, with its outer circumferential end face extending over and in contact with the termination well region, thus electrically connecting the termination well region. The insulating protective layer covers the surface electrode end of the surface electrode and the termination well region and extends to the outer circumference of the semiconductor substrate.An electrode protection layer made of titanium is provided between the surface electrode and the insulating protective layer. Both the electrode protection layer and the insulating protective layer have openings that correspond to the electrode formation area of ​​the surface electrode, thus exposing the surface electrode. Power semiconductor devices, also known as power devices, are used in switching devices that control the delivery of power to motor loads and the like. Insulated-gate semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs), are widely used as power semiconductor devices. Power devices are increasingly capable of handling high currents, high voltages, and low losses, and are used in a wide range of applications. Power devices are often used in harsh environments, such as high altitudes, high temperatures, and high humidity, and therefore require high reliability against temperature cycling, humidity, and other environmental conditions. In the configuration of WO2021 / 064944 A1, the end region of the surface electrode in the Schottky blocking diode, where the electric field is strong, is covered with a protective layer, for example, made of titanium, which has high corrosion resistance. This prevents corrosion of the surface electrodes, which are made of aluminum, a wiring material that corrodes easily. However, in the configuration of WO2021 / 064944 A1, because multiple metal materials are in contact with each other, there is a possibility that electrode corrosion could occur due to the local battery effect in the presence of moisture. Summary The present disclosure has been prepared to solve the aforementioned problems and has the objective of providing a semiconductor device suitable for improving moisture resistance or acid resistance. The features and advantages of the present disclosure can be summarized as follows. According to one aspect of the first disclosure, a semiconductor device comprises a semiconductor substrate; wiring provided on the semiconductor substrate; and a protective layer covering at least a portion of the wiring; wherein the wiring has a first metal layer and a second metal layer provided on the first metal layer, the second metal layer having a metal having a higher resistance to moisture or acid than the first metal layer, and a contact portion between the first metal layer and the second metal layer in the wiring is not exposed to a component provided on the protective layer. According to one aspect of the second disclosure, a semiconductor device comprises a semiconductor substrate having an active region, a wiring region outside the active region, and a termination region outside the wiring region; wiring provided on the wiring region; and a protective layer covering at least a portion of the wiring; wherein the wiring comprises a first metal layer and a second metal layer provided on the first metal layer, the second metal layer comprising a metal having a higher resistance to moisture or acid than the first metal layer; and the protective layer extending from an upper surface of the second metal layer to both side surfaces of the first metal layer. According to one aspect of the third disclosure, a semiconductor device comprises a semiconductor substrate; a contact electrode provided on the semiconductor substrate; and a protective layer provided on the contact electrode; wherein the contact electrode has a first metal layer and a second metal layer provided on the first metal layer, the second metal layer having a metal that has a higher resistance to moisture or acid than the first metal layer; a contact opening is formed in the contact electrode in which the first metal layer is exposed by the second metal layer; and a contact area between the first metal layer and the second metal layer, opposite the contact opening, is covered with the protective layer. Other and further tasks, features and benefits of the revelation will become more apparent from the following description. Brief description of the drawings Fig. 1 is a top view of a semiconductor device according to embodiment 1. Fig. 2 is an enlarged view of an active region according to embodiment 1. Fig. 3 is a cross-sectional view obtained by cutting Fig. 2 along line AB. Fig. 4 is an enlarged view of an edge region of an active region according to embodiment 1. Fig. 5 is a cross-sectional view obtained by cutting Fig. 4 along line CD. Figs. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 to 21 are cross-sectional views illustrating a method for manufacturing the semiconductor device according to embodiment 1. Fig. 22 is an enlarged view of an edge region of an active area according to embodiment 2. Fig. 23 is a cross-sectional view taken along line CD of Fig. 22.Figure 24 is an enlarged view of an edge region of an active region according to embodiment 3. Figure 25 is a cross-sectional view taken along line CD of Figure 24. Figure 26 is an enlarged view of an edge region of an active region according to embodiment 4. Figure 27 is a cross-sectional view obtained by sectioning Figure 26 along line CD. Figure 28 is a top view of a semiconductor device according to embodiment 5. Figure 29 is an enlarged view of an edge region of an active region according to embodiment 5. Figure 30 is a cross-sectional view obtained by sectioning Figure 29 along line EF. Description of the embodiments Semiconductor devices according to the respective embodiments are described with reference to the drawings. The same or corresponding components are assigned the same reference numerals, and repeated descriptions may be omitted. Design 1 Fig. 1 is a top view of a semiconductor device 100 according to embodiment 1. The semiconductor substrate of the semiconductor device 100 has an active region 101, gate wiring 102 outside the active region 101, and a termination region 104 outside the gate wiring. A main electrode of the semiconductor device 100 is formed on the upper surface of the active region 101. The main electrode is, for example, a source electrode. The main electrode corresponds to a contact electrode 41, which is described below. A gate wiring section 42 is provided in a gate wiring area 102, which surrounds the active area 101. This gate wiring is electrically connected to a gate electrode that serves as a control electrode. The gate wiring 42 is connected to a gate contact point 103. A termination area 104 for maintaining a breakdown voltage is configured to surround the active area 101, the gate wiring 102, and the gate contact point 103. A dicing line area 105, corresponding to the cutting lines used when cutting chips, is provided to surround the termination area 104. Fig. 2 is an enlarged view of the active region 101 according to embodiment 1. Fig. 2 is an enlarged view of region 106 in Fig. 1. Fig. 3 is a cross-sectional view obtained by cutting Fig. 2 along line AB. As shown in Fig. 3, the semiconductor device 100 has an n+-type semiconductor substrate 1. An n+-type buffer layer 2 is formed on the semiconductor substrate 1. An n-type drift layer 3 is formed on the upper surface side of the buffer layer 2. A p-type well layer 4 is selectively formed on the upper surface side of the drift layer 3. An n+-type source layer 5 and a p+-type contact layer 6 are formed on the upper surface side of the well layer 4. An n-type JFET-doped layer 7 is formed between the well layers 4. A gate insulation layer 8 is provided on the well layer 4, the source layer 5, and the JFET-doped layer 7 on the upper surface of the semiconductor substrate 1. A gate electrode layer 9 is provided on the gate insulation layer 8. The gate electrode layer 9 consists, for example, of polysilicon. An interlayer insulation layer 10 is formed on the gate electrode layer 9. On the upper surface of the semiconductor substrate 1, a Ni silicide layer 11 is formed on the source layer 5 and the contact layer 6. A barrier metal layer 12 is provided on the Ni silicide layer 11 and the interlayer insulation layer 10. The barrier metal layer 12 consists, for example, of Ti / TiN. A metal layer 13 is formed on the barrier metal layer 12. The metal layer 13 is, for example, an Al electrode.The Ni silicide layer 11, the barrier metal layer 12 and the metal layer 13 can together be referred to as a source electrode or a contact point electrode 41. A Ni silicide layer 14 is formed on the back surface of the semiconductor substrate 1. An Al electrode 15 is formed on the back surface of the Ni silicide layer 14. The Ni silicide layer 14 and the Al electrode 15 together can be called a drain electrode. Fig. 4 is an enlarged view of an edge region 107 of the active region 101 according to embodiment 1. Fig. 5 is a cross-sectional view obtained by cutting Fig. 4 along line CD. As shown in Fig. 5, a p-type field limiting ring (FLR) layer 16 and an n+-type channel stopper layer 17 are formed in the termination region 104 on the side of the upper surface of the drift layer 3. In this way, a breakdown voltage holding structure, called an FLR structure, is formed in the termination region 104. A field insulation layer 18 is formed on the upper surface of the semiconductor substrate 1 in the termination region 104. A protective layer 19, such as a nitride layer, is formed on the field insulation layer 18. A protective layer 20, such as a polyimide layer, is formed on the protective layer 19.Protective layer 19, for example, is an inorganic protective layer that exhibits excellent moisture resistance and prevents moisture penetration. Protective layer 20, for example, is an organic protective layer that provides stress reduction. In the gate wiring region 102, a gate electrode 21 is formed on the field insulation layer 18. The gate electrode 21 is a wiring layer connected to the gate electrode layer 9. The gate electrode 21 is made of polysilicon. A barrier metal layer 22 is formed on the gate electrode 21. The barrier metal layer 22 consists, for example, of Ti silicide / TiN. A metal layer 23 is formed on the barrier metal layer 22. The metal layer 23 consists, for example, of Al. In the active region 101, a metal layer 24 is formed on the field insulation layer 18 with the barrier metal layer 22 inserted between them. The metal layer 24 consists, for example, of Al. A metal layer 25, serving as an electrode protection layer, is formed on metal layers 23 and 24. Metal layer 25 is made of, for example, titanium. The barrier layer 22, metal layer 23, and metal layer 25 on metal layer 23 form the gate wiring 42. The barrier layer 22, metal layer 24, and metal layer 25 on metal layer 24 form the contact electrode 41. Protection layers 19 and 20 are formed on metal layer 25. Protection layers 19 and 20 cover the entire gate wiring 42 and the end of the contact electrode 41. In the semiconductor device 100, the source electrode is formed on the upper surface of the semiconductor substrate 1, and the drain electrode is formed on the back surface of the semiconductor substrate 1. As a result, a main current flows in the vertical direction of the semiconductor substrate 1. In a MOSFET, which is formed by the source layer 5, the well layer 4, the drift layer 3, the gate insulation layer 8, and the gate electrode layer 9, the main current is controlled by the gate. As shown in Fig. 2, the unit cells are arranged in a striped pattern. The gate electrode layers 9 are also arranged in a striped pattern. The gate electrode layer 9 is connected to a gate electrode 21 in the gate wiring region 102 adjacent to one end of the active region 101. In the contact hole 30 shown in Fig. 4, which is surrounded by X, the gate electrode 21 is connected to the gate wiring 42. Furthermore, the semiconductor substrate 1 and the contact electrode 41 are in contact with each other in the contact hole 29 shown in Fig. 2 and Fig. 4, which is surrounded by X. This causes the source to be connected to ground. Next, a method for fabricating the semiconductor device 100 is described. Figures 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 to 21 are cross-sectional views illustrating a fabrication method for the semiconductor device 100 according to embodiment 1. Figures 6 and 7 are, respectively, an AB cross-sectional view of the active region 101 and a CD cross-sectional view of the circumferential region after the steps of forming the diffusion layers, MOS gates, interlayer layers, and wiring have been completed. The steps up to this point can be performed by a general semiconductor process; therefore, a description of this process is omitted. Next, a titanium layer 26 is formed on the metal layers 13 and 24 using a sputtering technique or the like. Figures 8 and 9 are cross-sectional views, taken along lines AB and CD respectively, in the state where the titanium layer 26 has been formed. Next, a masking agent structure is formed using a general photolithography technique. Figures 10 and 11 are cross-sectional views, taken along lines AB and CD respectively, in the state where the masking agent 27 has been structured. Next, the Ti layer 26 is etched using the masking agent 27 as a mask. Subsequently, the metal layer 25 is formed at the predetermined position. Figures 12 and 13 are cross-sectional views, taken along lines AB and CD respectively, in the state where the metal layer 25 has been formed. At this time, the size, position, etc., of the masking agent 27 are adjusted as necessary so that the metal layer 25 can cover the metal layers 23 and 24. Next, after removal of the masking agent 27, a nitride layer 28 is formed using a process such as deposition. Figures 14 and 15 are cross-sectional views, taken along lines AB and CD respectively, in a state where the nitride layer 28 has been formed. Furthermore, masking agent structuring is carried out using a general photolithography technique. Figures 16 and 17 are cross-sectional views, taken along lines AB and CD respectively, in a state where the masking agent 27 has been formed. Next, the nitride layer 28 is etched using the masking agent 27 as a mask to form the protective layer 19 at a predetermined position. Figures 18 and 19 are cross-sectional views, taken along lines AB and CD respectively, in a state where the protective layer 19 has been formed. At this time, the size, position, etc., of the masking agent 27 are adjusted so that the area where the metal layer 23 or the metal layer 24 and the metal layer 25 are in contact with each other is completely covered by the protective layer 19. Next, the masking agent 27 is removed. Figures 20 and 21 are cross-sectional views, taken along lines AB and CD respectively, in a state where the masking agent 27 has been removed. The subsequent steps can be carried out by a general semiconductor process; therefore, a description thereof is omitted. The operation of the semiconductor device 100 is described next. When a positive voltage applied to the gate junction 103 is equal to or greater than the MOSFET's threshold voltage, the MOSFET turns on. As a result, the drain voltage drops, a main current flows between the source and the drain, and the semiconductor device 100 switches to the ON state. Conversely, when the negative voltage applied to the gate junction 103 in the ON state becomes equal to or less than the threshold voltage, the MOSFET turns off. As a result, the current between the source and the drain is interrupted, the drain voltage rises, and the semiconductor device 100 switches to the OFF state. In the off state, a depletion layer extends laterally from the side of the active region 101 towards the end of the termination region 104. At this time, the electric field strength is set to a predetermined value or less by the FLR layer 16 and the channel stopper layer 17. Therefore, the gate wiring 42, which is formed in the region closest to the termination region 104 at the end of the active region 101, is more susceptible to the influence of the drain voltage than the active region 101 itself. Furthermore, in high-temperature and high-humidity environments, moisture can penetrate the device while ionization occurs from the outside. In particular, in injection-molded products, there is a risk of moisture penetrating from the chip end through the resin interface. Thus, especially in the periphery of the chip, the metal layer 23 of the gate wiring 42, which consists of Al, is more susceptible to corrosion than other areas due to the effects of temperature, humidity, and electric field. In contrast, in this embodiment, the Al metal layer 23 is covered with the metal layer 25, which is a Ti electrode exhibiting excellent corrosion resistance. Therefore, it is possible to improve moisture or acid resistance and enhance THB (temperature-humidity bias) resistance. Furthermore, in the gate wiring 42, the top surface and both side surfaces of the metal layer 23 are completely covered by the metal layer 25. In other words, the contact area between the metal layer 23 and the metal layer 25 is not exposed to the component located on the protective layer 19. This prevents the contact area between two types of metals, such as Al and Ti, from being exposed to the protective layer 20, the sealing resin, etc., and from being subjected to moisture. Therefore, it is possible to prevent metal corrosion caused by the local battery effect and to further improve moisture and acid resistance. Furthermore, the gate wiring 42 is covered with a protective layer 19. This makes it possible to further prevent the ingress of moisture and to improve moisture or acid resistance. In particular, by covering the entire upper surface and both side surfaces of the gate wiring 42 with the protective layer 19, it is possible to further improve moisture or acid resistance. Furthermore, part of the active area 101 must be bonded to an electrode of the housing by a process such as wire bonding or solder bonding. Therefore, parts of the metal layers 13 and 24 are exposed. That is, the contact electrode 41 has a contact opening 41a where the metal layer 24 is exposed by the metal layer 25. In the contact opening 41a, the metal layer 24 is not covered by the metal layer 25. Therefore, there is a risk that the contact area between the metal layers 24 and 25, that is, the end portion of the metal layer 25, may be exposed at a position opposite the contact opening 41a. In contrast, in this embodiment, the contact area between metal layer 24 and metal layer 25, opposite the contact point opening 41a, is covered with the protective layer 19. This means that in the contact point electrode 41, the contact area between metal layer 24 and metal layer 25 is not exposed to the component provided on the protective layer 19. Therefore, galvanic corrosion and local battery effects can be prevented, and moisture and acid resistance can be further improved. In this embodiment, the protective layer 20, which is a polyimide layer, is further applied to the protective layer 19. This makes it possible to mitigate stress, particularly in cast-sealed products. Furthermore, the protective layer 20 covers the corners of the gate wiring 42 and the contact electrode 41. This makes it possible to mitigate stress in areas where stress is likely to occur, such as steps in the wiring. In this embodiment, the metal layer 25 consists of Ti. It is desirable to set the thickness of this Ti layer so that no pores are generated, and considering the effect on etching and wafer warping, it is desirable to set the thickness at approximately 200 to 3000 Å. Furthermore, the metal layer 25 can be formed from a material containing Ti, Au, or Pt, which exhibits excellent moisture resistance. The metal layer 25 can comprise a metal that has higher moisture or acid resistance than the metal layers 23 and 24. In this embodiment, the metal layers 23 and 24 consist of Al. However, the metal layers 23 and 24 can also consist of Al or Cu. The metal layers 23 and 24 are not limited to pure Al, but can be AlSi or AlSiCu, or can be a wiring consisting mainly of Cu. The thickness of the nitride layer, serving as the protective layer 19, is desirablely set at a thickness that does not cause cracking in the layer under operating temperature conditions, and is desirablely approximately 5000 to 30000 Å, taking into account the effect on etching and wafer warping. The protective layer 19 can be an oxide layer. The protective layer 19 can be a glass coating, such as a plasma nitride layer or a plasma oxide layer. In this embodiment, in the gate wiring 42, which is located closest to the termination area 104 in the gate wiring area 102, the contact area between the metal layer 23 and the metal layer 24 is not exposed to the component provided on the protective layer 19. However, it is sufficient that in one of the wiring connections provided in the wiring area between the active area 101 and the termination area 104, the contact area between the metal layer 23 and the metal layer 24 is not exposed to the component provided on the protective layer 19. Such a configuration, in which the contact area of ​​different metal layers is not exposed, can be used in any wiring configuration on the semiconductor substrate 1. As described above, the configuration in which the contact area of ​​different metal layers is not exposed is particularly effective when used in wiring on the periphery of a chip, but the effect of improving moisture and acid resistance can be obtained regardless of whether it is used in wiring. For example, a configuration in which the contact area between metal layer 24 and metal layer 25 is not exposed may be used in the contact electrode 41, and the above configuration may not be used in the gate wiring 42. Similarly, a configuration in which the contact area between metal layer 23 and metal layer 25 is not exposed may be used in the gate wiring 42, and the above configuration may not be used in the contact electrode 41. Furthermore, "the contact area of ​​the different metal layers is not exposed to the component provided on the protective layer" means that the end portion of the contact surface of the different metal layers is not exposed to the component provided on the protective layer 19. In the example shown in Fig. 5, the top surface and both side surfaces of the gate wiring 42 are completely covered by the protective layer 19. The protective layer 19 is not limited to this, and it is sufficient that the protective layer 19 covers at least a portion of the gate wiring 42. For example, the protective layer 19 can extend from the top surface of the metal layer 25 to both side surfaces of the metal layer 23, covering only a portion of the gate wiring 42. This configuration also makes it possible to improve the moisture or acid resistance provided by the metal layer 25 and the protective layer 19. It is preferred that the contact area between the metal layers 23 and 25 and the contact area between the metal layers 24 and 25 are not exposed, but a portion of them may be exposed within a permissible extent. The semiconductor substrate 1 can be a silicon substrate or can consist of a wide-bandgap semiconductor. The wide-bandgap semiconductor is silicon carbide, a gallium nitride-based material, or diamond. Furthermore, the semiconductor device 100 is not limited to a MOSFET but can be another device, such as an IGBT. The modifications mentioned above can be suitably applied to the semiconductor device according to the following embodiments. The semiconductor device according to the following embodiments has many similarities with embodiment 1; therefore, the following description will focus on the differences compared to embodiment 1. Design 2 Fig. 22 is an enlarged view of the edge region 107 of the active region 101 according to embodiment 2. Fig. 23 is a cross-sectional view obtained by cutting Fig. 22 along line CD. This embodiment differs from embodiment 1 in that the metal layer 25 is provided only on the upper surfaces of metal layers 23 and 24. In other words, the side surfaces of metal layer 23 and the side surfaces of metal layer 24 are exposed by the metal layer 25. The remaining configuration is the same as that of embodiment 1. In this embodiment, metal layers 23 and 24 are partially covered by metal layer 25 to improve moisture resistance. Furthermore, in the gate wiring 42, a protective layer 19 extends from the upper surface of metal layer 25 to both side surfaces of metal layer 23. Therefore, even if metal layer 25 is only present on the upper surface of metal layer 23, the end of the contact surface between metal layer 23 and metal layer 25 can be covered by the protective layer 19. The end of the contact surface between metal layer 24 and metal layer 25 is also covered by the protective layer 19. This improves moisture resistance and acid resistance. As in embodiment 1, the protective layer 19 does not need to cover the entire gate wiring 42. The protective layer 19 can extend from the upper surface of the metal layer 25 to both side surfaces of the metal layer 23. Furthermore, the protective layer 19 can extend from the upper surface of the metal layer 25 to the side surface of the metal layer 24. This allows the end region of the metal layer 25 to be covered by the protective layer 19. embodiment 3 Fig. 24 is an enlarged view of the edge region 107 of the active region 101 according to embodiment 3. Fig. 25 is a cross-sectional view obtained by cutting Fig. 24 along line CD. The present embodiment differs from embodiment 1 in that the metal layer 24 of the contact electrode 41 is also completely covered with the metal layer 25. The remaining configuration is similar to that of embodiment 1. In this embodiment, the upper and side surfaces of the metal layers 23 and 24, which are Al electrodes, are all covered with the metal layer 25, which is a Ti electrode. This prevents the contact area between the metal layer 23 or the metal layer 24 and the metal layer 25 from being exposed, thereby improving moisture or acid resistance. Furthermore, covering part of the gate wiring 42 and the contact electrode 41 with the protective layer 19 can further improve moisture or acid resistance. Design 4 Fig. 26 is an enlarged view of the edge region 107 of the active region 101 according to embodiment 4. Fig. 27 is a cross-sectional view obtained by cutting Fig. 26 along line CD. The present embodiment differs from embodiment 1 in that the contact area between the metal layer 24 and the metal layer 25 in the contact electrode 41 is exposed to the protective layer 19. The remaining configuration is similar to that of embodiment 1. In this embodiment, the moisture resistance of the contact electrode 41 is lower than that in embodiment 1. However, the contact area between the metal layer 23 and the metal layer 25 in the gate wiring 42 is not exposed to the component provided on the protective layer 19.This makes it possible to improve moisture resistance or acid resistance in areas susceptible to the effects of temperature, humidity and electric fields. Design 5 Fig. 28 is a top view of a semiconductor device 100 according to embodiment 5. Fig. 29 is an enlarged view of the edge region 107 of the active region 101 according to embodiment 5. Fig. 30 is a cross-sectional view obtained by cutting Fig. 29 along line EF. In this embodiment, a source-cladding wiring region 108 is provided between the gate-cladding region 102 and the termination region 104. The source-cladding wiring region 108 is a region of the semiconductor substrate 1 where source-cladding wiring 48 is provided. In the source-cladding wiring region 108, a metal layer 32, which is an Al electrode, is formed on the barrier metal layer 22. The Ti metal layer 25 is formed on the metal layer 32. The barrier metal layer 22, the metal layer 32, and the metal layer 25 formed on the metal layer 32 constitute the source-cladding wiring 48. The source-cladding wiring 48 is connected to the trough layer 4 and the contact layer 6 via a contact hole 31. The source-cladding wiring 48 is connected to the source electrode of the active region 101. In this embodiment, the upper surface and both side surfaces of the metal layer 32 in the source-sheath wiring 48 are completely covered with the metal layer 25. Therefore, the contact area between the metal layer 32 and the metal layer 25 is not exposed to the component provided on the protective layer 19. Furthermore, the upper surface and both side surfaces of the source-sheath wiring 48 are completely covered with a protective layer 19. This can improve moisture resistance or acid resistance. In this embodiment, the source-sheath wiring 48 is the wiring located closest to the termination area 104. Therefore, taking into account the penetration path of moisture and the electrical field distribution in the termination area 104, the source-sheath wiring 48 is protected by the metal layer 25 and the protective layer 19, in addition to the gate wiring 42. It is also possible to protect only one of the gate wiring 42 and the source cladding wiring 48. Furthermore, an example has been shown in the present embodiment in which source wiring is provided in the wiring area, but in the case where the semiconductor device 100 is an IGBT, emitter wiring can be provided. However, technical features that are explained in each embodiment can be combined to suit a particular use. The following sections describe various aspects of the present revelation together as appendices. (Appendix 1) Semiconductor device comprising: a semiconductor substrate; wiring provided on the semiconductor substrate; and a protective layer covering at least a portion of the wiring; wherein the wiring comprises a first metal layer and a second metal layer provided on the first metal layer, the second metal layer comprising a metal having a higher resistance to moisture or acid than the first metal layer, and a contact portion between the first metal layer and the second metal layer in the wiring is not exposed to a component provided on the protective layer. (Appendix 2) Semiconductor device according to Appendix 1, wherein the semiconductor substrate has an active region, a wiring region outside the active region and a termination region outside the wiring region, and the wiring is provided in the wiring region. (Appendix 3) Semiconductor device comprising: a semiconductor substrate having an active region, a wiring region outside the active region, and a termination region outside the wiring region; wiring provided on the wiring region; and a protective layer covering at least a portion of the wiring; wherein the wiring comprises a first metal layer and a second metal layer provided on the first metal layer, the second metal layer comprising a metal having a higher resistance to moisture or acid than the first metal layer; and the protective layer extending from an upper surface of the second metal layer to both side surfaces of the first metal layer. (Appendix 4) Semiconductor device according to Appendix 3, wherein a contact part area between the first metal layer and the second metal layer in the wiring is not exposed to a component that is provided on the protective layer. (Appendix 5) Semiconductor device according to one of Appendices 2 to 4, wherein the wiring is a wiring that is provided closest to the termination area in the wiring area. (Appendix 6) Semiconductor device according to any of Appendices 1 to 5, wherein a top surface and both side surfaces of the first metal layer are completely covered with the second metal layer. (Appendix 7) Semiconductor device according to one of Appendices 2 to 5, further comprising a contact electrode having a third metal layer provided on the active area and a fourth metal layer provided on the third metal layer, the fourth metal layer having a metal having a higher resistance to moisture or acid than the third metal layer, wherein a contact opening is formed in the contact electrode in which the third metal layer is exposed from the fourth metal layer, and a contact area between the third metal layer and the fourth metal layer, opposite the contact opening, is covered with the protective layer. (Appendix 8) Semiconductor device according to one of Appendices 1 to 7, wherein the wiring is a gate wiring. (Appendix 9) Semiconductor device according to any one of Appendices 1 to 7, wherein the wiring is a source wiring or an emitter wiring. (Appendix 10) Semiconductor device according to any of Appendices 1 to 9, wherein the second metal layer comprises Ti, Au or Pt. (Appendix 11) Semiconductor device according to one of Appendices 1 to 10, wherein the first metal layer comprises Al or Cu. (Appendix 12) Semiconductor device according to one of Appendices 1 to 11, further comprising a polyimide layer provided on the protective layer. (Appendix 13) Semiconductor device according to Appendix 12, wherein the polyimide layer covers one corner of the wiring. (Appendix 14) Semiconductor device according to any of Appendices 1 to 13, wherein the protective layer is a nitride layer or an oxide layer. (Appendix 15) Semiconductor device according to one of Appendices 1 to 14, wherein the semiconductor substrate is made with a wide bandgap semiconductor. (Appendix 16) Semiconductor device according to Appendix 15, wherein the wide bandgap semiconductor is silicon carbide, a gallium nitride-based material or diamond. (Appendix 17) Semiconductor device comprising: a semiconductor substrate; a contact electrode provided on the semiconductor substrate; and a protective layer provided on the contact electrode; wherein the contact electrode has a first metal layer and a second metal layer provided on the first metal layer, the second metal layer having a metal that has a higher resistance to moisture or acid than the first metal layer; a contact opening is formed in the contact electrode in which the first metal layer is exposed by the second metal layer; and a contact area between the first metal layer and the second metal layer, opposite the contact opening, is covered with the protective layer. In the semiconductor device according to the first disclosure, the contact area between the first metal layer and the second metal layer is not exposed to the component provided on the protective layer. Therefore, the moisture resistance or acid resistance can be improved. In the semiconductor device according to the second disclosure, a protective layer is provided extending from the upper surface of the second metal layer to both side surfaces of the first metal layer. Therefore, the moisture resistance or acid resistance can be improved. In the semiconductor device according to the third disclosure, the contact area between the first metal layer and the second metal layer, which faces the contact point opening, is covered with a protective layer. Therefore, the moisture resistance or acid resistance can be improved. In light of the foregoing teachings, it is evident that many modifications and variations of the present disclosure are possible. It should therefore be understood that, within the scope of protection of the appended claims, the disclosure may be implemented differently than expressly described. The entire disclosure of Japanese patent application No. 2024-229253, filed on December 25, 2024, including the description, claims, drawings and abstract on which the priority of the present application is based, is incorporated herein by reference in its entirety. QUOTES INCLUDED IN THE DESCRIPTION This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature WO 2021 / 064944 A1 [0002, 0004] JP 2024-229253

[0080]

Claims

Semiconductor device (100) comprising: a semiconductor substrate (1); wiring (42, 48) provided on the semiconductor substrate (1); and a protective layer (19) covering at least a portion of the wiring (42, 48); wherein the wiring (42, 48) comprises a first metal layer (23, 32) and a second metal layer (25) provided on the first metal layer (23, 32), the second metal layer (25) comprising a metal having a higher resistance to moisture or acid than the first metal layer (23, 32), and a contact portion between the first metal layer (23, 32) and the second metal layer (25) in the wiring (42, 48) is not exposed to a component provided on the protective layer (19). Semiconductor device (100) according to claim 1, wherein the semiconductor substrate (1) has an active region (101), a wiring region (102, 108) outside the active region (101) and a termination region (104) outside the wiring region (102, 108), and the wiring (42, 48) is provided in the wiring region (102, 108). Semiconductor device (100) comprising: a semiconductor substrate (1) having an active region (101), a wiring region (102, 108) outside the active region (101) and a termination region (104) outside the wiring region (102, 108); wiring (42, 48) provided on the wiring region (102, 108); and a protective layer (19) covering at least a portion of the wiring (42, 48); wherein the wiring (42, 48) comprises a first metal layer (23, 32) and a second metal layer (25) provided on the first metal layer (23, 32), the second metal layer (25) comprising a metal having a higher resistance to moisture or acid than the first metal layer (23, 32); and the protective layer (19) extends from an upper surface of the second metal layer (25) to both side surfaces of the first metal layer (23, 32). Semiconductor device (100) according to claim 3, wherein a contact part area between the first metal layer (23, 32) and the second metal layer (25) in the wiring (42, 48) is not exposed to a component that is provided on the protective layer (19). Semiconductor device (100) according to one of claims 2 to 4, wherein the wiring (42, 48) is a wiring which is provided closest to the termination area (104) in the wiring area (102, 108). Semiconductor device (100) according to any one of claims 1 to 5, wherein an upper surface and both side surfaces of the first metal layer (23, 32) are completely covered with the second metal layer (25). Semiconductor device (100) according to one of claims 2 to 4, further comprising a contact electrode (41) comprising a third metal layer (24) provided on the active area (101) and a fourth metal layer (25) provided on the third metal layer (24), the fourth metal layer (25) comprising a metal having a higher moisture resistance or acid resistance than the third metal layer (24), wherein a contact opening (41a) is formed in the contact electrode (41) in which the third metal layer (24) is exposed by the fourth metal layer (25), and a contact area between the third metal layer (24) and the fourth metal layer (25), opposite the contact opening (41a), is covered with the protective layer (19). Semiconductor device (100) according to one of claims 1 to 7, wherein the wiring (42) is a gate wiring (42). Semiconductor device (100) according to any one of claims 1 to 7, wherein the wiring (48) is a source wiring (48) or an emitter wiring (48). Semiconductor device (100) according to any one of claims 1 to 9, wherein the second metal layer (25) comprises Ti, Au or Pt. Semiconductor device (100) according to one of claims 1 to 10, wherein the first metal layer (23, 32) comprises Al or Cu. Semiconductor device (100) according to one of claims 1 to 11, further comprising a polyimide layer (20) provided on the protective layer (19). Semiconductor device (100) according to claim 12, wherein the polyimide layer (20) covers a corner of the wiring (42, 48). Semiconductor device (100) according to any one of claims 1 to 13, wherein the protective layer (19) is a nitride layer or an oxide layer. Semiconductor device (100) according to one of claims 1 to 14, wherein the semiconductor substrate (1) is made with a wide bandgap semiconductor. Semiconductor device (100) according to claim 15, wherein the wide bandgap semiconductor is silicon carbide, a gallium nitride-based material or diamond. Semiconductor device (100) comprising: a semiconductor substrate (1); a contact electrode (41) provided on the semiconductor substrate (1); and a protective layer (19) provided on the contact electrode (41); wherein the contact electrode (41) comprises a first metal layer (24) and a second metal layer (25) provided on the first metal layer (24), the second metal layer (25) comprising a metal having a higher resistance to moisture or acid than the first metal layer (24); a contact opening (41a) is formed in the contact electrode (41) in which the first metal layer (24) is exposed from the second metal layer (25); and a contact area between the first metal layer (24) and the second metal layer (25), opposite the contact opening (41a), is covered with the protective layer (19).

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