METAL GATE BACKS IN SEMICONDUCTOR DEVICES

DE102025149799A1Undetermined Publication Date: 2026-07-09TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
DE102025149799
Authority / Receiving Office
DE · DE
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-04-11
Filing Date
2025-12-01
Publication Date
2026-07-09
Patent Text Reader

Abstract

A method comprises forming upper semiconductor channels for an upper device over lower semiconductor channels for a lower device; forming a high-k-gate dielectric layer that wraps around each of the upper and lower semiconductor channels; forming a first gate metal over the high-k-gate dielectric layer; back-etching the first gate metal to expose upper portions of the high-k-gate dielectric layer while leaving lower portions of the high-k-gate dielectric layer, the back-etching comprising dry etching to etch the first gate metal and produce a copolymer by-product that covers the exposed upper portions of the high-k-gate dielectric layer;and performing a post-cleaning process to remove the copolymer by-product, wherein the post-cleaning process includes a first wet cleaning to remove silicon oxide components of the copolymer by-product and a second wet cleaning to remove metal oxide components of the copolymer by-product.
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Citation Information

Patent Citations

  • US63742600B1

  • USPATENTANMELDUNGNR.63/742,600