Semiconductor device

Abstract

Semiconductor device (1) comprising: an insulating substrate (2) formed such that a metal plate (3), an insulating resin plate (4) and a circuit plate (5) are laminated in that order; a semiconductor element (6) that is attached to the circuit board (5) of the insulating substrate (2); a wiring element (8) which is connected to an electrode arranged on a front surface of the semiconductor element (6) or to the circuit board (5) of the insulating substrate (2); a housing (10) which accommodates the insulating substrate (2), the semiconductor element (6) and the wiring element (8); and a potting material (13) which contains a thermosetting resin, wherein the potting material (13) seals the insulating substrate (2), the semiconductor element (6) and the wiring element (8) which are housed in the casing (10); wherein the circuit plate (5) of the insulating substrate (2) on the insulating resin plate (4) is selectively formed as a combination of a circuit pattern (5A) with a potting material bonding pattern (5B), wherein the potting material bonding pattern (5B) includes an opening (5B1) or a recess (5B2) which is arranged in the circuit board (5), wherein the potting material bonding pattern (5B) is arranged between the semiconductor element (6) attached to the circuit board (5) and an end of the wiring element (8) which is attached to the circuit board (5), and wherein the potting material (13) is in contact with and adheres to the insulating resin plate (4) of the insulating substrate (2) in the region of the interior of the opening (5B1) or the recess (5B2).

Description

Technical field

[0001] The present invention relates to a semiconductor device. State of the art

[0002] A power semiconductor module, in which one or more semiconductor elements (semiconductor chips) are provided in a housing sealed with a potting compound, is known as a semiconductor device. The power semiconductor module is designed, for example, such that the power semiconductor element is mounted on an insulating substrate. The insulating substrate consists of a metal plate, an insulating resin plate formed on a surface of the metal plate, and a circuit plate in which a predetermined circuit is formed such that a conductive metal foil, such as a copper foil, is selectively formed on the insulating resin plate. The metal plate consists of copper foil with excellent conductivity. Furthermore, the insulating resin plate consists of an insulating resin.

[0003] The power semiconductor element is soldered to the circuit board of the insulating substrate, so that an electrode located on one surface of the power semiconductor element is electrically connected to the circuit board. Furthermore, an electrical connection can be achieved using bonding wires or similar materials between another electrode located on the other surface of the power semiconductor element, the circuit board, the external connections, and so on.

[0004] The power semiconductor chip is housed in a package. A thermosetting resin potting compound is then injected to cover the power semiconductor chip and the bonding wires within the package. This protects and insulates the semiconductor chip, bonding wires, circuit board, and other components inside the package.

[0005] The thermoset resin potting compound exhibits lower adhesion to the circuit board of the insulating substrate than to the insulating resin plate. Furthermore, the coefficient of thermal expansion of the potting compound differs from that of the circuit board. Therefore, it is likely that the potting compound will detach from the interface between the potting compound and the circuit board of the insulating substrate, as heat is repeatedly generated during the operation of the power semiconductor chip. If the detachment of the potting compound progresses to the point where it reaches a bonding wire connection, it can affect the condition of the bonding wire.

[0006] To improve the adhesive properties between the potting material and the circuit board of the insulating substrate, a semiconductor device was provided in which many micro-recessed parts are formed in the part in which the semiconductor chip is glued (patent literature 1), except for the area in which a semiconductor chip is mounted on the front surface of the circuit board.

[0007] US 5,539,253 A discloses a resin-sealed semiconductor device comprising a heat sink on which a semiconductor chip is mounted. An output terminal is connected to the semiconductor chip. A housing surrounds the chip and part of the output terminal. The interior of the housing is filled with a sealing resin containing an aggregate such as glass particles. The chip is mounted in the area of ​​an upper surface of the heat sink, and the remaining area is covered with an epoxy resin film 10 µm to 20 µm thick.

[0008] US 2005 / 0263482A1 discloses a method for manufacturing a circuit assembly in which upwardly projecting sections are formed in a portion of a conductive pattern formed on the front face of a circuit substrate. The front face of the circuit substrate, including the projecting sections, is then coated with a coating resin. The coating resin is then etched to expose the top surfaces of the projecting sections. The circuit elements are then fixed and electrically connected. Finally, an electrical circuit formed on the front face is sealed, thus completing a hybrid integrated circuit device. List of printed works and patent literature

[0009] Patent literature 1: Japanese unexamined patent disclosure JP 2004 - 186 662 A Disclosure of the invention Problem to be solved by the invention

[0010] However, forming a large number of micro-recessed parts on the front surface of a circuit board is very time-consuming. This leads to an increase in manufacturing costs, which in turn results in a decrease in production efficiency.

[0011] In order to advantageously solve the problem described above, it is therefore an object of the present invention to provide a semiconductor device which makes it possible to improve the adhesive properties between a circuit board of an insulating substrate and a potting resin containing a thermosetting resin. Means of solving the problems

[0012] According to one aspect of the present invention, a semiconductor device is provided comprising: an insulating substrate constructed such that a metal plate, an insulating resin plate, and a circuit plate are laminated in that order; a semiconductor element attached to the circuit plate of the insulating substrate; a wiring element connected to an electrode arranged on the front surface of the semiconductor element or to the circuit plate of the insulating substrate; a housing accommodating the insulating substrate, the semiconductor element, and the wiring element; and a potting material enclosing a thermosetting resin, wherein the potting material seals the insulating substrate, the semiconductor element, and the wiring element housed in the housing.wherein the circuit board of the insulating substrate is selectively formed as a combination of a circuit pattern with a potting compound bonding pattern on the insulating resin board, wherein the potting compound bonding pattern includes an opening or a recess arranged in the circuit board, wherein the potting compound bonding pattern is arranged between the semiconductor element attached to the circuit board and an end of the wiring element attached to the circuit board, and wherein the potting compound is in contact with and adheres to the insulating resin board of the insulating substrate in the region of the interior of the opening or recess. Impact of the invention

[0013] According to the embodiment described above, the circuit board of the insulating substrate is selectively formed as the combination of the circuit pattern with the potting compound bonding pattern. Since the potting compound is in contact with the insulating resin board of the insulating substrate in the part where the potting compound bonding pattern is located, an improvement in adhesion properties is achieved compared to a conventional semiconductor device in contact with the circuit board. Consequently, this can prevent delamination from progressing to the bonding wire connection point. Brief description of the drawings Fig. Figure 1 shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. Fig. Figure 2 shows a top view of the semiconductor device according to one embodiment of the present invention. Fig. Figure 3 shows a top view of an insulating substrate in Fig. 2 represents the semiconductor device shown. Fig. Figure 4 presents a diagram in which the adhesion strength between a thermosetting resin used as a potting material and an insulating resin used in an insulating resin board, and also between the thermosetting resin and the copper foil used in a circuit board, is investigated. Fig. Figure 5 shows a top view of a conventional semiconductor device. Fig. Figure 6 shows a top view of an insulating substrate in Fig. 5 represents the semiconductor device shown. Implementation methods of the invention

[0014] Embodiments of a semiconductor device of the present invention are described in detail below with reference to the drawings.

[0015] Fig. Figure 1 shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. Fig. Figure 2 shows a top view of the semiconductor device according to one embodiment of the present invention. Fig. Figure 3 shows a top view of an insulating substrate in Fig. 2 represents the semiconductor device shown. Fig. Figure 1a shows an outline of the cross-sectional view along the in Fig. 2 shown line 1A-1A, and Fig. 1b shows an outline of the cross-sectional view along the in Fig. 2 shown line 1B-1B.

[0016] A semiconductor device 1 according to the present embodiment comprises an insulating substrate 2 on which a semiconductor chip 6 is attached with solder 7, which is a bonding material. The insulating substrate 2 is formed from a metal plate 3, an insulating resin plate 4 laminated onto one of the surfaces of the metal plate 3, and a circuit board 5 laminated onto the insulating resin plate 4.

[0017] The metal plate 3 of the insulating substrate 2 consists of a metal material with excellent thermal conductivity, such as aluminum or copper. The insulating resin plate 4 consists of an insulating resin. Any resin with insulating properties is suitable for the insulating resin plate 4. However, the resin preferably has excellent thermal conductivity so that heat can be dissipated from the semiconductor chip 6. Materials such as a liquid crystal polymer, which has excellent thermal conductivity, and an epoxy resin, which is the same material as a potting compound 13 described below, can be used for the insulating resin plate 4 of the insulating substrate 2. The insulating resin plate 4 can be formed by applying the resins described above to the metal plate 3.

[0018] The circuit board 5 of the insulating substrate 2, which consists of a metal material with excellent electrical conductivity, such as copper, is selectively formed on a surface of the insulating resin board 4, so that a predetermined circuit can be configured using a conductive metal foil, such as copper foil. The semiconductor chip 6 is attached to a surface of the circuit board 5 by solder 7. A groove 7a of the solder 7 is formed around the circumference of the semiconductor chip 6 on the side where the circuit board 5 is located. Furthermore, one end of the bonding wire 8, which is a wiring element, is attached to one surface of the circuit board 5. Various electronic components, such as a capacitor chip, can also be attached to one surface of the circuit board 5.

[0019] The semiconductor chip 6 can be, for example, a diode chip, a MOSFET power chip, or an insulated-gate bipolar transistor (IGBT) chip. The specific type of semiconductor chip is not important. When multiple semiconductor chips 6 are arranged on the circuit board 5 of the insulating substrate 2, the chips can be of the same type or a combination of different semiconductor chips. If the semiconductor chip 6 is a vertical semiconductor element, two electrodes are provided on its opposite main surfaces. One electrode located on one of the main surfaces is electrically connected to the circuit board 5 by the solder 7. One end of the bonding wire 8 is attached to the other electrode, which is located on the other main surface. Additionally, the semiconductor element 6 can be a lateral semiconductor element, without being restricted to a vertical semiconductor element.

[0020] The one in the Fig. 1 and Fig. The bonding wire 8 shown in Figure 2 consists of a thin, conductive conductor made of aluminum, aluminum alloy, or the like. However, the wiring element is not limited to the bonding wire 8 and can also be, for example, a busbar. Furthermore, it can be a combination of a conductor pin and a wiring board (for example, a printed circuit board).

[0021] The insulating substrate 2, the semiconductor chip 6, and the bonding wire 8 are housed in a casing 10. The casing 10 includes an integrated conductor 11, which is electrically connected to the outside. In the semiconductor device 1 according to the present embodiment, a conductor 11 is provided which extends from the side of the inner surface of the casing 10 to the outside, so that it projects beyond its outer surface. On the side of the inner surface of the casing 10, the conductor 11 is joined to the other end of the bonding wire 8, one end of which connects the semiconductor chip 6 and the circuit board 5 of the insulating substrate 2.

[0022] The housing 10 is formed from another insulating resin and the like. The lower end of the housing 10 is joined to the circumference of the metal plate 3 and the insulating resin plate 4 of the insulating substrate 2 by means of an insulating adhesive 12. This ensures that the insulating properties between the insulating substrate 2 and the housing 10 are maintained and eliminates any gap between the insulating substrate 2 and the housing 10. This prevents the potting material 13 from escaping through the gap.

[0023] The potting material 13 is poured into a cavity through the upper end of the housing 10, so that the circuit board 5 of the insulating substrate 2, the semiconductor chip 6, and the bonding wire 8 are each potted with it. A potting material 13 composed of a thermosetting resin, such as an epoxy resin, is preferable because it exhibits excellent thermal resistance properties and high insulating properties.

[0024] Fig. 1a and Fig. Figure 1b each represents an overview of the cross-sectional view of the semiconductor device 1 according to the present embodiment. Fig. 2 shows a top view of the Fig. 1 represents the semiconductor device 1 shown in the present embodiment.

[0025] As in Fig. As shown in Figure 1a, semiconductor chips 61 and 62 are mounted on a circuit board 5, which is a single board. The circuit board 5 is connected to the line 11 (left side in the figure) by means of the bonding wire 8. Another bonding wire 8, attached to the other main surface of semiconductor chip 61, is connected to another circuit board 5 on which a semiconductor chip 63 is mounted. Furthermore, another bonding wire 8, attached to the other main surface of semiconductor chip 62, is attached to yet another circuit board 5 on which a semiconductor chip 64 is mounted.

[0026] As in Fig. As shown in Figure 1b, the semiconductor chips 63 and 64 are mounted on their respective circuit boards 5, which are arranged adjacent to each other and electrically isolated. A further bonding wire 8, attached to the other main surface of the semiconductor chip 63, is connected to a circuit pattern 5A, which is located on the right side of the Fig. 2 is shown. Another bonding wire 8, attached to the other main surface of the semiconductor chip 64, is attached to the circuit pattern 5A, which is the same as described above and is used jointly. The jointly used circuit pattern 5A is connected to line 11 (left side of the figure) by another bonding wire 8. Furthermore, the circuit board 5, on which the semiconductor chip 63 is mounted, is connected to line 11 (right side of the figure) by another bonding wire 8. To interpret the configuration described above, the jointly used circuit pattern 5A, shown on the right side in the figure, is shown in the diagram. Fig. 2 circuit patterns shown 5A in Fig. 1b shown slightly distorted.

[0027] The housing 10 of the semiconductor device 1, shown in the figure, consists of insulating resin, such as PPS resin or the like, and has an almost cuboid shape containing a cavity, thus forming a frame. The housing 10 accommodates the insulating substrate 2, four semiconductor chips 6 (61, 62, 63, and 64), and the bonding wires 8 in the cavity. The circuit boards 5 of the insulating substrate 2 and the Fig. The bonding wires 8 shown in Figure 2 are arranged such that the semiconductor chips 61, 62, 63 and 64 can function as switching elements. Additionally, a representation of the potting material 13 is shown in Figure 2. Fig. 2 omitted to facilitate understanding of the present invention.

[0028] In a Fig. In the example shown, one circuit board 5, in which the semiconductor chip 61 is mounted, is arranged adjacent to another circuit board 5, which has an almost L-shape and on which the semiconductor chip 63 is mounted on the insulating resin board 4. Electrodes (not shown) are arranged on the two respective opposing main surfaces of the semiconductor chip 61 and the semiconductor chip 63. In the almost L-shaped circuit board 5, a plurality of openings 5B1 are formed together with the concave groove 7a, which are arranged under the semiconductor chip 63 as a potting compound bonding pattern 5B between an area in which the semiconductor chip 63 is mounted and another area in which the bonding wire 8 is attached. Two groups of bonding wires 8 are attached to the almost L-shaped circuit board 5.One group of bonding wires 8 is attached to the other main surface of the semiconductor chip 61, thereby electrically connecting the electrode located on one main surface of the semiconductor chip 63 in series with the other main surface of the semiconductor chip 61. The other group of bonding wires 8 is attached to the conductor 11, thereby electrically connecting the electrode located on one main surface of the semiconductor chip 63 with the conductor 11. Since the potting compound bonding pattern 5B is formed between the groove 7a located under the semiconductor chip 63 and the two groups of bonding wires 8, with each group being bonded at different locations, the delamination of the potting compound 13 occurring at the groove 7a can be prevented from progressing to the sides where the bonding wires 8 are bonded.

[0029] In the insulating substrate 2, each of the circuit plates 5, to which the semiconductor chip 61, 62, 63, or 64 is attached, is selectively formed on the insulating resin plate 4 such that the predetermined circuit pattern 5A is combined with the potting compound bonding pattern 5B. The circuit pattern (circuit section) is a conductive metal foil in which a circuit wiring diagram is formed, and the potting compound bonding pattern 5B (connected section) is a conductive metal foil in which a pattern is formed as an opening or recess that can increase the bond strength with the potting compound. The potting compound bonding pattern 5B is, as shown in Fig. Figure 2 shows an opening 5B1 arranged in the circuit pattern 5A and a recess 5B2 arranged around the circumference of the circuit pattern 5A, which is formed such that it is opposite the interior of the circuit pattern 5A.

[0030] In the area where the potting compound bonding patterns 5B, such as the opening 5B1 and the recess 5B2, are arranged, no circuit board is formed. The potting compound 13 in the housing 10 is in contact with and adheres to the insulating resin plate 4 of the insulating substrate 2 in this area (the interior of the opening 5B1 and the recess 5B2). Compared to the circuit board 5, the insulating resin plate 4 has higher adhesive properties with the potting compound 13, so the adhesive properties with the potting compound 13 can be improved in each of the areas where potting compound bonding patterns 5B are arranged.

[0031] Fig. Figure 3 shows a top view of the insulating substrate 2. The potting compound bonding patterns 5B, such as the openings 5B1 and the recesses 5B2, are provided in each of the areas E1, E2, E3, E4, and E5, which are surrounded by dashed lines within the area where the circuit board 5 is formed. These areas E1, E2, E3, E4, and E5 are located near the point where the semiconductor chip is attached with solder 7.

[0032] The detachment of the potting compound 13, which occurs on the circuit board 5, originates, for example, from the groove 7a of the solder 7 as the starting point, spreading around the perimeter of the area where the semiconductor chip is mounted, and develops gradually. To prevent the potting compound 13 from detaching and from reaching a connection point, which is one end of the bonding wire 8, the areas E1, E2, E3, E4, and E5, in which the potting compound bonding patterns 5B are arranged, are preferably provided between the area where the semiconductor chip 6 is mounted and the connection point of the bonding wire 8.To prevent the potting material 13 from detaching further, the areas E1, E2, E3, E4, and E5 are preferably provided between the area where the semiconductor chip 6 is mounted and the connection point where the bonding wire 8 is attached to the circuit board, such that each is located near the semiconductor chip 6. Furthermore, it is preferred that the openings 5B1 and the recesses 5B2 are formed along the end portion of the semiconductor chip 6 or the groove 7a. A plurality of openings 5B1 can be arranged in several rows or in a zigzag pattern, except in a single row.

[0033] However, if the potting compound bonding patterns 5B, such as the openings 5B1 and the recesses 5B2, are positioned too close to the semiconductor chip 6, it is likely that a fillet of the solder 7, which bonds the semiconductor chip 6 to the circuit board 5, will flow into the openings 5B1 and the recesses 5B2 during manufacturing. This can reduce the effect of improving adhesion properties. For example, if the fillet of the solder 7 is approximately eight times the thickness of the solder 7, specifically approximately 100 µm thick, it may protrude approximately 0.8 mm from the end of the semiconductor chip 6. The openings 5B1 and the recesses 5B2 are preferably positioned at least 1.0 mm or approximately ten times the thickness of the solder 7 from the end of the semiconductor chip 6.

[0034] If an electronic component other than the semiconductor chip 6, such as a capacitor chip, is arranged so that it is attached to the circuit board 5 of the insulating substrate 2 by the solder 7, the potting compound bonding patterns 5B, such as the openings 5B1 and the recesses 5B2 described above, can also be arranged near the electronic component. In this case as well, the openings 5B1 and the recesses 5B2 are preferably arranged so that they are at least 1.0 mm or approximately ten times the thickness of the solder 7 away from the end part of the electronic component.

[0035] One or more openings 5B1 are arranged at nearly equal intervals in regions E1, E4, and E5. If multiple openings 5B1 are arranged without a gap between the semiconductor chip 6 and the bonding wire 8 connection point, or if a linear opening is arranged between them, such that the openings 5B1 are coupled, this improves the adhesive properties of the potting material 13. On the other hand, a current path—either from the semiconductor chip 6 through the circuit board 5 to the bonding wire 8, or in the opposite direction—will bypass the opening. Consequently, this can increase the resistance or inductance. If the openings 5B1 are arranged side by side between the semiconductor chip 6 and the bonding wire 8 connection point, it is preferable to have more than one opening at intervals.However, if the interval between the openings 5B1 is excessively long, this can reduce the effect that prevents progressive detachment from a portion of the semiconductor chip. Therefore, it is preferable that the interval between the openings 5B1 be, for example, approximately 2 mm or less.

[0036] The size and shape of opening 5B1 are not subject to any particular restrictions. In the Fig. 2 and Fig. In the present embodiment shown in Figure 3, the opening 5B1 has an elliptical shape or a shape in which semicircles are joined such that they replace the corresponding short sides of a rectangle, and has a length of approximately 2 mm in the longitudinal direction and a length of approximately 1 mm in the lateral direction. An interval between the openings is approximately 2 mm long. The length of the opening 5B1 in the lateral direction is approximately ten times the thickness of the plumb line 7.

[0037] The recess 5B2 is located in areas E1, E2, and E3. The recess 5B2 improves the adhesive properties around the perimeter of the circuit pattern 5A. The recess 5B2 can be positioned independently of or adjacent to the opening 5B1. The recess 5B2 is preferably located near the semiconductor chip 6 or other electronic component and the opening 5B1.

[0038] In the semiconductor device 1 according to the present embodiment, the circuit board 5 of the insulating substrate 2 is selectively formed not only from the circuit pattern 5A, but also from a combination of the circuit pattern 5A and the potting compound bonding pattern 5B. The presence of the opening 5B1 and the recess 5B2 of the potting compound bonding pattern 5B enables the adhesive properties with the potting compound 13 to be increased in the area where the potting compound bonding pattern 5B is provided.

[0039] Fig. Figure 4 shows a diagram illustrating the results of an investigation into the bond strength between the thermosetting resin used for the potting material and the insulating resin used for the insulating resin plate 4 of the insulating substrate 2, and between the thermosetting resin and the copper foil used for the circuit board 5. Fig. Figure 4 shows that the insulating resin exhibits a higher adhesive strength with the potting material than with the copper foil. Thus, it shows that, according to the present invention, the adhesive properties are improved because the opening 5B1 and the recess 5B allow the potting material 13 to adhere to the insulating resin plate 4 when the circuit plate 5 is configured such that the circuit pattern 5A is combined with the potting material bonding pattern 5B.

[0040] For comparison, show Fig. 5 and Fig. 6 top views of a conventional semiconductor device 101 and its insulating substrate 102, respectively.

[0041] The semiconductor device 101 comprises the insulating substrate 102. The insulating substrate 102 is configured from a metal plate (not shown), an insulating resin plate 104 laminated onto a surface of the metal plate, and a circuit plate 105 laminated onto the insulating resin plate 104. A semiconductor chip 106 is attached to a surface of the circuit 105 by solder. One end of a bonding wire 108 is attached to an electrode located on a main surface of the semiconductor chip 106.

[0042] A housing 110 accommodates the insulating substrate 102, the semiconductor chip 106, and the bonding wire 108. An electrically connected conductor 111 is integrated into the housing 110. The conductor 111 is attached to the inner surface of the housing 110 at the other end of the bonding wire 108, at one end of which the semiconductor chip 106 and the circuit board 105 of the insulating substrate 102 are attached.

[0043] The lower part of the housing 110 is attached to the circumference of the metal plate 103 and the insulating resin plate 104 of the insulating substrate 102 by the insulating adhesive (not shown). Illustrations of the potting material filled into the housing 110 were provided in the Fig. 5 and Fig. 6 omitted.

[0044] The in Fig. 5 and Fig. The conventional semiconductor device 101 shown in Figure 6 differs from the semiconductor device 1 according to the embodiment of the present invention in that the circuit board 105 of the insulating substrate 102 is selectively formed on the insulating resin board 104 using a predetermined circuit pattern. The Fig. Circuit board 105 shown in section 6 is formed only using the circuit pattern and not using the one shown in Fig. The 3 depicted potting material bonding pattern is formed. Then the opening 5B1 and the recess 5B2, which are in Fig. Figure 3 is shown, but not arranged therein. In comparison to the conventional semiconductor device 101, which contains the insulating substrate 102 comprising the circuit board 105, the semiconductor device 1 according to the present embodiment exhibits excellent adhesive properties of the potting material 13. Explanation of reference symbols 1 Semiconductor device 2 Insulating substrate 3 metal plates 4 insulating resin plates 5 circuit board 5A Circuit Pattern 5B Potting compound bonding pattern 6 Semiconductor chip (semiconductor element) 7 Lot 8 Bonding wire (wiring element) 10 Housings (accommodation) 13 Potting compound

Claims

[1] Semiconductor device (1) comprising: an insulating substrate (2) formed such that a metal plate (3), an insulating resin plate (4) and a circuit plate (5) are laminated in that order; a semiconductor element (6) that is attached to the circuit board (5) of the insulating substrate (2); a wiring element (8) which is connected to an electrode arranged on a front surface of the semiconductor element (6) or to the circuit board (5) of the insulating substrate (2); a housing (10) which accommodates the insulating substrate (2), the semiconductor element (6) and the wiring element (8); and a potting material (13) which contains a thermosetting resin, wherein the potting material (13) seals the insulating substrate (2), the semiconductor element (6) and the wiring element (8) which are housed in the casing (10); wherein the circuit plate (5) of the insulating substrate (2) on the insulating resin plate (4) is selectively formed as a combination of a circuit pattern (5A) with a potting material bonding pattern (5B), wherein the potting material bonding pattern (5B) includes an opening (5B1) or a recess (5B2) which is arranged in the circuit board (5), wherein the potting material bonding pattern (5B) is arranged between the semiconductor element (6) attached to the circuit board (5) and an end of the wiring element (8) which is attached to the circuit board (5), and wherein the potting material (13) is in contact with and adheres to the insulating resin plate (4) of the insulating substrate (2) in the region of the interior of the opening (5B1) or the recess (5B2). [2] Semiconductor device (1) according to claim 1, wherein the potting material bonding pattern (5B) is arranged closer to the semiconductor element (6) attached to the circuit board (5).

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