METHOD FOR DETECTING FAULTY PIXEL ADDRESSING AND TEST CIRCUIT FOR DETECTING ADDRESSING ERRORS IN AN IMAGE SENSOR

Abstract

Method for detecting faulty pixel addressing in an image sensor comprising a pixel array, wherein the method comprises: Obtaining an actual fixed pattern noise for targeted pixel addresses of the image sensor; Correlate the actual fixed pattern noise with a reference fixed pattern noise known for the targeted pixel addresses; and Detecting an addressing error for the image sensor based on the correlation results.

Description

TECHNICAL AREA

[0001] The present invention relates generally to image sensors, such as CMOS image sensors used in cameras, and in particular to the detection of errors associated with image sensor decoding. BACKGROUND

[0002] Fig. Figure 1 illustrates an exemplary CMOS image sensor, and although these details are useful for understanding the teachings presented here, they should be understood as non-restrictive. The illustrated CMOS image sensor 10, where “CMOS” denotes a complementary metal-oxide semiconductor, comprises a cover glass and a microlens array 12, an active pixel sensor array 14 together with associated analog processing circuits 16, an analog-to-digital converter or ADC 18, and digital signal processing circuits 20 that operate on the analog data converted into digital form by the ADC 18.

[0003] The sensor 10 also includes processing and interface circuits 22 for connection to one or more elements of the sensor 10, such as the digital processing circuits 20. The sensor 10 further includes a control register 24 for controlling certain processes, such as the operation of the exposure timing and control circuits 26 and the image output timing and control circuits 28. In turn, these circuits control a row decoder circuit 30 and a column decoder circuit 32, which are used to output data from the active pixel array 14.

[0004] By activating one row of the pixel array 14 after the other with the row decoder circuit 30, the active pixel sensor array 14 outputs analog signals representing pixel data for the selected row. The analog processing circuits 16 include sample-and-hold circuits for acquiring the analog pixel data. After any analog processing, the acquired analog data is converted into the digital domain by the ADC 18 and further processed in the digital processing circuits 20.

[0005] Fig. Figure 2 illustrates an exemplary "floor plan" based on the one in Fig. The exemplary sensor 10 shown in Figure 1 is applicable. A counter in the timing and control circuit 28 implements automatic scans of the pixel array 14. More specifically, the counter generates the address signals for the row and column decoder circuits 30 and 32. This scheme enables independent addressing of each pixel in the active pixel array 14.

[0006] Fig. Section 3 provides exemplary pixel circuit details for the pixel circuits that are described in the Fig. 1 and Fig. The 2 displayed active pixel array comprises 14. Fig. Figure 3 illustrates the row / column output scheme implemented in the sensor's active pixel array 14. In particular, transistors Q1 and Q2, associated with row / column activation, and transistors Q3 and Q4, providing storage and saturation control respectively, are shown.

[0007] Certain failures among the various types of failures, which correspond to the type in the examples of the Fig. The errors associated with the sensors illustrated in 1-3 are particularly problematic with regard to their impact on operation, the difficulty of their detection, or both. Addressing errors, for example, are especially problematic. More specifically, if either the row decoding or the column decoding fails in such a way as to cause addressing errors, the data output for selected pixels may actually represent data for unselected pixels in a different row or column of the active pixel array 14.

[0008] It is recognized here that sensor addressing errors cause more than just artifacts or a distortion of the image data output by the sensor and represent a significant design safety consideration in applications where the sensor 10 is used for machine shielding, autonomous vehicle guidance, area monitoring, or other high-security and / or safety-critical imaging functions. For example, in safety-critical machine vision or other object detection applications, faulty sensor addressing can cause the imaging system to miss objects that would otherwise have been detected.

[0009] Several well-known approaches to detecting sensor addressing errors involve feeding test patterns or images into the sensor. These fed patterns or images can be integrated or external. In either case, the image data read by the sensor involved should match the fed test pattern or image. Unfortunately, the use of test patterns represents a potentially time-consuming type of verification test, and its use generally requires that the sensor be taken offline—for example, that its normal or nominal imaging operation be interrupted for test pattern feeding.

[0010] Another approach requires appending some type of data or marker representing the address of each pixel. This appendage is executed when the pixel signals are output by the pixel array involved. However, this approach to addressing error detection requires a specially designed sensor, and such sensors tend to be more expensive than cost-effective, general-purpose CMOS image sensors.

[0011] DE 102 05 691 A1 discloses a method for verifying the functional reliability of an image sensor and a device comprising an image sensor. The image sensor includes a plurality of light-sensitive pixels. Gray values ​​from at least one light-sensitive pixel are read out. A current noise measure of the gray values ​​of the at least one pixel is determined. Furthermore, a dark noise measure for the at least one pixel is provided, and the current noise measure is compared with the dark noise measure. A functional defect is assumed if the current noise measure fails to meet a predefined criterion with respect to the dark noise measure.

[0012] US patent 2005 / 0068431A1 discloses a method for suppressing certain noise components in a pixel-based display. SUMMARY

[0013] The present teachings provide a method according to claim 1 for detecting faulty pixel addressing in an image sensor and a corresponding test circuit according to claim 9. The dependent claims define further embodiments. The method and the test circuit, hereinafter also referred to as the device, advantageously utilize the characteristic "fixed pattern noise" of the sensor to detect addressing errors. In general, pixel addressing errors are detected based on a comparison of the pattern noise captured in data outputs from a targeted address of the sensor with a characteristic fixed pattern noise known for the sensor.

[0014] In one embodiment, a method for detecting faulty pixel addressing in an image sensor comprising a pixel array includes obtaining actual fixed-pattern noise for targeted pixel addresses of the image sensor and correlating the actual fixed-pattern noise with a reference fixed-pattern noise known for the targeted pixel addresses. The method further includes detecting an addressing error for the image sensor based on the correlation results.

[0015] In another embodiment, a test circuit configured to detect addressing errors in an image sensor includes a processing circuit and a computer-readable medium that stores a template of the fixed pattern noise (FPN). The template contains reference FPN values ​​for at least one range of pixel addresses of the sensor, and the test circuit further includes a sensor interface circuit configured to communicate between the processing circuit and the image sensor.

[0016] In essence, the processing circuit is configured to obtain the actual fixed pattern noise for targeted pixel addresses of the image sensor and to correlate this actual fixed pattern noise with a reference fixed pattern noise known for the targeted pixel addresses. The processing circuit is further configured to detect an addressing error for the image sensor based on the correlation results.

[0017] Of course, the present invention is not limited to the features and advantages mentioned above. Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram of an example image sensor. Fig. 2 and Fig. 3. Further circuit details for the image sensor of Fig. 1 ready. Fig. Figure 4 is a table containing mitigation information that identifies the main failure mechanisms for an image sensor used in a safety-critical application. Fig. Figure 5 is a diagram of an example fixed noise pattern for an image sensor. Fig. Figure 6 is a diagram of an embodiment of a solid noise pattern template according to the present teachings. Fig. Figure 7 is a diagram of an embodiment of an evaluation process of the solid noise pattern according to the present teachings. Fig. Figure 8 is a graphical representation of correlation processing results according to an embodiment of a fixed pattern noise evaluation. Fig. Figure 9 is a table containing further mitigation information that identifies the main risks and corresponding mitigations used with respect to an image sensor in one or more embodiments disclosed herein. Fig. Figure 10 is a table of measured and expected temperature values ​​for an exemplary image sensor circuit and device. Fig. 11 is a diagram of pseudocode according to an embodiment of an image sensor test taught herein. Fig. Table 12 identifies additional circuit control mechanisms that can be used individually or in combination to test an image sensor according to one or more embodiments disclosed herein. Fig. Figure 13 is a block diagram of an imaging device which includes an image sensor and further includes a test circuit which is configured to test the image sensor according to an embodiment disclosed herein. Fig. 14 is a logic flow diagram of an embodiment of a method of an image sensor test disclosed herein. DETAILED DESCRIPTION

[0018] Fig. Figure 4 illustrates a mitigation table that identifies the selected row / column line output or signal of an image sensor as a safety-critical output. The illustrated table identifies a row / column decoding check as a mitigation method. Of particular interest is that the mitigation check disclosed herein does not require any specialized sensor circuitry or features, but instead can be used directly with generic or other general-purpose image sensors, as in the examples from the Fig. Seeing 1-3 is valid.

[0019] In one aspect of the faulty addressing detection taught here, fault detection involves determining whether the fixed pattern noise (FPN) output by the pixel array at given address positions of the pixel array matches a characteristic FPN known for those address positions. Here, FPN is understood to refer to the unique and fixed pattern of intensity or brightness variations detected across pixels in an imaging array, caused by variations in the sensitivity or receptivity of the individual pixels and / or the associated gain circuitry.

[0020] In general, each row or column in the pixel array of a given sensor will have a characteristic FPN. Thus, a test circuit, to the extent that it—like a programmed processor—knows the characteristic FPN for each row and / or column of pixels in the pixel array, can detect that its row / column selection input to the sensor is not being decoded correctly for one or more rows or columns of the pixel array, based on detecting that the FPN obtained for a given row / column address does not match the FPN that is characteristic for that given row / column address.

[0021] More generally, it is recognized here that each imaging sensor has statistically unique FPNs for the rows and columns comprising its pixel array. By attempting to read from specific addresses of the pixel array and determining whether the corresponding output FPN is characteristic for the addresses being read, the test circuit and method taught here thus detect addressing errors—also referred to as decoding errors. Nonrestrictive examples of detected errors include swapped rows, swapped columns, etc.

[0022] In particular, FPN appears both in the active pixel array and in the dark rows and columns of the pixel array. It should be noted that a typical image sensor has one or more "dark" rows / columns. A dark row or column is optically black and insensitive to incident light. Usually, dark rows and columns surround the optically active pixel area—that is, the area of ​​the pixel array that responds to incident light—and these dark rows and columns can be addressed in the same way as the rows and columns within the active pixel area of ​​the pixel array.

[0023] Fig. Figure 5 illustrates an example FPN for the pixel array of a CMOS image sensor. Here, the rows and columns of the pixel array exhibit a characteristic FPN, and Fig. Figure 6 illustrates a considered approach for generating an FPN “template” 40 as part of a factory calibration or characterization process for a given sensor. In the illustrated example, the FPN is characterized at 24 degrees Celsius and is based on averaging over 100 dark images 42, so that the FPN template 40 is generated for the sensor. It is understood that in an example case, the FPN template 40 comprises a file, data set, or other electronic data that includes FPN values ​​corresponding to at least some of the sensor's rows / columns—e.g., the dark rows and columns.

[0024] Accordingly, it illustrates Fig. 7 An exemplary approach for using FPN Template 40 at runtime in a device or system that includes the sensor characterized by FPN Template 40. For example, the sensor head or camera of a machine vision system includes a CMOS image sensor for area monitoring, etc., and also includes persistent memory for storing the FPN template for the image sensor. The sensor head or camera further includes check circuitry for outputting pixel data from the sensor based on inputting row / column addresses to the sensor, at least for the addresses represented in the FPN template. Such circuitry may be at least partially the same as the normal addressing / interface circuitry used to read the sensor for normal image acquisition and processing.

[0025] The test circuitry correlates the pixel data stored for specific addresses in FPN template 40 with the actual pixel data read by the sensor when those address values ​​are input. If a given read address input is correctly decoded by the sensor, the actual pixel data output by the sensor should correlate strongly with the pixel data comprising the characteristic FPN stored in FPN template 40 for that address.

[0026] Fig. Figure 7 illustrates, for example, that a specific row i in the pixel array of an image sensor is selected and read by the sensor. The pixel data read by the sensor for the selected row i is correlated with each row of pixel data in FPN template 40. This can be understood as a row-to-row correlation process, and the highest or strongest correlation result is expected to be perceived for the row of pixel data in FPN template 40 that corresponds to the selected row address—that is, the row address that was input into the sensor to output the pixel data.

[0027] In other words, if the address for line i is targeted by a read command input into the sensor, the pixel data output by the pixel array for this read operation should, in the absence of an addressing error, correlate most strongly with the characteristic FPN of line i, as known from FPN template 40.

[0028] Fig. Figure 8 provides further exemplary details. In this case, line number 196 is purportedly read by the sensor, and the pixel data obtained from this reading is correlated with each line of pixel data in the FPN template 40. This can be understood as correlating the actual FPN, as read by the sensor for line address 196, with the characteristic FPN—e.g., as determined as part of a factory calibration of the sensor—of each line represented in the FPN template 40. As expected in the absence of addressing errors in the sensor, the pixel data output by the sensor exhibits its strongest correlation with the characteristic FPN of line 196 in the FPN template.

[0029] Fig. Figure 9 illustrates a table summarizing certain false-positive risks associated with correlation processing and corresponding proposed mitigation countermeasures, as suggested in one or more embodiments. In particular, the false positive probability (FPN) is highly dependent on the sensor temperature, and the FPN becomes less pronounced at lower temperatures—that is, differences in the FPN between different rows or columns are less pronounced at lower sensor temperatures. One mitigation measure under consideration is therefore to employ heating to ensure that the sensor is at an appropriate temperature.

[0030] Of course, in the presence of heating failures or under certain other conditions, it is still possible that insufficient FPN differences exist between different rows or columns in the sensor. Thus, another false-positive risk arises if the sensor addressing failure is such that reading from a selected row or column incorrectly accesses pixel data from multiple rows or columns. To mitigate this failure risk, the correlation processing can be configured to declare an error condition if it detects a relatively strong correlation between multiple rows or columns in FPN template 40 and the actual pixel data read from a selected row or column of the sensor.Such errors can arise from actual addressing errors or from the fact that the FPN is not sufficiently pronounced across the rows / columns of the sensor at cooler temperatures.

[0031] Fig. Figure 10 illustrates empirical temperature data obtained for an example sensor in a prototype camera product. The table presents the observed relationships between external ambient temperatures and the sensor temperatures inside the prototype camera. The data indicate that reliable address failure detection is available at external ambient temperatures as low as 0 degrees Celsius. Of course, operation at even lower external ambient temperatures may be tolerated with other camera designs and / or depending on further mitigations.

[0032] For example, it is being considered here that a dynamic change in the analog-to-digital or ADC resolution is used. The ADC resolution under discussion here is understood as the one used to output pixel values ​​from the sensor's pixel array – in this example, an ADC is... Fig. Figure 1 is shown. Additionally or alternatively, dynamic gain and / or offset control for the sensor is used as a further mitigation measure. As explained, dynamic control of the gain and / or offset values ​​associated with operating and / or reading a sensor pixel array can be used to improve the distinguishability of the actual FPN shown by the different rows / columns in the sensor.

[0033] Fig. Figure 11 illustrates exemplary pseudocode for performing line-wise correlation processing for the detection of sensor addressing errors, as considered in one or more of the present embodiments. By examining the pseudocode, it becomes apparent that the algorithm requires the selected line—that is, the line read by the sensor for a given input address—to have the highest correlation with the line at the same address in the FPN template.

[0034] Thus, the FPN of the read line is compared with the FPN of each line in FPN template 40, and the test passes only if the correlation between the FPN of the read line and the FPN in FPN template 40 for the line address of the read line is strongest. More generally, pixel data is read from the sensor for a specific address (or address range). In the absence of addressing errors, the FPN represented by the read pixel data should correlate most strongly with the FPN stored in FPN template 40 for the same address or address range.

[0035] Additionally, the algorithm can be extended to require that the correlation results are at least as strong as a defined threshold – e.g., 0.8 on a correlation scale from 0 (no correlation) to 1 (perfect correlation). Naturally, the algorithm can be adapted for column-wise processing, etc.

[0036] Other aspects of the addressing error detection considered here take into account both runtime and turn-on detection processing. In a runtime detection approach, the considered test circuit uses low-integration (low-exposure) test images to obtain actual FPN patterns for the sensor, employing both dark columns and / or dark rows, as well as, at least in some embodiments, pixels in the active pixel array. This flexibility is permitted because the camera or sensor head containing the sensor will generally be warm enough during runtime operation to ensure a sufficiently pronounced FPN between different rows and columns of the sensor.

[0037] On the other hand, the sensor may be too cold when switched on to exhibit sufficiently distinct FPN patterns between different rows and / or columns. However, waiting for the sensor to warm up before performing an address check is impractical, and in safety-critical applications, it may be necessary to prevent the operation of a shielded machine or other external operations until all safety-critical checks have been successfully completed.

[0038] Therefore, it is considered here that an address check of a power-on event is performed based on the use of extended exposure times, e.g., exposure times from 500 ms to several seconds. The use of long exposure times is effective when the ambient temperature is cold, or otherwise when the sensor has not reached normal operating temperatures. Furthermore, in one or more embodiments, the test circuit for the cold / power-on address check reads only the dark columns and / or the dark rows of the sensor to correlate the FPN pattern with the FPN template 40. Thus, in one or more embodiments, it is considered here that the FPN template 40 includes temperature-dependent FPN properties for both the dark columns / rows and the active columns / rows of the sensor.

[0039] The uniqueness or distinctiveness of the FPN, as perceived for pixel data read from different rows / columns of the sensor, is a key aspect of reliable addressing error detection. To this end, in some embodiments considered here, the test circuit regulates and modifies the sensor's FPN patterns by applying known, integrated analog offsets and / or by changing analog gains. In other words, by changing one or more parameters of the sensor's operation—commonly referred to as changing the sensor's "operating point"—the FPN patterns exhibited by the sensor are altered.

[0040] As such, the sensor's characteristic FPN pattern can be learned as part of the factory calibration for some or all rows / columns for each of several different operating points. Then, the FPN correlation processing taught here can be performed in situ—that is, within the product containing the sensor—during in-service or field testing of this sensor for each of the multiple operating points, providing the test circuit with a larger dataset so that it can detect addressing errors more reliably.

[0041] This can be viewed as generating a different FPN template 40 for each operating point, or it can be considered as having a multidimensional or multi-sided FPN template 40. During an actual in-situ test, the test circuit would select an operating point—for example, by setting the appropriate gain and / or offset values ​​for the sensor. While the test circuit holds the selected operating point, it would output pixel data from the sensor for selected addresses and compare this data with the data of the FPN template 40 for the selected operating point. Such a test would be performed at some or all of the operating points, and the overall pass / fail status of the test can be based on the aggregation of test results.With a particularly strict security setting, the entire test may be considered failed if any test at any of the operating points fails.

[0042] The in Fig. Table 12 represents an exemplary collection of mitigations and / or improvements for implementing FPN-based correlation processing, as taught here, for the reliable detection of sensor addressing errors. It is evident that the analog offset of the analog processing circuits 16 can be controlled so that a specific offset is introduced into the pixel intensities of the sensor 10. Additionally or alternatively, the FPN shown by the sensor 10 can be modified or made more pronounced by controlling the analog gain on a per-row / per-column basis, e.g., by increasing the analog gain of the Fig. 1 analog processing circuits 16. Furthermore, additionally or alternatively, the test circuit under consideration can dynamically adjust the resolution and / or the reference voltage of the ADC 18, which is used to digitize pixel values ​​from the sensor 10, so that this acts as a mechanism to improve the distinguishability between the actual FPN shown by different rows / columns of the sensor.

[0043] Fig. Figure 13 illustrates a potential test circuit 50 according to an exemplary embodiment. The test circuit 50 is located, for example, in an imaging device 48, which may be a camera or another device or assembly. It is understood that all parts, or at least a part, of the test circuit 50 may be shared with the imaging device 48. In some embodiments, the test circuit 50 is implemented, for example, in or otherwise integrated within the overall image processing and control circuits that are necessarily implemented in the imaging device 48 for integrating and using an image sensor 52, which may be a CMOS image sensor.

[0044] The test circuit 50 includes a processing circuit 54, which contains a CPU or other digital processing circuits 56. The processing circuit 54 includes, for example, one or more microprocessors, microcontrollers, DSPs, FPGAs, or other programmable logic devices, ASICs, etc., together with supporting circuitry. The processing circuit 54 includes, for example, a program and data memory or storage device 60, or is associated with one. The program and data memory or storage device 60 includes, for example, FLASH, EEPROM, or other persistent memory. Of course, the processing circuit 54 can also include or be associated with non-persistent memory, such as SRAM.

[0045] Generally speaking, the program and data storage or storage 60 comprises a computer-readable medium which, in one or more embodiments, provides persistent, non-temporary storage for a computer program 62 and one or more FPN templates 40. In a particular example, the program and data storage or storage 60 stores at least one FPN template 40 which includes characteristic FPN data for the image sensor 52.

[0046] For example, the test circuit 50 includes a sensor interface circuit 58 and I / O circuits that couple the processing circuit 54 to the image sensor 52. The processing circuit 54 outputs, for example, outgoing read addresses to the image sensor 52 and receives incoming pixel data as read by the sensor 52 for these read addresses. The processing circuit 54 also outputs data or signals representing a control signal for the operating point OP. The OP control signal regulates the ADC resolution, gain, and / or offset values ​​used to define one or more operating points of the image sensor 52 for the purpose of sensor addressing testing.

[0047] While the processing circuit 54 may comprise fixed circuits in one or more embodiments, it is also considered here to implement the test circuits 54 using programmable circuits – e.g., a microprocessor. In such embodiments, the programmable circuits are specially adapted so that they execute the operations disclosed herein based on their execution of the computer program instructions, which comprise the computer program 62, as stored in the program and data memory or storage 60.

[0048] The test circuit 50 can also include or be associated with a temperature sensor 68 and / or a heater 70. In one considered embodiment, the FPN template(s) 40 comprise more than one FPN template 40, each such FPN template 40 being associated with a different temperature range. In turn, the processing circuit 54 receives temperature readings—e.g., ambient temperature measurements—from the temperature sensor 68 via the I / O circuits 58 and selects the appropriate FPN template 40, which it uses to detect addressing errors. Additionally or alternatively, there is only one FPN template 40, but it includes temperature-dependent subsections or parts, and the processing circuit 54 uses the detected temperature to access the appropriate part of the subsection of the FPN template 40.

[0049] In addition, or in one or more further embodiments, the processing circuit 54 controls a heater 70 – e.g., an electrical coil, a power resistor, or another heating circuit – so that the image sensor 52 does not become so cold that its actual row / column FPN is not pronounced. The processing circuit 54 can, for example, activate the heater 70 as needed so that the image sensor 52 is kept at or above a minimum temperature value.

[0050] In general, according to one embodiment considered here, the test circuit 50 is configured to detect addressing errors in an image sensor 52 and includes the processing circuit 54, the computer-readable medium 60 which stores a template 40 of the fixed pattern noise (FPN) comprising reference FPN values ​​for at least a range of pixel addresses of the sensor 52. Furthermore, the test circuit 50 includes a sensor interface circuit 58 configured to communicatively couple the processing circuit 54 with the image sensor 52.

[0051] The processing circuit 54 is configured to obtain the actual fixed pattern noise for targeted pixel addresses of the image sensor 52 and to correlate the actual fixed pattern noise with a reference fixed pattern noise known for the targeted pixel addresses. Furthermore, the processing circuit 52 is configured to detect an addressing error for the image sensor based on the correlation results.

[0052] For example, in at least one such embodiment, the processing circuit 54 is configured to obtain the actual fixed pattern noise for targeted pixel addresses of the image sensor by obtaining an actual fixed pattern noise for a targeted row or column of the pixel array, and to correlate the actual fixed pattern noise with the reference fixed pattern noise by obtaining the reference fixed pattern noise for a range of rows or columns of the pixel array. This range includes the targeted row or column.

[0053] The processing circuit 54 is configured to correlate the actual fixed pattern noise for the targeted row or column with the reference fixed pattern noise for each row or column in the area. Furthermore, the processing circuit 54 is configured to detect the addressing error for the image sensor based on the correlation results by deciding that an addressing error exists if the actual fixed pattern noise for the targeted row or column does not correlate "uniquely" with the reference fixed pattern noise for the targeted row or column.

[0054] In general, "unambiguous" correlation means a correlation result that exceeds a defined correlation threshold. It can also mean that the actual fixed pattern noise for the targeted pixel addresses does not show a strong correlation with any reference fixed pattern noise in FPN template 40, except for the reference fixed pattern noise corresponding to the targeted pixel addresses. Furthermore, it can mean that the correlation result seen between the actual fixed pattern noise and the reference fixed pattern noise corresponding to the targeted pixel addresses exceeds all other correlation results by a defined margin.

[0055] Although the actual fixed pattern noise read by the sensor 52 for a targeted row or column may produce a strong correlation with the reference fixed pattern noise contained in the FPN template 40 for the targeted row or column, it may also correlate strongly with other row-column data in the FPN template 40. Such ambiguities arise, for example, at lower sensor temperatures, where the actual fixed pattern noise of the sensor 52 is less pronounced across rows or columns of the sensor 52.

[0056] Furthermore, in one or more of the present embodiments, the test circuit 50 is configured to perform a method for detecting faulty pixel addressing in an image sensor comprising a pixel array, irrespective of the specific architecture of the test circuit 50. The method involves obtaining an actual fixed pattern noise for targeted pixel addresses of the image sensor, correlating the actual fixed pattern noise with a reference fixed pattern noise known for the targeted pixel addresses, and detecting an addressing error for the image sensor based on the correlation results.

[0057] The procedure is performed when the device or apparatus containing the image sensor 52 under test is switched on, and the procedure may involve using extended exposure times to read the actual fixed pattern noise from the sensor 52. Additionally or alternatively, the procedure is performed during operation and further involves using nominal exposures corresponding to an operating frame rate.

[0058] In some embodiments, the method involves heating the sensor 52 to a desired minimum operating temperature, and one or more embodiments of the method include storing factory characterization information that comprises temperature-dependent reference fixed pattern noise data for at least one range of pixel addresses of the sensor. That is, the FPN template 40 contains temperature-dependent characterization data. For example, the FPN template 40 stores factory characterization information that comprises temperature-dependent reference fixed pattern noise data for all pixel addresses of the sensor 52.

[0059] In further exemplary details of the method under consideration, the step of obtaining the actual fixed pattern noise for targeted pixel addresses of the image sensor comprises obtaining actual fixed pattern noise for a targeted row or column of the pixel array. The step of correlating the actual fixed pattern noise with the reference fixed pattern noise comprises obtaining the reference fixed pattern noise for a range of rows or columns of the pixel array, the range including the targeted row or column, and correlating the actual fixed pattern noise for the targeted row or column with the reference fixed pattern noise for each row or column in the range.The step of detecting an addressing error for the image sensor 52 based on the correlation results includes deciding that there is an addressing error if the actual fixed pattern noise for the targeted row or column does not uniquely correlate with the reference fixed pattern noise for the targeted row or column.

[0060] Fig. Figure 14 provides a flowchart for an exemplary procedure 1400, which can be understood as an implementation of the processing described above. It is understood that one or more steps of procedure 1400 may be performed in a different order than suggested by the illustration, and that one or more steps may be performed simultaneously and in conjunction with other operations, and may be repeated or run in a loop.

[0061] In some embodiments, for example, the method 1400 is performed when the imaging device 48 is switched on for one or more arbitrary operating points of the image sensor 14 and is performed on a repeated and / or triggered basis during normal operation of the imaging device 48. In at least one embodiment, safety-critical failure detection requirements determine the frequency with which the method 1400 is executed.

[0062] In any case, procedure 1400 includes reading (block 1402) actual fixed pattern noise (FPN) values ​​from targeted pixel addresses of the image sensor 52 and determining (block 1404) whether the actual FPN values ​​match reference FPN values ​​characteristic of the pixels actually located at the targeted pixel addresses. Procedure 1400 further includes deciding (block 1406) that an addressing error exists for the image sensor if the actual FPN values ​​do not match the reference FPN values ​​for the targeted pixel addresses.

[0063] In an example of the test circuit 50 implementing procedure 1400, the test circuit 50 is configured to read actual fixed pattern noise (FPN) values ​​from targeted pixel addresses of the image sensor 52 and to determine whether the actual FPN values ​​match the reference FPN values ​​known from the FPN template for the pixels actually located at the targeted pixel addresses. The test circuit 50 is further configured to determine that an addressing error exists for the image sensor 52 if the actual FPN values ​​do not match the reference FPN values ​​for the targeted pixel addresses.

[0064] As previously noted, it is understood that the “conformity check” specified for Procedure 1400 may be more demanding or nuanced than a simple match / no match evaluation. For example, the actual FPN values, as read by Sensor 52, may encompass a targeted row or column of pixels in the sensor's pixel array, and Procedure 1400 may require an unambiguous match, as defined by one of the following or any combination thereof: - Correlate the actual FPN values ​​with the reference FPN values ​​for multiple rows or columns in FPN template 24 and ensure that the largest correlation response is captured with respect to the reference FPN values ​​corresponding to the targeted row or column; - Ensure that the correlation response between the actual FPN values ​​and the reference FPN values ​​for the targeted row or column is at or above a defined minimum response threshold; - Ensure that the correlation response captured between the actual FPN values ​​and the reference FPN values ​​for the targeted row or column is greater by a defined range in magnitude than the correlation response seen with respect to all other rows or columns evaluated in FPN Template 40; and - Ensure that there are not multiple rows or columns of the FPN template 40 that produce a strong correlation response with respect to the actual FPN values ​​read by the image sensor 52.

[0065] In particular, modifications and other embodiments of the disclosed invention(s) will be apparent to a person skilled in the art who benefits from the teachings presented in the preceding descriptions and the associated drawings. Therefore, it is understood that the invention(s) is / are not limited to the specific disclosed embodiments and that modifications and other embodiments are intended to be included within the scope of protection of this disclosure. Although specific terms may be used here, they are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

[1] Method for detecting faulty pixel addressing in an image sensor comprising a pixel array, the method comprising: Obtaining an actual fixed pattern noise for targeted pixel addresses of the image sensor; Correlate the actual fixed pattern noise with a reference fixed pattern noise known for the targeted pixel addresses; and Detecting an addressing error for the image sensor based on the correlation results. [2] The method of claim 1, further comprising the use of extended exposure times when obtaining the fixed pattern noise when the ambient temperature is cold or when the image sensor has not reached normal operating temperatures. [3] Method according to claim 1 or 2, wherein the method is carried out during the runtime and further comprises the use of nominal exposures corresponding to an operating frame rate. [4] Method according to one of claims 1-3, further comprising heating the sensor to a desired minimum operating temperature. [5] Method according to one of claims 1-4, further comprising storing factory characterization information comprising temperature-dependent reference fixed pattern noise data for at least one range of pixel addresses of the sensor. [6] Method according to any one of claims 1-4, further comprising storing factory characterization information comprising temperature-dependent reference fixed pattern noise data for all pixel addresses of the sensor. [7] Method according to any one of claims 1-6, wherein obtaining the actual fixed pattern noise for targeted pixel addresses of the image sensor comprises obtaining an actual fixed pattern noise for a targeted row or column of the pixel array, wherein correlating the actual fixed pattern noise with the reference fixed pattern noise comprises obtaining the reference fixed pattern noise for a range of rows or columns of the pixel array, the range including the targeted row or column, and correlating the actual fixed pattern noise for the targeted row or column with the reference fixed pattern noise for each row or column in the range, and wherein detecting the addressing error for the image sensor based on the correlation results comprises deciding that there is an addressing error,if the actual fixed pattern noise for the targeted row or column does not uniquely correlate with the reference fixed pattern noise for the targeted row or column, and where a unique correlation means a correlation result that is above a defined correlation threshold. [8] Method according to any one of claims 1-7, wherein Obtaining the actual fixed pattern noise for targeted pixel addresses of the image sensor includes reading values ​​of the actual fixed pattern noise (FPN) from targeted pixel addresses of the image sensor; This includes correlating the actual fixed pattern noise with the reference fixed pattern noise known for the targeted pixel addresses, and determining whether the actual FPN values ​​match reference FPN values ​​characteristic of the pixels actually located at the targeted pixel addresses; and This includes detecting an addressing error for the image sensor based on the correlation results. Deciding that an addressing error for the image sensor exists if the actual FPN values ​​do not match the reference FPN values ​​for the targeted pixel addresses. [9] Test circuit designed to detect addressing errors in an image sensor, the test circuit comprising: a processing circuit; a computer-readable medium that stores a template of the fixed pattern noise (FPN) comprising reference FPN values ​​for at least one range of pixel addresses of the sensor; and a sensor interface circuit configured to communicatively couple the processing circuit with the image sensor; and the processing circuit is set up as follows: Obtaining an actual fixed pattern noise for targeted pixel addresses of the image sensor; Correlate the actual fixed pattern noise with a reference fixed pattern noise known for the targeted pixel addresses; and Detecting an addressing error for the image sensor based on the correlation results. [10] Test circuit according to claim 9, wherein the test circuit is configured as follows: Obtaining the actual fixed pattern noise for targeted pixel addresses of the image sensor by obtaining an actual fixed pattern noise for a targeted row or column of the pixel array; Correlating the actual fixed pattern noise with the reference fixed pattern noise by obtaining the reference fixed pattern noise for a range of rows or columns of the pixel array, the range including the targeted row or column, and correlating the actual fixed pattern noise for the targeted row or column with the reference fixed pattern noise for each row or column in the range; and Detecting the addressing error for the image sensor based on the correlation results by deciding that there is an addressing error if the actual fixed pattern noise for the targeted row or column does not uniquely correlate with the reference fixed pattern noise for the targeted row or column. [11] Test circuit according to claim 9, wherein the test circuit is configured as follows: Reading actual fixed pattern noise (FPN) values ​​from targeted pixel addresses of the image sensor; Determine whether the actual FPN values ​​match the reference FPN values ​​known from the FPN template for the pixels actually located at the targeted pixel addresses; and Determine that an addressing error exists for the image sensor if the actual FPN values ​​do not match the reference FPN values ​​for the targeted pixel addresses.

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