Semiconductor device and method for its manufacture

Abstract

Semiconductor device (1A, 1B, 1C) comprising the following: a drift layer (3) of a first conductivity type; a mesa region (5) located between adjacent trenches on the drift layer (3); a gate electrode (8) which is buried in each trench by a gate insulating film; a base region (9) of a second conductivity type, which is buried in the mesa region (5); several emitter regions (11) of the first conductivity type, which are periodically buried in a surface layer section of the basal region (9) along a longer direction of the trench; and Contact regions (12) of the second conductivity type, which are alternately buried in the longer direction together with the emitter regions (11) such that each emitter region (11) is arranged between the contact regions, lie deeper than the emitter region and extend immediately below the emitter region in such a way that they are separated from each other, wherein a contact region contact width (W) e ) in the longer direction defined in a surface of the contact region (12) is less than an emitter region contact width (W) bc ) in the longer direction defined in a surface of the emitter region, where an effective contact region width (W eff ) of an interface between the contact region (12) and the base region (9) in the longer direction is larger than an emitter injection width (W) inj) a pn transition interface between the emitter region and the base region (9) in the longer direction, where a length (A) is half the emitter injection width (W) inj ) is smaller than a creep distance (d crp ) of a pn transition interface (11n2) along a curve in a cross-sectional view along the longer direction between the emitter region (11) and the contact region (12).

Description

TECHNICAL AREA

[0001] The present invention relates to a semiconductor device and a method for its manufacture, and relates in particular to techniques that can be effectively applied to semiconductor devices in conjunction with, for example, a trench insulated-gate bipolar transistor (IGBT), and to a method for manufacturing the semiconductor devices. GENERAL STATE OF THE ART

[0002] A trench IGBT is known in which a trench is buried in a main face of a semiconductor substrate and a gate (or control) electrode is buried in the trench by a gate insulating film. Since the recent development of increased channel integration density and reduced one-state voltage through trench IGBTs has made the fields in which the trench IGBT can be applied have become more numerous compared to planar IGBTs. Furthermore, a trench IGBT is also known as an IGBT structure in which the n-type emitter regions and the p-type contact regions are arranged alternately in island regions located between adjacent trenches along the longitudinal direction of the island regions. In this IGBT, the emitter injection width of a pn junction between the n-type emitter region and the p-type base region is reduced along the longitudinal direction of the island region to decrease the gate width.Therefore, an improvement in the latch-up strength of parasitic thyristors is possible.

[0003] However, in a vertical trench IGBT disclosed in patent document 1, the emitter injection width is relatively dependent on the width (emitter region contact width) of the surface of an n-type emitter region defined in the longitudinal direction of the island region. Thus, if the emitter injection width is reduced to decrease the gate width, the surface area of ​​the n-type emitter region is reduced, and the contact resistance between the n-type emitter region and an emitter electrode electrically connected to the n-type emitter region increases. Consequently, the one-state voltage increases.

[0004] In particular, the width of the island region is generally reduced in the trench IGBT to increase the number of island regions and thus the current density. Therefore, when the island region width is reduced, the surface area of ​​the n-type emitter region decreases, and the contact resistance between the n-type emitter region and the emitter electrode increases. For this reason, the surface area of ​​the emitter region must be maximized to achieve a downward scaling of the island region.

[0005] DE 11 2012 004 026 T5 discloses a semiconductor device comprising a trench gate, a bottom section in a drift layer, and a communication section extending from a surface of a base layer to communicate with the bottom section.

[0006] US 2009 / 0179260 A1 discloses a method for manufacturing a semiconductor device.

[0007] EP 962 987 A2 discloses a vertical power MOSFET with trench gate containing MOSFET cells in the form of longitudinal strips.

[0008] US 2011 / 0241098 A1 discloses a three-dimensional stacked flash memory array with a truncated gate line and a manufacturing process.

[0009] JP 2014-027076 A discloses a semiconductor device with a source layer formed on a first surface of a substrate. CITATION LIST PATENT DOCUMENT

[0010] Patent Document 1: JP 2013-187440 A REVELATION OF THE INVENTION PROBLEM TO BE SOLVED BY THE INVENTION

[0011] One object of the invention is to provide a technique that can improve the latch-up strength of an IGBT used in a single device or power IC, or a semiconductor device operating similarly to the IGBT, and can reduce a one-state voltage. MEANS TO SOLVE THE PROBLEM

[0012] To achieve the objective, one aspect of the semiconductor device according to the present invention comprises: a drift layer of a first conductivity type; a mesa region arranged between adjacent trenches on the drift layer; a gate electrode buried in each trench by a gate insulating film; a base region of a second conductivity type buried in the mesa region; several emitter regions of the first conductivity type periodically buried in a surface layer section of the base region along a longitudinal direction of the trench;and contact regions of the second conductivity type, which are alternately buried in the longitudinal direction together with the emitter regions such that each emitter region is arranged between the contact regions, lie deeper than the emitter region and extend immediately below the emitter region in such a way that they are separated from each other, wherein a contact region contact width in the longer direction, defined in a surface of the contact region, is less than an emitter region contact width in the longer direction, defined in a surface of the emitter region.

[0013] One aspect of the method for manufacturing a semiconductor device according to the present invention comprises the following: forming a base region of a second conductivity type in a surface layer section of a semiconductor substrate of a first conductivity type; selectively implanting first interference ions of the second conductivity type into several regions that are periodically buried in a surface layer section of the base region along one direction; selectively implanting second interference ions of the first conductivity type into the surface layer section of the base region between the several regions in which the first interference ions are implanted along one direction, in a pattern that is arranged at a larger interval than an arrangement pattern of the several regions and is arranged with the same center-to-center spacing as the several regions, and with a lower acceleration energy than the first interference ions;and activating the first and second interference ions in such a way that a contact region of the second conductivity type is formed in the region where the first interference ions are implanted and an emitter region of the first conductivity type is formed in the region where the second interference ions are implanted. IMPACT OF THE INVENTION

[0014] According to the present invention, an improvement in the latch-up strength of an IGBT or a semiconductor device that operates similarly to the IGBT and a reduction in the input voltage are possible. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view illustrating a main section of a semiconductor device according to a first embodiment of the present invention; Fig. 2 is a cross-sectional view showing a main section of a cross-sectional structure along line IIa-IIa of Fig. 1 illustrates; Fig. 3 is a cross-sectional view showing a main section of a cross-sectional structure along line IIb-IIb of Fig. 1 illustrates; Fig. 4 is a cross-sectional view showing a main section of a cross-sectional structure along line IIc-IIc of Fig. 1 illustrates; Fig. Figure 5 is an enlarged cross-sectional view showing a section of Fig. 4 illustrates; Fig. 6 is an enlarged cross-sectional view showing a section of Fig. 4 illustrates; Fig. 7 is an enlarged cross-sectional view showing a section of Fig. 2 illustrated; Fig. Figure 8 is a diagram illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view illustrating a main section at a position corresponding to line IIa-IIa of Fig. 1 corresponds to; Fig. Figure 9 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line IIa-IIa of Fig. 1 corresponds to; Fig. Figure 10 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line IIa-IIa of Fig. 1 corresponds to; Fig. Figure 11 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line IIa-IIa of Fig. 1 corresponds to; Fig. 12 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a plan view illustrating a main section of the plane structure of an interfering atom incorporation mask; Fig. Figure 13 is a cross-sectional view showing a main section of a cross-sectional structure along line IIIa-IIIa of Fig. 12 illustrated; Fig. Figure 14 is a cross-sectional view showing a major section of a cross-sectional structure along line IIIb-IIIb of Fig. 12 illustrated; Fig. Figure 15 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a plan view illustrating a main section of the plane structure of the interfering atom incorporation mask; Fig. Figure 16 is a cross-sectional view showing a main section of a cross-sectional structure along line IVa-IVa of Fig. 15 illustrated; Fig. Figure 17 is a cross-sectional view showing a main section of a cross-sectional structure along line IVb-IVb of Fig. 15 illustrated; Fig. Figure 18 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line IIa-IIa of Fig. 1 corresponds to; Fig. Figure 19 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view illustrating a main section at a position corresponding to line IIb-IIb of Fig. 1 corresponds to; Fig. Figure 20 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view illustrating a main section at a position corresponding to line IIc-IIc of Fig. 1 corresponds to; Fig. Figure 21 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line IIa-IIa of Fig. 1 corresponds to; Fig. Figure 22 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line IIa-IIa of Fig. 1 corresponds to; Fig. Figure 23 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line IIa-IIa of Fig. 1 corresponds to; Fig. Figure 24 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line IIa-IIa of Fig. 1 corresponds to; Fig. Figure 25 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line IIa-IIa of Fig. 1 corresponds to; Fig. Figure 26 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line IIa-IIa of Fig. 1 corresponds to; Fig. Figure 27 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line IIa-IIa of Fig. 1 corresponds to; Fig. Figure 28 is a process flow diagram illustrating some of the manufacturing steps to describe the method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. 29 is a plan view illustrating a main section of a semiconductor device according to a second embodiment of the present invention; Fig. Figure 30 is a cross-sectional view showing a main section of a cross-sectional structure along the Va-Va line. Fig. 29 illustrated; Fig. 31 is a cross-sectional view showing a main section of a cross-sectional structure along the line Vb-Vb of Fig. 29 illustrated; Fig. 32 is a plan view illustrating a main section of a semiconductor device according to a third embodiment of the present invention; Fig. 33 is a cross-sectional view showing a main section of a cross-sectional structure along line VIa-VIa of Fig. 32 illustrated; Fig. Figure 34 is a cross-sectional view showing a main section of a cross-sectional structure along the line VIb-VIb of Fig. 32 illustrated; Fig. Figure 35 is a diagram illustrating a method for manufacturing the semiconductor device according to the third embodiment of the present invention, and a cross-sectional view illustrating a main section at a position corresponding to line VIa-VIa of Fig. 32 corresponds to; Fig. Figure 36 is a diagram illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line VIa-VIa of Fig. 32 corresponds to; Fig. 37 is a diagram illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention, and a plan view illustrating a main section of the plane structure of an etching mask; Fig. Figure 38 is a cross-sectional view showing a main section of a cross-sectional structure along line VIIa-VIIa of Fig. 37 illustrates; Fig. Figure 39 is a cross-sectional view showing a major section of a cross-sectional structure along line VIIb-VIIb of Fig. 37 illustrates; Fig. Figure 40 is a diagram illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line VIa-VIa of Fig. 32 corresponds to; Fig. Figure 41 is a diagram illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line VIa-VIa of Fig. 32 corresponds to; Fig. Figure 42 is a diagram illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line VIa-VIa of Fig. 32 corresponds to; Fig. Figure 43 is a diagram illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line VIa-VIa of Fig. 32 corresponds to; Fig. Figure 44 is a diagram illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention, and a cross-sectional view illustrating the main section at the position indicated by line VIa-VIa of Fig. 32 corresponds to; Fig. Figure 45 is a plan view illustrating a main section of a modification example of the semiconductor device according to the third embodiment of the present invention; Fig. Figure 46 is a cross-sectional view illustrating a main section of a semiconductor device according to a fourth embodiment of the present invention; Fig. Figure 47 is a cross-sectional view illustrating a main section of the semiconductor device according to the fourth embodiment of the present invention; Fig. 48 is an enlarged view showing section A in Fig. 47 illustrates; Fig. 49 is a diagram illustrating a method for manufacturing the semiconductor device according to the fourth embodiment of the present invention; Fig. Figure 50 is a diagram illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention; Fig. Figure 51 is a diagram illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention; Fig. Figure 52 is a diagram illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention; Fig. Figure 53 is a diagram illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention; Fig. Figure 54 is a diagram illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention; Fig. Figure 55 is a diagram illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention; Fig. Figure 56 is a diagram illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention; Fig. Figure 57 is a diagram illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention; Fig. Figure 58 is a diagram illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention; Fig. Figure 59 is a diagram illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention; and Fig. Figure 60 is a cross-sectional view illustrating a main section of a modification example of the semiconductor device according to the fourth embodiment of the present invention. TYPES OF IMPLEMENTATION OF THE PRESENT INVENTION

[0015] Semiconductor devices according to the first to fourth embodiments of the present invention are described below with reference to the drawings. The first to fourth embodiments below describe examples in which a first conductivity type is the n-type and a second conductivity type is the p-type. However, the relationship between the conductivity types can also be reversed, so that the first conductivity type is the p-type and the second conductivity type is the n-type. In the specification and the accompanying drawings, the majority carriers are electrons in the layers or regions to which an 'n' is appended, and the majority carriers are holes in the layers or regions to which a 'p' is appended. Furthermore, the symbols '+' and '-' added to an n or p indicate that the perturbation atom concentration of a semiconductor region is higher or lower, respectively, than that of a semiconductor region without the symbols.

[0016] In the description of the following first to fourth embodiments and the accompanying drawings, the same components are designated with the same reference numerals, and their repeated description is omitted. Furthermore, in the accompanying drawings described in the first to fourth embodiments, the scales and dimensional ratios differ from the actual scales and dimensional ratios to facilitate viewing and understanding. The present invention is not limited to the following first to fourth embodiments, provided that its essence and scope of protection are not altered.

[0017] In the following embodiments, the first and second directions, which are orthogonal to each other in the same plane, are referred to as an X-direction and a Y-direction, respectively. Fig. 1, Fig. 12, Fig. 13, Fig. 15, Fig. 29, Fig. 32, Fig. 37 and Fig. 45 is the horizontal direction defined as the X direction, and the vertical direction is defined as the Y direction.

[0018] In the Fig. In 2, 3, 7-11, 13, 16-19, 21-27, 30, 31, 33-36, 38-44 and 47-60, the horizontal direction is defined as the X-direction. Fig. In 4-6, 14, 17, 20 and 46, the horizontal direction is defined as the Y direction.

[0019] To make viewing the drawings easier, the following was done in the Fig. 5 and Fig. 6. The hatching, which denotes a cross-section, has been omitted. (First embodiment) Structure of the semiconductor device according to the first embodiment

[0020] As an example of a semiconductor device 1A according to a first embodiment of the present invention, a trench IGBT is described in which a drift layer 3 of the trench IGBT is implemented through a section of a semiconductor substrate, as shown in the Fig. 1-4 illustrated.

[0021] As in Fig. As illustrated in Figure 1, the X-direction and the Y-direction, which are orthogonal to each other, are defined in a principal surface of the semiconductor substrate, which has the drift layer 3 in its interior. As shown in Fig. As illustrated in Figure 2, mesa regions 5 are divided by trenches 4 that lie side by side in the X direction. As in Fig. As can be seen in Figure 1, several trenches 4 and several mesa regions 5 are arranged periodically in the X direction to form several planar patterns, each extending in a strip shape parallel along the Y direction.

[0022] In a trench IGBT, several tiny structured transistor cells are electrically connected in parallel. Therefore, a multi-cell structure capable of handling a large amount of current is implemented. Fig. Figures 1-3 illustrate a section of the semiconductor device 1A according to the first embodiment, in which triple transistor cells 2 and triple mesa regions 5 are arranged. However, the present invention is not limited to the structure shown in the Fig. 1-3 is illustrated.

[0023] As in Fig. As illustrated in Figure 2, several trenches 4, arranged side by side in the X direction, are cut into the top of the drift layer 3. Regions arranged and divided between a pair of opposing trenches 4 beneath the multiple trenches 4 are each defined as the “mesa regions 5”. A gate insulating film 6 is arranged on the inner wall of each of the multiple trenches 4.

[0024] Gate electrodes 8 are buried in each of the trenches 4 by the gate insulating film 6. As in the Fig. As can be seen in 1-3, a base region 9 of a second conductivity type (p-type) is buried in a surface layer section of the mesa region 5 in each transistor cell 2.

[0025] Several emitter regions 11 of a first conductivity type (n + -type) are periodically buried in the surface layer section of the basal region 9 along the Y-direction. In addition, several contact regions 12 of the second conductivity type (p) are present. + -Type) arranged between emitter regions 11.

[0026] The multiple emitter regions 11 and the multiple contact regions 12 are arranged alternately in the Y-direction. The depth of the contact region 12 is greater than the depth of the emitter region 11, so that a pair of contact regions 12 can sink towards bounded regions immediately below the two sides of the emitter regions 11, with the pair of contact regions 12 being separated from each other, as shown in Fig. 4 illustrates.

[0027] Several transistor cells 2 contain, as a common region, the common drift layer 3, which can consist of the semiconductor substrate, and a buffer layer 21 of the first conductivity type (n-type) and a collector region 22 of the second conductivity type (p-type). + -type), which are arranged on the back side of drift layer 3.

[0028] The drift layer 3 consists, for example, of single-crystal silicon. Both the trench 4 and the mesa region 5 extend from the surface of the mesa region 5 in a depth direction. The trench 4 is, for example, excavated with a width of approximately one micrometer and a depth of approximately five to ten micrometers. However, in the present invention, the dimensions of the trench 4 are not limited by these exemplary values. The width of the mesa region 5 in the X-direction, for example, is in the range of 0.1 to one micrometer and can, for example, be 0.5 micrometers.

[0029] The gate insulating film 6, for example, is a silicon dioxide (SiO2) film formed by a thermal oxidation process. However, the silicon dioxide film can also be formed by a method other than thermal oxidation. Furthermore, the gate insulating film 6 can, for example, be a silicon dioxide film or a silicon nitride (SisN4) film deposited by a chemical vapor deposition (CVD) process, or it can consist of stacked films implemented by a combination of these films.

[0030] In particular, the SiO2 film formed by the thermal oxidation process is preferred and advantageous because the thermal oxidation film has a high quality of dense structure, which is required for a power component (power semiconductor component), enabling operation with a high breakdown voltage.

[0031] For the gate electrode 8, for example, a polycrystalline silicon film or a doped polysilicon film containing impurities can be used as a conductive film with low resistivity. The depth of the base region 9 is less than the depth of the bottom of the trench 4. When a voltage at least as high as a threshold voltage is applied to the gate electrode 8, an inversion layer channel is induced in a section of the base region 9 that comes into contact with the side wall of the trench 4 immediately below the emitter region 11.

[0032] The emitter region 11 and the contact region 12 are arranged such that they connect two facing side walls of the trenches 4, the two side walls being assigned as a pair of side walls, each of the side walls being selected from among the side walls of the adjacent trenches 4, as shown in Fig. Figure 2 illustrates this. Furthermore, emitter region 11 and contact region 12 are arranged such that they have the same width as mesa region 5 in the X direction. Or, in other words, emitter region 11 and contact region 12 are arranged to bridge a pair of gate insulating films 6 that are opposite each other in the X direction of mesa region 5.

[0033] Base region 9 has a higher concentration of extraneous atoms than drift layer 3. Emitter region 11 has a higher concentration of extraneous atoms than both base region 9 and contact region 12. Contact region 12 has a higher concentration of extraneous atoms than base region 9 in order to reduce the contact resistance between an emitter electrode 20 and base region 9, as described below.

[0034] Buffer layer 21 is located between drift layer 3 and collector region 22. Buffer layer 21 and collector region 22 have a higher concentration of extraneous atoms than drift layer 3.

[0035] The n-drift layer 3 has a disturbance atom concentration of, for example, approximately 7×10 13 / cm 3 The basal region of p-type 9 has a perturbation atom concentration of, for example, approximately 1×10⁻⁵. 17 / cm 3 . The n + -Emitter region 11 has a perturbation atom concentration of, for example, approximately 1×10 20 / cm 3 , the p + -Contact region 12 has a disturbance atom concentration of approximately 3×10 13 / cm 3 up to 3×10 19 / cm 3 For example, the p + -Contact region 12 has a disturbance atom concentration of approximately 1×10 19 / cm 3 have.

[0036] The buffer layer of n-type 21 preferably has an interfering atom concentration of, for example, approximately 1×10 16 / cm 3 , and the p + Collector region 22 has a disturbance atom concentration of, for example, approximately 1×10 13 / cm 3 .

[0037] As in the Fig. 2 and Fig. As illustrated in Figure 3, an intermediate insulating film 15, for example a SiO2 film, is deposited such that the entire surface of the trench 4 and the mesa region 5 is covered. Then a contact hole 16 is cut into the intermediate insulating film 15, which penetrates the surface of the intermediate insulating film 15 and the intermediate insulating film 15 up to the surface of the mesa region 5.

[0038] As if through a dotted line in Fig. As shown in Figure 1, the structure of the contact hole 16 extends along the Y-direction in the planar structure of the mesa region 5 or along the longer direction of the mesa region 5 in the planar structure. For example, the planar structure of the contact hole 16 is formed into a strip shape or a rectangular structure in which the width of the contact hole 16 along the X-direction is approximately 0.5 micrometers on a mask plane.

[0039] As in the Fig. 2 and Fig. As illustrated in Figure 3, a barrier metal film 17 is selectively coated in the contact hole 16 onto the inner wall of the contact hole 16, the surface of the emitter region 11, and the surface of the contact region 12. The surface of the emitter region 11 and the surface of the contact region 12 are exposed at the bottom of the contact hole 16. The contact hole 16 is then filled with a contact plug 19 to cover the barrier metal film 17.

[0040] The barrier metal film 17, for example, is a composite film containing a titanium nitride (TiN) film and a titanium (Ti) film arranged on the TiN film. For example, the contact plug 19 can be implemented using a high-melting-point metal, such as tungsten (W). The barrier metal film 17 is arranged to prevent metal atoms from the contact plug 19 from diffusing into a semiconductor in the mesa region 5.

[0041] The reason for this is that if the metal atoms of the contact plug 19 diffuse into the semiconductor of the mesa region 5, the mesa region 5 is damaged and the contact resistance increases. The barrier metal film 17 is not placed on the surface of the intermediate insulating film 15 and is selectively buried in the contact holes 16.

[0042] As in the Fig. As illustrated in Figures 2-4, the emitter electrode 20 is positioned over the trenches 4 and the mesa regions 5 such that the intermediate insulating film 15 and the contact plugs 19 are covered. The emitter electrode 20 is electrically connected to the emitter regions 11 and the contact regions 12 by the contact plugs 19 and the barrier metal films 17, which are buried in the contact holes 16.

[0043] The emitter electrode 20 can, for example, consist of an aluminum (Al) film or an aluminum alloy film, such as an aluminum silicon (Al-Si) alloy, an aluminum copper (Al-Cu) alloy or an aluminum copper silicon (Al-Cu-Si) alloy.

[0044] A protective film 23 is deposited on the emitter electrode 20 such that the emitter electrode 20 is covered. For example, a bonding window is cut into the protective film 23 to expose a bond contact island for electrical connection to the outside, and the bond contact island is assigned to a section of the emitter electrode 20, although the bonding window is not shown in the drawing. The protective film 23 consists, for example, of a polyimide-based insulating resin.

[0045] A collector electrode 24 is electrically and metallurgically connected to the collector region 22 in such a way as to reduce the contact resistance. The collector electrode 24 is, for example, a composite layer of several metal films, such as Al and Ni films, with a gold (Au) film being arranged on the uppermost layer of the composite layer. Functioning of the semiconductor device according to the first embodiment

[0046] Next, the functioning of the semiconductor device according to the first embodiment will be described with reference to the Fig. 2 and Fig. 3 described.

[0047] In a state where a first reference potential - for example zero volts - is applied to the emitter electrode 20 and a second reference potential - for example 650 V - which is higher than the first reference potential, is applied to the collector electrode 24, the IGBT is switched off at a voltage of the gate electrode 8 that is lower than a threshold voltage.

[0048] Then, a potential difference between the emitter electrode 20 and the collector electrode 24 of the IGBT is set to zero volts. If a voltage higher than the threshold voltage is applied to the gate electrode 8 via a gate drive circuit through a gate resistor (although the gate drive circuit is not shown in the drawing), an n-type inversion layer is induced in a section of the p-type base region 9 facing the gate electrode 8, with the gate insulating film 6 positioned between the p-type base region 9 and the gate electrode 8. The inversion layer becomes a channel.

[0049] Then a voltage higher than an integrated potential – approximately 0.8 V – of the p - n -The transition between the collector region 22 and the buffer layer 21 is configured such that a forward bias is applied to the collector electrode 24. Electrons are emitted from the emitter electrode 20 through the n + -Emitter region 11, the channel of the basal region of p-type 9 and the drift layer 3 of n - -Type injected into collector region 22.

[0050] Furthermore, holes are injected from the collector region 22 through the buffer layer 21 to the drift layer 3. Then the IGBT is switched on. In the conductive state, the voltage drop between the emitter electrode 20 and the collector electrode 24 is defined as the "on-state voltage" of the IGBT.

[0051] To change the IGBT from the conductive state to the off-state, the voltage between the emitter electrode 20 and the gate electrode 8 is adjusted to a value not greater than the threshold voltage. Then, charges accumulated in the gate electrode 8 are dissipated through the gate resistor to the gate control circuit.

[0052] At this moment, the channel, which had been inverted to the n-type, reverts to the p-type, and the channel disappears. As a result, no electrons are supplied, and the IGBT is switched off. Detailed structure of emitter region and collector region

[0053] Next, emitter region 11 and contact region 12 will be described.

[0054] As in Fig. As illustrated in point 1, there are several n + -Emitter regions 11 and several p + -Contact regions 12 are arranged along the longer direction of trench 4 in the planar structure. As in Fig. As illustrated in Figure 5, the contact regions 12 are arranged side by side, and the emitter region 11 is located between the contact regions 12. The contact regions 12 are buried so that they lie deeper than the emitter region 11.

[0055] The lower sections of the two contact regions 12 extend to regions immediately below emitter region 11 on both sides of emitter region 11, and the two contact regions 12 are separated from each other. The depth d bc The contact region 12, for example, is approximately 1.5 micrometers, and the depth d e The size of emitter region 11, for example, is approximately 0.5 micrometers.

[0056] As in Fig. As illustrated in section 5, a contact region contact width W is bc, which is the length of the surface of contact region 12, measured along the Y direction, or measured along the longer direction of trench 4 or mesa region 5, less than an emitter region contact width W e , which is the length of the surface of emitter region 11, measured along the Y-direction. The contact region 12 and the emitter region 11 are in contact with the emitter electrode 20 via the contact plug 19 and the barrier metal film 17, as shown in Fig. 4 illustrates.

[0057] The width of each of the contact base interfaces 12p, which forms a curved interface between the p + -Contact region 12 or the base region of p-type 9, where the width is measured along the Y-direction on a straight line connecting both upper ends of the contact-base interface 12p, is referred to as an “effective contact region width W eff“defined. The width of an emitter-base pn transition interface 11n1, measured along the Y direction, is defined as an “emitter injection width W”. inj “ defined. Here, the emitter-basis pn transition interface 11n1 is an interface between the n + -Emitter region 11 and the base region of p-type 9, and the emitter-base pn transition interface 11n1 is in Fig. 5 represented by a straight line. The effective contact region width W eff is larger than the emitter injection width W inj Although the first embodiment is not limited to the following values, for example the contact region contact width W can be bc approximately two micrometers, and the emitter region contact width W e can be approximately three micrometers.

[0058] The contact region contact width W bc is the width of the surface of contact region 12, and the emitter region contact width We is the width of the surface of emitter region 11. Furthermore, the effective contact region width W is eff approximately four micrometers, and the emitter injection width W inj is approximately one micrometer.

[0059] As in Fig. Figure 6 illustrates a length A that is half the emitter injection width W. inj is smaller than a creep distance d crp an emitter-contact pn transition interface 11n2, which is an interface between the emitter region 11 and the contact region 12, along a curve in a cross-sectional view along the Y direction.

[0060] The semiconductor device 1A according to the first embodiment has a structure in which n + -Emitter regions 11 and the p + -Contact regions 12 are arranged alternately in the Y direction, as shown in the Fig. Figures 1-4 illustrate this. The emitter injection width W is shown in the structure. injreduced to the gate width immediately below emitter region 11, with reference to Fig. 5, to reduce, thereby making it possible to improve the latch-up strength of a parasitic thyristor.

[0061] Furthermore, the emitter region contact width W e to increase the surface area of ​​emitter region 11, thereby making it possible to reduce the one-state resistance.

[0062] In the semiconductor device 1A according to the first embodiment, as described in the Fig. As illustrated in Figures 4-6, the emitter region 11 is located between a pair of contact regions 12. Because the soils of the contact regions 12 lie deeper than the emitter region 11, both of the lower sections of the contact regions 12 extend laterally towards bounded sections immediately below both sides of the emitter region 11, such that the two contact regions 12 are separated from each other by the emitter region 11. Therefore, in contrast to the vertical trench IGBT disclosed in JP 2013-187440 A, the emitter injection width W depends inj not relative to the emitter region contact width W e ab, which is the width of the surface of emitter region 11, measured along the Y direction.

[0063] As a result, a reduction in the emitter injection width W is possible. inj possible without the emitter region contact width W eto reduce the emitter region, which is connected to the emitter electrode 20 by the contact plug 19 and the barrier metal film 17. Or in other words: Increasing the emitter region contact width W e is possible without the emitter injection width W inj to enlarge.

[0064] The reason for the advantageous effects described above is as follows. The emitter injection width W inj is determined by the distance between the two contact regions 12, whose lower sections extend on both sides towards localized sections immediately below the two sides of the emitter region 11, such that the two contact regions 12 are separated from each other by the emitter region 11. Even if the emitter region contact width W e As the emitter injection width W increases and the width of emitter region 11 becomes larger, the emitter injection width W now varies. inj not.

[0065] Therefore, in the semiconductor device 1A according to the first embodiment, the reduction of the emitter injection width W is inj possible without the emitter region contact width W e The surface area of ​​emitter region 11 can be reduced, thus minimizing the total channel length immediately below emitter region 11. This also allows for a reduction in channel integration density.

[0066] Because the emitter region contact width W e can be enlarged without increasing the emitter injection width W inj To increase the size, it is possible to improve the latch-up strength and reduce the one-state stress of the trench IGBT.

[0067] The emitter region contact width W e can be smaller than the contact region contact width W bc. That is, the emitter region 11 can be formed such that lower sections of the two contact regions 12, which fit with both sides of the emitter region 11, extend in the direction of localized sections immediately below the base of the emitter region 11, since the emitter region 11 is located between the two contact regions 12.

[0068] In a structure where n + -Emitter regions 11 and the p + -Contact regions 12 are arranged alternately in the Y-direction, namely the longer direction in the planar structure of the trench 4 or the mesa region 5, as in Fig. As illustrated in Figure 5, the p-type basal region 9, located directly below the emitter region 11, serves as a key channeling region. Therefore, if the emitter region 11 has an emitter region contact width W e and the emitter injection width W injIf the channels, which are identical to each other, are arranged periodically, the channel integration density generally decreases to a value that is lower than that of the prior art structure, in which an emitter region 11 is continuously buried in a strip along the Y-direction. In the prior art structure, there is the case that the one-state voltage can increase correspondingly to the decrease in channel integration density.

[0069] Here, the emitter injection width W is defined. inj It is designed to be larger if the channel integration density needs to be increased to reduce the one-state voltage. However, if the emitter injection width W injAs the voltage increases, the voltage drop caused by holes located immediately below emitter region 11 becomes greater than the integrated potential of the pn junction between emitter region 11 and base region 9 when the semiconductor device is switched off, and therefore latch-up is likely to occur. Latch-up is also caused by the structure in which the contact regions 12 and emitter regions 11 are arranged alternately.

[0070] This means that since emitter region 11 is configured in such a way that emitter region 11 bridges adjacent trenches 4, as in Fig. As illustrated in point 2, holes must be located in the Y-direction of Fig. 5. Move so that the holes are in the p + -Contact region 12 can flow.

[0071] Therefore, the voltage drop is increased by a value corresponding to the emitter injection width W. injThis corresponds to the width of the emitter-base pn transition interface 11n1, and latch-up is likely. Therefore, in a structure where the emitter regions 11 and the contact regions 12 are arranged alternately in the Y direction, a regime for increasing the emitter injection width W is required. inj , which is the width of the emitter-base pn transition interface 11n1 to determine the emitter injection width W inj Making it larger than a certain value, which can be several micrometers, for example, is difficult to achieve.

[0072] In the semiconductor device according to the first embodiment, the emitter region contact width W e and the emitter injection width W injdifferent from each other. In particular, the floors of the two contact regions 12, which converge with the two sides of the emitter region 11, are lower than the emitter region 11, and the lower sections of the two contact regions 12 extend on both sides to sections immediately below the two sides of the floor of the emitter region 11 in a configuration in which the emitter region 11 is located between the contact regions 12.

[0073] The distance, or emitter injection width W inj The distance between the contact regions 12 immediately below the floor of the emitter region 11 can, for example, preferably be in the range of 0.1 micrometers to two micrometers.

[0074] Furthermore, the channel integration density can be increased by simply reducing the width of the contact regions 12 in the Y-direction relative to the width of the emitter regions 11, either to increase the proportion of emitter regions 11 in the planar structure or to increase the number of emitter regions 11. However, if the width of the contact region 12 in the Y-direction is simply reduced relative to the width of the emitter regions 11, either to increase the proportion of emitter regions 11 in the planar structure or to increase the number of emitter regions 11, the hole current density immediately below the emitter regions 11 increases because the concentration of holes flowing in the channel increases due to the increase in the number of injected electrons.

[0075] Latch-up is determined by the hole current density and a resistance component in a section traversed by the holes. Therefore, in a structure where the width of the contact region 12 in the Y-direction is relatively reduced to increase the proportion of emitter regions 11 in the planar structure or to increase the number of emitter regions 11, even if the channel integration density increases, latch-up is likely to occur.

[0076] While the emitter injection width W inj If kept at a constant value, the effective contact region width W can be eff The effective contact region width W can be increased to reduce the hole current density. In the semiconductor device 1A according to the first embodiment, as described above, the effective contact region width W can be increased. eff be larger than the contact region contact width W bc , because the contact region contact width W bcis smaller than the emitter region contact width W e and the effective contact region width W eff is larger than the emitter injection width W inj Therefore, according to the potential profile, an increase in the percentage of holes that lead into the p is possible. + -flow into contact region 12 and are attracted by the electrons in the channel.

[0077] As a result, the hole current density is immediately below the n + -Emitter region 11 is reduced. Therefore, an improvement in the latch-up strength of emitter region 11 is possible, even if the contact region contact width W is reduced. bc the surface area of ​​contact region 12 is relatively reduced to decrease the proportion of the emitter region contact width W e to increase and increase the channel integration density. Since the channel integration density can be increased, a reduction in the one-state voltage is also possible.

[0078] The specific resistance of the base region 9 immediately below the emitter region 11 is higher than that of the contact region 12. However, in the first embodiment, as in Fig. Figure 6 illustrates the width A, which is half the emitter injection width W. inj is smaller than the creep distance d crp Therefore, a reduction of the resistance R1 from the center of the emitter injection width W is necessary. inj from base region 9 immediately below emitter region 11 to contact region 12, and an improvement in latch-up strength is possible.

[0079] Since the contact region 12 is arranged such that it lies deeper than the emitter region 11 and extends directly below the floor of the emitter region 11, dispersion of the hole stream I is holeto the contact region 12. Therefore, a rapid movement of the holes, which remain directly below the emitter region 11, to the emitter electrode 20 through the contact region 12 is possible.

[0080] The latch-up strength can be increased by designing the contact region 12 to be deeper than the emitter region 11, thereby reducing the saturation current. However, if the depth of the contact region 12 is too great, the latch-up strength will decrease. Therefore, it is preferred that the depth d bc the contact region at least 0.5 micrometers and at most 2 micrometers from depth d e emitter region 11.

[0081] As in Fig. As illustrated in Figure 7, an upper edge section 17d of the barrier metal film 17 is slightly lower than an upper edge section 16d of the contact hole 16. A surface 19a of the contact plug 19 is a concave surface with a central recess. Since the surface 19a of the contact plug 19 is concave, an increase in the contact area between the contact plug 19 and the emitter electrode 20 deposited on the contact plug 19 is possible.

[0082] Therefore, a reduction in the contact resistance between emitter region 11 and emitter electrode 20, and in the contact resistance between contact region 12 and emitter electrode 20, is possible. Consequently, even if the width of contact hole 16 is reduced due to downscaling of the IGBT, a reduction in the one-state voltage of the IGBT is possible. Method for manufacturing the semiconductor device according to the first embodiment

[0083] Next, a method for manufacturing the semiconductor device according to the first embodiment is described with reference to the Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27 to Fig. 28. The following description describes a case in which interference ions for forming the emitter region 11 and interference ions for forming the contact region 12 are implanted into a surface layer section of the base region 9, and a heat treatment for activating the interference ions is carried out together. However, the present invention is not limited to this method.

[0084] (a) First, an n - Semiconductor substrate 3SUB produced. Then, as in Fig. Figure 8 illustrates multiple trenches 4 in a main area of ​​the semiconductor substrate 3 SUB excavated, and Mesa Region 5, which is situated and divided between adjacent trenches 4, is being excavated. As in Fig. As illustrated in Figure 1, trench 4 and mesa region 5 are buried in a strip-shaped parallel structure, which, for example, has a width of approximately 1 micrometer and a depth of approximately 5 to 10 micrometers.

[0085] The trench 4 is formed by selectively etching the main surface of the semiconductor substrate 3. SUB The trench was excavated using photolithography and dry etching techniques, such as RIE. As a result, several mesa regions 5 are arranged in the X-direction – the latitude direction of trench 4 or mesa region 5.

[0086] (b) Then, in the main area of ​​the semiconductor substrate 3 SUBThe gate insulating film 6, which is a SiO2 film, is induced in the trench 4, for example, by a thermal oxidation process. During deposition, the gate insulating film 6 is also deposited on the surface of an upper part of the mesa region 5 in the main area of ​​the semiconductor substrate 3. SUB deposited and continuously buried in trench 4 and on the surface of the upper part of mesa region 5.

[0087] Then, as for example in Fig. Figure 9 illustrates a doped polysilicon film with low resistivity as a gate material 7 on the main surface of the semiconductor substrate 3. SUB deposited to fill the trenches 4. For example, the gate material 7 is applied with a thickness of approximately 1 micrometer with reference to a trench width of 1 micrometer.

[0088] (c) Then the gate material 7 is back-etched by dry etching, such as RIE. Then, as in Fig. Figure 10 illustrates that the gate material 7 is selectively removed from the trench 4 and the mesa region 5, and the gate electrode 8, consisting of the gate material 7, is buried in the trench 4. During removal and deposition, the gate electrode 8 is selectively buried in the trench 4 through the gate insulating film 6, and the main area of ​​the semiconductor substrate 3 SUB is essentially flat.

[0089] During removal and application, the gate material 7 is back-etched at an etch rate that exhibits selectivity with respect to the gate insulating film 6. Therefore, the gate insulating film 6 acts as an etch stopper on the mesa region 5 and can prevent the surface of the upper part of the mesa region 5 from being etched.

[0090] (d) Then the gate insulating film 6 on the surface of the upper part of the mesa region 5 is selectively removed by wet etching such that the surface of the upper part of the mesa region 5 is exposed. Then, as described in Fig. Figure 11 illustrates the basal region of p-type 9 being buried in the surface layer section of mesa region 5. The basal region 9 is implanted, for example, by boron ions ( 11 B + ) or boron difluoride ions ( 49 BF2 + ) as p-type interference ions and implementing a heat treatment to activate the implanted interference ions.

[0091] The base region 9 is shallower than the trench 4. For example, the base region 9 is provided with a depth of approximately 2 to 8 micrometers relative to the depth of the trench 4, which is in the range of 5 to 10 micrometers. In the first embodiment, the base region 9 is formed after the gate electrode 8 has been embedded in the trench 4. However, the base region 9 can be located on the entire surface of the surface layer section of the main area of ​​the semiconductor substrate 3. SUB are deposited before the trench 4 in the main area of ​​the semiconductor substrate 3 SUB is dug. In this case, trench 4 is thus dug in the main area of ​​the semiconductor substrate 3. SUB dug that it runs through base region 9.

[0092] (e) Then, first p-type perturbation ions are selectively implanted into several regions that are periodically buried in the surface layer section of basal region 9 in the Y direction. In particular, first, as in the Fig. 12, Fig. 13 to Fig. Figure 14 illustrates that several first masks RM1 are formed as perturbation atom incorporation masks on the surface layer section of the basal region 9 in the Y direction at certain intervals b1.

[0093] The first masks RM1 are formed by applying a photosensitive resist film to the entire main surface of the semiconductor substrate 3. SUBThe material is deposited, and, for example, an exposure and development process is carried out for the light-sensitive resist film to process the light-sensitive resist film into a specific structure. The first masks RM1 are buried in strip-shaped parallel structures that extend continuously in the X-direction, so that they cross the trench 4 between adjacent mesa regions 5. For example, the first masks RM1 are formed with a width a1 of approximately 4 micrometers and arranged at an interval b1 of approximately 2 micrometers and a center-to-center distance of approximately 6 micrometers in the Y-direction.

[0094] (f) Then, as in the Fig. 13 and Fig. Figure 14 illustrates, for example, boron ions ( 11 B + ) selectively implanted as the first interference ions in the surface layer section of the basal region 9 between the first masks RM1, which lie next to each other in the Y direction. Here is Fig. 13 a cross-sectional view showing a main section of a cross-sectional structure along line IIIa-IIIa of Fig. 12 illustrated. Fig. Figure 14 is a cross-sectional view showing a major section of a cross-sectional structure along line IIIb-IIIb of Fig. 12 illustrated. The boron ions ( 11 B + ) are under conditions such as a dose of approximately 1×10 15 / cm 2 up to 1×10 16 / cm 2 and an acceleration energy of approximately 120 keV. During implantation, several first perturbation ion implantation regions 12A are created, into which the first perturbation ions - boron ions ( 11 B + ) - are implanted periodically in the surface layer section of the base region 9 with a center distance MP1 between the first masks RM1 in the Y direction.

[0095] (g) Then, after the first masks RM1 have been removed, second n-type perturbation ions are selectively implanted in the surface layer section of the basal region 9 between several first perturbation ion implantation regions 12A in the Y direction. The implantation is carried out at an interval larger than that between the arrangement patterns of the several first perturbation ion implantation regions 12A, with the same center-to-center spacing as that between the several first perturbation ion implantation regions 12A, and with an acceleration energy lower than that of the first perturbation ions.

[0096] In particular, first, as in the Fig. 15, Fig. 16 to Fig. Figure 17 illustrates the formation of second masks RM2 with a center-to-center distance MP2 equal to the center-to-center distance between the first masks RM1. The second masks RM2 are deposited on the first perturbation atom ion implantation regions 12A such that an interval b2 in the same direction as that in which the first masks RM1 are arranged is larger than the interval b1 between the first masks RM1 lying side by side, and the width a2 of the second masks RM2 along the same direction as that in which the first masks RM1 are arranged is smaller than the width a1 of the first mask RM1.

[0097] The second masks RM2 are produced by processing a photosensitive resist film that covers the entire main surface of the semiconductor substrate 3 SUB It is deposited in a specific structure, similar to the first masks RM1. Similar to the first masks RM1, the second masks RM2 are buried in strip-shaped parallel structures that extend continuously in the X-direction, so that they cross the trench 4 between adjacent mesa regions 5. For example, the second masks RM2 are formed with a width a2 of approximately 3 micrometers and arranged at intervals b2 of approximately 3 micrometers and with the same center-to-center spacing as that between the first masks RM1 in the Y-direction.

[0098] (h) Then, as in the Fig. 16 and Fig. Figure 17 illustrates the second perturbation ions selectively entering the surface layer section of the basal region 9 between the second masks RM2, which lie side by side, with an acceleration energy of less than that of the first perturbation ions - boron ions ( 11 B + ) - implanted. For example, arsenic ions ( 75 As + ) are used as the second interference ions.

[0099] Here is Fig. 16 a cross-sectional view showing a main section of a cross-sectional structure along line IVa-IVa of Fig. 15 illustrated. Fig. Figure 17 is a cross-sectional view showing a main section of a cross-sectional structure along line IVb-IVb of Fig. 15 illustrates. The arsenic ions ( 75 As + ) are under conditions such as a dose of approximately 1×10 15 / cm 2 up to 1×10 16 / cm 2 and implanted with an acceleration energy of approximately 120 keV.

[0100] During implantation, as in Fig. Figure 17 illustrates a second interference ion implantation region 11A, in which the second interference ion - arsenic ion ( 75 As +) - are implanted, flatter than the first interference atom ion implantation region 12A in the surface layer section of the base region 9 between the first interference atom ion implantation regions 12A. Several second interference atom ion implantation regions 11A are arranged with the same center-to-center spacing as the first interference atom ion implantation regions 12A.

[0101] The width a2 of the second mask RM2 in the Y-direction is larger than the interval b1 between the first masks RM1, which are adjacent. The interval b2 between the second masks RM2, which are adjacent, is smaller than the width a1 of the first mask RM1 in the Y-direction. Therefore, as in Fig. As illustrated in Figure 17, the second interference atom ion implantation region 11A and the first interference atom ion implantation region 12A partially overlap.

[0102] (i) Then, after the second masks RM2 have been removed, the first and second interference ions are activated. That is, the p + -Contact region 12 is buried in the first interference atom ion implantation region 12A, into which the first interference ions - boron ions ( 11 B + ) - were implanted. Furthermore, the n + -Emitter region 11 in the second interference ion- implantation region 11A, into which the second interference ions - arsenic ions ( 75 As + ) - were implanted.

[0103] In particular, heat treatments are used to activate the implanted boron ions ( 11 B + ) and the implanted arsenic ions ( 75 As + ) carried out jointly. Therefore, as in the Fig. 18, Fig. 19 to Fig. 20 illustrates the n + -Emitter region 11, into the arsenic ions ( 75 As + ) when the second perturbation ions were doped, and the p +-Contact region 12, into which boron ions ( 11 B + ) when the first interference ions were doped.

[0104] Here is Fig. 18 a cross-sectional view illustrating a main section at a position corresponding to line IIa-IIa of Fig. 1 corresponds to. Fig. 19 is a cross-sectional view illustrating a main section at a position corresponding to line IIb-IIb of Fig. 1 corresponds to. Fig. 20 is a cross-sectional view illustrating a main section at a position corresponding to line IIc-IIc of Fig. 1 corresponds to.

[0105] During the formation process, the arsenic ions ( 75 As + ) implanted with a dose higher than the dose of boron ions ( 11 B + Therefore, as in Fig. Figure 20 illustrates an overlap region between a section of the region into which the boron ions ( 11 B +) were implanted, and a section of the region into which the arsenic ions ( 75 As + ) were implanted, which n + -Emitter region 11.

[0106] During the formation process, the arsenic ions ( 75 As + ) selectively implanted as follows. Specifically, the distance between the second interference atom ion implantation regions 11A, into which the arsenic ions ( 75 As + ) were implanted, greater than the distance between the arrangement patterns of several first perturbation ion implantation regions 12A, into which the first perturbation ions - boron ions ( 11 B + ) - were implanted. In the second perturbation atom ion implantation regions 11A, the implantation is implemented with the same center-to-center spacing as the several first perturbation atom ion implantation regions 12A, but with a lower acceleration energy than the first perturbation ions.

[0107] Furthermore, the implantation in the second perturbation atom ion implantation regions 11A is implemented in the surface layer section of the base region 9 between several first perturbation atom ion implantation regions 12A in the Y direction. Therefore, as in Fig. Figure 20 illustrates that the contact regions 12, which lie next to each other, with the emitter region 11 located between the contact regions 12, lie deeper than the emitter region 11 and can extend immediately below the emitter region 11 in such a way that they are separated from each other.

[0108] The emitter injection width W inj , which in Fig. As illustrated in 20, it depends on the distance between adjacent contact regions 12 in the Y direction, that is, the width a1 of the first mask RM1 in the Y direction.

[0109] Therefore, a change in the emitter injection width W can inj, which is caused by the positional deviation between the first mask RM1 for forming the contact region 12 and the second mask RM2 for forming the emitter region 11, can be avoided. Furthermore, as shown in Fig. Figure 5 illustrates the contact region contact width W bc be smaller than the emitter region contact width W e , and the effective contact region width W eff can be larger than the emitter injection width W inj .

[0110] The maximum width of an overlap section between the first perturbation atom ion implantation region 12A and the second perturbation atom ion implantation region 11A need not be approximately 0.3 micrometers according to an arrangement. The structure in which the contact regions 12, which are in contact with both sides of the emitter region 11, lie deeper than the emitter region 11 and extend immediately below the base of the emitter region 11 such that they are separated from each other, as in Fig. As illustrated in Figure 4, this can be achieved through the diffusion of atoms during heat treatment.

[0111] (j) Then, as in Fig. 21 illustrates the intermediate layer insulating film 15, which contains a SiO 2- The film is located on the main surface of the semiconductor substrate 3. SUB, which includes the top of trench 4 and the top of mesa region 5, for example by a CVD process. Then the contact hole 16 is etched into the interlayer insulating film 15, for example by a photolithography technique and a dry etching technique, so that it extends from the surface of the top part of the interlayer insulating film 15 to the surface of the top part of mesa region 5.

[0112] As if through a dotted line in Fig. As shown in Figure 1, the contact holes 16 are dug in a strip-shaped parallel planar structure in the mesa region 5 along the Y-direction, specifically the longer direction in the planar structure of trench 4 or mesa region 5. The contact hole 16 is dug such that it passes over the emitter region 11 and the contact region 12, which are buried in the surface layer section of mesa region 5.

[0113] Then, as in Fig. Figure 22 illustrates that the barrier metal film 17 is deposited on the inner wall of the contact hole 16, on the surface of the mesa region 5, and on the surface of the intermediate insulating film 15, for example, by a PVD process. The barrier metal film 17 is a composite film that contains—from the underside—a titanium (Ti) film and a titanium nitride (TiN) film. The titanium film is deposited with a thickness of, for example, approximately 40 nanometers. The titanium nitride film is deposited with a thickness of, for example, approximately 100 nanometers.

[0114] (k) Then, as in Fig. Figure 23 illustrates, for example, a tungsten (W) film deposited as a plug material 18 by a CVD process to fill the contact hole 16. For example, the plug material 18 is deposited with a thickness of approximately 0.7 micrometers relative to the contact hole 16, which has a width of 0.5 micrometers. Upon deposition, the tungsten film formed by the CVD process exhibits better step coverage in a finely stepped section than an aluminum film or an aluminum alloy film deposited by a sputtering process.

[0115] Therefore, filling the contact hole 16 with the tungsten film with good step coverage is possible even if the width of the mesa region 5 in the X-direction is reduced due to downward scaling and the aspect ratio of the contact hole 16 increases. The aspect ratio – depth / width – of the width of the contact hole 16 in the X-direction to the depth of the contact hole 16 can be in the range of approximately 0.8 to 1.5.

[0116] (1) Then the plug material 18 and the barrier metal film 17 are back-etched by dry etching, such as RIE, and the plug material 18 on the contact hole 16 and the intermediate insulating film 15 is selectively removed. The barrier metal film 17 on the intermediate insulating film 15 is also selectively removed. As described in Fig. As illustrated in Figure 24, the contact hole 16 is filled with the contact plug 19 formed from the plug material 18.

[0117] The barrier metal film 17, which selectively remains in the contact hole 16, is induced during deposition; the contact plug 19 is selectively buried in the contact hole 16 by the barrier metal film 17; and the surface of the intermediate insulating film 15 is essentially flat.

[0118] During deposition, as in Fig. Figure 4 illustrates that the contact plug 19 is electrically connected to the n + -Emitter region 11 and the p + -Contact region 12, which are buried in the surface layer section of base region 9, are connected by the barrier metal film 17.

[0119] As in Fig. As illustrated in Figure 24, the upper edge section 17d of the barrier metal film 17, which remains in the contact hole 16, lies slightly lower than the upper edge section 16d of the contact hole 16. The surface 19a of the contact plug 19 is a concave surface in which a central section is recessed.

[0120] (m) Then a metallic film, which is an Al film or an aluminum alloy film, consisting of an Al-Si alloy, an Al-Cu alloy or an Al-Cu-Si alloy, is applied to the entire main surface of the semiconductor substrate 3 SUB , which contains the top surface of the intermediate insulating film 15 and the top surface of the contact plug 19, for example deposited by a sputtering process.

[0121] The metallic film is then structured by etching, and the emitter electrode 20 comes into contact with the barrier metal film 17 and the contact plug 19 in the contact hole 16 and is electrically connected to the barrier metal film 17, and the contact plug 19 is deposited on the intermediate insulating film 15, as shown in Fig. 25 illustrated.

[0122] Structuring, as in Fig. Figure 4 illustrates the emitter electrode 20 being electrically connected to the n + -Emitter region 11 and the p +-Contact regions 12, which are buried in the surface layer section of the p-type basal region 9, are connected by the contact plug 19 and the barrier metal film 17. The surface 19a of the contact plug 19, which comes into contact with the emitter electrode 20, is a concave surface with a central recess.

[0123] Therefore, the contact area between the emitter electrode 20 and the contact plug 19 is larger than when the contact plug 19 has a flat surface. As a result, a reduction in the contact resistance between the emitter region 11 and the contact region 12 and the emitter electrode 20 is possible.

[0124] (n) Then the back side of the semiconductor substrate 3 SUB for example, ground by a back-grinding process in such a way that the thickness of the semiconductor substrate 3 SUB in a substrate back grinding step S11 in Fig. 28 is reduced.

[0125] Then, as in Fig. Figure 26 illustrates the n-type buffer layer 21 and the p + -Collector region 22 in a surface layer section of the back side of the semiconductor substrate 3 SUB in a buffer layer and collector region formation step S12 in Fig. 28 buried.

[0126] The buffer layer 21 and the collector region 22 are formed by the following procedure. First, for example, phosphorus ions ( 31 P + ) as n-type interference ions into the back side of the semiconductor substrate 3 SUB implanted, and boron ions ( 11 B + ) are introduced as p-type interference ions into the back side of the semiconductor substrate 3 SUB implanted. Then a heat treatment is performed to activate the implanted disturbance ions in order to form the buffer layer 21 and the collector region 22.

[0127] The buffer layer 21 is deposited at a position that is located in the depth direction from the back side of the semiconductor substrate 3. SUB her lies deeper than the collector region 22, and the remaining semiconductor substrate 3 SUB The drift layer 3. The perturbation ions for depositing the n-type buffer layer 21 are implanted under the condition in which the acceleration energy is greater than that of the perturbation ions for forming the p-type collector region 22. Several transistor cells 2 implementing the trench IGBT are arranged in parallel by the formation.

[0128] (o) Then, as in Fig. Figure 27 illustrates the protective film 23, which consists, for example, of an insulating polyimide-based resin, in a protective film deposition step S13 in Fig. 28 is deposited in such a way that the entire surface of the emitter electrode 20 is covered. Then, in a lifetime control step S14, Fig. 28, as in Fig. 27 illustrates charged particles, such as electron beams, helium (He) lines or X-rays, from the top of the main surface of the semiconductor substrate 3 SUB here to the main surface of the semiconductor substrate 3 SUB The radiated charged particles break crystals in the semiconductor substrate 3. SUB , in order to induce defects. Therefore, lifetime control is implemented.

[0129] (p) Then, in a hydrogen curing step, S15 is in Fig. 28 a hydrogen curing for the semiconductor substrate 3 SUB executed to eliminate the defects caused by the radiation of charged particles in the previous lifetime control step S14 in Fig. 28 were caused, or to reverse a change in the threshold voltage of the IGBT. In hydrogen annealing, for example, the semiconductor substrate 3 SUBexposed to a hydrogen atmosphere at a temperature of approximately 360°C for about 60 minutes.

[0130] During hydrogen annealing, it is difficult to conduct hydrogen (H2) through the barrier metal film 17, which contains a titanium film. However, as described in Fig. Figure 27 illustrates that the barrier metal film 17 is selectively deposited in the contact hole 16 and is not deposited on the surface of the interlayer insulating film 15. Therefore, hydrogen passes through the protective film 23, the emitter electrode 20, and the interlayer insulating film 15 from the top surface of the main area of ​​the semiconductor substrate 3. SUB here.

[0131] Therefore, a trouble-free supply of hydrogen to the main surface of the semiconductor substrate 3 SUBand achieving the effect of sufficient hydrogen healing, that is, sufficient elimination of the defects caused by the radiation of the charged particles, or reversing a change in the threshold voltage of the IGBT, is possible. Finally, the collector electrode 24 is bonded to the collector region 22 in a collector electrode formation step S16 in Fig. 28 arranged. This establishes a wafer process for the semiconductor device 1A according to the [document / section] Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 to Fig. Figure 7 illustrates the first embodiment of the present invention, which is essentially complete.

[0132] The method for manufacturing the semiconductor device 1A according to the first embodiment of the present invention does not necessarily include the lifetime control step S14 and the hydrogen annealing step S15. In general, a method for reducing the injection efficiency of holes from the collector region 22 is used to reduce the one-state voltage and switching losses—for example, turn-off losses—of the IGBT.

[0133] Therefore, if a reduction in the lifetime of minority carriers is not necessary, the lifetime control step S14 and the hydrogen annealing step S15 do not need to be carried out.

[0134] As described above, in the process for manufacturing the semiconductor device 1A according to the first embodiment of the present invention, arsenic ions ( 75 As +) selectively implanted as follows. Specifically, the interval b2 between the second masks RM2 is on the first interference ion implantation regions 12A, into which the first interference ions -- boron ions ( 11 B + ) -- to be implanted, wider than the interval b1 between the first masks RM1, which are adjacent. In addition, the width a2 of the second mask RM2 is smaller than the width a1 of the first mask RM1.

[0135] Furthermore, arsenic ions ( 75 As + ) implanted into the surface layer section of the basal region 9 between the first perturbation ion implantation regions 12A, using the second masks RM2, which are arranged at the center-to-center distance MP2, which is the same as the center-to-center distance MP1 between the first mask RM1. An acceleration energy is chosen at which a projection area is narrower than that of the first perturbation ions, and the arsenic ions ( 75 As +) are implanted with the selected acceleration energy.

[0136] Therefore, the method for manufacturing the semiconductor device 1A according to the first embodiment of the present invention, as described in Fig. 5 and Fig. Figure 20 illustrates the contact regions 12, which lie adjacent to each other, with the emitter region 11 located between the contact regions 12, deeper than the emitter region 11. Furthermore, the contact regions 12, which lie adjacent to each other, with the emitter region 11 located between the contact regions 12, can extend immediately below the emitter region 11 and can be separated from each other.

[0137] Furthermore, a change in the emitter injection width W can inj This can be avoided by misalignment between the first RM1 masks, which are in the Fig. 12 and Fig. 14 are illustrated, and the second masks RM2 for forming the emitter region 11, which are in the Fig. 15 and Fig. 17 are illustrated, which is caused. As in Fig. As illustrated in section 5, the contact region contact width W can be bc be smaller than the emitter region contact width W e , and the effective contact region width W eff can be larger than the emitter injection width W inj .

[0138] In the method for manufacturing the semiconductor device 1A according to the first embodiment of the present invention, as described above, the beaming of the charged particles can, if necessary, be carried out in the lifetime control step and the hydrogen annealing step.

[0139] In the case where the emission of charged particles is performed in the lifetime control step and the hydrogen curing step, it is difficult to conduct hydrogen through the titanium film once the defects caused by the emission of charged particles in the previous lifetime control step have been eliminated or a change in the IGBT threshold voltage has been reversed. The barrier metal film 17, which contains the titanium film, is selectively buried in the contact hole 16 and is not deposited on the surface of the intermediate insulating film 15.

[0140] Therefore, the trouble-free supply of hydrogen to the main surface of the semiconductor substrate 3 SUB from the top of the main surface of the semiconductor substrate 3 SUBThis is possible, for example, through the protective film 23, the emitter electrode 20, and the interlayer insulating film 15. As a result, it is possible to achieve the effect of sufficient hydrogen regeneration, i.e., the elimination of defects caused by the radiation of charged particles, or a sufficient change in the threshold voltage of the IGBT.

[0141] Since the barrier metal film 17 can be used, an increase in contact resistance caused by the diffusion of atoms in the contact plug 19 can be avoided. As a result, an increase in the switching speed of the IGBT is possible.

[0142] In the method for manufacturing the semiconductor device 1A according to the first embodiment of the present invention, the plug material 18 is etched back to remove the barrier metal film 17 on the interlayer insulating film 15. Therefore, the barrier metal film 17 is selectively deposited in the contact hole 16. As a result, a reduction in the number of manufacturing steps is possible, and a reduction in the cost of the semiconductor device 1A, which contains a high-speed switching IGBT, is possible.

[0143] In the method for manufacturing the semiconductor device 1A according to the first embodiment of the present invention, the plug material 18 is etched back to remove the barrier metal film 17 on the intermediate insulating film 15. Furthermore, the barrier metal film 17 that selectively remains in the contact hole 16 is deposited. Therefore, the barrier metal film 17 is deposited in the contact hole 16 by self-alignment.

[0144] As a result, it is unnecessary to pay attention to a deviation between the structuring position of the barrier metal film 17 and the position of the contact hole 16, and the production of an IGBT containing a fine transistor cell 2 is easily possible.

[0145] In the method for manufacturing the semiconductor device 1A according to the first embodiment of the present invention, the second interference ions for forming the emitter region 11 and the first interference ions for forming the contact region 12 are first implanted into the surface layer section of the base region 9. Then, heat treatments to activate the interference ions are carried out simultaneously to form the emitter region 11 and the contact region 12. However, the present invention is not limited to the method mentioned above.

[0146] For example, the heat treatments can be carried out in different steps. In the case that the heat treatments are carried out in different steps, either the emitter region 11 or the contact region 12 can be formed first. However, boron ions ( 11 B + ) or boron difluoride ions ( 49 BF2 +), which are p-type interference ions, have a higher diffusion coefficient than arsenic ions ( 75 As + ) or phosphorus ions ( 31 P + ), which are n-type interference ions.

[0147] Therefore, it is preferred that the implantation of boron ions ( 11 B + ) or boron difluoride ions ( 49 BF2 + ), the interference ions are of the p-type, and the heat treatment to activate the interference ions is performed first. (Second embodiment)

[0148] In the first embodiment, a semiconductor device 1A was described, which is a single device with a single IGBT. In contrast, a second embodiment describes a semiconductor device 1B in which a trench IGBT and a diode are integrated.

[0149] As in the Fig. 29, Fig. 30 to Fig. Figure 31 illustrates that in the semiconductor device 1B according to the second embodiment of the present invention, a section of an n - A drift layer 3 is provided on a semiconductor substrate made, for example, of single-crystal silicon. The semiconductor device 1B according to the second embodiment is a reverse-biased IGBT (RC-IGBT) in which a trench IGBT and a diode are connected in reverse parallel to a semiconductor substrate.

[0150] As in Fig. As illustrated in Figure 29, an X-direction and a Y-direction, which are orthogonal to each other, are defined in a principal surface of the semiconductor substrate, which has the drift layer 3 in the principal surface. As shown in the Fig. 30 and Fig. As illustrated in Figure 31, several mesa regions 5, containing a transistor mesa region 5a, a diode mesa region 5b, and a floating mesa region 5c, are divided in the main area of ​​the semiconductor substrate by trenches 4 that lie side by side in the X direction. Fig. As can be seen in Figure 29, several trenches are arranged periodically in the X direction.

[0151] For example, several transistor mesa regions 5a and several diode mesa regions 5b are arranged periodically and alternately in the X direction. The floating mesa region 5c, for example, is positioned between the transistor mesa region 5a and the diode mesa region 5b, thus realizing an integrated structure. The trenches 4, the transistor mesa regions 5a, the diode mesa regions 5b, and the floating mesa regions 5c each define stripe-shaped planar structures that extend parallel along the Y direction.

[0152] The trench IGBT has a multi-cell structure in which several tiny structured transistor cells 2a are electrically connected in parallel to obtain a large amount of current. The diode also has a multi-cell structure in which several tiny structured diode cells 2b are electrically connected in parallel to obtain a high breakdown voltage.

[0153] Fig. 29, Fig. 30 to Fig. Figure 31 illustrates a section of the semiconductor device 1B according to the second embodiment, in which a transistor cell 2a, a diode cell 2b, a transistor mesa region 5a, a diode mesa region 5b, and a floating mesa region 5c are formed. However, the present invention is not limited to the second embodiment, which is described in the Fig. 29, Fig. 30 to Fig. 31 is illustrated.

[0154] As in the Fig. 30 and Fig. As illustrated in Figure 31, several trenches 4, lying side by side in the X direction, are dug in the drift layer 3. Several mesa regions 5 – the transistor mesa region 5a, the diode mesa region 5b, and the floating mesa region 5c – are defined, nested within each other and divided between a pair of opposing trenches 4 beneath the multiple trenches 4.

[0155] A gate insulating film 6 is arranged along the inner wall of each of the multiple trenches 4. A gate electrode 8 is buried in each trench 4 through the gate insulating film 6.

[0156] As in the Fig. 29, Fig. 30 to Fig. As can be seen in Figure 31, transistor cell 2a contains a p-type 9 base region buried in a surface layer section of transistor mesa region 5a, and several n + -Emitter regions 11, which are periodically buried in a surface layer section of the basal region 9 along the Y direction.

[0157] Transistor cell 2a contains several p + -Contact regions 12, which are arranged alternately in the Y direction together with the emitter regions 11 such that the emitter region 11 lies between the transistor cells 2a, are deeper than the emitter region 11 and extend directly below the emitter region 11 in such a way that they are separated from each other.

[0158] The transistor cells 2a contain, as a common region, the common drift layer 3, which is the semiconductor substrate, and a buffer layer of n-type 21 and a collector region of the second conductivity type 22 with a high concentration of impurities, which are deposited on the back side of the drift layer 3.

[0159] The floating mesa region 5c is positioned between the diode cell 2b, which will be described below, and the transistor cell 2a. The emitter region 11 is not buried within the floating mesa region 5c, and a p-type floating region 9a, which is not electrically connected to an emitter electrode 20 and is electrically floating, is formed within the floating mesa region 5c.

[0160] The collector region 22, which corresponds to the transistor cell 2a, extends over the other main surface - back side - which is opposite the floating mesa region 5c.

[0161] Diode cell 2b contains an anode region of the second conductivity type 29, which is buried in a surface layer section of the diode mesa region 5b. Diode cell 2b also contains the common drift layer 3, which is the semiconductor substrate, the buffer layer of the first conductivity type 21, which is buried in a surface layer section on the back side of drift layer 3, and a cathode region of the first conductivity type 22b, which has a high concentration of impurities and is buried in the surface layer section on the back side of drift layer 3 such that it faces diode mesa region 5b.

[0162] The anode region 29 is shallower than the trench 4 and is buried in the same step as, for example, the basal region 9. A cathode region 22b is buried at a position that is shallower than the buffer layer 21 in a depth direction from the back side of the drift layer 3, together with the n +The collector region 22 is arranged and is electrically and metallurgically connected to a collector electrode 24, which is deposited on the back side of the drift layer 3. The cathode region 22b has a higher concentration of impurities than the buffer layer 21.

[0163] An intermediate insulating film 15 is arranged such that the entire surface of the trench 4, the transistor mesa region 5a, the diode mesa region 5b and the floating mesa region 5c is covered.

[0164] A contact hole 16a is embedded in the interlayer insulating film 15 such that it extends from the surface of the interlayer insulating film 15 to the transistor mesa region 5a through the interlayer insulating film 15. A contact hole 16b is also embedded in the interlayer insulating film 15 such that it extends from the surface of the interlayer insulating film 15 to the diode mesa region 5b through the interlayer insulating film 15.

[0165] As if through a dotted line in Fig. As shown in Figure 29, the contact hole 16a extends in the Y direction, namely the longer direction in the planar structure of the trench 4 or the transistor mesa region 5a - in the transistor mesa region 5a - and is arranged to correspond to the position where the emitter region 11 and the contact region 12 are formed.

[0166] As if through a dotted line in Fig. As shown in Figure 29, the contact hole 16b extends in the Y-direction, specifically the longer direction, in the planar structure of the trench 4 or the diode mesa region 5b, and is arranged such that it faces the anode region 29. For example, the contact holes 16a and 16b are strip-shaped parallel planar structures with a width of 0.5 micrometers, similar to the contact hole 16 according to the first embodiment.

[0167] As in the Fig. 30 and Fig. As illustrated in Figure 31, a barrier metal film 17 is buried in the contact hole 16a, similar to the contact hole 16 according to the first embodiment. The barrier metal film 17 is selectively deposited on the inner wall of the contact hole 16a and on the surfaces of the emitter region 11 and the contact region 12, which are exposed through the bottom of the contact hole 16a.

[0168] Furthermore, the contact hole 16a is filled with a contact plug 19 through the barrier metal film 17. Similar to the contact hole 16 according to the first embodiment, the barrier metal film 17 is selectively deposited on the inner wall of the contact hole 16b, and the surface of the anode region 29, which is exposed through the bottom of the contact hole 16b, is buried in the contact hole 16b.

[0169] The contact hole 16b is filled with a contact plug 19 through the barrier metal film 17. The barrier metal film 17 is not deposited on the surface of the intermediate insulating film 15 and is selectively buried in each of the contact holes 16a and 16b.

[0170] As in the Fig. 30 and Fig. As illustrated in Figure 31, the emitter electrode 20 is deposited on the trench 4 and the mesa region 5 such that the intermediate insulating film 15 and the contact plug 19 are covered. The emitter electrode 20 is electrically connected to the emitter region 11 and the contact region 12 by the contact plug 19 and the barrier metal film 17, which are buried in the contact hole 16a.

[0171] Furthermore, the emitter electrode 20 is electrically connected to the anode region 29 by the contact plug 19 and the barrier metal film 17, which are buried in the contact hole 16b. A protective film 23 is deposited on the emitter electrode 20 in such a way that the emitter electrode 20 is covered.

[0172] The collector electrode 24 is deposited on the back side of the drift layer 3 in such a way that the back side is covered. The collector electrode 24 is electrically and metallurgically connected to the collector region 22 and the cathode region 22b in such a way that the contact resistance is reduced.

[0173] The n + -Emitter region 11 and the p + -Contact region 12 according to the second embodiment has the same structure as the n + -Emitter region 11 and the p + -Contact region 12 according to the first embodiment. Specifically, as shown in Fig. 5 to see, the p +-Contact regions 12, which lie adjacent to each other, where the n + -Emitter region 11 between the p + The contact regions 12 are arranged deeper than the emitter region 11. The contact regions 12 extend directly below the emitter region 11 in such a way that they are separated from each other.

[0174] The contact region contact width W bc The contact region 12 is smaller than the emitter region contact width W. e the surface of the emitter region 11, which is connected to the emitter electrode 20 by the contact plug 19 and the barrier metal film 17. The effective contact region width W eff The contact-base interface 12p in the Y direction is larger than the emitter injection width W. inj an emitter-base pn transition interface 11n1 in the Y direction.

[0175] As in Fig. Figure 6 shows a width A that is half the emitter injection width W. injthe emitter-base pn transition interface 11n1 in the Y direction is smaller than a creep distance d crp an emitter contact pn junction interface 11n2 along a curve in a cross-sectional view along the Y direction.

[0176] The barrier metal film 17 and the contact plug 19 according to the second embodiment have the same structure as the barrier metal film 17 and the contact plug 19 according to the first embodiment. Specifically, as shown in Fig. Figure 7 shows an upper edge section 17d of the barrier metal film 17 slightly lower than an upper edge section 16d of the contact hole 16, which corresponds to the contact holes 16a and 16b. A surface 19a of the contact plug 19 is a concave surface in which a central section is recessed.

[0177] The semiconductor device 1B according to the second embodiment contains the diode cell 2b on which the diode and the floating mesa region 5c are arranged, in contrast to the semiconductor device 1A according to the first embodiment. Therefore, mainly a perturbation atom incorporation mask structure can be modified to implement the semiconductor device 1B according to the second embodiment using a fabrication process that is essentially the same as that used to fabricate the semiconductor device 1A according to the first embodiment.

[0178] Therefore, in the semiconductor device 1B according to the second embodiment, the same effect can be achieved with the structure mentioned above as in the semiconductor device 1A according to the first embodiment. (Third embodiment) Structure of the semiconductor device according to the third embodiment

[0179] A semiconductor device 1C according to a third embodiment of the present invention has essentially the same structure as the semiconductor device 1A according to the first embodiment of the present invention, with the exception of the structure of a gate insulating film 36, as shown in the Fig. 32, Fig. 33 to Fig. Figure 34 illustrates the semiconductor device 1C according to the third embodiment, which includes the gate insulating film 36 with a thickness that differs from that of the gate insulating film 6 according to the first embodiment.

[0180] As in the Fig. 32, Fig. 33 to Fig. As illustrated in Figure 34, the semiconductor device 1C according to the third embodiment of the present invention comprises a drift layer 3, which is a section of a semiconductor substrate, similar to the semiconductor device 1A according to the first embodiment. Furthermore, the semiconductor device 1C according to the third embodiment comprises a mesa region 5, which is arranged and divided between trenches 4 that lie side by side in the X-direction on the drift layer 3, and a gate electrode 8 that is buried in the trench 4 by the gate insulating film 36.

[0181] The semiconductor device 1C according to the third embodiment further comprises a p-type base region 9, which is buried in a surface layer section of the mesa region 5, and several n + -Emitter regions 11, which are periodically buried in the surface layer section of the basal region 9 along the Y direction.

[0182] Furthermore, the semiconductor device 1C according to the third embodiment contains several p + -Contact regions 12, which are arranged alternately in the Y direction together with the emitter regions 11, such that the emitter region 11, which are arranged between the contact regions 12, are deeper than the emitter region 11 and extend immediately below the emitter region 11 in such a way that they are separated from each other.

[0183] The semiconductor device 1C according to the third embodiment further comprises an intermediate insulating film 15, which is deposited on the drift layer 3 such that the emitter region 11 and the contact region 12 are covered. Contact holes 16 are embedded in the intermediate insulating film 15 such that they face the emitter region 11 and the contact region 12.

[0184] The semiconductor device 1C according to the third embodiment further comprises a barrier metal film 17 which is buried in the contact hole 16 and is selectively deposited on the inner wall of the contact hole 16 and on the surfaces of the emitter region 11 and the contact region 12, which are exposed through the bottom of the contact hole 16.

[0185] The semiconductor device 1C according to the third embodiment further comprises a contact plug 19 which is buried in the contact hole 16 through the barrier metal film 17, and an emitter electrode 20 which is deposited on the intermediate insulating film 15 in such a way that it is connected to the contact plug 19.

[0186] As in the Fig. 32, Fig. 33 to Fig. As can be seen from 34, the gate insulating film 36 contains a first section 36a, which is located in the Fig. 32 and Fig. 33 is shown and is arranged at least between the gate electrode 8 and the base region 9 immediately below the emitter region 11. Furthermore, the gate insulating film 36 contains a second section 36b, which is located in the Fig. 32 and Fig. 34 is shown and is located at least between the gate electrode 8 and the base region 9 immediately below the contact region 12.

[0187] Or, to put it another way: The gate insulating film 36 contains the first section 36a, which is arranged at least on the side walls of the trenches 4, between which the base region 9 is located immediately below the emitter region 11. Furthermore, the gate insulating film 36 contains the second section 36b, which is thicker than the first section 36a and is arranged at least on the side walls of the trenches 4, between which the base region 9 is located immediately below the contact region 12.

[0188] As in the Fig. 33 and Fig. As illustrated in Figure 34, the gate insulating film 36 further comprises a third section 36c, which is thicker than the first section 36a and is located at least at the bottom of the trench 4 – between the drift layer 3 and the gate electrode 8. The first section 36a, the second section 36b, and the third section 36c are continuous and integral.

[0189] As in the Fig. 32 and Fig. As illustrated in Figure 33, the first section 36a is arranged such that it extends from a section between the gate electrode 8 and the base region 9 immediately below the emitter region 11 to a section between the gate electrode 8 and the base region 9 immediately below the contact region 12. A portion of the first section 36a projects from the base region 9 immediately below the contact region 12 in the Y-direction and is connected to the second section 36b.

[0190] As in Fig. As illustrated in Figure 33, the first section 36a is arranged such that it extends from a section between the gate electrode 8 and the base region 9 immediately below the emitter region 11 to a section between the emitter region 11 and the gate electrode 8. Part of the first section 36a projects forward of the emitter region 11 and is terminated by the top of the mesa region 5.

[0191] The first section 36a is arranged such that it extends from a section between the gate electrode 8 and the base region 9 immediately below the emitter region 11 to a section between the bottom of the trench 4 and the gate electrode 8 – between the drift layer 3 and the gate electrode 8. A portion of the first section 36a projects towards the bottom of the trench 4 – towards the drift layer 3 – and is connected to the third section 36c.

[0192] As in Fig. As illustrated in Figure 34, the second section 36b – similar to the first section 36a – is arranged such that it extends from a section between the gate electrode 8 and the base region 9 immediately below the contact region 12 to a section between the contact region 12 and the gate electrode 8. Part of the second section 36b projects beyond the contact region 12 and is terminated by the surface of the mesa region 5.

[0193] Similarly, the second section 36b is arranged such that it extends from a section between the gate electrode 8 and the base region 9 immediately below the contact region 12 to a section between the bottom of the trench 4 and the gate electrode 8 – between the drift layer 3 and the gate electrode 8. A portion of the second section 36b projects towards the bottom of the trench 4 – towards the drift layer 3 – and is connected to the third section 36c.

[0194] The first section 36a, for example, is a thermally oxidized SiO2 film deposited by a thermal oxidation process. The second section 36b and the third section 36c, for example, are SiO2 films deposited by a deposition process such as CVD.

[0195] The first section 36a has a thickness of, for example, approximately 100 nanometers. The second section 36b has a thickness of, for example, approximately 150 nanometers. The third section 36c has a thickness of, for example, approximately 200 nanometers.

[0196] In the semiconductor device 1C according to the third embodiment, a channel charge is induced in the base region 9 immediately below the emitter region 11 by the gate insulating film 36, which is arranged between the gate electrode 8 and the base region 9 immediately below the emitter region 11. Therefore, the first section 36a, which is arranged between the gate electrode 8 and the base region 9 immediately below the emitter region 11, essentially functions as a gate film that induces a channel charge.

[0197] The second section 36b, located between the gate electrode 8 and the base region 9 immediately below the contact region 12, or the third section 36c, formed at the bottom of the trench 4, does not function as the gate film that essentially induces a channel charge. In the semiconductor device 1C according to the third embodiment, the second section 36b and the third section 36c are thicker than the first section 36a.

[0198] Therefore, a reduction in the capacitance between the gate and the emitter and the capacitance between the gate and the collector is possible compared to prior art technology, where the first section 36a, the second section 36b, and the third section 36c are uniformly formed with the same thickness. As a result, a reduction in the switching time and switching losses of the trench IGBT is possible. Furthermore, an increase in the switching speed of the trench IGBT is possible.

[0199] In particular, in the trench IGBT, the width of the mesa region 5 is generally reduced to increase the number of mesa regions 5 and thus improve the current density. This increases the number of trenches 4, which necessarily leads to an increase in the number of second sections 36b and third sections 36c that do not function as the gate film, which essentially induces a channel charge. Therefore, the structure in which the second section 36b and the third section 36c are thicker than the first section 36a, as in the semiconductor device 1C according to the third embodiment, is useful for increasing the switching speed of the IGBT. Method for manufacturing the semiconductor device according to the third embodiment

[0200] Next, a method for manufacturing the semiconductor device 1C according to the third embodiment is described with reference to the Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42, Fig. 43 to Fig. 44. In the process for manufacturing the semiconductor device 1C according to the third embodiment, the steps are essentially the same as those in the process for manufacturing the semiconductor device 1A according to the first embodiment, with the exception of the deposition of the gate insulating film 36. Therefore, the description focuses on the step for deposition of the gate insulating film 36, and a detailed description of the other steps is not repeated.

[0201] (a1) First, an n - Semiconductor substrate 3 SUB produced. Then, as in Fig. Figure 8 illustrates the trenches 4 in the main surface of the semiconductor substrate 3 SUBexcavated, and the mesa region 5, which is arranged and divided between adjacent trenches 4 in the X direction, is buried in the same steps as in the first embodiment.

[0202] (b1) Then, as in Fig. Figure 35 illustrates a deposited film 31, which is a SiO2 film, on the main surface of the semiconductor substrate 3 SUB For example, it is deposited using a CVD process to fill the trenches 4. The deposited film 31 is deposited with a thickness of approximately 1 micrometer, for example, with reference to a trench width of 1 micrometer.

[0203] (c1) Then the deposited film 31 is etched back by dry etching, such as RIE. As in Fig. Figure 36 illustrates that the deposited film 31 is applied to the main surface of the semiconductor substrate 3. SUB, specifically on Trench 4 and Mesa Region 5, selectively removed by etching, and the isolated film 31, which is buried in Trench 4, is dug up.

[0204] (d1) Then, as in the Fig. 37, Fig. 38 to Fig. Figure 39 illustrates a third mask, RM3, deposited as an etching mask on Mesa Region 5 using a photolithography technique. Here is Fig. 37 a plan view illustrating a main section of the layer structure of the etching mask. Fig. Figure 38 is a cross-sectional view showing a main section of a cross-sectional structure along line VIIa-VIIa of Fig. 37 illustrated. Fig. Figure 39 is a cross-sectional view showing a major section of a cross-sectional structure along line VIIb-VIIb of Fig. 37 illustrated.

[0205] The third mask RM3 is buried in a strip-shaped parallel plane structure, in which a first section m3a, which is in the Fig. 37 and Fig. 38 is illustrated, and a second section m3b, which is in the Fig. 37 and Fig. Figure 39 illustrates that they are arranged alternately and repeatedly in the Y direction.

[0206] The width xa of the first section m3a in the X direction is essentially equal to the width 5x of the mesa region 5 in the X direction, and the width xb of the second section m3b in the X direction is greater than the width 5x of the mesa region 5 in the X direction.

[0207] As in Fig. As illustrated in Figure 38, the face surfaces of the first section m3a, which are opposite each other in the X-direction, are flush with the face surfaces of the mesa region 5, which are opposite each other in the X-direction. As shown in Fig. As illustrated in Figure 39, the side faces of the second section m3b, which are opposite each other in the X direction, are arranged outside the side faces of the mesa region 5, which are opposite each other in the X direction.

[0208] A dimensional difference between the position of the side surface of the second section m3b and the position of the side surface of the mesa region 5 corresponds to the thickness of the second section 36b of the gate insulating film 36. The width xa of the first section m3a is, for example, approximately 0.5 micrometers, and the width xb of the second section m3b is, for example, approximately 0.7 micrometers.

[0209] Similar to the first mask RM1 or the second mask RM2 according to the first embodiment, the third mask RM3 is formed by processing a photosensitive resist film which covers the entire main surface of the semiconductor substrate 3 SUB is deposited in a specific structure.

[0210] (e1) Then the deposited film 31, which is buried in the trench 4, is sequentially etched from the surface by highly directional dry etching, such as RIE or ion milling, using the third mask RM3 as the etching mask. As described in the Fig. 40 and Fig. As illustrated in Figure 41, a deposited film 31c, which remains with a thickness of, for example, approximately 200 nanometers, is arranged at the bottom of trench 4 between the third mask RM3 by etching.

[0211] As in Fig. As illustrated in Figure 41, a deposited film 31b, which remains with a thickness of, for example, approximately 150 nanometers, is positioned on the side wall of mesa region 5 immediately below the second section m3b of the third mask RM3. The deposited film 31c is buried in a strip shape along the longer direction—the Y-direction—of trench 4 and mesa region 5. The deposited film 31b extends from the top to the bottom of mesa region 5 and is integrally connected to the deposited film 31c. As shown in Fig. As illustrated in Figure 40, the deposited film 31b is not deposited on the side wall of Mesa Region 5 immediately below the first section m3a of the third mask RM3.

[0212] This means that the deposited film 31c is deposited on the side wall of mesa region 5 in a structure in which the side wall of mesa region 5 is periodically exposed along the longer direction - Y-direction - of mesa region 5.

[0213] (f1) Then, after the third mask RM3 has been removed, a thermal oxidation process is carried out to deposit a thermally oxidized film 32, which is a SiO2 film, with a thickness of, for example, approximately 100 nanometers in a section of the sidewall of mesa region 5 that is not covered by the deposited film 31b and the deposited film 31c, as shown in Fig. 42 illustrated.

[0214] This means that the thermally oxidized film 32, which is thinner than the deposited film 31b and the deposited film 31c, is buried in an exposed section of the sidewall of mesa region 5 between the deposited films 31b that lie side by side in the longer direction – Y-direction – of mesa region 5. During deposition, as in the Fig. 42 and Fig. Figure 43 illustrates that the thermally oxidized film 32 was also deposited on the surface of an upper part of the mesa region 5.

[0215] During deposition, the gate insulating film 36 is formed, which contains the first section 36a, which is the thermally oxidized film 32, the second section 36b, which is the deposited film 31b, and the third section 36c, which is the deposited film 31c.

[0216] Then, as in Fig. 9, the gate material 7 on the main surface of the semiconductor substrate 3 SUBarranged to fill the trench 4, similar to the first embodiment. Then the gate material 7 is back-etched by dry etching, such as RIE, to form the gate electrode 8 in the trench 4, as shown in Fig. 44 illustrated.

[0217] In this arrangement, the thermally oxidized film 32 is deposited on the surface of the upper part of the mesa region 5. Similar to the first embodiment, the gate material 7 is back-etched with an etch rate that exhibits selectivity with respect to the thermally oxidized film 32. Therefore, the thermally oxidized film on the mesa region 5 acts as an etch stopper and can prevent the surface of the upper part of the mesa region 5 from being etched.

[0218] Then the same steps are performed as in the first embodiment, for example to create the base region of p-type 9, the n + -Emitter region 11, the p +-to form contact region 12, the intermediate insulating film 15, the contact hole 16, the barrier metal film 17 and the contact plug 19.

[0219] Furthermore, the same steps as in the first embodiment are carried out to, for example, prepare the emitter electrode 20, the n-type buffer layer 21, the p + -Collector region 22, the protective film 23 and the collector electrode 24.

[0220] Then the lifetime control step in S14 and the hydrogen annealing step in S15 are carried out. This essentially completes a wafer process for the semiconductor device 3C according to the third embodiment of the present invention.

[0221] As described above, according to the method for manufacturing the semiconductor device according to the third embodiment of the present invention, it is possible to deposit the gate insulating film 36 with a non-uniform thickness.

[0222] In the semiconductor device 1C according to the third embodiment, the first section 36a of the gate insulating film 36 is formed such that it extends from a section between the gate electrode 8 and the base region 9 immediately below the emitter region 11 to a section between the gate electrode 8 and the base region 9 immediately below the contact region 12. As in the Fig. 32 and Fig. As illustrated in Figure 33, a part of the first section 36a of the gate insulating film 36 projects to the base region 9 immediately below the contact region 12 and is connected to the second section 36b. However, the present invention is not limited to the structure mentioned above.

[0223] As in Fig. As illustrated in Figure 45, the gate insulating film 36 can be configured such that the second section 36b extends from a section between the gate electrode 8 and the base region 9 immediately below the contact region 12 to a section between the gate electrode 8 and the base region 9 immediately below the emitter region 11. A portion of the gate insulating film 36 may protrude towards the base region 9 immediately below the emitter region 11 and may be connected to the first section 36a.

[0224] In the event that part of the gate insulating film 36 protrudes to the base region 9 immediately below the emitter region 11 and is connected to the first section 36a, the third mask RM3, which is in Fig. As illustrated in Figure 37, the width of the second section m3b in the Y-direction is increased, and the width of the first section 3ma in the Y-direction is decreased. Therefore, increasing the width of the second section 36b of the gate insulating film 36 in the Y-direction is easily possible. Furthermore, reducing the width of the first section 36a in the Y-direction is also possible. (Fourth embodiment)

[0225] A semiconductor device 1D according to a fourth embodiment is characterized in that it contains a resistance-reducing layer 41 which is arranged directly below an emitter region, as shown in Fig. 46 illustrates, and a gate insulating film 46 in which one section corresponding to a region that comes into contact with the resistance-reducing layer 41 is thinner than the other section.

[0226] In the semiconductor device 1D according to the fourth embodiment, the resistance-reducing layer 41 in the upper part of the base region 9 is coated with a higher concentration (p ++ ) as the base region 9 is buried in such a way that it extends between adjacent contact regions 12. Fig. 46 is a cross-sectional view illustrating a main section at a position corresponding to line IIc-IIc of Fig. 1 corresponds to.

[0227] Fig. 47 is a cross-sectional view illustrating a main section at a position corresponding to line IIa-IIa of Fig. 1 corresponds to. As in Fig. As illustrated in Figure 47, in the semiconductor device according to the fourth embodiment, it is preferred that the thickness of one section of the gate insulating film 46, which is positioned at the same level as the resistance reduction layer 41, is smaller than the thickness of the other section of the gate insulating film 46.

[0228] In particular, the thickness of a region of the gate insulating film 46 that is positioned at the same height as the resistance reduction layer 41 is smaller than the thickness of a region of the gate insulating film 46 that comes into contact with the emitter region 11 on the resistance reduction layer 41, the base region 9 below the resistance reduction layer 41 and the drift layer 3 below the base region 9.

[0229] A concave section is recessed into the resistance-reducing layer 41, which is buried in an interface with a gate electrode 48, in order to reduce the thickness of a region of the gate insulating film 46, which is positioned at the same level as the resistance-reducing layer 41, as shown in Fig. Figure 48 illustrates the thickness t of the thinned region is adjusted such that the potential of the surface of the drag-reducing layer 41 on the sidewall side of the trench 4 varies when a gate stress is applied and a desired inversion layer is deposited.

[0230] In the semiconductor device 1D according to the fourth embodiment, the structures, apart from the resistance reduction layer 41 and the gate insulating film 46, correspond to the elements, layers or regions designated by the same or similar reference numerals in the semiconductor devices according to the first to third embodiments, so that the description of the fourth embodiment is not repeated.

[0231] In the semiconductor device 1D according to the fourth embodiment, the resistance-reducing layer 41 is located in a state of high concentration below the emitter region 11, so that the resistance of a region below the emitter region 11 is reduced and current flows only with difficulty through a pn junction. Thus, if hole current flows during a shutdown operation, a rise in the potential in the region of the resistance-reducing layer 41 is prevented, and latch-up occurs only with difficulty in the semiconductor device 1D according to the fourth embodiment.

[0232] The emitter region contact width W e can be enlarged to increase the channel integration density and thus reduce the one-state stress.

[0233] In the semiconductor device 1D according to the fourth embodiment, the thickness of a section of the gate insulating film 46 that comes into contact with the resistance reduction layer 41 is small.

[0234] If the thickness of the gate insulating film 46 is uniform on the side wall of the trench 4, an inversion layer is less likely to be deposited on the surface of the resistance-reducing layer 41 below the emitter region 11, and the gate threshold voltage increases. Therefore, the semiconductor device is less likely to be switched on.

[0235] Therefore, the thickness of a section of the gate insulating film 46 that comes into contact with the resistance-reducing layer 41 is smaller than the thickness of an end section of the gate insulating film 46. Therefore, it is easy to control the surface potential of the resistance-reducing layer 41 and avoid an increase in the gate threshold voltage. Therefore, a combination of forming the resistance-reducing layer 41 and controlling the thickness of the gate insulating film 46 makes it possible to form the semiconductor device according to the fourth embodiment, in which latch-up is less likely and an increase in the gate threshold voltage is prevented.

[0236] A method is known in which a section of the gate insulating film between emitter region 11 and base region 9 is not thin, but rather a section of the gate insulating film positioned below emitter region 11, further below base region 9, and in contact with the upper part of drift layer 3, is thinner than the other section. This thinning method is disclosed, for example, in JP H6-13621 A.

[0237] The thinning process has the advantage that, when a reverse bias is applied to the gate electrode, the conductivity type of a section of drift layer 3 near the gate is reversed to obtain a high breakdown voltage. However, if the concentration of base region 9 is low and the resistance increases, current is likely to flow through the pn junction, resulting in latch-up. Consequently, the semiconductor device is likely to become unusable.

[0238] In the semiconductor device according to the fourth embodiment, a section of the gate insulating film 46 that comes into contact with the upper part of the drift layer 3 is not thinned, but rather a section of the gate insulating film 46 between the emitter region 11 and the base region 9 is thinner than the other section. Therefore, latch-up is less likely. The other effects of the semiconductor device 1D according to the fourth embodiment are the same as those of the semiconductor device according to the first embodiment. Method for manufacturing the semiconductor device according to the fourth embodiment

[0239] Next, a method for manufacturing the semiconductor device 1D according to the fourth embodiment is described with reference to the Fig. 49, Fig. 50, Fig. 51, Fig. 52, Fig. 53, Fig. 54, Fig. 55, Fig. 56, Fig. 57, Fig. 58 to Fig. 59 described. Fig. 49, Fig. 50, Fig. 51, Fig. 52, Fig. 53, Fig. 54, Fig. 55, Fig. 56, Fig. 57, Fig. 58 to Fig. 59 are cross-sectional views illustrating a main section at a position corresponding to line IIa-IIa of Fig. 1 corresponds to.

[0240] In the process for manufacturing the semiconductor device 1D according to the fourth embodiment, the steps, with the exception of the steps for forming the resistance-reducing layer 41, the gate insulating film 46, and the gate electrode 48, are essentially the same as those in the process for manufacturing the semiconductor device 1A according to the first embodiment. Therefore, the description focuses on the steps for forming the resistance-reducing layer 41, the gate insulating film 46, and the gate electrode 48, and a detailed description of the other steps is not repeated.

[0241] (a2) First, an n - Semiconductor substrate 3 SUB produced. Then, as in Fig. 49 illustrates an insulating film 45 on the top side of the semiconductor substrate 3 SUB for example, deposited by a thermal oxidation process. The insulating film 45 also acts as an etch stopper that withstands several insulating film deposition processes, which will be described below. The insulating film 45, which is in Fig. As illustrated in Figure 49, it is deposited in such a way that it is considerably thicker than a gate insulating film, which is described below.

[0242] (b2) Then, as in Fig. Figure 50 illustrates the same steps as those carried out in the first embodiment to create the trench 4 in the main surface of the semiconductor substrate 3. SUB- using the insulating film 45 as an etching mask - to dig and form the mesa region 5, which is arranged and divided between the trenches 4 side by side in the X direction.

[0243] (c2) Then, as in Fig. Figure 51 illustrates a first gate insulating film 46a, which is a SiO2 film, with a constant thickness deposited in the trench 4, for example, by a thermal oxidation process. The thickness of a sidewall section of the insulating film 45 on the semiconductor substrate 3 SUB is increased by thermal oxidation.

[0244] In Fig. 51 is the thickness of a thermally oxidized film newly generated on the sidewall section of the insulating film 45, equal to the thickness of the thermally oxidized film generated on the sidewall of the trench 4. However, the expression in Fig. Figure 51 is shown schematically. In practice, the thickness of the thermally oxidized film grown on the side wall section of the insulating film 45 is less than the thickness of the thermally oxidized film grown on the side wall of the trench 4.

[0245] (d2) Then a doped polysilicon film with low resistivity is deposited as a first gate electrode 48a on the first gate insulating film 46a to fill the trench 4.

[0246] Then, as in Fig. Figure 52 illustrates that the doped polysilicon film is back-etched, for example, by RIE, and the amount of back-etched doped polysilicon film is adjusted such that the top side of the doped polysilicon film is positioned corresponding to the bottom side of the resistance-reducing layer 41, which is intended to be buried in the following step. The doped polysilicon film remaining after back-etching becomes the first gate electrode 48a.

[0247] (e2) Then, as in Fig. Figure 53 illustrates a section of the first gate insulating film 46a, exposed from the doped polysilicon film, selectively removed by complete etching using a difference between the etching rates of the oxide film and the doped polysilicon film.

[0248] (f2) Then, as in Fig. Figure 54 illustrates, for example, a second gate insulating film 46b, which is a SiO2 film, with a constant thickness deposited in the trench 4 by a thermal oxidation process. The second gate insulating film 46b is deposited on the top and side surfaces of the insulating film 45, on the inner wall surface of the upper part of the trench 4, on the upper end surface of the first gate insulating film 46a, and on the top surface of the first gate electrode 48a. The second gate insulating film 46b, which is in Fig. 54 illustrates that it is thinner than the first gate insulating film 46a.

[0249] (g2) Then, as in Fig. Figure 55 illustrates that in the second gate insulating film 46b, which is deposited in the trench 4, only a section deposited on the top side of the first gate electrode 48a is selectively removed. The removal process is carried out by dry etching with high directivity, such as RIE.

[0250] This means that directional etching is performed such that the top surface of the first gate electrode 48a is exposed and the lower edge of the second gate insulating film 46b is continuous with the upper edge of the first gate insulating film 46a. Because directional etching is performed, the set thickness t of the second gate insulating film 46b can be maintained after etching. The thickness of the second gate insulating film 46b at which an inversion layer is likely to be deposited in the resistance-reducing layer 41 under high concentration conditions can be maintained.

[0251] (h2) Then, a gate material intended to function as the second gate electrode 48b is deposited, for example by a CVD process, onto the first gate electrode 48a, the top of which is exposed, and the first gate insulating film 46a, the top of which is exposed, to fill the trench 4. In addition to doped polysilicon, for example a high-melting-point metal such as tungsten (W), molybdenum (Mo) or titanium (Ti) can be used as the gate material.

[0252] Then, an upper part of the gate material is etched back to form the second gate electrode 48b. As in Fig. As illustrated in Figure 56, the thickness of the second gate electrode 48b is controlled to a specific value. That is, the thickness of the second gate electrode 48b is adjusted by back-etching such that the top surface of the second gate electrode 48b is aligned with the top surface of the resistance-reducing layer 41, which is intended to be deposited in the following step.

[0253] (i2) Then, as in Fig. Figure 57 illustrates a third gate insulating film 46c, which is, for example, a SiO2 film or a silicon nitride film (Si3N4 film), with a constant thickness, deposited by a CVD process in a section of the trench 4 that is exposed towards the etched space. The third gate insulating film 46c is deposited on the surface of the second gate insulating film 46b and the top surface of the second gate electrode 48b.

[0254] As in Fig. As illustrated in Figure 57, the sum of the thickness of the third gate insulating film 46c and the thickness t of the second gate insulating film 46b may be essentially equal to the thickness of the first gate insulating film 46a or may be greater than the thickness of the first gate insulating film 46a.

[0255] (j2) Then, as in Fig. Figure 58 illustrates that in the third gate insulating film 46c deposited in the trench 4, a section deposited on the top of the second gate electrode 48b is selectively removed by dry etching with high directivity, such as RIE, in such a way as to expose the top of the second gate electrode 48b.

[0256] The third gate insulating film 46c, which remains after selective etching, the first gate insulating film 46a and the second gate insulating film 46b form the gate insulating film 46, which is in Fig. 47 is illustrated.

[0257] (k2) Then, a gate material intended to function as a third gate electrode 48c is deposited onto the second gate electrode 48b, the top of which is exposed, for example by a CVD process, such that it is continuous with the second gate electrode 48b, and a space above the trench 4 is filled by the deposition. For example, doped polysilicon, high-melting-point metal, or metal silicide or polycide with a high melting point can be used as the gate material.

[0258] The top surface of the gate material is etched back to the level that was in Fig. Figure 59 illustrates how to form the third gate electrode 48c. The third gate electrode 48c, which remains after back-etching, the first gate electrode 48a, and the second gate electrode 48b form the gate electrode 48, which is shown in Fig. 47 is illustrated.

[0259] Then - similar to the process in the Fig. 12, Fig. 13 to Fig. The process described in section 14 involves the selective implantation of p-type perturbation ions in the Y-direction such that contact region 12 is formed, although the illustration of the ion implantation is omitted from the drawing. Then, further p-type perturbation ions are selectively implanted between the regions into which several initial perturbation ions have been implanted, such that the resistance-reducing layer 41 is deposited.

[0260] Then, second n-type perturbation ions are selectively implanted such that emitter region 11 is formed. Once the ions are implanted, the diffusion coefficient and projection distances of the first and second perturbation ions are selected to deposit the resistance-reducing layer 41 below emitter region 11.

[0261] Then the same steps are taken as described in the Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26 to Fig. 27 are carried out. In the same steps as those described in the Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26 to Fig. As described in 27, an activation process is carried out such that the activated resistance reduction layer 41 is positioned at the same level as the second gate electrode 48b and the second gate insulating film 46b.

[0262] The semiconductor device 1D according to the fourth embodiment, which is described in the Fig. 46, Fig. 47 to Fig. As illustrated in Figure 48, it can be produced using the steps mentioned above. (First modification example of the fourth embodiment)

[0263] In the semiconductor device according to the fourth embodiment, only a section of the gate insulating film 46 that comes into contact with the resistance-reducing layer 41 is selectively thinned, which makes it easy to deposit an inversion layer. However, as in a semiconductor device 1E according to a first modification example of the fourth embodiment, which is described in Fig. Figure 60 illustrates that the thickness of a region of a gate insulating film 56 that comes into contact with the emitter region 11 may be small, as long as an inversion layer can be easily deposited in the resistivity reduction layer 41.

[0264] Fig. 60 is a cross-sectional view illustrating a main section at a position corresponding to line IIa-IIa of Fig. 1 corresponds to. Fig. Figure 60 illustrates a condition in which a region of the gate insulating film 56, which comes into contact with the resistance reduction layer 41 and the emitter region 11, is thinner than another section of the gate insulating film 56, which comes into contact with the base region 9 and extends with a constant thickness in the vertical direction.

[0265] Therefore, in a structure where not only the thickness of a region in contact with the resistance reduction layer 41 in the gate insulating film 56 is small, but also the thickness of a region in contact with the resistance reduction layer 41 and the emitter region 11, the production of the gate insulating film 56 and a gate electrode 58 is simplified.

[0266] In particular, the deposition of the third gate insulating film 46c, which is in Fig. 57 is illustrated, but this is not necessary. Furthermore, the fabrication of the third gate electrode 48c, which is shown in Fig. As illustrated in Figure 59, the fabrication of the second gate electrode 48b and the third gate electrode 48c is not carried out separately, and the second gate electrode 48b can be formed integrally in a single fabrication step. Therefore, it is possible to simplify the method for fabricating the semiconductor device according to the fourth embodiment and thus improve productivity. (Second modification example of the fourth embodiment)

[0267] In the semiconductor device according to the fourth embodiment, the gate electrode 48 is provided with a depth such that the uppermost surface of the gate electrode 48 is flush with the top surface of the emitter region 11. However, the gate electrode 48 can also be arranged in a position that is lower than that shown in Fig. 47, such that the top surface of the gate electrode is flush with the top surface of the resistance reduction layer 41.

[0268] In a method for manufacturing the semiconductor device according to the second modification example of the fourth embodiment, for example, the third gate insulating film 46c, which is in Fig. Figure 57 illustrates that the material is deposited with a sufficient thickness to fill the trench 4. Then, a contact hole – a through-hole – is buried in the third gate insulating film 46c so that it extends to the second gate electrode 48b. Therefore, the second gate electrode 48b acts as the top layer of the gate electrode.

[0269] Then the contact hole – the through-hole – is filled with a through-hole plug. This allows for an electrical connection of the second gate electrode 48b to a surface wire. The other steps are the same as those in the method for manufacturing the semiconductor device 1D according to the fourth embodiment of the present invention.

[0270] Therefore, according to the second modification example of the fourth embodiment, in which the top of the gate electrode is lower than the bottom of the emitter region 11, a reduction of the parasitic capacitance between the emitter and the gate is possible, and the deposition of an inversion layer in the resistance reduction layer 41 is possible in a simple way. (Third modification example of the fourth embodiment)

[0271] In the description of the method for manufacturing the semiconductor device 1D according to the fourth embodiment, after the trench 4 has been dug, the surface structure, such as the emitter region 11 or the resistance reduction layer 41, which is located in Fig. 60 are illustrated. However, the present invention is not limited to the semiconductor device 1D according to the fourth embodiment. For example, the sequence of steps can be modified such that, after the surface structure, such as the emitter region 11 or the resistance reduction layer 41, has been deposited, the trench 4, which is in Fig. Figure 50 illustrates the process of digging. This change improves flexibility in selecting a gate electrode metal.

[0272] The present invention has been described in detail above on the basis of the first to fourth embodiments. LEGEND OF THE LETTERS OR REFERENCE NUMBERS 1A, 1B, 1C Semiconductor Device 2, 2a TRANSISTOR CELL 2b DIODE CELL 3 n - -DRIFT LAYER 3 SUB SEMI-CONDUCTOR SUBSTRATE 4 DITCHES 5 MESA REGION 5a TRANSISTOR-MESA REGION 5b Diode Mesa Region 5c Floating Mesa Region 6 GATE INSULATION FILM 7 GATE MATERIAL - POLYSILICON FILM - 8 GATE ELECTRODE 9 BASE REGION OF THE p-TYPE 9a FLOATEND REGION 11 n + -EMMITTERREGION 11n1 EMMITTER-BASE-pn-TRANSFER INTERFACITION 11n2 EMMITTER-CONTACT-pn-TRANSFER LIMIT 12 p + -CONTACT REGION 12p CONTACT-BASE-INTERFACE 15 Intermediate layer insulating film 16, 16a, 16b CONTACT HOLE 17 PENMERAL FILM 18 STOPPER MATERIAL 19 CONTACT PLUGS 20 EMMITTER ELECTRODE 21 buffer layer of type n 22 p + -COLLECTOR REGION 23 PROTECTIVE FILM 24 COLLECTOR ELECTRODE 41 Resistance Reduction Layer 45 insulating film 46 GATE INSULATION FILM 46a FIRST GATE INSULATION FILM 46b SECOND GATE INSULATION FILM 46c THIRD GATE INSULATION FILM 48 GATE ELECTRODE 48a FIRST GATE ELECTRODE 48b SECOND GATE ELECTRODE 48c THIRD GATE ELECTRODE 56 GATE INSULATION FILM 58 GATE ELECTRODE d bc DEPTH OF THE CONTACT REGION d e DEPTH OF EMITE REGION W bc CONTACT REGION CONTACT WIDTH W e EMPIENT REGIONAL CONTACT BREATH W eff EFFECTIVE CONTACT AREA WIDTH W inj EMITE INJECTION WIDTH

Claims

[1] Semiconductor device (1A, 1B, 1C) comprising the following: a drift layer (3) of a first conductivity type; a mesa region (5) located between adjacent trenches on the drift layer (3); a gate electrode (8) which is buried in each trench by a gate insulating film; a base region (9) of a second conductivity type, which is buried in the mesa region (5); several emitter regions (11) of the first conductivity type, which are periodically buried in a surface layer section of the basal region (9) along a longer direction of the trench; and Contact regions (12) of the second conductivity type, which are alternately buried in the longer direction together with the emitter regions (11) such that each emitter region (11) is arranged between the contact regions, lie deeper than the emitter region and extend immediately below the emitter region in such a way that they are separated from each other, wherein a contact region contact width (W) e ) in the longer direction defined in a surface of the contact region (12) is less than an emitter region contact width (W) bc ) in the longer direction defined in a surface of the emitter region, where an effective contact region width (W eff ) of an interface between the contact region (12) and the base region (9) in the longer direction is larger than an emitter injection width (W) inj) a pn transition interface between the emitter region and the base region (9) in the longer direction, where a length (A) is half the emitter injection width (W) inj ) is smaller than a creep distance (d crp ) of a pn transition interface (11n2) along a curve in a cross-sectional view along the longer direction between the emitter region (11) and the contact region (12). [2] Semiconductor device (1A, 1B, 1C) according to claim 1, wherein the depth of the contact region, starting from the depth of the emitter region, is at least 0.5 micrometers and at most two micrometers. [3] Semiconductor device (1A, 1B, 1C) according to claim 1, wherein the emitter region and the contact region are arranged such that they connect the adjacent trenches. [4] Semiconductor device (1A, 1B, 1C) according to claim 1, wherein the emitter region has a higher concentration of interfering atoms than the contact region. [5] Semiconductor device (1A, 1B, 1C) according to claim 1, further comprising: an intermediate insulating film (15) designed to cover the emitter region and the contact region; a barrier metal film (17) deposited on an inner wall of a contact hole passing through the interlayer insulating film (15) and on a surface of each of the emitter region and the contact region that are exposed through a bottom of the contact hole; a contact plug (19) which is buried in the contact hole through the barrier metal film; and an emitter electrode (20) which is deposited on the interlayer insulating film in such a way that it is connected to the contact plug. [6] Semiconductor device (1A, 1B, 1C) according to claim 5, wherein the contact hole extends in a strip shape along the longer direction. [7] Semiconductor device (1A, 1B, 1C) according to claim 5, wherein an upper edge section of the barrier metal film (17) is slightly lower than an upper edge section of the contact hole. [8] Semiconductor device (1A, 1B, 1C) according to claim 5, wherein a surface of the contact plug (19) has a concave shape. [9] Semiconductor device (1A, 1B, 1C) according to claim 5, wherein the barrier metal film (17) is a composite film comprising a titanium film and a titanium nitride film, and the contact plug (19) is a tungsten film. [10] Semiconductor device (1A, 1B, 1C) according to any one of claims 5 to 9, further comprising: a diode mesa region (5) located between the adjacent trenches on the drift layer (3); an anode region of the second conductivity type, which is buried in a surface layer section of the diode mesa region (5); and a cathode region of the first conductivity type, which is deposited on a back side opposite a surface layer section of the drift layer (3) such that it is opposite the diode mesa region (5). [11] Semiconductor device (1A, 1B, 1C) according to claim 1, wherein the gate insulating film comprises a first section which is formed at least on side walls of the trenches at positions where the base region (9) is arranged immediately below the emitter region between the side walls of the trenches, and a second section which is thicker than the first section and which is formed at least on side walls of the trenches at positions where the base region (9) is arranged immediately below the contact region between the side walls of the trenches. [12] Semiconductor device (1A, 1B, 1C) according to claim 11, wherein the first section is arranged such that it extends from a section between the gate electrode (8) and the base region (9) immediately below the emitter region to a section between the gate electrode (8) and the base region (9) immediately below the contact region. [13] Semiconductor device (1A, 1B, 1C) according to claim 11, wherein the second section is arranged such that it extends from a section between the gate electrode (8) and the base region (9) immediately below the contact region to a section between the gate electrode (8) and the base region (9) immediately below the emitter region. [14] Semiconductor device (1A, 1B, 1C) according to claim 12 or 13, wherein the first section is arranged such that it extends from the section between the gate electrode (8) and the base region (9) immediately below the emitter region to a section between the emitter region and the gate electrode (8). [15] Semiconductor device (1A, 1B, 1C) according to claim 12 or 13, wherein the second section is arranged such that it extends from the section between the gate electrode (8) and the base region (9) immediately below the contact region to a section between the contact region and the gate electrode (8). [16] Semiconductor device (1A, 1B, 1C) according to claim 11, wherein the gate insulating film further comprises a third section formed at the bottom of the trench and having a greater thickness than the first section. [17] Semiconductor device (1A, 1B, 1C) according to claim 16, wherein the first section is a thermally oxidized film and the second and third sections are deposited films. [18] Semiconductor device (1A, 1B, 1C) according to claim 1, further comprising: a resistance-reducing layer of the second conductivity type, which is formed directly below the emitter region and has a higher concentration than the contact region. [19] Semiconductor device (1A, 1B, 1C) according to claim 18, wherein in the gate insulating film a section which comes into contact with the resistance reduction layer is thinner than the other section. [20] Method for manufacturing a semiconductor device (1A, 1B, 1C) comprising the following: Forming trenches in a main area of ​​a semiconductor substrate and forming a mesa region (5) located between the trenches; Formation of a base region (9) of a second conductivity type in a surface layer section of a semiconductor substrate of a first conductivity type; targeted implantation of first disturbance ions of the second conductivity type into several regions that are periodically buried in a surface layer section of the basal region (9), along a longer direction of the trench; Targeted implantation of second perturbation ions of the first conductivity type into the surface layer section of the basal region (9) between the multiple regions in which the first perturbation ions are implanted along the longer direction, in a pattern arranged at a larger interval than an arrangement pattern of the multiple regions and with the same center-to-center spacing as the multiple regions, and with a lower acceleration energy than the first perturbation ions; and Activating the first and second interference ions in such a way that a contact region of the second conductivity type is formed in the region where the first interference ions are implanted and an emitter region of the first conductivity type is formed in the region where the second interference ions are implanted. wherein during activation a heat treatment is carried out such that a contact region contact width in the longer direction, which is defined in a surface of the contact region, is smaller than an emitter region contact width in the longer direction, which is defined in a surface of the emitter region, wherein during activation one or the heat treatment is carried out such that an effective contact region width of an interface between the contact region and the base region (9) in the longer direction is greater than an emitter injection width of a pn transition interface between the emitter region and the base region (9) in the longer direction, where a length (A) is half the emitter injection width (W) inj ) is smaller than a creep distance (d crp ) a pn transition interface (11n2) between the emitter region (11) and the contact region (12), wherein the pn transition interface (11n2) is along a curve in a cross-sectional view along the longer direction. [21] Method for manufacturing a semiconductor device (1A, 1B, 1C) according to claim 20, wherein during activation a heat treatment is carried out such that the contact region is deeper than the emitter region and extends directly below the emitter region. [22] Method for manufacturing a semiconductor device (1A, 1B, 1C) according to claim 20, wherein the second interference ions are implanted with a higher dose than the first interference ions. [23] Method for manufacturing a semiconductor device (1A, 1B, 1C) according to claim 20, comprising the following: Formation of an intermediate insulating film on the main surface of the semiconductor substrate containing the mesa region (5); Forming a contact hole such that it passes through the interlayer insulating film; Formation of a barrier metal film on the intermediate insulating film, including the interior of the contact hole; Forming a plug material on the barrier metal film in such a way that the contact hole is filled with the plug material; selective removal of the plug material and the barrier metal film on the intermediate insulating film such that the contact hole is filled with a contact plug made of the plug material; Emitting charged particles towards the main surface of the semiconductor substrate from a top surface of the main surface of the semiconductor substrate to control the lifetime; and Implementing hydrogen annealing for the semiconductor substrate. [24] Method for manufacturing a semiconductor device (1A, 1B, 1C) according to any one of claims 20 to 23, comprising the following: Formation of a deposited film on a side wall of the mesa region (5) in a structure in which the side wall of the mesa region (5) is periodically exposed along the longer direction of the mesa region (5); and Implementing a thermal oxidation process for the semiconductor substrate and forming a thermally oxidized film with a smaller thickness than the deposited film in the exposed section of the sidewall between the deposited films side by side in the longer direction of the mesa region (5), and forming a gate insulating film comprising the deposited film and the thermally oxidized film.

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