Display substrate and display device

Abstract

A display substrate, comprising: a substrate (01) with a display area (AA) and a peripheral area (BB) located on at least one side of the display area (AA); several subpixels (02) located in the display area (AA); multiple data lines (03) located in the display area (AA) and electrically connected to the multiple subpixels (02), wherein the multiple data lines (03) are configured to provide data signals for the multiple subpixels (02); multiple power lines (04) located in the display area (AA) and electrically connected to the multiple subpixels (02), wherein the multiple power lines (04) are configured to provide power signals for the multiple subpixels (02); several data signal input lines (07) located in the peripheral area (BB); several selector switches (06) located in the peripheral area (BB) and between the multiple data lines (03) and the multiple data signal input lines (07), wherein at least one of the multiple selector switches (06) is electrically connected to at least two of the multiple data lines (03) and one of the multiple data signal input lines (07); a first current bus (08) located in the peripheral area (BB) and on a side of the multiple selector switches (06) facing away from the display area (AA); and several power connection cables (09) located in the peripheral area (BB) and between the first power bus (08) and the several power lines (04); wherein the multiple power connection cables (09) are electrically connected to the first power bus (08) and the multiple power lines (04), wherein the display substrate is characterized by that the first current bus (08) contains several openings (KB) formed at intervals; and that orthographic projections of the openings (KB) on the substrate (01) partially overlap with the orthographic projections of the data signal input lines (07) on the substrate (01).

Description

Technical field

[0001] The present disclosure relates to the field of display, in particular to a display substrate and a display device. background

[0002] With the advancement of intelligent display technology, organic light-emitting diode (OLED) displays are becoming a hotspot in current display research. An increasing number of active matrix organic light-emitting diode (AMOLED) display substrates are entering the market. Compared to a conventional thin-film transistor liquid crystal display (TFT-LCD), the AMOLED display offers a faster response time and a higher contrast ratio. CN 1 10 190 103 A discloses a generic display panel comprising a display area and a stepped area outside the display area. The display panel includes multiple power supply lines arranged within the display area, extending in a first direction and extending in a second direction.On the substrate and in the stage area, a functional component area comprising several functional components and a power supply signal line area comprising a first power supply line pattern extending in the first direction are arranged. The functional component area includes a gating circuit area comprising several gating circuit units. The gating circuit unit comprises a third transistor and a fourth transistor. The drain of the third transistor is connected to one data line. The drain of the fourth transistor is connected to another data line. The source is simultaneously connected to a driver chip.

[0003] US 2015 / 0 243 722 A1 discloses an organic light-emitting diode device comprising a substrate, a display section, a gate-in-panel (GIP) circuit section, a chip-on-film (COF), and a printed circuit board. A display section is formed on the substrate, which displays an image. The display section comprises organic light-emitting elements as well as various thin-film transistors and capacitors for driving the organic light-emitting elements. US 2021 / 0 181 888 A1 discloses a touch display panel comprising a display area and a peripheral area. The display area is used to display one or more images and may include structures such as pixel units. To implement touch functionality, the display area may include multiple first touch electrodes and multiple second touch electrodes. The peripheral area surrounds the display area. The peripheral area may be used for wiring / conducting. Summary

[0004] A display substrate provided in embodiments of the present invention comprises: a substrate with a display area and a peripheral area located on at least one side of the display area; several subpixels located in the display area; multiple data lines located in the display area and electrically connected to the multiple subpixels, the multiple data lines being configured to provide data signals for the multiple subpixels; multiple power lines located in the display area and electrically connected to the multiple subpixels, the multiple power lines being configured to provide power signals to the multiple subpixels; several data signal input lines located in the peripheral area; several selector switches located in the peripheral area and between the multiple data lines and the multiple data signal input lines, wherein at least one of the multiple selector switches is electrically connected to at least two of the multiple data lines and one of the multiple data signal input lines; a first current bus located in the peripheral area and on a side of the multiple selector switches facing away from the display area; and Several power connection cables located in the periphery and between the first power bus and the multiple power lines; wherein the multiple power connection cables are electrically connected to the first power bus and the multiple power lines, the first power bus containing multiple openings formed at intervals; and orthographic projections of the openings on the substrate partially overlap with the orthographic projections of the data signal input lines on the substrate.

[0005] Optionally, in embodiments of the present invention, an orthographic projection of at least one of the several power connection cables on the substrate overlaps at least partially with an orthographic projection of at least one of the several selector switches on the substrate.

[0006] Optionally, in embodiments of the present invention, the multiple power connection cables correspond one-to-one with the multiple selector switches; and an orthographic projection of each of the power connection cables on the substrate overlaps at least partially with an orthographic projection of a corresponding selector switch on the substrate.

[0007] Optionally, in embodiments of the present invention, the at least one of the several selector switches comprises at least two thin-film transistors; the at least two thin-film transistors comprise gates and at least one source and at least two drains located on a side of the gates that differs from the substrate; and An orthographic projection of each of the power connecting cables on the substrate overlaps at least partially with an orthographic projection of one of the source and drain of the correspondingly arranged selector switch on the substrate.

[0008] Optionally, in embodiments of the present invention, the orthographic projection of the power connection cable on the substrate does not overlap with orthographic projections of the gates on the substrate.

[0009] Optionally, in embodiments of the present invention, each selector switch comprises two thin-film transistors; wherein the gates comprise a first gate and a second gate, wherein the at least one source comprises a first source and the at least two drains comprise a first drain and a second drain the two thin-film transistors as a whole comprise: a first active layer located on the substrate; the first gate and the second gate, which are located on a side of the first active layer facing away from the substrate, wherein the first gate and the second gate are located on the same layer but do not overlap; the first source, the first drain and the second drain, which are located on a side of the first gate and the second gate facing away from the substrate, wherein the first source, the first drain and the second drain are on the same layer but do not overlap; and the first source is located between the first drain and the second drain; the first source is electrically connected to one of the several data signal input lines; the first drain and the second drain are electrically connected to two of the several data lines; The orthographic projection of the power cable onto the substrate covers an orthographic projection of the first source onto the substrate; and The orthographic projection of the power cable on the substrate does not overlap with orthographic projections of the first gate and the second gate on the substrate. The first gate, the first active layer, the first source and the first drain form one of the two thin-film transistors, while the second gate, the first active layer, the first source and the second drain form the other of the two thin-film transistors, with the two thin-film transistors sharing the first source.

[0010] Optionally, in embodiments of the present invention, the power connection cable has a first width in a direction perpendicular to the data lines, the first source has a second width in the direction perpendicular to the data lines, and the first width is approximately equal to the second width.

[0011] Optionally, in embodiments of the present invention, orthographic projections of the multiple power connection cables on the substrate are located within orthographic projections of gaps between the multiple selector switches on the substrate.

[0012] Optionally, in embodiments of the present invention, the power connection cable has a third width in a direction perpendicular to the data lines, the gap has a fourth width in the direction perpendicular to the data lines, and the third width is smaller than the fourth width.

[0013] Optionally, in embodiments of the present invention, the display substrate further comprises: a second current bus located between the multiple selector switches and the multiple current lines; the second current bus being electrically connected to the multiple current lines; and the multiple power connection cables are electrically connected to the first power bus and the second power bus.

[0014] Optionally, in embodiments of the present invention, the display substrate further comprises: a third current bus located in the peripheral area; An orthographic projection of the third current bus on the substrate overlaps at least partially with an orthographic projection of the first current bus on the substrate, and the third current bus is electrically connected to the first current bus.

[0015] Optionally, in embodiments of the present invention, at least one of the several subpixels comprises a driver thin-film transistor, a terminal electrode and a storage capacitor; The driver thin-film transistor includes a driver active layer located on the substrate, a driver gate located on a side of the driver active layer facing away from the substrate, a gate insulator layer located on a side of the driver gate facing away from the substrate, an interlayer dielectric layer located on a side of the gate insulator layer facing away from the substrate, and a driver source and a driver drain located on a side of the interlayer dielectric layer facing away from the substrate; The connection electrode is located on the side of the driver source and driver drain facing away from the substrate; The storage capacitor contains a first capacitor electrode and a second capacitor electrode; the first capacitor electrode and the driver gate are located on the same layer; the second capacitor electrode is located between the gate insulating layer and the interlayer dielectric layer; and At least one type of power connection cable, first power bus and data line are located on the same layer as the connection electrode.

[0016] Optionally, in embodiments of the present invention, at least one type of current line, a second current bus, and a third current bus are located on the same layer as the driver source and the driver drain; and A data signal input line and the second capacitor electrode are located on the same layer.

[0017] Optionally, in embodiments of the present invention, the driver active layer and the first active layer are located on the same layer; The first gate, the second gate, and the driver gate are located on the same layer; and The first source, the first drain, and the second drain are located on the same layer as the driver source and the driver drain.

[0018] Optionally, in embodiments of the present invention, an orthographic projection of the first current bus on the substrate overlaps at least partially with orthographic projections of the data signal input lines on the substrate.

[0019] Optionally, in embodiments of the present invention, the multiple openings are subdivided into multiple opening groups arranged along a second direction; each opening group contains multiple openings arranged along a first direction, and the first direction intersects the second direction; and The openings in at least two adjacent groups of openings are arranged in a staggered pattern.

[0020] Optionally, in embodiments of the present invention, the multiple data signal input lines include first data signal input lines and second data signal input lines; the first data signal input lines and the second data signal input lines are arranged alternately along a first direction; The first data signal input lines and driver gates are located on the same layer; and The second data signal input lines and the second capacitor electrodes are located on the same layer.

[0021] Optionally, in embodiments of the present invention, at least one of the several subpixels further comprises: a light-emitting diode located on a side of the terminal electrode facing away from the substrate; and the driver drain, the terminal electrode and the light-emitting diode are electrically connected sequentially.

[0022] A display device provided in embodiments of the present invention, including the display substrate mentioned above. Brief description of the drawings Fig. Figure 1a is a schematic structure diagram of some display substrates in related technologies. Fig. Figure 1b is a schematic structure diagram of some display substrates in related technologies. Fig. Figure 2 is a schematic structure diagram of other display substrates in related technologies. Fig. Figure 3 is a schematic structural diagram of some display substrates in embodiments of the present disclosure. The in Fig. The embodiment shown in Figure 3 is an illustrative example. Fig. Figure 4a is a schematic structure diagram of some selector switches in some display substrates in embodiments of the present invention. Fig. Figure 4b is a schematic structure diagram of other selector switches in some display substrates in embodiments of the present invention. Fig. 5a is a schematic sectional view structure diagram of the in Fig. 3 display substrates shown along a direction AA'. Fig. 5b is a schematic sectional view structure diagram of the in Fig. 3 shown display substrate along a direction BB'. Fig. 5c is a schematic sectional view structure diagram of the in Fig. 3 shown display substrates along a direction CC'. Fig. Figure 5d is a schematic sectional view structure diagram of subpixels in embodiments of the present invention. Fig. Figure 6a is a schematic structure diagram of other display substrates in embodiments of the present invention. Fig. Figure 6b is a schematic sectional view structure diagram of a display substrate, which is shown in Fig. 6a shows, along a direction AA'. Fig. Figure 7 is a schematic structure diagram of some further display substrates in embodiments of the present invention. Fig. Figure 8 is a schematic structure diagram of some further display substrates in embodiments of the present invention. Fig. Figure 9 is a schematic structure diagram of some further display substrates in embodiments of the present invention. Fig. Figure 10 is a schematic structure diagram of some further display substrates in embodiments of the present invention. Fig. Figure 11a is a schematic structure diagram of some further display substrates in embodiments of the present invention. Fig. Figure 11b is a schematic structure diagram of some further display substrates in embodiments of the present invention. Detailed description of the embodiments

[0023] To clarify the objectives, technical solutions and advantages of embodiments of the present invention, a clear and complete description of the technical solutions in embodiments of the present invention is given below in combination with the accompanying drawings in the embodiments of the present invention.

[0024] Unless otherwise defined, technical or scientific terms used in the present invention shall be understood by those skilled in the art in the field to which the present invention belongs. "First," "second," and similar words mentioned in the present invention do not represent any order, number, or importance, but merely distinguish different parts. Words such as "contain" or "comprise" imply that elements or things preceding the words cover elements or things listed after the words without excluding other elements or things. Similar words such as "connect" or "connected" are not limited to a physical or mechanical connection, but may include a direct or indirect electrical connection.

[0025] It should be noted that the dimensions and shapes of figures in drawings do not represent true proportions and are intended only to indicate the content of the present invention. Throughout, identical or similar numbers denote identical or similar components or components with identical or similar functions.

[0026] Generally speaking, as in Fig. 1a and Fig. As shown in Figure 1b, a display substrate comprises a display area 1 and a peripheral area 2 surrounding the display area 1; a pixel array is arranged in the display area 1; and a circuit pattern is arranged in the peripheral area 2. The pixel array comprises several subpixels and signal lines used for the subpixels, the signal lines including, for example, gate lines, data lines, power lines, and the like. Generally, one gate line is arranged for each row of subpixels, and one or two data lines are arranged for each row of subpixels. The circuit pattern for providing appropriate signals for the gate lines and the data lines is arranged in the peripheral area 2, for example, a gate driver circuit (GOA circuit) and the like for providing signals for the gate lines.

[0027] For example, the circuit pattern can be located in a lower frame area 3 in the peripheral area. For example, a simplified design for the circuit pattern located in the lower frame area 3 can achieve a narrower frame to further increase the screen-to-body ratio.

[0028] For example, the circuit layout can be simplified using multiplexing (MUX) technology. According to multiplexing technology, several data lines (e.g., two data lines) in the peripheral area are connected to a selector switch. At different times, electrical signals are transmitted to different data lines via the selector switch, thus reducing the amount of wiring in the peripheral area and the space occupied by circuits.

[0029] For example, in the display substrate two data lines can be connected to a selector switch so that the two data lines share an equal signal channel, i.e. a setup mode of MUX 1:2 (namely an either / or selection circuit) is used, therefore the number of wires in peripheral area 2 is reduced by half, then the wiring occupancy space is reduced, and the purpose of reducing the frame is finally achieved.

[0030] In some cases, while achieving the narrow frame, the frame of the display substrate and corners of the display area may be rounded to further improve the display effect of the display area and the overall attractiveness of the display substrate, but such a design may affect the circuit layout in the peripheral area.

[0031] At least one embodiment of the present invention provides a display substrate. Fig. Figure 2 is a planar schematic diagram of the display substrates in the embodiment of the present invention.

[0032] Fig. Figure 3 is a planar schematic diagram of a specific structure in the display substrates in the embodiment of the present invention; Fig. 4a are some structural schematic diagrams of selector switches 06; Fig. 4b are other structural schematic diagrams of selector switches 06; Fig. 5a is a schematic sectional view structure diagram of the in Fig. 3 shown display substrate along a direction AA'; Fig. 5b is a schematic sectional view structure diagram of the in Fig. 3 shown display substrate along a direction BB'; and Fig. 5c is a schematic sectional view structure diagram of the in Fig. 3 shown display substrates along a direction CC'. Fig. 5d is a schematic section view structure diagram of subpixels.

[0033] As in Fig. The display substrate provided in embodiments of the present invention, as shown in Figures 3 to 5c, may comprise: a substrate 01, wherein the substrate 01 comprises a display area AA and a peripheral area BB located on at least one side of the display area AA; the embodiments are introduced by assuming, as an example, that the peripheral area BB is located around the display area AA; multiple subpixels 02 located in the display area AA, wherein the multiple subpixels 02 can emit light to achieve a display function; multiple data lines 03 located in the display area AA and electrically connected to the multiple subpixels 02, wherein the multiple data lines 03 are configured to provide data signals for the multiple subpixels 02; multiple power lines 04 located in the display area AA and electrically connected to the multiple subpixels 02, wherein the multiple power lines 04 are configured to provide power signals for the multiple subpixels 02; several data signal input lines 07, which are located in the peripheral area BB; Several selector switches 06, located in the peripheral area BB and arranged at intervals, wherein the several selector switches 06 are located between the several data lines 03 and the several data signal input lines 07; wherein at least one of the several selector switches 06 is electrically connected to at least two of the several data lines 03 and one of the several data signal input lines 07; wherein the several selector switches 06 can selectively transmit data signals to the several data lines 03; the embodiments are introduced such that each selector switch 06 is, by way of example, connected to two data lines 03; furthermore, the several data signal input lines 07 are located on a side of the several selector switches 06 facing away from the display area AA, and at least one of the several selector switches 06 is electrically connected to one of the several data signal input lines 07;The embodiments are introduced by assuming, as an example, that each selector switch 06 is connected to a data signal input line; a first power bus 08 located in the peripheral area BB and on a side of the several selector switches 06 facing away from the display area AA; and several power connection cables 09, which are located in the peripheral area BB and between the first power bus 08 and the several power lines 04, wherein the several power connection cables 09 are each electrically connected to the first power bus 08 and the several power lines 04.

[0034] For example, the first power bus 08 can be connected to the subpixels 02 in the display area AA by the multiple power connection cables 09 and the multiple power lines 04 to provide power to the subpixels 02.

[0035] For example, as in Fig. As shown in Figure 2, the multiple power connection cables 09 are located in a lower frame CC in the peripheral area BB.

[0036] For example, as in Fig. As shown in Figure 3, the multiple power connection cables 09 extend along a line direction F2 of the subpixels. Furthermore, in an extension direction of an edge of the display area AA adjacent to the multiple power connection cables 09, i.e., in a direction F1 in the figure, the multiple selector switches 06 are arranged at intervals, and the multiple power connection cables 09 are also arranged at intervals.

[0037] In a specific application, in embodiments of the present invention, as in Fig. As shown in Figure 3, an orthographic projection of at least one of the several power cables on the substrate overlaps at least partially with an orthographic projection of at least one of the several selector switches on the substrate. Therefore, the occupancy space of the power cables can be reduced. Consequently, the occupancy space of the lower frame CC of the peripheral area BB is reduced, and the narrow frame is achieved.

[0038] According to the display substrate provided by the embodiments of the present invention, by designing the circuit pattern in the peripheral area, for example by designing the circuit pattern in the lower frame CC of the peripheral area BB, the occupation space of the lower frame CC of the peripheral area BB can be reduced, and a narrow frame design is also achieved.

[0039] In a specific application, in embodiments of the present invention, as in Fig. As shown in Figures 3 to 5c, the multiple power connection cables can be arranged in a one-to-one correspondence with the multiple selector switches, i.e., one power connection cable 09 corresponds to one selector switch 06. Then, at least the orthographic projection of each of the multiple power connection cables onto the substrate partially overlaps with the orthographic projection of a corresponding selector switch on the substrate. Therefore, the occupancy space of the power connection cables can be reduced. Consequently, the occupancy space of the lower frame CC of the peripheral area BB is reduced, and furthermore, the narrow frame is achieved. In addition, multiple power connection cables 09 can be arranged in this way, thus facilitating the transmission stability of power signals.

[0040] In a specific application, in embodiments of the present invention, as in Fig. As shown in Figures 3 to 5c, at least one of the multiple selector switches contains at least two thin-film transistors; the at least two thin-film transistors comprise gates and at least one source and at least two drains located on one side of the gates that differs from the substrate. For example, as shown in Fig. Figure 3 shows that each of the multiple selector switches contains two thin-film transistors; or each of the multiple selector switches contains three thin-film transistors; or each of the multiple selector switches contains six thin-film transistors, which is not defined here.

[0041] In a specific application, in embodiments of the present invention, the orthographic projection of the power cable onto the substrate overlaps at least partially with the orthographic projection of a source or drain onto the substrate. For example, in Fig. As shown in Figures 3 to 5c, the orthographic projection of the power connection cable 09 on the substrate 01 overlaps at least partially with the orthographic projection of a source (e.g. 064) on the substrate 01.

[0042] In a specific application, in embodiments of the present invention, as in Fig. As shown in Figures 3 to 5c, the orthographic projection of the power link cable 09 on the substrate 01 does not overlap with orthographic projections of the gates (such as 062 and 063) on the substrate 01. Under normal conditions, when the gate of the thin-film transistor is charged with a signal, the thin-film transistor can be controlled to turn on, allowing the source and drain of the thin-film transistor to form signal communication paths. In embodiments of the present invention, the orthographic projection of the power link cable on the substrate does not overlap with the orthographic projections of the gates on the substrate. In this way, it is possible to prevent the power link cables and the gates of the thin-film transistors from forming a parasitic capacitance, and an adverse influence of the power link cables on the turning-on and turning-off of the thin-film transistors is avoided.

[0043] In a specific application, in embodiments of the present invention, as in Fig. As shown in Figures 3 to 5c, selector switches 06 contain two thin-film transistors; that is, selector switch 06 with two thin-film transistors contains: a first active layer 061 located on the substrate 01; a first gate 062 and a second gate 063, which are located on a side of the first active layer 061 facing away from the substrate 01, wherein the first gate 062 and the second gate 063 are on the same layer but do not overlap; a first source 064, a first drain 065 and a second drain 066, which are located on a side of the first gate 062 and the second gate 063 facing away from the substrate 01, wherein the first source 064, the first drain 065 and the second drain 066 are on the same layer but do not overlap; the first source 064 is located between the first drain 065 and the second drain 066; the first source 064 is electrically connected to one of the several data signal input lines 07; and the first drain 065 and the second drain 066 are electrically connected to two of the several data lines 03.

[0044] For example, as in Fig. As shown in Figure 4a, the first active layer 061 can have an integral structure. Or as in Fig. As shown in 4b, the first active layer 061 can also be divided into separate parts to improve a heat radiation effect.

[0045] Optionally, an orthographic projection of both the first gate 062 and the second gate 063 on substrate 01 does not overlap with orthographic projections of the first source 064, the first drain 065, and the second drain 066 on substrate 01. For example, the orthographic projection of the first gate 062 on substrate 01 lies between the orthographic projections of the first drain 065 and the first source 064 on substrate 01. The orthographic projection of the second gate 063 on substrate 01 lies between the orthogonal projections of the first source 064 and the second drain 066 on substrate 01.

[0046] In a specific application, in embodiments of the present invention, as in Fig. As shown in Figures 3 to 5c, the orthographic projection of the power cable 09 on substrate 01 overlaps the orthographic projection of the first source 064 on substrate 01. Furthermore, the orthographic projection of the power cable 09 on substrate 01 does not overlap with the orthographic projections of the first gate 062 and the second gate 063 on the substrate. Since the first source is used for signal input, it has little influence on the switching on and off of a thin-film transistor; therefore, by reducing the footprint, the influence of the power cables on the switching on and off of the thin-film transistors can also be reduced.

[0047] In a specific application, in embodiments of the present invention, as in Fig. 3 and Fig. As shown in Figure 5a, for the power cable 09 and the first source 064, whose orthographic projections overlap, the power cable 09 has a first width W1 in direction F1, and the first source 064 has a second width W2 in the direction of F1, and the first width W1 is approximately equal to the second width W2. In this way, the width of the power cable can be designed according to the first source, thus reducing the design difficulties of the power cable. Of course, the first width can also be smaller than the second width, which is not defined here.

[0048] In a specific application, in embodiments of the present invention, as in Fig. 3 and Fig. As shown in Figure 5b, the display substrate further comprises a second power bus 010, which is located between the multiple selector switches 06 and the multiple power lines 04. The second power bus 010 is electrically connected to the multiple power lines 04. Furthermore, the multiple power connection cables 09 are electrically connected to the first power bus 08 and the second power bus 010. Therefore, the first power bus 08 can sequentially provide the power signals for the multiple power lines 04 via the multiple power connection cables 09 and the second power bus 010.

[0049] For example, an orthographic projection of the second current bus 010 on the substrate does not overlap with the orthographic projections of the multiple selector switches 06 on the substrate 01. The second current bus 010 may be located in the peripheral area. For example, the second current bus 010 may be located between the multiple selector switches 06 and the display area AA, or the second current bus 010 may also be located within the display area AA.

[0050] In a specific application, in embodiments of the present invention, as in Fig. 6a and Fig. As shown in Figure 6b, the display substrate further comprises a third current bus 012 located in the peripheral area; the orthographic projection of the third current bus 012 onto the substrate 01 overlaps at least partially with the orthographic projection of the first current bus 08 onto the substrate 01; and the third current bus 012 is electrically connected to the first current bus 08 via a through-hole. Therefore, based on the multilayer wiring design of equal width, a parallel connection of current buses can reduce the resistance of the current buses, thus reducing the voltage drop of the first current bus 08 to ensure long-range uniformity of the display substrate.

[0051] In a specific application, in embodiments of the present invention, as in Fig. As shown in Figure 3, the orthographic projection of the first current bus 08 on the substrate 01 overlaps at least partially with the orthographic projections of the data signal input lines 07 on the substrate 01. For example, the orthographic projection of the first current bus 08 on the substrate 01 overlaps at least partially with the orthographic projections of the data signal input lines 07 on the substrate 01.

[0052] In a specific application, in embodiments of the present invention, as in Fig. 3 and Fig. As shown in 6a, a signal source end (e.g., multiple signal input pads DZ in Fig. 3) The display substrate inputs data signals into the multiple selector switches 06 via multiple data signal input lines 07. When the signal source end inputs the data signals into a selector switch 06 via each data signal input line 07, the data signals are input into the first source 064 of the selector switch. In conjunction with control signals provided by a first control line 014 and a second control line 015, the data signals on the first source 064 can be transmitted to two data lines 03 at different times.For example, first, an on signal can be input into the first control line 014 to turn on the first source 064 and the first drain 065, and at that moment the data signals from the first source 064 are transmitted to the first drain 064 via a data line 03; and second, the on signal is input into the second control line 015 to turn on the first source 064 and the second drain 066, and at that moment the data signals from the first source 064 are transmitted to the other data line 03 via the second drain 066. After the data signals have been input into each data line 03, the subpixels connected to each data line 03 also receive the data signals. After, for example, each subpixel 02 has received the power signals and the data signals, the purpose of displaying images on the display substrate can be achieved by interacting with other electrical signals.

[0053] In a specific application, in embodiments of the present invention, as in Fig. 3 and Fig. As shown in Figure 6a, at least one of the several subpixels 02 (such as each subpixel 02) can contain a pixel driver circuit and a light-emitting diode (LED). The pixel driver circuit has a transistor and a capacitor and generates an electrical signal through the interaction of the transistor and the capacitor. The generated electrical signal is fed into a first electrode of the LED. Additionally, a second electrode of the LED is charged with a corresponding voltage to drive the LED to emit light.

[0054] For example, a 7T1C pixel circuit can be assumed to be the pixel driver circuit, and a 2T1C pixel circuit can also be assumed to be the pixel driver circuit, which is not defined here.

[0055] In a specific application, in one embodiment of the present disclosure according to Fig. 3 and in embodiments of the present invention as described in Fig. As shown in Figures 4 to 5d, the pixel driver circuit can include a driver thin-film transistor 021 and a terminal electrode 022 (introduced only by using the driver thin-film transistor 021 and the terminal electrode 022 as examples). The driver thin-film transistor 021 comprises a driver active layer 0211 located on the substrate 01, a driver gate 0212 located on a side of the driver active layer 0211 facing away from the substrate 01, and a driver source 0213 and a driver drain 0214 located on a side of the driver gate 0212 facing away from the substrate 01. The terminal electrode 022 is located on a side of the driver source 0213 and the driver drain 0214 facing away from the substrate 01.On the side of the terminal electrode 022 facing away from the substrate 01, there is a light-emitting diode 023 (with a first electrode 0231, a phosphor layer 0232, and a second electrode 0233 arranged in series along a direction away from the substrate 01); and the driver drain 0214, the terminal electrode 022, and the light-emitting diode 023 are connected in series. When a voltage is applied between the first electrode 0231 and the second electrode 0233, the phosphor layer 0232 can emit light. For example, the first electrode 0231 of the light-emitting diode 023 is electrically connected to the driver drain 0214 via the terminal electrode 022, so that the driver thin-film transistor can control the light-emitting states of the light-emitting diode 023.

[0056] For example, the materials of the driver gate 0212 and the driver drain 0214 can be conductive materials. Materials of a conductive layer can include metallic materials such as aluminum, molybdenum, and titanium, or alloy materials and the like, and can also include a metal oxide such as indium tin oxide (ITO) materials and the like. Embodiments of the present invention do not define materials of different functional layers.

[0057] In a specific application, in an embodiment of the present disclosure according to Fig. 3, and in embodiments of the present invention as described in Fig. As shown in Figure 5d, each subpixel 02 can further contain: a buffer layer 024, a first gate insulator layer 025, a second gate insulator layer 026, an intermediate dielectric layer 027, a passivation layer 028, a first flat layer 029, a second flat layer 030, a pixel-defining layer 031, a support layer 032, and a packaging layer 033, arranged sequentially along a direction away from the substrate 01. The driver active layer 0211 is located between the buffer layer 024 and the first gate insulator layer 025; the driver gate 0212 is located between the first gate insulator layer 025 and the second gate insulator layer 026. The driver source 0213 and the driver drain 0214 are located between the interlayer dielectric layer 027 and the passivation layer 028; and the terminal electrode 022 is located between the first flat layer 029 and the second flat layer 030.The pixel-defining layer 031 is configured to define a pixel area on the substrate 01, and the above light-emitting diode 023 is located in the pixel area.

[0058] For example, the pixel-defining layer 031 contains multiple openings, each corresponding to multiple subpixels 02, and the light-emitting diodes 023 are formed within these multiple openings. For example, the packaging layer 033 can comprise multiple packaging sublayers, such as the three packaging sublayers shown in the figures. For example, the three packaging sublayers comprise a first inorganic packaging sublayer, an organic packaging sublayer, and a second inorganic packaging sublayer, which are overlapped to enhance the packaging effect of the packaging layer 033.

[0059] For example, the gate insulator layer (including a first gate insulator layer 025 and a second gate insulator layer 026), the interlayer dielectric layer 027, the buffer layer 024, the flat layer 028, the pixel-defining layer 031, the support layer 032, the packaging layer 033, and the like are all formed from insulating materials. Depending on the requirements, organic insulating materials can be selected, such as polyimide materials, resin materials, and the like; inorganic insulating materials can also be selected, such as silicon oxide, silicon nitride, silicon oxynitride, and the like; and embodiments of the present invention do not specifically define materials for various functional layers.

[0060] It must be noted that the buffer layer 024, the first gate insulator layer 025, the second gate insulator layer 026, the interlayer dielectric layer 027, the passivation layer 028, the first flat layer 029 and the second flat layer 030 in the display area AA can all extend to the peripheral area BB; furthermore, the relative positional relationship of the membrane layers in the peripheral area BB is the same as that in the display area AA and is not repeated in the embodiments of the present invention.

[0061] It must be noted that, as in Fig. Figure 5c shows that a power line 04 and the second power bus 010 are directly electrically connected. Furthermore, the first source 064 is electrically connected to the first active layer 061 via several through-holes passing through the first gate insulator layer 025, the second gate insulator layer 026, and the interlayer dielectric layer 027. Additionally, the first source 064 is electrically connected to the data signal input lines 07 via a through-hole passing through the interlayer dielectric layer 027.

[0062] Additionally, as in Fig. 3 and Fig. As shown in Figure 5d, each subpixel 02 can also contain a storage capacitor 034; the storage capacitor 034 comprises a first capacitor electrode 0341 and a second capacitor electrode 0342; the first capacitor electrode 0341 and the driver gate 0212 are located on the same layer; and the second capacitor electrode 0342 is located between the gate insulating layer 026 and the interlayer dielectric layer 027.

[0063] For example, part of the structure of the display area AA in the display substrate can be on the same layer as part of the structure of the peripheral area BB, and the structures are explained and introduced below. It should be noted that in embodiments of the present invention, the presence of multiple structures on the same layer refers to multiple structures that can be formed by a structuring process in a single manufacturing process within the same material layer, thus simplifying the manufacturing process of the display substrate.

[0064] For example, as in Fig. As shown in Figures 3 to 5d, at least one type of power connection cable 09, first power bus 08, and data lines 03 can be located on the same layer as the connection electrodes 022. For example, if the power connection cables 09 and the connection electrodes 022 are located on the same layer, then, if the connection electrodes 022 are manufactured in the display area AA, the power connection cables 09 of the peripheral area BB can be manufactured simultaneously, thus simplifying the processes for manufacturing the display substrate. Of course, the power connection cables 09 and the connection electrodes 022 can also be located on a different layer, and this is not defined in the embodiments of the present invention.

[0065] For example, as in Fig. As shown in Figures 3 to 5d, the first current bus 08 and the connection electrodes 022 are located on the same layer. In this way, if the connection electrodes 022 are manufactured in the display area AA, the first current bus 08 of the peripheral area BB can be manufactured simultaneously, thus simplifying the processes for manufacturing the display substrate. Of course, the first current bus 08 and the connection electrodes 022 can also be located on a different layer, and this is not defined in the embodiments of the present invention.

[0066] For example, as in Fig. In layers 3 to 5d, the data lines 03 and the connection electrodes 022 are located on the same layer. In this way, if the connection electrodes 022 are manufactured in the display area AA, the data lines 03 can be manufactured simultaneously, thus simplifying the processes for manufacturing the display substrate. Of course, the data lines 03 and the connection electrodes 022 can also be located on different layers, and this is not defined in the embodiments of the present invention.

[0067] For example, as in Fig. In layers 3 to 5d, the power connection cables 09, the first power bus 08, and the data lines 03 are located on the same layer as the connection electrodes 022. In this way, when the connection electrodes 022 are manufactured in the display area AA, the power connection cables 09, the first power bus 08, and the data lines 03 of the peripheral area BB can be manufactured simultaneously, and the processes for manufacturing the display substrate are simplified.

[0068] If the power connection cables 09 and the first power bus 08 are located on the same layer, and if the first power bus 08 and the connection electrodes 022 are also located on the same layer, this means that the power connection cables 09 and the connection electrodes 022 are located on the same layer. The selector switches 06 and the connection electrodes 022 are generally located on different layers; therefore, the power connection cables 09 and the first power bus 08 are located on different layers than the selector switches 06, and thus the problem of a short circuit between the power connection cables 09, the first power bus 08, and the selector switches 06 is further reduced.

[0069] For example, as in Fig. As shown in Figures 3 to 6b, at least one type of power lines 04, second power bus 010, and third power bus 012 can be located on the same layer as the driver sources 0213 and the driver drains 0214. For example, the power lines 04 can be located on the same layer as the driver sources 0213 and the driver drains 0214. In this way, if the driver sources 0213 and the driver drains 0214 are manufactured in the display area AA, the power lines 04 can be manufactured simultaneously, and the processes for manufacturing the display substrate are simplified.

[0070] For example, as in Fig. As shown in Figures 3 to 6b, the second current bus 010 can be located on the same layer as the driver sources 0213 and the driver drains 0214. In this way, if the driver sources 0213 and the driver drains 0214 are manufactured in the display area AA, the second current bus 010 of the peripheral area BB can be manufactured simultaneously, and the processes for manufacturing the display substrate are simplified. Of course, the second current bus 010 can also be located on a different layer than the driver sources 0213 and the driver drains 0214, and this is not defined in the embodiments of the present invention.

[0071] For example, as in Fig. As shown in Figures 3 to 6b, the third current bus 012 can be located on the same layer as the driver sources 0213 and the driver drains 0214. In this way, if the driver sources 0213 and the driver drains 0214 are manufactured in the display area AA, the third current bus 012 of the peripheral area BB can be manufactured simultaneously, and the processes for manufacturing the display substrate are simplified. Of course, the third current bus 012 can also be located on a different layer than the driver sources 0213 and the driver drains 0214, and this is not defined in the embodiments of the present invention.

[0072] For example, as in Fig. As shown in Figures 3 to 5d, the data signal input lines 07 and the second capacitor electrodes 0342 can be located on the same layer. In this way, if the second capacitor electrodes 0342 are manufactured in the display area AA, the data signal input lines 07 of the peripheral area BB can be manufactured simultaneously, and the processes for manufacturing the display substrate are simplified. Of course, the data signal input lines 07 and the second capacitor electrodes 0342 can also be located on different layers. For example, part of the data signal input lines 07 can be located on the same layer as the driver gate, and the other part of the data signal input lines 07 can be located on the same layer as the second capacitor electrodes, with the two parts offset. This is not defined in the embodiments of the present invention.

[0073] For example, some structures of the thin-film transistors in the selector switches 06 may also be located on the same layer as some structures of the driver thin-film transistors in the pixel driver circuits. For example, the first active layers 061 are located on the same layer as the driver active layers 0211, and the first gates 062, the second gates 063 and the driver gates 0212 are located on the same layer, and the first sources 064, the first drains 065, the second drains 066 and the driver sources 0213 are located on the same layer.Of course, the first active layers 061 and the driver active layers 0211 cannot be located on the same layer, the first gates 062 and the driver gates 0212 cannot be located on the same layer, the first sources 064 and the driver sources 0213 cannot be located on the same layer, and this is not defined in the embodiments of the present invention.

[0074] In a specific application, the materials of the first flat layers 029 in embodiments of the present invention can be organic materials. Since organic materials tend to absorb water and oxygen, water and oxygen can adversely affect other membrane layers. On this basis, in embodiments of the present invention, as described in Fig. 6a and Fig. As shown in Figure 6b, the first current bus 08 comprises several openings KB arranged at intervals; and the orthographic projections of the openings KB on the substrate 01 partially overlap with the orthographic projections of the data signal input lines 07 on the substrate 01. In this way, the water and oxygen in the first flat layers 029 are released through the openings KB, thereby improving the reliability of the display substrate.

[0075] In a specific application, embodiments of the present invention, as described in Fig. 7 and Fig. As shown in Figure 8, several openings KB are subdivided into several opening groups ZB-k (1 ≤ k ≤ K, where k and K are integers, K is the total number of opening groups, and Figure 7 takes K = 4 as an example), arranged along a second direction F2, and each opening group ZB-k comprises several openings KB arranged along the first direction F1. In this way, by arranging several scattered openings KB, the water and oxygen in the first shallow layers 029 can be further released, thereby further improving the reliability of the indicator substrate.

[0076] In a specific application, in embodiments of the present invention, the first direction F1 intersects with the second direction F2. For example, the first direction F1 is perpendicular to the second direction F2.

[0077] In a specific application, embodiments of the present invention, as described in Fig. Figure 7 shows openings in at least two adjacent opening groups that are offset. For example, openings in each pair of adjacent opening groups can be offset. For instance, if four opening groups are used, the display substrate has opening groups ZB-1, ZB-2, ZB-3, and ZB-4. Openings in opening group ZB-1 and openings in opening group ZB-2 are offset; for example, the openings in opening group ZB-2 correspond to the gap positions between adjacent openings in opening group ZB-1. Openings in opening group ZB-2 and openings in opening group ZB-3 are offset; for example, the openings in opening group ZB-2 correspond to the gap positions between adjacent openings in opening group ZB-3.Openings in opening group ZB-3 and openings in opening group ZB-4 are arranged offset, for example, the openings in opening group ZB-2 correspond to the gap positions between adjacent openings in opening group ZB-3.

[0078] In a specific application, embodiments of the present invention, as shown in FIG. 8, can also have multiple openings arranged in an array. This reduces the difficulty in designing the openings.

[0079] In a specific application, embodiments of the present invention, as described in Fig. 7 and Fig. Figure 8 shows that the gaps between any two adjacent openings in each opening group are approximately equal. For example, the gaps between the centers of any two adjacent openings in each opening group can be approximately equal.

[0080] It must be established that in an actual process, due to constraints of the process conditions or other factors, the characteristics are not perfectly equal, but rather exhibit a deviation. In such cases, the equality of the characteristics can be achieved as long as the conditions are approximately met. For example, equality may be permitted within a tolerance range.

[0081] One embodiment of the present invention provides a schematic structure diagram of the display substrate, and as shown in Fig. As shown in Figure 9, a deformation is performed for application modes of the embodiment. Only the differences between this embodiment and the embodiments above are given below, and the similarities are not repeated here.

[0082] In a specific application, embodiments of the present invention, as described in Fig. Figure 9 shows the orthographic projections of the multiple power bus cables 09 on the substrate 01 within the orthographic projections of the gaps between the multiple selector switches 06 on the substrate 01. In this way, the orthographic projections of the multiple power bus cables 09 on the substrate 01 do not overlap with the orthographic projections of the multiple selector switches 06 on the substrate 01. This reduces the degree of overlap between the first power bus and the selector switches, thereby reducing any parasitic capacitance formed by the first power bus and the selector switches, and allows both the first power bus and the selector switches to operate normally.

[0083] By way of example, embodiments of the present invention, as in Fig. As shown in Figure 9, a power connection cable was placed according to a gap.

[0084] In a specific application, embodiments of the present invention, as described in Fig. Figure 10 shows that for the power connecting cables and the gaps that are overlapped by orthographic projection, the power connecting cables each have a third width W3 in the direction F1, the gaps each have a fourth width W4 in the direction F1, and the third width is smaller than the fourth width.

[0085] Furthermore, in a specific application, embodiments of the present invention, as described in Fig. As shown in Figure 10, the orthographic projections of one part of the multiple power connection cables 09 on substrate 01 overlap the orthographic projections of the first sources 064 on substrate 01. The orthographic projections of the other part of the multiple power connection cables 09 on substrate 01 are located in the orthographic projections of the gaps between the selector switches 06 on substrate 01.

[0086] For example, the display substrate can be a self-illuminating display substrate such as an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), or a non-self-illuminating display substrate such as a liquid crystal diode (LCD), and the type of display substrate is not defined in the embodiments of the present invention.

[0087] For example, if the display substrate is OLED or QLED, the display substrate can be packaged to form a display device.

[0088] If the display substrate is, for example, an LCD display substrate, the display substrate further comprises an opposing substrate, the display substrate and the opposing substrate are arranged opposite each other, and a liquid crystal material is filled between the display substrate and the opposing substrate to form the LCD display device. For example, the opposing substrate is a colored membrane substrate containing structures such as a colored membrane layer for generating monochromatic light and a black matrix layer for light blocking. Structures of the display substrate are not specifically defined in the embodiments of the present invention.

[0089] The display substrate provided by the embodiments of the present invention can have irregular corners, such as arc-shaped corners, and a narrow frame design can also be achieved so that a high screen-to-body ratio is achieved and a better display effect is obtained.

[0090] One embodiment of the present invention provides some schematic structure diagrams of display substrates, and as shown in Fig. 11a and Fig. As shown in Figure 11b, a deformation is performed for application modes of the embodiments. Only the differences between the embodiment and the embodiments above are given below, and the similarities are not repeated here.

[0091] In a specific application, in embodiments of the present invention, as in Fig. 11a and Fig. As shown in Figure 11b, the multiple data signal input lines 07 can comprise first data signal input lines 071 and second data signal input lines 072; and the first data signal input lines 071 and the second data signal input lines 072 are arranged alternately along the first direction F1. In this way, interference of the arrangement on the same layer can be reduced.

[0092] In a specific application, in embodiments of the present invention, as in Fig. 11a and Fig. As shown in Figure 11b, the first data signal input lines 071 and the driver gates can be arranged on the same layer. In this way, the first data signal input lines 071 and the driver gates can be formed by the same structuring process.

[0093] In a specific application, in embodiments of the present invention, as in Fig. 11a and Fig.As shown in Figure 11b, the second data signal input lines 072 and the second capacitor electrodes can be arranged on the same layer. In this way, the second data signal input lines 072 and the second capacitor electrodes can be formed by the same structuring process.

[0094] At least one embodiment of the present invention further provides a display device, and the display device comprises the display substrate. For example, the display device can be any product or component with a display function, such as a mobile phone, a tablet PC, a television, a display, a notebook computer, a digital picture frame, or a navigator, and the specific mode of the display device is not defined in the embodiments of the present invention.

Claims

[1] A display substrate comprising: a substrate (01) with a display area (AA) and a peripheral area (BB) located on at least one side of the display area (AA); several subpixels (02) located in the display area (AA); multiple data lines (03) located in the display area (AA) and electrically connected to the multiple subpixels (02), wherein the multiple data lines (03) are configured to provide data signals for the multiple subpixels (02); multiple power lines (04) located in the display area (AA) and electrically connected to the multiple subpixels (02), wherein the multiple power lines (04) are configured to provide power signals for the multiple subpixels (02); several data signal input lines (07) located in the peripheral area (BB); several selector switches (06) located in the peripheral area (BB) and between the multiple data lines (03) and the multiple data signal input lines (07), wherein at least one of the multiple selector switches (06) is electrically connected to at least two of the multiple data lines (03) and one of the multiple data signal input lines (07); a first current bus (08) located in the peripheral area (BB) and on a side of the multiple selector switches (06) facing away from the display area (AA); and several power connection cables (09) located in the peripheral area (BB) and between the first power bus (08) and the several power lines (04); wherein the multiple power connection cables (09) are electrically connected to the first power bus (08) and the multiple power lines (04), wherein the display substrate characterized by is, that the first current bus (08) contains several openings (KB) formed at intervals; and that orthographic projections of the openings (KB) on the substrate (01) partially overlap with the orthographic projections of the data signal input lines (07) on the substrate (01). [2] Display substrate according to claim 1, wherein an orthographic projection of at least one of the several power connection cables (09) on the substrate (01) overlaps at least partially with an orthographic projection of at least one of the several selector switches (06) on the substrate (01). [3] Display substrate according to claim 2, wherein the multiple power connection cables (09) are in a one-to-one correspondence with the multiple selector switches (06); and an orthographic projection of each of the power connection cables (09) on the substrate (01) overlaps at least partially with an orthographic projection of a corresponding selector switch (06) on the substrate (01). [4] Display substrate according to claim 3, wherein the at least one of the several selector switches (06) comprises at least two thin-film transistors; the at least two thin-film transistors comprise gates and at least one source and at least two drains located on one side of the gates facing away from the substrate (01); and an orthographic projection of each of the power connecting wires (09) on the substrate (01) overlaps at least partially with an orthographic projection of one of the source and drain of the correspondingly arranged selector switch (06) on the substrate (01). [5] Display substrate according to claim 4, wherein the orthographic projection of the power connection cable (09) on the substrate (01) does not overlap with orthographic projections of the gates on the substrate (01). [6] Display substrate according to claim 5, wherein each selector switch (06) comprises two thin-film transistors, the gates comprising a first gate (062) and a second gate (063), the at least one source comprising a first source (064) and the at least two drains comprising a first drain (065) and a second drain (066); the two thin-film transistors as a whole comprising: a first active layer (061) located on the substrate (01); the first gate (062) and the second gate (063), which are located on a side of the first active layer (061) facing away from the substrate (01), wherein the first gate (062) and the second gate (063) are on the same layer but do not overlap; the first source (064), the first drain (065) and the second drain (066), which are located on a side of the first gate (062) and the second gate (063) facing away from the substrate (01), wherein the first source (064), the first drain (065) and the second drain (066) are on the same layer but do not overlap; and the first source (064) is located between the first drain (065) and the second drain (066); the first source (064) is electrically connected to one of the several data signal input lines (07); the first drain (065) and the second drain (066) are electrically connected to two of the several data lines (03); The orthographic projection of the power connection cable (09) on the substrate (01) covers an orthographic projection of the first source (064) on the substrate (01); and The orthographic projection of the power connection cable (09) on the substrate (01) does not overlap with orthographic projections of the first gate (062) and the second gate (063) on the substrate (01). the first gate (062), the first active layer (061), the first source (064) and the first drain (065) form one of the two thin-film transistors, while the second gate (063), the first active layer (061), the first source (064) and the second drain (066) form the other of the two thin-film transistors, with the two thin-film transistors sharing the first source (064). [7] Display substrate according to claim 6, wherein the power connection cable (09) has a first width in a direction perpendicular to the data lines (03), the first source (064) has a second width in the direction perpendicular to the data lines (03), and the first width is approximately equal to the second width. [8] Display substrate according to claim 1, wherein orthographic projections of the multiple power connection cables (09) on the substrate (01) are located within orthographic projections of gaps between the multiple selector switches (06) on the substrate (01). [9] Display substrate according to claim 8, wherein the power connection cable (09) has a third width in a direction perpendicular to the data lines (03), and the gap has a fourth width in the direction perpendicular to the data lines (03), and the third width is smaller than the fourth width. [10] Display substrate according to any one of claims 1 to 9, further comprising: a second current bus (010) located between the multiple selector switches (06) and the multiple power lines (04); the second current bus (010) being electrically connected to the multiple power lines (04); and the multiple power connection cables (09) being electrically connected to the first current bus (08) and the second current bus (010). [11] Display substrate according to claim 10, further comprising: a third current bus (012) located in the peripheral area (BB); an orthographic projection of the third current bus (012) on the substrate (01) overlaps at least partially with an orthographic projection of the first current bus (08) on the substrate (01), and the third current bus (012) is electrically connected to the first current bus (08). [12] Display substrate according to claim 11, wherein at least one of the several subpixels (02) comprises a driver thin-film transistor (021), a terminal electrode (022) and a storage capacitor (034); The driver thin-film transistor (021) includes a driver active layer (0211) located on the substrate (01), a driver gate (0212) located on a side of the driver active layer (0211) facing away from the substrate (01), a gate insulator layer (026) located on a side of the driver gate (0212) facing away from the substrate (01), an interlayer dielectric layer (027) located on a side of the gate insulator layer (026) facing away from the substrate (01), and a driver source (0213) and a driver drain (0214) located on a side of the interlayer dielectric layer (027) facing away from the substrate (01); the connection electrode (022) is located on a side of the driver source (0213) and the driver drain (0214) facing away from the substrate (01); The storage capacitor (034) contains a first capacitor electrode (0341) and a second capacitor electrode (0342); the first capacitor electrode (0341) and the driver gate (0212) are located on the same layer; the second capacitor electrode (0342) is located between the gate insulating layer (026) and the interlayer dielectric layer (027); and At least one type of the power connection cable (09), the first power bus (08) and the data line (03) are located on the same layer as the connection electrode (022). [13] Display substrate according to claim 12, wherein at least one type of current line (04), second current bus (010) and third current bus (012) is located on the same layer as the driver source (0213) and the driver drain (0214); and the data signal input line (07) and the second capacitor electrode (0342) are located on the same layer. [14] Display substrate according to claim 13, wherein the driver active layer (0211) and the first active layer (061) are located on the same layer; The first gate (062), the second gate (063) and the driver gate (0212) are located on the same layer; and the first source (064), the first drain (065) and the second drain (066) are located on the same layer as the driver source (0213) and the driver drain (0214). [15] Display substrate according to claim 14, wherein an orthographic projection of the first current bus (08) on the substrate (01) overlaps at least partially with orthographic projections of the data signal input lines (07) on the substrate (01). [16] Display substrate according to claim 15, wherein the multiple openings (KB) are divided into multiple opening groups (ZB-k) arranged along a second direction; each opening group (ZB-k) contains multiple openings (KB) arranged along a first direction, and the first direction intersects the second direction; and the openings (KB) in at least two adjacent opening groups are offset. [17] Display substrate according to claim 12, wherein the multiple data signal input lines (07) include first data signal input lines (071) and second data signal input lines (072); the first data signal input lines (071) and the second data signal input lines (072) are arranged alternately along a first direction; The first data signal input lines (071) and driver gates (0212) are located on the same layer; and The second data signal input lines (072) and the second capacitor electrode (0342) are located on the same layer. [18] Display substrate according to any one of claims 12 to 17, wherein at least one of the several subpixels (02) further comprises: a light-emitting diode (023) located on a side of the terminal electrode (022) facing away from the substrate (01); and the driver drain (0214), the terminal electrode (022) and the light-emitting diode (023) are electrically connected sequentially. [19] A display device comprising the display substrate according to any one of claims 1 to 18.

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