Semiconductor device and method for manufacturing the semiconductor device

Abstract

Semiconductor device (101, 102, 103, 104) comprising: • an insulating substrate (6); • a semiconductor element (1); • a capacitor (15); • a first terminal (13) having a surface (130); and a second terminal (14) which has an area (140), wherein the insulating substrate (6) has an insulating layer (4) and a conductor structure (3) provided on the insulating layer (4), the semiconductor element (1) is connected to the conductor structure (3), the first terminal (13) is electrically connected to the semiconductor element (1), the area (130) of the first terminal (13) and the area (140) of the second terminal (14) face each other, the capacitor (15) is positioned between the area (130) of the first terminal (13) and the area (140) of the second terminal (14), which face each other, and the capacitor (15) is connected to the first terminal (13) and the second terminal (14).• a first metal terminal (18) and a second metal terminal (18) are attached to the capacitor (15), and • the first metal terminal (18) is in contact with a side opposite the surface (130) of the first terminal (13), and the second metal terminal (18) is in contact with a side opposite the surface (140) of the second terminal (14), whereby the first terminal (13) and the second terminal (14) are inserted between the first metal terminal (18) and the second metal terminal (18).

Description

Technical field The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. State of the art Patent document 1 discloses a semiconductor device equipped with a capacitor. EP 2 631 946 A1 discloses a semiconductor module with at least one capacitor and at least one bridge circuit, which has a low-inductance design. US 2008 / 0013298A1 discloses methods and devices for the passive mounting of components for integrated circuits. DE 10 2017 111 824 A1 discloses a package with a component that is connected at the carrier level. US 6 940 164 B1 discloses a power module containing a switching semiconductor element and a smoothing capacitor. US 5 399 905 A1 discloses a resin-sealed semiconductor device comprising a plurality of current-sensing resistors mounted on the terminals of a terminal frame and electrically connected in parallel. State of the art documents Patent document(s) [Patent Document 1] International Publication No. 2018 / 008424 Summary Problem to be solved by the invention In a semiconductor device equipped with a capacitor, temperature changes within the device create a stress on the capacitor, which in some cases damages it. Such problems were not adequately addressed in conventional semiconductor devices. The present disclosure was made to solve the aforementioned problems, and one of its objectives is to provide a semiconductor device that reduces the stress generated in a capacitor due to temperature changes in the semiconductor device, thereby preventing damage to the capacitor. Means to solve the problem This problem is solved by the features of the independent claims. The dependent claims contain advantageous embodiments of the invention. A semiconductor device according to one aspect of the present disclosure is a semiconductor device comprising an insulating substrate, a semiconductor element, a capacitor, a first terminal with a surface, and a second terminal with a surface, wherein the insulating substrate has an insulating layer and a conductor structure provided on the insulating layer, the semiconductor element is connected to the conductor structure, the first terminal is electrically connected to the semiconductor element, the surface of the first terminal and the surface of the second terminal face each other, the capacitor is positioned between the surfaces of the first terminal and the surfaces of the second terminal, which face each other, the capacitor is connected to the first terminal and the second terminal, and a first metal terminal and a second metal terminal are attached to the capacitor.and the first metal terminal is in contact with a side opposite the surface of the first terminal, and the second metal terminal is in contact with a side opposite the surface of the second terminal, whereby the first terminal and the second terminal are inserted between the first metal terminal and the second metal terminal. Effects of the invention According to the present disclosure, a semiconductor device reduces a stress that is generated in a capacitor due to temperature changes in the semiconductor device, thereby preventing damage to the capacitor. The tasks, characteristics, aspects, and advantages of the technology revealed in the present specification will become clearer with reference to the following detailed description and accompanying figures. Brief description of the characters Fig. 1 A top view illustrating a semiconductor device according to embodiment 1. Fig. 2 A side view illustrating the semiconductor device according to embodiment 1. Fig. 3 A top view illustrating a semiconductor device according to embodiment 2. Fig. 4 A side view illustrating the semiconductor device according to embodiment 2. Fig. 5 A cross-sectional view illustrating the semiconductor device according to embodiment 2, taken along line AA in Fig. 3. Fig. 6 A top view illustrating a semiconductor device according to embodiment 3. Fig. 7 A top view illustrating a semiconductor device according to embodiment 4. Fig. 8 A cross-sectional view illustrating the semiconductor device according to embodiment 4, taken along line BB in Fig. 7.9 A flowchart illustrating a method for manufacturing the semiconductor device according to embodiment 2. Description of the embodiment(s) <A. Ausführungsform 1 > <A-1. Konfiguration> Fig. 1 is a top view of a semiconductor device 101 according to embodiment 1. Fig. 2 is a side view of the semiconductor device 101 of embodiment 1. The semiconductor device 101 comprises a semiconductor element 1, a solder 2, an insulating substrate 6, wires 7, a wire 8, a wire 9, a base plate 10, a solder 11, a terminal 12a, a terminal 12b, a terminal 13, a terminal 14 and a capacitor 15. The insulating substrate 6 has an insulating layer 4, a conductor structure 3 provided on one main surface of the insulating layer 4, and a conductor structure 5 provided on the other main surface of the insulating layer 4. The conductor structure 5 is connected to a base plate 10 via a solder 11. That is, the insulating substrate 6 is attached to the base plate 10 via the solder 11. The insulating substrate 6 need not contain the conductor structure 5. In this case, the insulating layer 4 is connected to the base plate 10. The insulating layer 4 is, for example, directly connected to the base plate 10. The base plate 10 and the insulating substrate 6 can be integrated by directly connecting the insulating layer 4 and the base plate 10. The base plate 10 is, for example, connected to cooling fins. The semiconductor element 1 is a switching element. The semiconductor element 1 is, for example, a bipolar transistor, a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), or a reverse-conducting IGBT (RC-IGBT). Although Fig. 1 illustrates a case in which the semiconductor device 101 comprises one semiconductor element (that is, the semiconductor element 1), the semiconductor device 101 can comprise a variety of semiconductor elements. For example, the semiconductor device 101 can comprise a variety of switching elements. Furthermore, the semiconductor device 101 can, for example, comprise a switching element and a diode. The ladder structure 3 has a ladder structure 3a, a ladder structure 3b, a ladder structure 3c, and a ladder structure 3d. Semiconductor element 1 is connected to conductor structure 3b via solder 2. In other words, semiconductor element 1 is connected to conductor structure 3 via solder 2. The semiconductor element 1 has a signal electrode 1a and a power electrode 1b. The signal electrode 1a is an electrode for injecting a signal into the semiconductor element 1 to control the on / off state of the semiconductor element 1, which is a switching element. The signal electrode 1a is a gate electrode if the semiconductor element 1 is a MOSFET or an IGBT. The signal electrode 1a is a base electrode if the semiconductor element 1 is a bipolar transistor. Power electrode 1b is an emitter electrode if semiconductor element 1 is an IGBT or a bipolar transistor. Power electrode 1b is a source electrode if semiconductor element 1 is a MOSFET. Power electrode 1b and conductor structure 3a are connected by wires 7. Power electrode 1b and conductor structure 3c are connected by wires 8. Signal electrode 1a and conductor structure 3d are connected by wire 9. Terminal 12a is connected to conductor structure 3a. Terminal 12b is connected to conductor structure 3b. Terminal 13 is connected to conductor structure 3c. Terminal 14 is connected to conductor structure 3d. Terminals 12a, 12b, 13, and 14 are each connected to conductor structures 3 via a connecting material such as a solder (not illustrated), or they can be directly connected to conductor structures 3. Connections 12a and 12b are power connections. Terminal 13 and terminal 14 are signal terminals. Terminal 13 is electrically connected to the power electrode 1b via the conductor structure 3c and the wire 8. The potential of the power electrode 1b can be detected from outside the semiconductor device 101 via terminal 13. Terminal 14 is electrically connected to signal electrode 1a via conductor structure 3d and wire 9. A gate signal for controlling semiconductor element 1 can be fed into semiconductor element 1 from outside semiconductor device 101 via terminal 14. Connection 13 has an area of ​​130. Connection 14 has an area of ​​140. For example, terminals 13 and 14 are terminals that each have a flat, plate-like shape. Surfaces 130 and 140 are, for example, surfaces of terminal 13 and terminal 14, respectively, which have a flat, plate-like shape, and they have a specific width and extent. Connection 13 and connection 14 are arranged such that surface 130 and surface 140 face each other. Surface 130 and surface 140 face each other in one direction within a plane of the insulating substrate 6. Capacitor 15, for example, is a ceramic capacitor. Using a ceramic capacitor as capacitor 15 facilitates the improvement of the performance of the semiconductor device 101. Capacitor 15 is located between surface 130 and surface 140. Capacitor 15 is connected to terminal 13 and terminal 14. The capacitor 15 is connected to the surface 130 and the surface 140, for example, using a connecting material (not illustrated) such as solder. One electrode (not illustrated) of capacitor 15 is electrically connected to terminal 13, and the other electrode (not illustrated) of capacitor 15 is electrically connected to terminal 14. When the capacitor 15 is mounted on the conductor structure 3, a stress is generated in the capacitor 15 due to deformation of the insulating substrate 6 caused by temperature changes, which can lead to damage to the capacitor 15. When the capacitor 15 is mounted on the conductor structure 3, the base plate 10 is severely deformed due to temperature changes, and this deformation is transferred to the capacitor 15 through the deformation of the insulating substrate 6, generating a significant stress in the capacitor 15. In the semiconductor device 101 according to embodiment 1, the capacitor 15 is mounted between terminal 13 and terminal 14; therefore, the influence of the deformation of the insulating substrate 6 on the capacitor 15 is prevented, thereby reducing the stress generated in the capacitor 15. As a result, damage to the capacitor 15 is prevented and the reliability of the semiconductor device 101 is improved. If the capacitor 15 is connected to terminals 13 and 14 at a position away from the insulating substrate 6, the stress generated in the capacitor 15 due to the deformation of the insulating substrate 6 can be further reduced. The capacitor 15 can be separated from the insulating substrate 6 by a distance that is, for example, equal to or greater than the distance between area 130 and area 140. Alternatively, the capacitor 15 can be separated from the insulating substrate 6 by a distance that is, for example, twice the distance or greater than the distance between area 130 and area 140. By reducing the stress generated in the capacitor 15, it is possible to use a capacitor with low mechanical strength for the capacitor 15. Semiconductor element 1, for example, is a semiconductor element that uses either a silicon semiconductor or a wide-bandgap semiconductor. The wide-bandgap semiconductor is, for example, a semiconductor with a wider bandgap than the silicon semiconductor. The wide-bandgap semiconductor is, for example, a SiC semiconductor or a GaN semiconductor. If semiconductor element 1 uses a wide-bandgap semiconductor, the semiconductor device 101 can be operated at a high speed. Furthermore, if semiconductor element 1 uses a wide-bandgap semiconductor, operation at a higher temperature is possible than if semiconductor element 1 uses a silicon semiconductor.While the semiconductor element is operated at a high temperature, the insulating substrate 6 is susceptible to deformation; in the semiconductor device 101 according to embodiment 1, damage to the capacitor 15 due to the influence of the deformation of the insulating substrate 6 on the capacitor 15 is prevented. While in embodiment 1 the case was described as an example in which two terminals (that is, terminal 13 and terminal 14) connected to the capacitor 15 are electrically connected to the same semiconductor element (that is, the semiconductor element 1), one of the two terminals to which the capacitor 15 is connected may be electrically connected to the semiconductor device 1, and the other terminal may not be electrically connected to the semiconductor element 1 and may, for example, be brought out of the semiconductor device 101. Furthermore, the two terminals to which the capacitor 15 is connected may, for example, each be electrically connected to different semiconductor elements. Finally, the capacitor 15 may, for example, be connected to a power terminal. In the semiconductor device 101, the semiconductor element 1 and the capacitor 15 can be sealed by means of a sealing material, and the semiconductor device 101 can have a housing in which the semiconductor element 1 is housed. <B. Ausführungsform 2> <B-1. Konfiguration> Fig. 3 is a top view of a semiconductor device 102 according to embodiment 2. Fig. 4 is a side view of the semiconductor device 102 of embodiment 2. Fig. 5 is a cross-sectional view taken along a line AA in Fig. 3. Differences with respect to the semiconductor device 101 according to embodiment 1 are that the semiconductor device 102 has a housing 16 and that the positions of the terminal 13 and the terminal 14 are defined by the housing 16. Furthermore, the semiconductor device 102 differs from the semiconductor device 101 according to embodiment 1 in that the semiconductor element 1 and the capacitor 15 are sealed with a sealing material 17. The semiconductor device 102 according to embodiment 2 is similar to the semiconductor device 101 according to embodiment 1 in other respects. In Fig. 3, a sealing material 17 is omitted for visibility reasons. In Fig. 4, only a part of the housing 16 is illustrated for visibility reasons, and the sealing material 17 is illustrated in such a way that it does not obscure other elements. The positions of terminal 13 and terminal 14 are defined by the housing 16, allowing the capacitor 15 to be mounted between them. This configuration prevents changes in the distance between terminals 13 and 14, simplifying the assembly of the capacitor 15 during manufacturing. Furthermore, it improves work efficiency, such as verifying the position of the capacitor 15, thus increasing productivity and yield. Additionally, the quality of the semiconductor device 102 is improved because the positions of terminals 13 and 14 are less likely to shift. For example, terminal 13 and terminal 14 are cast into the housing 16, so that the positions of terminal 13 and terminal 14 are defined by the housing 16. A convex portion 160, projecting towards the interior of the housing 16, is provided on the inner peripheral surface of the housing 16. The terminal 13 faces the convex portion 160 on the opposite side of the surface 130, and the terminal 14 faces the convex portion 160 on the opposite side of the surface 140. The convex portion 160 defines the positions of the terminal 13 and the terminal 14. While Figs. 3, 4 to 5 illustrate a case in which a convex part is provided on the inner peripheral surface of the housing 16, a plurality of convex parts can be provided on the inner surface of the housing 16, wherein a convex part to which the connection 13 is oriented on the side opposite the surface 130 may differ from a convex part to which the connection 14 is oriented on the side opposite the surface 140. Either the positions of port 13 and port 14 defined by overmolding port 13 and port 14 in the housing 16, or the positions of port 13 and port 14 defined by the convex part 160, can be applied. In embodiment 2, the capacitor 15 is also mounted between terminal 13 and terminal 14, so that the stress generated in the capacitor 15 due to temperature changes in the semiconductor device 102 is reduced, thereby preventing damage to the capacitor 15 and improving the reliability of the semiconductor device 102. <B-2. Verfahren zur Herstellung> Fig. 9 is a flowchart illustrating an example of a method for manufacturing the semiconductor device according to embodiment 2. First, the insulating substrate 6 and the base plate 10 are connected (step S1). Next, the semiconductor element 1 is connected to the insulating substrate 6 (step S2). Finally, wiring is carried out using wires 7, 8, and 9 (step S3). Next, terminals 13 and 14 are overmolded in the housing 16 so that surfaces 130 and 140 face each other (step S4). At this point, terminals 13 and 14 are positioned so that the capacitor 15 can be mounted between them. Next, capacitor 15 is connected to terminal 13 and terminal 14, and capacitor 15 is mounted between terminal 13 and terminal 14 (step S5). Next, the housing 16 is attached to the base plate 10 (step S6). Next, the semiconductor element 1 and capacitor 15 are sealed using the sealing material 17 (step S6). The preceding steps result in the fabrication of the semiconductor device 102. Steps S4 and S5 can be performed before steps S1, S2, and S3, or they can be performed in parallel with steps S1, S2, and S3. Furthermore, step S5 can be performed after step S6. <C. Ausführungsform 3> Fig. 6 is a top view of a semiconductor device 103 according to embodiment 3. In the semiconductor device 103, the terminal 13 has a guide 13a which projects from the surface 130 in a direction perpendicular to that surface. In the semiconductor device 103, the terminal 14 has a guide 14a which projects from the surface 140 in a direction perpendicular to that surface. Except for these points, the semiconductor device 103 is similar to the semiconductor device 101 according to embodiment 1. Guide 13a faces capacitor 15 in the direction within the plane of surface 130. Guide 14a faces capacitor 15 in the direction within the plane of surface 140. The guide 13a and the guide 14a are positioned between the capacitor 15 and the insulating substrate 6. In the semiconductor device 103, the terminal 13 is provided with the guide 13a, and the terminal 14 is provided with the guide 14a, thereby forming a pocket in which the capacitor 15 is mounted. In the manufacture of the semiconductor device 103, the position of the capacitor 15 in the direction within the plane of surface 130 or surface 140 is defined by the guide 13a and the guide 14a. This simplifies the positioning of the capacitor 15 when it is mounted at terminal 13 and terminal 14, thereby improving work efficiency. Furthermore, it is not necessary for the capacitor 15 to be supported by a device or the like, which reduces restrictions regarding the location where the capacitor 15 is mounted. While in embodiment 3 a housing was described in which the connection 13 with the guide 13a and the connection 14 with the guide 14a are provided, it can also be applied that either the first connection 13 with the guide 13a or the connection 14 with the guide 14a is provided. In embodiment 3, the capacitor 15 is also mounted between terminal 13 and terminal 14, so that the stress generated in the capacitor 15 due to temperature changes in the semiconductor device is reduced, thereby preventing damage to the capacitor 15 and improving the reliability of the semiconductor device 103. In the semiconductor device 103, the semiconductor element 1 and the capacitor 15 can be sealed by means of a sealing material, and the semiconductor device 103 can have a housing in which the semiconductor element 1 is accommodated. Similar to the semiconductor device 102 according to embodiment 2, the semiconductor device 103 can have the housing 16, which defines the positions of the terminal 13 and the terminal 14. <D. Ausführungsform 4> Fig. 7 is a top view of a semiconductor device 104 according to embodiment 4. Fig. 8 is a cross-sectional view of the semiconductor device 104, which is taken along a line BB in Fig. 7. The difference with respect to the semiconductor device 101 according to embodiment 1 is that in the semiconductor device 104 the capacitor 15 is connected to terminal 13 and terminal 14 via metal terminals 18. In other respects, the semiconductor device 104 is similar to the semiconductor device 101 according to embodiment 1. Two metal terminals 18 are attached to the capacitor 15. The two metal terminals 18 are attached to the capacitor 15, for example, via a connecting material (not illustrated), such as solder. Each of the two metal terminals 18 has a retaining part 18a. For example, as illustrated in Fig. 8, the retaining part 18a has a convex shape towards the side of the capacitor 15. The retaining part 18a of metal terminal 18 is in contact with a surface 131 of terminal 13, which is opposite surface 130, and the retaining part 18a of the other metal terminal 18 is in contact with a surface 141 of terminal 14, which is opposite surface 140. Accordingly, the two metal terminals 18 each incorporate terminal 13 and terminal 14, and the capacitor 15 is electrically connected to terminal 13 and terminal 14. The capacitor 15 and terminal 13, and the capacitor 15 and terminal 14, are each electrically connected via metal terminals 18. The metal terminals 18 may or may not be in contact with surface 130 and surface 140. In the manufacture of the semiconductor device 104, the metal terminals 18 are attached to the capacitor 15, and then the capacitor 15 is mounted between the terminal 13 and the terminal 14 such that the metal terminals 18 insert the terminal 13 and the terminal 14 between them, thereby establishing an electrical connection between the capacitor 15 and the terminal 13 and the terminal 14. The distance between the retaining elements 18a of the two metal terminals 18, which are attached to the capacitor 15 before the capacitor 15 is attached to terminals 13 and 14, is, for example, shorter than the distance between the surface 131 of terminal 13 and the surface 141 of terminal 14, as illustrated by the dashed lines in Fig. 8. When the capacitor 15 is attached to terminals 13 and 14, the electrical connection between the capacitor 15 and terminals 13 and 14 is more securely established by an elastic force exerted by the two retaining elements 18a, which insert terminals 13 and 14 between them. The metal terminals 18, terminal 13, and terminal 14 can be connected via a joining material such as solder. In embodiment 4, the capacitor 15 is also mounted between terminal 13 and terminal 14, so that the load generated in the capacitor 15 is reduced, thereby preventing damage to the capacitor 15 and improving the reliability of the semiconductor device 104. In the semiconductor device 104, the semiconductor element 1 and the capacitor 15 can be sealed by means of a sealing material, and the semiconductor device 104 can have a housing in which the semiconductor element 1 is accommodated. Similar to the semiconductor device 102 according to embodiment 2, the semiconductor device 104 can have the housing 16, which defines the positions of the terminal 13 and the terminal 14. Furthermore, in the semiconductor device 104 according to embodiment 4, the connection 13 can be provided with the guide 13a, and the connection 14 can be provided with the guide 14a. Reference symbol list 1 Semiconductor element, 1a Signal electrode, 1b Power electrode, 2 Solder, 3, 3a, 3b, 3c, 3d Conductor structure, 4 Insulating layer, 5 Conductor structure, 6 Insulating substrate, 7, 8, 9 Wire, 10 Base plate, 12a, 12b, 13, 14 Terminal, 13a, 14a Guide, 15 Capacitor, 16 Housing, 17 Sealing material, 18 Metal terminal, 18a Retaining part, 101, 102, 103, 104 Semiconductor device, 130, 131, 140, 141 Surface, 160 Convex part.

Claims

Semiconductor device (101, 102, 103, 104) comprising: • an insulating substrate (6); • a semiconductor element (1); • a capacitor (15); • a first terminal (13) having a surface (130); and a second terminal (14) which has an area (140), wherein the insulating substrate (6) has an insulating layer (4) and a conductor structure (3) provided on the insulating layer (4), the semiconductor element (1) is connected to the conductor structure (3), the first terminal (13) is electrically connected to the semiconductor element (1), the area (130) of the first terminal (13) and the area (140) of the second terminal (14) face each other, the capacitor (15) is positioned between the area (130) of the first terminal (13) and the area (140) of the second terminal (14), which face each other, and the capacitor (15) is connected to the first terminal (13) and the second terminal (14).• a first metal terminal (18) and a second metal terminal (18) are attached to the capacitor (15), and • the first metal terminal (18) is in contact with a side opposite the surface (130) of the first terminal (13), and the second metal terminal (18) is in contact with a side opposite the surface (140) of the second terminal (14), whereby the first terminal (13) and the second terminal (14) are inserted between the first metal terminal (18) and the second metal terminal (18). Semiconductor device (101) according to claim 1, wherein the surface (130) of the first terminal (13) and the surface (140) of the second terminal (14) are facing each other in one direction within a plane of the insulating substrate (6). Semiconductor device (101) according to claim 1 or 2, wherein the second terminal (14) is electrically connected to the semiconductor element (1). Semiconductor device (101) according to claim 3, wherein: • the semiconductor element (1) is a switching element, • the semiconductor element (1) has a power electrode (1b) and a signal electrode (1a), • the signal electrode (1a) is an electrode for a signal to control the semiconductor element (1) on / off, • the first terminal (13) is electrically connected to the power electrode (1b), and • the second terminal (14) is electrically connected to the signal electrode (1a). Semiconductor device (103) according to one of claims 1 to 4, wherein either one or both of these apply, namely that a guide (13a) is formed at the first terminal (13) which projects out of the surface (130) of the first terminal (13) in a direction perpendicular to the surface (130) and is directed towards the capacitor (15) in the direction within the plane of the surface (130) of the first terminal (13), and that a guide (14a) is formed at the second terminal (14) which projects out of the surface (140) of the second terminal (14) in a direction perpendicular to the surface (140) and is directed towards the capacitor (15) in the direction within the plane of the surface (140) of the second terminal (14). Semiconductor device (101) according to one of claims 1 to 5 further comprising a base plate (10), wherein the insulating substrate (6) is connected to the base plate (10). Semiconductor device (101) according to one of claims 1 to 6, wherein the semiconductor element (1) is a semiconductor element comprising a SiC semiconductor. Semiconductor device (102) according to one of claims 1 to 7 further comprising: a housing (16) which receives the semiconductor element (1) inside it, wherein: the first terminal (13) and the second terminal (14) are cast into the housing (16). Semiconductor device (102) according to one of claims 1 to 7 further comprising: • a housing (16) which receives the semiconductor element (1) inside therein, wherein: • at least one convex part (160) which projects towards the interior of the housing (16) is provided on the inner peripheral surface of the housing (16), • the first terminal (13) is facing one of the at least one convex part (160) on a side which is opposite the surface (130) of the first terminal (13), and • the second terminal (14) is facing one of the at least one convex part (160) on a side which is opposite the surface (140) of the second terminal (14). Semiconductor device (102) according to claim 9, wherein the first terminal (13) and the second terminal (14) are cast into the housing (16). Method for manufacturing the semiconductor device (102) according to any one of claims 1 to 7, wherein the semiconductor device (102) further comprises a housing (16) which receives the semiconductor element (1) inside it, comprising: • overmolding the first terminal (13) and the second terminal (14) in the housing (16) such that the surface (130) of the first terminal (13) and the surface (140) of the second terminal (14) face each other; and • after overmolding, connecting the capacitor (15) to the first terminal (13) and the second terminal (14). Method for manufacturing the semiconductor device (102) according to any one of claims 8 to 10, comprising: • overmolding the first terminal (13) and the second terminal (14) in the housing (16) such that the surface (130) of the first terminal (13) and the surface (140) of the second terminal (14) face each other; and • after overmolding, connecting the capacitor (15) to the first terminal (13) and the second terminal (14).

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