Semiconductor device and method for manufacturing a semiconductor device

Abstract

One objective is to provide a technique suitable for suppressing fracture of an insulating substrate, even if warping occurs in a product after injection molding. A semiconductor device comprises: an insulating substrate having an insulating layer, a front surface structure, and a back surface structure; a semiconductor element mounted on the front surface structure; and a molding resin sealing the insulating substrate and the semiconductor element, with one surface of the back surface structure exposed on one side to a surface facing the insulating layer.The rear surface structure is bonded to a heat sink by a soldering agent; a surface of the rear surface structure bonded to the heat sink is arranged at the same height position as a surface of the molded resin facing the heat sink; a first slot for dividing the front surface structure into a plurality of areas is provided on the front surface structure; a second slot for dividing the rear surface structure into a plurality of areas is provided on the rear surface structure; and the first slot and the second slot do not overlap each other, or only a part of the first slot and a part of the second slot overlap each other in a thickness direction of the insulating substrate.

Description

Technical field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. State of the art

[0002] For example, patent document 1 discloses a semiconductor device comprising a plurality of wiring layers (corresponding to a surface structure), an insulating substrate (corresponding to an insulating layer) to which first back surfaces of the plurality of wiring layers are bonded, a plurality of heat-radiating layers (corresponding to a back surface structure) in which a second main surface is bonded to the insulating substrate, a semiconductor element bonded to one of the first main surfaces of the plurality of wiring layers, and a sealing resin covering the insulating substrate, the plurality of wiring layers, and the semiconductor element.Since the majority of wiring layers bonded to the surface of the insulating substrate and the majority of heat-radiating layers bonded to the rear surface of the insulating substrate are arranged to overlap each other in a thickness direction of the insulating substrate, the difference in the expansion-shrinkage amount between the front surface and the rear surface of the insulating substrate as a result of temperature changes is reduced, and any warping occurring in the insulating substrate is suppressed. State of the art documents Patent document(s)

[0003] Patent document 1: International Publication No. 2020 / 149225 Summary Problem to be solved by the invention

[0004] However, the technique described in patent document 1 does not account for the warping of a product that occurs after injection molding. Specifically, a slot for dividing the substrate into multiple wiring layers on the front surface and a slot for dividing it into multiple heat-radiating layers on the rear surface are located at the same position in the thickness direction of the insulating substrate. This creates the problem that the entire substrate, which contains the multiple wiring layers and the multiple heat-radiating layers, is prone to warping and cracking.

[0005] Accordingly, one objective of the present disclosure is to provide a technique suitable for suppressing a break in an insulating substrate, even if a warp occurs in a product after injection molding. Means to solve the problem

[0006] A semiconductor device according to the present disclosure comprises: an insulating substrate having an insulating layer, a front surface structure formed on a front surface of the insulating layer, and a rear surface structure formed on a rear surface of the insulating layer; a semiconductor element mounted on the front surface structure; and a sealing resin sealing the insulating substrate and the semiconductor element, with one surface of the rear surface structure being exposed on one side to a surface facing the insulating layer, the rear surface structure being bonded to a heat sink by a solder, and a surface of the rear surface structure bonded to the heat sink being at the same height as a surface of the sealing resin.which faces the heat sink, is arranged, a first slot is provided for dividing the front surface structure into a plurality of areas on the front surface structure, a second slot is provided for dividing the rear surface structure into a plurality of areas on the rear surface structure, and the first slot and the second slot do not overlap each other or only a part of the first slot and a part of the second slot overlap each other in a thickness direction of the insulating substrate. Effects of the invention

[0007] According to the present disclosure, a part is wherein the first slot is on one side of the front surface of the insulating substrate and the second slot is on one side of the rear surface thereof in the thickness direction of the insulating substrate.<hier fehlt wohl „überlappen“> , reduced. Thus, a break in the insulating substrate can be suppressed, even if warping of a product occurs after injection molding.

[0008] These and other tasks, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description when it is adopted in conjunction with the accompanying drawings. Brief description of the drawings [ Fig. Figure 1] is a cross-sectional view of a semiconductor device according to one embodiment. [ Fig. 2] is a flowchart that illustrates a method for manufacturing the semiconductor device according to the embodiment. [ Fig. Figure 3] is a cross-sectional view illustrating a die-bonding process according to the embodiment. [ Fig. Figure 4] is a cross-sectional view illustrating a lead bonding process according to the embodiment. [ Fig. Figure 5] is a cross-sectional view illustrating a wire-bonding process according to the embodiment. [ Fig. Figure 6] is a cross-sectional view illustrating a forming process according to the embodiment. [ Fig. Figure 7] is a cross-sectional view showing a solder assembly process according to the embodiment. [ Fig. Figure 8] is a cross-sectional view of a semiconductor device to explain the occurrence of a solder cavity according to the embodiment. [ Fig. Figure 9] is a bottom view showing an example of an insulating substrate included in the semiconductor device according to the embodiment. [ Fig. Figure 10] is a bottom view showing another example of the insulating substrate included in the semiconductor device according to the embodiment. [ Fig. Figure 11] is an enlarged cross-sectional view around a second slot provided on a rear surface structure included in the semiconductor device according to the embodiment. [ Fig.

[12] is an enlarged cross-sectional view around a second slot provided on a rear surface structure included in a semiconductor device according to a modification example of the embodiment. [ Fig. Figure 13] is a cross-sectional view of a semiconductor device to explain the occurrence of a solder cavity according to a related technique. Description of the embodiment(s)<Ausführungsform><Konfiguration einer Halbleitervorrichtung>

[0009] One embodiment is described below using the diagrams. Fig. Figure 1 is a cross-sectional view of a semiconductor device according to the embodiment.

[0010] As in Fig. As shown in Figure 1, the semiconductor device comprises an insulating substrate 1, a plurality of semiconductor elements 2, a plurality of conductor frames 3 and a molded resin 5 as a sealing resin.

[0011] The insulating substrate 1 has an insulating layer 1a, a front surface structure 1b, and a back surface structure 1c. The insulating layer 1a is made of ceramic. The front surface structure 1b is made of metal, such as copper or aluminum, and is formed on a front surface of the insulating layer 1a. A first slot 6 for subdividing the front surface structure 1b into a plurality of areas is provided on the front surface structure 1b. The back surface structure 1c is made of metal, such as copper or aluminum, and is formed on a back surface of the insulating layer 1a. A second slot 7 for subdividing the back surface structure 1c into a plurality of areas is provided on the back surface structure 1c.The second slot 7 is formed in a grid-like shape in one thickness direction of the insulating substrate 1. The second slot 7 is designed such that it surrounds the semiconductor element 2 in the thickness direction of the insulating substrate 1.

[0012] The majority of semiconductor elements 2 are attached to the front surface structure 1b by means of a soldering compound 4. The majority of semiconductor elements 2 are elements that function, for example, as switching elements or rectifier elements. The switching element is, for example, an insulated-gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET). The rectifier element is a diode element.

[0013] A material that forms the majority of semiconductor elements 2 is, for example, silicon (Si). However, the material that forms the majority of semiconductor elements 2 is not limited to silicon; a wide-bandgap semiconductor material is also applicable, such as silicon carbide (SiC), gallium nitride (GaN), or diamond (C). The wide-bandgap semiconductor material is a material that has a wider bandgap than Si. The majority of semiconductor elements 2 made from the wide-bandgap semiconductor material can operate using high currents and in high-temperature environments. Thus, the material forming the majority of semiconductor elements 2 is preferably a wide-bandgap semiconductor material.

[0014] For example, the material of the majority of conductor frames 3 is copper. The majority of conductor frames 3 are bonded to a surface electrode of the semiconductor element 2 by the solder 4, are bonded to the front surface structure 1b by the solder 4, and are connected to a wire contact point of the semiconductor element 2 by means of an aluminum wire 8.

[0015] The molding resin 5, for example, is a thermosetting epoxy system resin. The molding resin 5 seals the insulating substrate 1 and the semiconductor element 2, while exposing one surface of the back surface structure 1c on one side to a surface of the same facing the insulating layer 1a.

[0016] Here, the semiconductor device is bonded to the heat sink 10 (see Fig. 7) However, the surface of the rear surface structure 1c, which is bonded to the heat sink 10, is located at the same height as a surface of the mold resin 5 facing the heat sink 10. Thus, there is no level difference between the rear surface structure 1c and the mold resin 5. <Verfahren einer Fertigung einer Halbleitervorrichtung>

[0017] A method for manufacturing a semiconductor device will next be described using Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 to Fig. 7 described. Fig. Figure 2 is a flowchart illustrating the process of manufacturing the semiconductor device according to the embodiment. Fig. Figure 3 is a cross-sectional view illustrating a die-bonding process according to the embodiment. Fig. Figure 4 is a cross-sectional view illustrating a lead bonding process according to the embodiment. Fig. Figure 5 is a cross-sectional view illustrating a wire bonding process according to the embodiment. Fig. Figure 6 is a cross-sectional view illustrating a forming process according to the embodiment. Fig. Figure 7 is a cross-sectional view depicting a solder assembly process according to the embodiment. Only one main process in the semiconductor device manufacturing procedure is extracted and shown in Figure 7. Fig. 2 simply illustrated.

[0018] First, as in Fig. 2 and Fig. Figure 3 shows that in step S1, the solder 4 is applied to the front surface structure 1b of the insulating substrate 1, the semiconductor element 2 is placed on it, and the solder 4 is melted, for example by remelting, to bond the semiconductor element 2 to the insulating substrate 1. Although this embodiment illustrates bonding by the solder 4 as an example, the configuration is not limited to this. Sintering by silver or copper can be performed.

[0019] Next, as in Fig. 2 and Fig. 4 shown, the solder 4 is arranged on the surface electrode of the semiconductor element 2 and the front surface structure 1b, the conductor frame 3 is placed on it and the solder 4 is melted, for example by remelting, to bond the surface electrode of the semiconductor element 2 and the conductor frame 3 and to bond the front surface structure 1b and the conductor frame 3.

[0020] Next, as in Fig. 2 and Fig. Figure 5 shows that in one step S3 a wire contact point of the semiconductor element 2 and a signal connection of the conductor frame 3 are bonded to the aluminum wire 8, which has a diameter of approximately 100 to 400 µm, by ultrasonic waves.

[0021] Next, as in Fig. 2 and Fig. Figure 6 shows that in step S4, a wire-bonded product and a tablet-shaped resin (the material of the molding resin 5) are inserted into a lower mold of a molding tool (not shown in the diagrams). An upper mold is closed, and the resin is gelled at a high temperature of approximately 180 °C. It is then injected under pressure through a sprue and gate into a cavity within the molding tool. The gelled resin is re-cured at a high temperature and becomes the molding resin 5, which has the same shape as the cavity. This is then removed from the molding tool.

[0022] Next, as in Fig. 2 and Fig. Figure 7 shows that in step S5 a solder 11 and the semiconductor device as the product completed by forming are arranged on the heat sink 10 as a heat radiating element, and the solder 11 is melted, for example by remelting, to bond the semiconductor device and the heat sink 10.

[0023] In the processes described above, the insulating substrate 1 is exposed to high temperatures during the die-bonding process (step S1), the lead-bonding process (step S2), the forming process (step S4), and the soldering assembly process (step S5). The ceramic forming the insulating layer 1a of the insulating substrate 1 is a brittle material and therefore exhibits low tolerance to bending. Consequently, it is important to prevent warping as much as possible in each process.

[0024] However, since conductivity and heat dissipation properties are functionally required in the insulating substrate 1, the front surface structure 1b and the back surface structure 1c are bonded to the front and back surfaces, respectively, and structuring is performed. Because copper has excellent performance properties, it is generally used for the front surface structure 1b and the back surface structure 1c. Since copper is a material with high strength, and there is a difference in the coefficient of linear expansion between copper and ceramic, warping occurs according to temperature changes if the balance between the front and back surfaces of the insulating layer 1a is uneven.The front surface structure 1b is generally subdivided into multiple areas by the first slot 6 and exhibits lower strength than the front surface structure 1b without subdivision. The second slot 7 is provided on the rear surface structure 1c to reduce strength in order to achieve a balance with the front surface structure 1b, which exhibits decreasing strength.

[0025] Since the rear surface structure 1c serves as a heat dissipation path, transferring heat generated by the semiconductor element 2 to the heat sink 10, the second slot 7 is not located directly beneath the semiconductor element 2, but rather around the area immediately below it. That is, the second slot 7 is positioned such that it surrounds a position of the front surface structure 1b corresponding to the location of the semiconductor element 2.

[0026] Next, a solder cavity 12 is described that occurs in the solder 11. Fig. Figure 13 is a cross-sectional view of a semiconductor device to explain the occurrence of the solder cavity 12 according to a related technique. Fig. Figure 8 is a cross-sectional view of a semiconductor device to explain the occurrence of the solder cavity 12 according to the embodiment.

[0027] If, during solder bonding of the semiconductor device to the heat sink 10, air is drawn into the solder 11 and remains in the solder 11, the air causes the solder cavity 12 to block heat radiation, as in Fig. Figure 13 illustrates this. The solder cavity 12 appears more readily when an area of ​​a bonding element bonded to the heat sink 10 becomes smaller, but hardly appears from a bonding material that has a large area, such as the insulating substrate 1. However, heat radiation occurs mainly directly beneath the semiconductor element 2 in the insulating substrate 1, which has the large area. Thus, as shown in Fig. Figure 8 shows that if the solder cavity 12 can be diverted to the second slot 7 provided on the rear surface structure 1c, the influence on the heat dissipation properties is reduced, and a semiconductor device with high heat dissipation properties can be achieved. Since the position of the solder cavity 12 is not specified, the effect of diverting the solder cavity 12 from directly below the semiconductor element 2 is further improved by creating a reduced-pressure atmosphere and shaking the semiconductor device.

[0028] It is necessary to ensure that the second slot 7 is not filled with the molding resin 5 in order to divert the solder cavity 12 to the second slot 7, as described above. When the wire-bonded product is inserted into the lower mold of the mold tool, its positioning must be carried out by the conductor frame 3. This is because the processing is carried out in such a way as to prevent a gap between the conductor frame 3 and the mold tool, so that no resin leaks out when the upper and lower molds are closed and the resin is injected into the cavity. However, a slight misalignment occurs due to the accuracy of a holding device used to bond the conductor frame 3 and the insulating substrate 1 with the solder 4 and the resulting gap.Thus, it is possible to design the insulating substrate 1 so that it is in contact only with one surface of the lower shape, but it is difficult to fit the rear surface structure 1c without a gap around the rear surface structure 1c.

[0029] Thus, if the rear surface structure 1c is not completely subdivided as in the front surface structure 1b, but only an outermost periphery of it is connected, flow of the molding resin 5 into the second slot 7 can be suppressed. It is preferred that a width of part of the connected outermost periphery of the rear surface structure 1c is approximately 1 mm or more, although this depends on the pressure during resin injection and the flatness of the insulating substrate 1.

[0030] Fig. Figure 9 is a bottom view showing an example of the insulating substrate 1 included in the semiconductor device according to the embodiment. Fig. Figure 10 is a bottom view showing another example of the insulating substrate 1 contained in the semiconductor device according to the embodiment. As in Fig. As shown in Figure 9, if the outermost periphery of the back surface structure 1c is not connected, resin flow from the outermost periphery of the back surface structure 1c must be suppressed by pressing a layer, which, for example, has damping properties, against the back surface structure 1c during injection molding. However, it is more difficult to suppress this flow as the thickness of the back surface structure 1c increases. As shown in Fig. As shown in Figure 10, since the back surface structure 1c is connected in the outermost periphery of the back surface structure 1c, the layer which, for example, has the damping properties is unnecessary, and the flow of the resin can be suppressed without limiting the thickness of the back surface structure 1c.

[0031] The suppression of warping of the individual insulating substrate 1 is as described above. It is also important to suppress fracture of the insulating substrate 1 even in cases where warping of the product occurs after injection molding. This warping is caused by a difference in expansion and contraction between the molding resin 5 and the insulating substrate 1. Accordingly, it is important to keep the linear coefficients of expansion of the molding resin 5 and the insulating substrate 1 as close to each other as possible.

[0032] A key component for determining mechanical properties, such as the linear expansion coefficient of the molding resin 5, is the resin and a filler. The linear expansion coefficient can be reduced by increasing the proportion of filler. However, if the filler proportion is too high, the resin's flowability during injection molding will deteriorate. Therefore, the filler proportion is adjusted so that the linear expansion coefficient realistically ranges from 100 ppm / °C to 20 ppm / °C.

[0033] Meanwhile, if the insulating substrate 1 is a composite body of ceramic (the insulating layer 1a) and copper structures on its front and back surfaces (the front surface structure 1b and the back surface structure 1c), the coefficient of linear expansion can be adjusted by changing its thickness. Silicon nitride, for example, is mainly used for ceramics; its coefficient of linear expansion is 3.5 ppm / °C, and the coefficient of linear expansion of the copper structure is 16.7 ppm / °C. The coefficient of linear expansion of the composite body will take on a value between these two values, and the value closer to each is determined by the strength contribution of each material. The strength contribution can be approximated by the product of each material's volume and its elasticity coefficient.

[0034] The molding resin 5 has a linear coefficient of thermal expansion of 10 ppm / °C, which is a value between the linear coefficients of thermal expansion of silicon nitride and copper, and it is sufficient that each strength is equivalent to the other. The elastic coefficient of silicon nitride is 300 GPa and the elastic coefficient of copper is 117 GPa. If the thickness of silicon nitride is t1, the thickness of copper is t2, and the area fraction of copper is approximately 90%, although this varies depending on a design specification, then 300 × t1 × 1 = 117 × t2 × 0.9 and t2 = 300 / (117 × 0.9) × t1 ≈ 2.85 × t1 are determined.

[0035] This means that if the total thickness of the copper structures on the front and back surfaces is 2.8 times that of the ceramic, and the copper structures on the front and back surfaces have the same thickness (1.4 times that of the ceramic), the coefficient of linear expansion is approximately 10 ppm / °C. If the thickness of the copper structure is further increased, the coefficient of linear expansion can be greater than 10 ppm / °C. Theoretically, the coefficient of linear expansion can be brought infinitely close to that of copper by designing the component with a high copper content. However, considering manufacturing limitations of the insulating substrate 1 and size limitations of the semiconductor device, the upper limit for the thickness of the copper structures on the front and back surfaces is approximately 3 to 3.5 times that of the ceramic.

[0036] Warping of the individual insulating substrate 1 and warping of the product after injection molding cannot be prevented. Accordingly, it is also important to make the insulating layer 1a, which consists of ceramic as a brittle material, resistant to breakage.

[0037] If the slot is not provided on the front surface structure 1b and the back surface structure 1c, the front surface structure 1b and the back surface structure 1c protect the insulating layer 1a and exhibit resistance to bending. However, if the slot is provided, bending occurs in a part having the first slot 6 (or the second slot 7), and fracture occurs easily because there is a large difference in strength between a part having the front surface structure 1b (or the back surface structure 1c) and the part having the first slot 6 (or the second slot 7). Fracture occurs more easily if the first slot 6 and the second slot 7 overlap each other in the thickness direction of the insulating substrate 1.

[0038] To solve such a problem, the first slot 6 and the second slot 7 do not overlap, or only a portion of the first slot 6 and a portion of the second slot 7 overlap in the thickness direction of the insulating substrate 1 in the embodiment. The case in which only a portion of the first slot 6 and a portion of the second slot 7 overlap is described below. Both the first slot 6 and the second slot 7 have at least one straight portion.If a portion of the first slot 6 and a portion of the second slot 7 overlap each other in the thickness direction of the insulating substrate 1, then the length of a portion in which a predetermined straight portion of the first slot 6 and a predetermined straight portion of the second slot 7 overlap each other is 50% or less of the total length of the predetermined straight portion of the first slot 6 and the length of the predetermined straight portion of the second slot 7. Fig. 9 and Fig. 10 the second slot 7 is formed into a grid-like shape and has a plurality of straight parts.

[0039] In this way, since the part where the first slot 6 and the second slot 7 overlap is reduced, the structure can be achieved which suppresses a break in the insulating substrate 1, even if a warping of a product occurs after injection molding. <wirkung>

[0040] As described above, the semiconductor device according to the embodiment comprises: the insulating substrate 1, which has the insulating layer 1a, the front surface structure 1b formed on the front surface of the insulating layer 1a, and the back surface structure 1c formed on the back surface of the insulating layer 1a; the semiconductor element 2, which is mounted on the front surface structure 1b; and the molding resin 5, which seals the insulating substrate 1 and the semiconductor element 2, while the surface of the back surface structure 1c is exposed on the side opposite the surface facing the insulating layer 1a.The rear surface structure 1c is bonded to the heat sink 10 by the solder 11; the surface of the rear surface structure 1c bonded to the heat sink 10 is located at the same height as the surface of the molding resin 5 facing the heat sink 10; the first slot 6 for dividing the front surface structure 1b into multiple areas is provided on the front surface structure 1b; the second slot 7 for dividing the rear surface structure 1c into multiple areas is provided on the rear surface structure 1c; and the first slot 6 and the second slot 7 do not overlap each other, or only a part of the first slot 6 and a part of the second slot 7 overlap each other in the thickness direction of the insulating substrate 1.

[0041] In particular, both the first slot 6 and the second slot 7 have at least one straight portion. The length of a portion in which the predetermined straight portion of the first slot 6 and the predetermined straight portion of the second slot 7 overlap is 50% or less of the total length of the predetermined straight portion of the first slot 6 and the length of the predetermined straight portion of the second slot 7 in the thickness direction of the insulating substrate 1.

[0042] Accordingly, the area where the first slot 6 on the front surface of the insulating substrate 1 and the second slot 7 on the rear surface overlap is reduced. This prevents breakage of the insulating substrate 1, even if warping of the product occurs after injection molding. With this configuration, the semiconductor device can be used for a long time.

[0043] Since the resin 5 does not fill the second slot 7, the solder cavity 12 remaining in the solder 4 can be diverted to the second slot 7 during solder bonding. Accordingly, the heat generated by the semiconductor element 2 can be efficiently radiated away.

[0044] Since the rear surface structure 1c is connected in the outermost periphery of the rear surface structure 1c, the flow of the molding resin 5 into the second slot 7 can be suppressed at the time of injection molding.

[0045] Since the second slot 7 surrounds the position of the front surface structure 1b, which corresponds to the position where the semiconductor element 2 is attached, the solder cavity 12 hardly occurs directly beneath the semiconductor element 2. Accordingly, the heat dissipation properties of the semiconductor device are improved.

[0046] The thickness of both the front surface structure 1b and the back surface structure 1c is 1.4 times or more the thickness of the insulating layer 1a. Accordingly, the effect of suppressing the warping of the insulating substrate 1 is increased, and furthermore, the effect of suppressing the warping of the product after injection molding is also increased.

[0047] Semiconductor element 2 is a wide-bandgap semiconductor element and can therefore be operated at a higher temperature compared to a silicon semiconductor element. However, the heat dissipation of the semiconductor device can be increased, as described above, thus preventing an increase in the temperature of semiconductor element 2. Consequently, a loss of semiconductor element 2 can be prevented.

[0048] Although the SiC MOSFET can be operated at high temperatures, performance deteriorates significantly at high temperatures. Therefore, the SiC MOSFET is preferably used at as low a temperature as possible. The heat generated by the semiconductor element 2 is efficiently transferred to the heat sink 10, and the temperature increase of the semiconductor element 2 can be suppressed. Thus, the configuration of the semiconductor device according to this embodiment is particularly suitable for the SiC MOSFET. <Modifikationsbeispiel der Ausführungsform>

[0049] A modification example of the embodiment is described next. Fig. Figure 11 is an enlarged cross-sectional view around the second slot 7 provided on the rear surface structure 1c included in the semiconductor device according to the embodiment. Fig. Figure 12 is an enlarged cross-sectional view around the second slot 7 provided on the rear surface structure 1c included in the semiconductor device according to the modification example of the embodiment.

[0050] In some cases, a high voltage can be applied to the sides of the front and rear surfaces of the insulating substrate 1 in the semiconductor device. For example, a voltage of approximately 400 V to 1000 V is applied in an electric vehicle. As in Fig. 11 shows, in a case where the second slot 7 passes through the rear surface structure 1c and is designed to reach the rear surface of the insulating layer 1a when the solder cavity 12 (see Fig. 8) is arranged in the second slot 7, the solder cavity 12 makes contact with the insulating layer 1a, and there is a possibility that a partial electrical discharge 13 from the insulating layer 1a will occur.

[0051] To avoid this problem, the procedure is as follows: Fig. As shown in Figure 12, the second slot 7 in the modified embodiment does not extend through the rear surface structure 1c and is not designed to reach the rear surface of the insulating layer 1a. That is, the rear surface structure 1c is firmly attached to the rear surface of the insulating layer 1a, even at the position where the second slot 7 is provided.

[0052] A method for manufacturing the insulating substrate 1 is described next. There is a method for applying the back surface structure 1c, in which the second slot 7 is formed by stamping in a press operation, for example on the insulating layer 1a, and a method for forming the second slot 7 by melting copper and performing a structuring by etching after the back surface structure 1c, in which the second slot 7 is not formed, has been applied, and the latter manufacturing method is generally used in many cases.

[0053] A portion of the back surface structure 1c, where the second slot 7 is not formed, is masked, and an etching solution is sprayed only onto that portion, where the second slot 7 is formed, to melt that portion and create the pattern. Although the insulating layer 1a is normally exposed in an etched area, the second slot 7 is formed by a partial stop etch in the center of the insulating substrate 1 in the thickness direction during etching on the back surface structure 1c. Thus, the insulating layer 1a is not exposed to the etched area. As a result, since the solder cavity 12 is not in contact with the insulating layer 1a, the occurrence of partial electrical discharge 13 can be suppressed.

[0054] Although the present revelation is described in detail above, the foregoing description is descriptive in all aspects and does not limit the revelation. It is therefore understood that numerous examples of modification, not presented here as examples, can be developed.

[0055] Each embodiment can be combined in any way desired, or each embodiment can be suitably varied or omitted. Explanation of reference symbols

[0056] 1 insulating substrate, 1a insulating layer, 1b front surface structure, 1c back surface structure, 2 semiconductor element, 5 molded resin, 6 first slot, 7 second slot, 10 heat sink, 11 solder.< / wirkung>

Claims

Semiconductor device comprising: an insulating substrate having an insulating layer, a front surface structure formed on a front surface of the insulating layer, and a rear surface structure formed on a rear surface of the insulating layer; a semiconductor element mounted on the front surface structure; and a sealing resin sealing the insulating substrate and the semiconductor element, with one surface of the rear surface structure exposed on one side to a surface facing the insulating layer, wherein the rear surface structure is bonded to a heat sink by a solder, and a surface of the rear surface structure bonded to the heat sink is arranged at the same height as a surface of the sealing resin facing the heat sink.a first slot is provided for dividing the front surface structure into a plurality of areas on the front surface structure, a second slot is provided for dividing the rear surface structure into a plurality of areas on the rear surface structure, and the first slot and the second slot do not overlap each other, or only part of the first slot and part of the second slot overlap each other in a thickness direction of the insulating substrate. Semiconductor device according to claim 1, wherein the sealing resin does not fill the second slot. Semiconductor device according to claim 1 or 2, wherein the rear surface structure is connected in an outermost periphery of the rear surface structure. Semiconductor device according to one of claims 1 to 3, wherein the second slot surrounds a position of the front surface structure corresponding to a position where the semiconductor element is located. Semiconductor device according to one of claims 1 to 4, wherein both the first slot and the second slot have at least one straight part, and a length of a part in which the straight part defined by the at least one straight part of the first slot and the straight part defined by the at least one straight part of the second slot overlap each other, is 50% or less of the total length of the straight part defined by the first slot and the length of the straight part defined by the second slot in the thickness direction of the insulating substrate. Semiconductor device according to any one of claims 1 to 5, wherein the thickness of both the front surface structure and the rear surface structure is 1.4 times or more the thickness of the insulating layer. Semiconductor device according to any one of claims 1 to 6, wherein the second slot does not pass through the rear surface structure and is not designed to reach the rear surface of the insulating layer. Semiconductor device according to any one of claims 1 to 7, wherein the semiconductor element is a wide bandgap semiconductor. Method of manufacturing the semiconductor device according to claim 7, wherein the second slot is formed by a half-etching of a stop etching in a center of the insulating substrate in the thickness direction during etching on the back surface structure.

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