Display substrate and display device

Abstract

A display substrate and a display device are disclosed, wherein the display substrate has a display area (100) and a non-display area (200) which is provided on and surrounds at least one side of the display area (100), wherein the display area (100) is provided with pixel driver circuits (PE) arranged in an array, and the non-display area (200) is provided with a gate driver circuit and a gating signal line group (DL), wherein the gating signal line group (DL) comprises: a plurality of gating signal lines, wherein the gate driver circuit is electrically connected to each of the pixel driver circuits (PE) and the gating signal line group (DL);a gating signal line extends along a first direction (D1), the plurality of gating signal lines are arranged along a second direction (D2), the gate driver circuit comprises a plurality of shift registers, a shift register comprises a gating sub-circuit (10) that is electrically connected to a portion of the gating signal lines in the gating signal line group (DL), and the gating sub-circuit (10) comprises a plurality of gating transistors, wherein for each shift register the plurality of gating transistors in the gating sub-circuit (10) are arranged along the first direction (D1).

Description

AREA OF TECHNOLOGY

[0001] The present disclosure relates to, but is not limited to, the field of display technologies, and in particular to a display substrate and a display device. BACKGROUND

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices and offer advantages such as self-illumination, wide viewing angles, high contrast ratios, low power consumption, very fast response times, lightness and thinness, flexibility, and low cost. With the continuous development of display technologies, flexible displays, which use an OLED or QLED as the light-emitting device and employ a thin-film transistor (TFT) for signal control, have become mainstream products in the display field. SUMMARY

[0003] The following is a detailed summary of the subject matter described in the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0004] In a first aspect, the present disclosure provides a display substrate having a display area and a non-display area provided on and surrounding at least one side of the display area, wherein the display area is provided with pixel driver circuits arranged in an array, and the non-display area is provided with a gate driver circuit and a gating signal line group, wherein the gating signal line group comprises a plurality of gating signal lines, and the gate driver circuit is electrically connected to both the pixel driver circuit and the gating signal line group; A gating signal line extends along a first direction, the multitude of gating signal lines are arranged along a second direction, and the first direction and the second direction intersect; The gate driver circuit comprises a plurality of shift registers, a shift register comprises: a gating sub-circuit, wherein the gating sub-circuit is electrically connected to a part of the gating signal lines in the gating signal line group, the gating sub-circuit comprises a plurality of gating transistors, for each shift register the plurality of gating transistors in the gating sub-circuit are arranged along the first direction.

[0005] In an exemplary implementation, the shift register comprises M gating signal terminals, and the gating signal line group comprises 2M gating signal lines; An m-th gating signal terminal is electrically connected to a (2m-1)-th gating signal line or a 2m-th gating signal line, and a signal of the (2m-1)-th gating signal line and a signal of the 2m-th gating signal line are mutually inverted signals, 1≤m≤M.

[0006] In an exemplary implementation, the non-display area has a signal line area and a component area; the gate driver circuit is located at least partially in the component area; the signal line area comprises a first signal line area, a second signal line area, and a third signal line area arranged sequentially along a direction close to the display area; and the component area comprises a first component area, a second component area, a third component area, and a fourth component area arranged sequentially along a direction close to the display area. The first signal line area is located on a side of the first component area far from the display area, and the third signal line area is located on a side of the fourth component area close to the display area; The gating signal line group is located in the first signal line area, and the gating sub-circuit is located in the first component area.

[0007] In an exemplary implementation, the second signal line area is located between the first signal line area and the first component area, or between the first component area and the second component area.

[0008] In an exemplary implementation, the length of the first signal line segment along the second direction is greater than the length of the second signal line segment along the second direction, and the length of the third signal line segment along the second direction is greater than the length of the second signal line segment along the second direction.

[0009] In an exemplary implementation, the non-display area is further equipped with a clock signal line group, and the gate driver circuit is electrically connected to the clock signal line group; The clock signal line group is located in the first signal line area and is arranged on a side of the gating signal line group furthest from the display area.

[0010] In an exemplary implementation, the clock signal line group comprises a control clock signal line group and an output clock signal line group; The control clock signal line group comprises a plurality of control clock signal lines, one control clock signal line extends along the first direction, the plurality of control clock signal lines are arranged along the second direction; the output clock signal line group comprises a plurality of output clock signal lines, one output clock signal line extends along the first direction, the plurality of output clock signal lines are arranged along the second direction, the line width of the output clock signal line is greater than the line width of the control clock signal line and the line width of the gating signal line; The shift register comprises a plurality of control clock terminals and a plurality of output clock terminals; each of the plurality of control clock terminals is electrically connected to one of the control clock signal lines in the control clock signal line group, and each of the plurality of output clock terminals is electrically connected to one of the output clock signal lines in the output clock signal line group; For each shift register, the multitude of control clock terminals are electrically connected to a portion of the signal lines in the control clock signal group, and the multitude of output clock terminals are electrically connected to a portion of the signal lines in the output clock signal line group; The output clock signal line group is located on one side of the control clock signal line group that is away from the display area.

[0011] In an exemplary implementation, the non-display area is further equipped with a first high-level power supply line and a second high-level power supply line; The shift register comprises: a first high-level power supply connection and a second high-level power supply connection; for each shift register, the first high-level power supply connection is electrically connected to the first high-level power supply line, and the second high-level power supply connection is electrically connected to the second high-level power supply line; The first high-level power supply line and the second high-level power supply line are located in the second signal line area; The line width of any one of the first high-level power supply lines and the second high-level power supply line is greater than the line width of any one of the signal lines located in the first signal line area.

[0012] In an exemplary implementation, the non-display area is further equipped with a first low-level power supply line and a second low-level power supply line; The shift register comprises: a first low-level power supply connection and a second low-level power supply connection; for each shift register, the first low-level power supply connection is electrically connected to the first low-level power supply line, and the second low-level power supply connection is electrically connected to the second low-level power supply line; The first low-level power supply line and the second low-level power supply line are located in the third signal line area, and the first low-level power supply line is located on one side of the second low-level power supply line that is away from the display area; A line width of any one of the first low-level power supply lines or the second low-level power supply line is greater than a line width of any one of the signal lines located in the first signal line area, and a line width of the first low-level power supply line is less than a line width of the second low-level power supply line.

[0013] In an exemplary implementation, the length of the second component area along the second direction is greater than the length of the first component area along the second direction, the length of the third component area along the second direction is greater than the length of the second component area along the second direction, and the length of the fourth component area along the second direction is greater than the length of the third component area along the second direction.

[0014] In an exemplary implementation, the shift register further comprises an input sub-circuit, a node setting sub-circuit, and a preprocessing sub-circuit; the plurality of control clock connections include: a first control clock connection to a third control clock connection; The node setting sub-circuit is electrically connected to at least a second high-level power supply terminal, a second low-level power supply terminal, a second control clock terminal, a third control clock terminal, a first node, and a third node, and is configured to provide a signal from the second high-level power supply terminal or the second low-level power supply terminal to the first node while controlling signals from the second control clock terminal, the third control clock terminal, and the third node; The input sub-circuit is electrically connected at least to the third control clock terminal, the third node and a fifth node and is configured to provide a signal from the third control clock terminal to the fifth node under control of signals from the third node and the third control clock terminal; The preprocessing sub-circuit is connected to at least a second node, a third node, a fourth node, a first high-level power supply terminal, and the first control clock terminal, and is configured to provide a signal from the first control clock terminal or the first high-level power supply terminal to the third node and the fourth node, controlling signals from the second node and the first control clock terminal; The gating sub-circuit is furthermore electrically connected to the second control clock terminal and the second node and configured to provide a signal from the second control clock terminal to the second node while controlling signals from a plurality of gating signal terminals; and The input sub-circuit, the node setting sub-circuit and the preprocessing sub-circuit are located in the second component area and are arranged along the first direction, and the preprocessing sub-circuit is located between the input sub-circuit and the node setting sub-circuit.

[0015] In an exemplary implementation, the preprocessing sub-circuit comprises a multitude of preprocessing transistors and a preprocessing capacitor; The preprocessing capacitor is located on one side of the multitude of preprocessing transistors near the node setting sub-circuit.

[0016] In an exemplary implementation, the shift register also includes a node separation sub-circuit; The node separation sub-circuit is electrically connected to a third control clock connection, a first high-level power supply connection, a second low-level power supply connection, a first node, a fifth node, a sixth node, a seventh node, an eighth node, and a ninth node, and is configured to provide a signal from the fifth node to each of the sixth through ninth nodes under control of signals from the third control clock connection and the first node, or to provide a signal from the first high-level power supply connection to the fifth node under control of a signal from the sixth node. The node separation sub-circuit is located in the third component area.

[0017] In an exemplary implementation, the shift register also includes an output sub-circuit; The output sub-circuit is electrically connected to at least a plurality of output clock terminals, a first low-level power supply terminal, and a plurality of signal output terminals, and is configured to output a signal from a corresponding output clock terminal or the first low-level power supply terminal to the plurality of signal output terminals; and The output sub-circuit is located in the fourth component area.

[0018] In an exemplary implementation, the output sub-circuit further comprises a plurality of output capacitors arranged in an array along the first direction and the second direction.

[0019] In an exemplary implementation, the shift register further comprises a reset sub-circuit and a noise reduction sub-circuit, and the plurality of control clock connections include: a first control clock connection to a third control clock connection; The reset sub-circuit is electrically connected to at least one global reset signal terminal, one third node, one fourth node, one first high-level power supply terminal, and one second low-level power supply terminal, and is configured to provide an electrical connection from the second low-level power supply terminal to the third node, the fourth node, and the first high-level power supply terminal under control of a signal from the global reset signal terminal; The noise reduction sub-circuit is electrically connected to at least one first node, one second node, one ninth node, one first control clock terminal, one second control clock terminal, and one second low-level power supply terminal, and is configured to provide a signal from the second control clock terminal to the second node by controlling a signal from the first control clock terminal, and to provide a signal from the second low-level power supply terminal to the first node by controlling a signal from the ninth node; and The reset sub-circuit and the noise reduction sub-circuit are located in the second component area, and the reset sub-circuit and the preprocessing sub-circuit are arranged along the second direction.

[0020] In one exemplary implementation, the non-display area is further equipped with a reset signal line; A global reset signal terminal of the shift register is electrically connected to the reset signal line, and the reset signal line is located in the first signal line area.

[0021] In an exemplary implementation, the gate driver circuit comprises: a plurality of shift register groups, wherein a shift register group comprises N1 shift register units, and a shift register unit comprises N2 shift registers, N1, N2≥2;

[0022] A portion of the gating signal lines connected to a plurality of gating signal terminals of a shift register are called gating signal line units; gating signal lines contained in gating signal line units connected to any two shift registers located in the same shift register unit are identical, and at least one of the gating signal lines contained in gating signal line units connected to any two shift register units located in the same shift register group is different; and gating signal lines contained in gating signal line units connected to n1th shift register units located in different shift register groups are identical, 1 ≤ n1 ≤ n1.

[0023] In an exemplary implementation, a portion of the control clock signal lines connected to a plurality of control clock terminals of a shift register are referred to as control clock signal line units, and a portion of the output clock signal lines connected to a plurality of output clock terminals of a shift register are referred to as output clock signal line units; at least one of the control clock signal lines contained in control clock signal line units connected to any two shift registers located in the same shift register unit is different, and at least one of the output clock signal lines contained in output clock signal line units connected to any two shift registers located in the same shift register unit is different; control clock signal lines contained in control clock signal line units connected to n²-th shift registers located in different shift register units are the same, and output clock signal lines contained in output clock signal line units connected to n²-th shift registers located in different shift register units are the same, 1≤n²≤N².

[0024] In an exemplary implementation, comprising: a base substrate and a driver structure layer arranged on the base substrate, wherein the shift register comprises a plurality of transistors; The driver structure layer comprises a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer and a second conductive layer stacked on the base substrate; The semiconductor layer comprises at least: active patterns of a multitude of transistors in the shift register; and The second conductive layer comprises at least: gate electrodes, first electrodes and second electrodes of the plurality of transistors in the shift register.

[0025] In an exemplary implementation, further comprising: a gating signal line, a control clock signal line, an output clock signal line, a first high-level power supply line, a second high-level power supply line, a first low-level power supply line, and a second low-level power supply line, wherein each signal line of the gating signal line, the control clock signal line, the output clock signal line, the first high-level power supply line, the second high-level power supply line, the first low-level power supply line, and the second low-level power supply line has a single-layer structure and is located in the first conductive layer, or has a double-layer structure and is located in the first conductive layer and the second conductive layer.

[0026] In an exemplary implementation, the non-display area is further provided with a first interconnect and a second interconnect, and the first interconnect and the second interconnect are located in the first conductive layer; The first electrodes of all gating transistors located in the same gating sub-circuit are electrically connected to the first connecting line, and the second electrodes of a plurality of gating transistors located in the same gating sub-circuit are electrically connected to the second connecting line; and Each electrode of a gate electrode, a first electrode and a second electrode in each gating transistor extends at least partially along the second direction, and the first connecting line and the second connecting line extend along the first direction.

[0027] In an exemplary implementation, the non-display area is further provided with a multitude of control clock interconnect lines and a multitude of control clock electrostatic enable circuits; the multitude of control clock interconnect lines correspond one-to-one with a multitude of control clock signal lines, and the multitude of control clock interconnect lines correspond one-to-one with the multitude of control clock electrostatic enable circuits; Each control clock connection line is electrically connected to a corresponding control clock signal line and a corresponding control clock electrostatic release circuit.

[0028] In an exemplary implementation, the control clock link line comprises a first control clock link section extending along the second direction and a second control clock link section extending along the first direction; For each control clock connection line, the first control clock connection part is electrically connected to a corresponding control clock signal line and the second control clock connection part, and the second control clock connection part is electrically connected to a corresponding control clock electrostatic release circuit; and The first control clock connection part is located in the second conductive layer, and the second control clock connection part is located in the first conductive layer.

[0029] In an exemplary implementation, the non-display area is further provided with a plurality of output clock interconnect lines and a plurality of output clock electrostatic release circuits; the plurality of output clock interconnect lines correspond one-to-one with a plurality of output clock signal lines, and the plurality of output clock interconnect lines correspond one-to-one with the plurality of output clock electrostatic release circuits; Each output clock connection line is electrically connected to a corresponding output clock signal line and a corresponding output clock electrostatic release circuit.

[0030] In an exemplary implementation, the output clock link line comprises a first output clock link segment extending along the second direction and a second output clock link segment extending along the first direction; For each output clock connection line, the first output clock connection part is electrically connected to a corresponding output clock signal line and the second output clock connection part, and the second output clock connection part is electrically connected to a corresponding output clock electrostatic release circuit; and The first output clock connection part is located in the second conductive layer, and the second output clock connection part is located in the first conductive layer.

[0031] In an exemplary implementation, the non-display area is further equipped with four power supply connection lines and four power supply electrostatic release circuits. A first power supply connection line is electrically connected to a first high-level power supply line and a first power supply electrostatic release circuit; A second power supply connection line is electrically connected to a second high-level power supply line and a second power supply electrostatic release circuit; A third power supply connection line is electrically connected to a first low-level power supply line and a third power supply electrostatic release circuit; and A fourth power supply connection line is electrically connected to a second low-level power supply line and a fourth power supply electrostatic release circuit.

[0032] In an exemplary implementation, a power supply interconnection line comprises a first power supply interconnection part extending along the second direction and a second power supply interconnection part extending along the first direction; In each power supply connection line, the first power supply connection part is electrically connected to a connected power supply line and to the second power supply connection part, and the second power supply connection part is electrically connected to a connected power supply electrostatic release circuit; and The first power supply connection part is located in the second conductive layer, and the second power supply connection part is located in the first conductive layer.

[0033] In an exemplary implementation, the distance between the edge of a first signal line located away from the display area and the edge of a second signal line located near the display area is approximately 3400 micrometers to 3450 micrometers; The first signal line is a signal line in a first signal line area that is furthest from a boundary of the display area, and the second signal line is a signal line in a third signal line area that is closest to the boundary of the display area.

[0034] In an exemplary implementation, the signals from at least two gating signal lines are mutually inverted signals for part of a time period.

[0035] In a second aspect, the present disclosure further provides a display device comprising the display substrate described above.

[0036] Other aspects of this revelation can be understood after the drawings and detailed descriptions have been read and understood. BRIEF DESCRIPTION OF THE FIGURES

[0037] The accompanying drawings serve to illustrate the technical solution of this disclosure and form part of the description. The attached drawings and embodiments of this disclosure are used to explain the technical solution of this disclosure and do not represent limitations of the technical solution of this disclosure. Fig. Figure 1 is a schematic diagram of the structure of a display device. Fig. Figure 2 is a first schematic diagram of a planar structure of a display substrate. Fig. Figure 3 is a second schematic diagram of a planar structure of a display substrate. Fig. Figure 4 is a third schematic diagram of a planar structure of a display substrate. Fig. 5A is an equivalent circuit diagram of a pixel driver circuit. Fig. 5B is a time sequence diagram of a pixel driver circuit. Fig. Figure 6 is an equivalent circuit diagram of a shift register. Fig. 7 is a working time sequence diagram of the shift register from Fig. 6. Fig. Figure 8 is a first schematic structure diagram of a display substrate according to an embodiment of the present disclosure. Fig. Figure 9 is a second schematic structure diagram of a display substrate according to an embodiment of the present disclosure. Fig. Figure 10 is a top view of a gating sub-circuit. Fig. Figure 11 is a schematic diagram of a connection of a multitude of shift registers. Fig. Figure 12 is a schematic diagram of a connection of a multitude of shift register groups. Fig. Figure 13 is a schematic cross-sectional diagram of a display substrate. Fig. Figure 14 is a schematic partial view of a non-display area of ​​a display substrate. Fig. Figure 15 is a schematic diagram of a pattern of a first conductive layer in Fig. 10. Fig. Figure 16 is a schematic view of a pattern of a semiconductor layer in Fig. 10. Fig. Figure 17 is a schematic representation, based on a pattern of a semiconductor in Fig. 10 was formed. Fig. 18 is a schematic diagram, based on a pattern of a second insulating layer in Fig. 10 was formed. Fig. Figure 19 is a schematic diagram of a pattern of a second conductive layer in Fig. 10. Fig. Figure 20 is a schematic diagram, based on a pattern of a second conductive layer in Fig. 10 has been formed. DETAILED DESCRIPTION OF THE REVELATION

[0038] To clarify the objectives, technical solutions, and advantages of this disclosure, the embodiments of this disclosure are described in detail below with reference to the accompanying drawings. It should be noted that the implementation modes can be implemented in many different forms. Those with ordinary technical knowledge can easily understand that the implementation modes and content can be transformed into various forms without deviating from the purpose and scope of this disclosure. Therefore, this disclosure should not be understood as being limited only to the content recorded in the following implementation modes. The embodiments and features in the embodiments of this disclosure can be combined arbitrarily, provided there is no conflict.To keep the following description of the embodiments of this disclosure clear and concise, a detailed description of some of the known functions and components is omitted. The drawings in the embodiments of this disclosure relate only to the structures involved in the embodiments of this disclosure, and other structures can be described with reference to conventional designs.

[0039] The scales of the drawings in this disclosure may be used as a reference in actual processes, but are not limited to this. For example, the width-to-length ratio of a channel, the thickness and spacing of individual layers, and the width and spacing of individual signal lines may be adjusted according to actual requirements. The number of pixels in a display substrate and the number of subpixels in each pixel are not limited to the numbers shown in the drawings. The drawings described in this disclosure are merely schematic structural diagrams, and an embodiment of this disclosure is not limited to the shapes, numerical values, or the like shown in the drawings.

[0040] The ordinal numbers “first”, “second”, “third”, etc. in the description do not serve to establish numerical limits, but only to avoid confusion between compositional elements.

[0041] For the sake of simplicity, the terms "center," "top," "bottom," "front," "back," "vertical," "horizontal," "top-," "bottom-," "inside," "outside," etc., which indicate directional or positional relationships, are used in the specification to illustrate the positional relationships between the assembly elements. They are not intended to indicate or imply that the devices or elements involved must have specific orientations and be structured and operated with those orientations, but only to describe the present specification easily and simply. Therefore, they should not be understood as limitations of the present disclosure. The positional relationships between the components may be modified depending on the direction in which the individual components are described. Therefore, suitable substitutions based on specific situations are permitted, and these are not limited to the terms used in the specification.

[0042] In this description, the terms "fastening," "mutual connection," and "connection" are to be understood in a broad sense unless otherwise specified and defined. For example, a connection may be a permanent connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection via middleware or internal communication within two elements. Those with ordinary technical knowledge will be able to understand the specific meanings of the above terms in this disclosure, depending on the specific situations.

[0043] In this description, a transistor refers to a device with at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. It is important to note that in this description, the channel region refers to the area through which current primarily flows.

[0044] In the description, the first electrode can be a drain electrode, and the second electrode can be a source electrode. Alternatively, the first electrode can be a source electrode and the second electrode can be a drain electrode. When transistors with opposite polarity are used, or when the current direction changes during the operation of a circuit, the functions of the "source electrode" and the "drain electrode" are sometimes interchangeable. Therefore, the terms "source electrode" and "drain electrode" are used interchangeably in the description.

[0045] In this description, the term "electrical connection" encompasses the connection of components by an element with a specific electrical effect. An "element with a specific electrical effect" is not particularly limited, as long as electrical signals can be sent and received between the connected components. Examples of an "element with a specific electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions, etc.

[0046] In this description, "parallel" refers to a state in which an angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" refers to a state in which an angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0047] In the description, the terms "film" and "layer" are interchangeable. For example, a "conductive layer" can sometimes be replaced by a "conductive film." Similarly, an "insulating film" can sometimes be replaced by an "insulating layer."

[0048] In the description, "arranged in the same layer" refers to a structure formed by patterning two (or more than two) structures through the same patterning process, where their materials may be the same or different. For example, the materials of the precursors for forming multiple structures arranged in the same layer are the same, and the final materials may be the same or different.

[0049] Triangles, rectangles, trapezoids, pentagons, hexagons, etc., are not strictly defined in this specification and may be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There may be some minor deformations caused by tolerances, and there may be chamfers, arced edges, distortions, etc.

[0050] In the present disclosure, “approximately” means that a limit is not so strictly defined and numerical values ​​within a range of process and measurement errors are permissible.

[0051] Fig. Figure 1 is a schematic diagram of the structure of a display device. As in Fig. As shown in Figure 1, the display device can include a timing controller, a source driver circuit, a gate driver circuit, and a pixel array. The timing controller is connected to both the source driver circuit and the gate driver circuit, and each source driver circuit is connected to a plurality of data signal lines (D1 to Dn). The gate driver circuit comprises a sampler driver circuit and a light emission driver circuit. The sampler driver circuit is connected to a plurality of sample signal lines (S1 to Sm), and the light emission driver circuit is connected to a plurality of light emission signal lines (E1 to Eo). The pixel array can contain multiple subpixels Pxij, where i and j can be natural numbers. At least one subpixel Pxij can include a circuit unit and a light-emitting device connected to the circuit unit.The circuit unit can include a pixel driver circuit, and the pixel driver circuit can be connected to a sample signal line, a light emission signal line, and a data signal line. In an exemplary implementation, the timing controller can provide a grayscale value and a control signal suitable for a source driver circuit specification to the source driver circuit; a clock signal, a sample start signal, etc., suitable for a sample driver circuit specification to the sample driver circuit; and a clock signal, an emission stop signal, etc., suitable for a light emission driver circuit specification to the light emission driver circuit. The source driver circuit can generate a data voltage that is applied to the data signal lines D1, D2, D3, ...and Dn using the grayscale value and control signal received from the timing controller. For example, the source driver circuit can sample the grayscale value using the clock signal and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn, taking one subpixel row as the unit, where n can be a natural number. The sampler driver circuit can receive the clock signal, sample start signal, etc., from the timing controller to generate a sample signal that is fed to the sample signal lines S1, S2, S3, ..., and Sm. For example, the sampler driver circuit can sequentially provide a sample signal with a one-level pulse to the sample signal lines S1 to Sm.For example, the sampler driver circuit can be implemented as a shift register and generate a sample signal in such a way that a sample start signal, provided as a one-level pulse, is sequentially passed to a circuit of the next stage under clock signal control, where m can be a natural number. The light-emitting driver circuit can receive the clock signal, the emission stop signal, etc., from the timing controller to generate an emission signal that is fed to the light emission signal lines E1, E2, E3, ... and Eo. For example, the light emission driver circuit can sequentially provide an emission signal with an off-level pulse to the light emission signal lines E1 to Eo.For example, the light-emitting driver circuit can be built in the form of a shift register and generate an emission signal in such a way that an emission stop signal, provided in the form of an off-level pulse, is sequentially transferred to a circuit of the next stage under control of the clock signal, where o can be a natural number.

[0052] Fig. Figure 2 is a first schematic diagram of a planar structure of a display substrate, Fig. Figure 3 is a second schematic diagram of a planar structure of a display substrate, and Fig. Figure 4 is a third schematic diagram of a planar structure of a display substrate. As in Fig. 2, Fig. 3 to Fig. As shown in Figure 4, the display substrate can contain several pixel units P arranged in a matrix, wherein at least one of the several pixel units P comprises a first subpixel P1 emitting light of a first color, a second subpixel P2 emitting light of a second color, and a third subpixel P3 emitting light of a third color, and the first subpixel P1, the second subpixel P2, and the third subpixel P3 each contain a pixel driver circuit and a light-emitting device.Pixel driver circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are each connected to a scanning signal line, a data signal line, and a light emission signal line, respectively. The pixel driver circuit is configured to receive a data voltage transmitted from the data signal line and output a corresponding current to the light-emitting device, controlling the scanning signal line and the light emission signal line. Light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are each connected to the pixel driver circuit of the subpixel containing the light-emitting device. The light-emitting device is configured to emit light of a corresponding brightness in response to a current output by the pixel driver circuit of the subpixel containing the light-emitting device.

[0053] In an example implementation, the first subpixel P1 can be a red (R) subpixel that emits red light, the second subpixel P2 can be a blue (B) subpixel that emits blue light, and the third subpixel P3 can be a green (G) subpixel that emits green light.

[0054] In exemplary embodiments, the subpixel can have the shape of a rectangle, a rhombus, a pentagon, or a hexagon. The present disclosure is not limited in this respect.

[0055] In an exemplary implementation, the three subpixels can be arranged horizontally next to each other, vertically next to each other, or in the form of a pyramid, which is not restricted in the present disclosure.

[0056] In other exemplary implementation modes, a pixel unit may comprise four subpixels, which may be arranged horizontally next to each other, vertically next to each other, or in the form of a square, and the present disclosure is not limited to these.

[0057] In an exemplary implementation, the pixel driver circuit can have a structure of 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C.

[0058] Fig. 5A is an equivalent circuit diagram of a pixel driver circuit. Fig. Section 5A illustrates the case where the pixel driver circuit has a structure of 7T1C as an example. As in Fig. As shown in Figure 5A, the pixel driver circuit can contain seven transistors (a first transistor M1 to a seventh transistor M7), a storage capacitor C, and the pixel driver circuit can be connected to seven signal lines (a data signal line Data, a first sampling signal line Gate1, a second sampling signal line Gate2, a light emission signal line EM, an initial signal line INIT, a first power supply line VDD and a second power supply line VSS).

[0059] In an exemplary implementation, the pixel driver circuit can comprise a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first electrode of the third transistor M3, the second electrode of the fourth transistor M4, and the second electrode of the fifth transistor M5. The second node N2 is connected to the second electrode of the first transistor, the first electrode of the second transistor M2, a control electrode of the third transistor M3, and the second terminal of the storage capacitor C. The third node N3 is connected to the second electrode of the second transistor M2, the second electrode of the third transistor M3, and the first electrode of the sixth transistor M6.

[0060] In an exemplary implementation, the first terminal of the storage capacitor C is connected to the first power supply line VDD, and the second terminal of the storage capacitor C is connected to the second node N2, i.e., the second terminal of the storage capacitor C is connected to the control electrode of the third transistor M3.

[0061] The control electrode of the first transistor M1 is connected to the second sampling signal line, Gate2. The first electrode of the first transistor M1 is connected to the initial signal line, INIT, and the second electrode of the first transistor is connected to the second node, N2. When a sampling signal with a level of on is applied to the second sampling signal line, Gate2, the first transistor M1 sends an initialization voltage to the control electrode of the third transistor M3 to initialize a charge on the control electrode of the third transistor M3.

[0062] A control electrode of the second transistor M2 is connected to the first sampling signal line Gate1, a first electrode of the second transistor M2 is connected to the second node N2, and a second electrode of the second transistor M2 is connected to the third node N3. When a sampling signal with a level of on is applied to the first sampling signal line Gate1, the second transistor M2 allows the control electrode of the third transistor M3 to be connected to the second electrode of the third transistor M3.

[0063] A control electrode of the third transistor M3 is connected to the second node N2, i.e., the control electrode of the third transistor M3 is connected to the second terminal of the storage capacitor C. A first electrode of the third transistor M3 is connected to the first node N1, and the second electrode of the third transistor M3 is connected to the third node N3. The third transistor M3 can be called the driver transistor, and the third transistor M3 determines the magnitude of a driver current that flows between the first power supply line VDD and the second power supply line VSS, according to a potential difference between the control electrode and the first electrode of the third transistor M3.

[0064] One control electrode of the fourth transistor M4 is connected to the first sampling signal line, Gate1; one electrode of the fourth transistor M4 is connected to the data signal line, Data; and one electrode of the fourth transistor M4 is connected to the first node, N1. The fourth transistor M4 can be described as a switching transistor, sampling transistor, etc., and it allows a data voltage from the data signal line, Data, to be input into the pixel driver circuit when a sampling signal with a level of 'on' is applied to the first sampling signal line, Gate1.

[0065] A control electrode of the fifth transistor M5 is connected to the light emission signal line EM, a first electrode of the fifth transistor M5 is connected to the first power supply line VDD, and a second electrode of the fifth transistor M5 is connected to the first node N1. A control electrode of the sixth transistor M6 is connected to the light emission signal line EM, a first electrode of the sixth transistor M6 is connected to the third node N3, and a second electrode of the sixth transistor M6 is connected to a first electrode of a light-emitting device. The fifth transistor M5 and the sixth transistor M6 can be referred to as light-emitting transistors.When a light emission signal with a level is applied to the light emission signal line EM, the fifth transistor M5 and the sixth transistor M6 of the light-emitting device enable it to emit light by forming a driver current path between the first power supply line VDD and the second power supply line VSS.

[0066] The control electrode of the seventh transistor M7 is connected to the first sampling signal line Gate1, the first electrode of the seventh transistor M7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor M7 is connected to the first electrode of the light-emitting device. When a sampling signal with a level of on is applied to the first sampling signal line Gate1, the seventh transistor M7 transmits an initialization voltage to the first electrode of the light-emitting device L to initialize or release the charge stored in the first electrode of the light-emitting device L.

[0067] In an exemplary implementation, a second electrode of the light-emitting device L is connected to the second power supply line VSS, the second power supply line VSS continuously provides a low-level signal, and the first power supply line VDD continuously provides a high-level signal.

[0068] Transistors can be divided into N-type and P-type transistors based on their characteristics. A P-type transistor has a low-level turn-on voltage (e.g., 0 V, -5 V, -10 V, or another suitable voltage) and a high-level turn-off voltage (e.g., 5 V, 10 V, or another suitable voltage). Similarly, an N-type transistor has a high-level turn-on voltage (e.g., 5 V, 10 V, or another suitable voltage) and a low-level turn-off voltage (e.g., 0 V, -5 V, -10 V, or another suitable voltage).

[0069] In one example implementation, the first transistor M1 through the seventh transistor M7 can be either P-type or N-type transistors. Using the same transistor type in a pixel driver circuit can simplify the process flow, reduce the complexity of a display panel, and improve product yield. In some possible implementations, the first transistor M1 through the seventh transistor M7 can include both a P-type and an N-type transistor.

[0070] In an exemplary implementation, low-temperature polysilicon thin-film transistors or oxide thin-film transistors, or both, can be used for the first transistor M1 through the seventh transistor M7. The active layer of a low-temperature polysilicon thin-film transistor consists of low-temperature polysilicon (LTPS), and the active layer of an oxide thin-film transistor consists of an oxide semiconductor (oxide). A low-temperature polysilicon thin-film transistor has advantages such as a high migration rate and fast charging, while an oxide thin-film transistor has advantages such as low leakage current.The low-temperature polysilicon thin-film transistor and the oxide thin-film transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide display substrate (LTPO), thus allowing the advantages of both the low-temperature polysilicon thin-film transistor and the oxide thin-film transistor to be utilized, low-frequency drive can be achieved, power consumption can be reduced, and display quality can be improved.

[0071] In an exemplary implementation, the first sampling signal line Gate1, the second sampling signal line Gate2, the light-emitting signal line EM and the initial signal line INIT can extend in a horizontal direction, and the second power supply line VSS, the first power supply line VDD and the data signal line Data can extend in a vertical direction.

[0072] In an exemplary implementation, the light-emitting device L can contain a first electrode (anode), an organic emitting layer and a second electrode (cathode) stacked together.

[0073] Fig. 5B is a time-of-flight sequence diagram of a pixel driver circuit. An exemplary embodiment of the present disclosure is described below by a work process of the in Fig. The pixel driver circuit shown in section 5A is described. Fig. 5 A comprises seven transistors (a first transistor M1 to a seventh transistor M7) and a storage capacitor C, and the seven transistors are all P-type transistors.

[0074] In an exemplary implementation, the working process of the pixel driver circuit can include the following stages.

[0075] In a first stage A1, called the reset stage, the signal from the second sampling line, Gate 2, is a low-level signal, and the signals from the first sampling line, Gate 1, and the light emission signal line, EM, are high-level signals. The signal from the second sampling line, Gate 2, is the low-level signal, so the first transistor, M1, is turned on, and a signal from the initial signal line, INIT, is sent to the second node, N2, to initialize (reset) the storage capacitor, C, to clear any initial charge in the storage capacitor. The signals from the first sampling line, Gate 1, and the light emission signal line, EM, are the high-level signals, so the second transistor, M2, the fourth transistor, M4, the fifth transistor, M5, the sixth transistor, M6, and the seventh transistor, M7, are turned off. In this stage, the light-emitting device, L, does not emit light.

[0076] In a second stage A2, referred to as the data write stage or threshold compensation stage, the signal from the first sampling signal line, Gate1, is a low-level signal, the signals from the second sampling signal line, Gate2, and the light emission signal line, EM, are high-level signals, and the data signal line, Data, outputs a data voltage. In this stage, the second terminal of the storage capacitor C is low-level, so the third transistor, M3, is switched on. The signal from the first sampling signal line, Gate1, is low-level, so the second transistor, M2, the fourth transistor, M4, and the seventh transistor, M7, are switched on.The second transistor M2 and the fourth transistor M4 are switched on, so that the data voltage output by the Data signal line is fed to the second node N2 via a first node N1, the switched-on third transistor M3, a third node N3, and the switched-on second transistor M2, and the storage capacitor C is charged with a difference between the data voltage output by the Data signal line and a threshold voltage of the third transistor M3. A voltage at the second end (the second node N2) of the storage capacitor C is Vd - |Vth|, where Vd is the data voltage output by the Data signal line and Vth is the threshold voltage of the third transistor M3.The seventh transistor, M7, is switched on, so that an initialization voltage from the INIT signal line is applied to the first electrode of the OLED to initialize (reset) the first electrode and clear any stored voltage, thus completing the initialization and ensuring that the light-emitting device L does not emit light. A high-level signal from the second sampling signal line, Gate2, switches off the first transistor, M1. The high-level signal from the light emission signal line, EM, switches off the fifth transistor, M5, and the sixth transistor, M6.

[0077] In a third stage A3, referred to as the light-emitting stage, the signal from the light-emitting signal line EM is a low-level signal, and the signals from the first sampling signal line Gate1 and the second sampling signal line Gate2 are high-level signals. A low-level signal from the light-emitting signal line EM turns on the fifth transistor M5 and the sixth transistor M6, and a power supply voltage output from the first power supply line VDD provides a drive voltage to a first electrode of the light-emitting device L via the fifth transistor M5, the third transistor M3, and the sixth transistor M6, which are turned on, to drive the light-emitting device L to emit light.

[0078] In a driver process of the pixel driver circuit, a driver current flowing through the third transistor M3 (driver transistor) is determined by a voltage difference between a gate electrode and the first electrode of the third transistor M3. The voltage of the second node N2 is Vdata-|Vth|, so the driver current of the third transistor M3 is as follows: I=K*(Vgs−Vth)2=K*[(Vdd−Vd+|Vth|)−Vth]2=K*(Vdd−Vd)2

[0079] Here, I is the driver current flowing through the third transistor M3, i.e., a driver current to drive the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power voltage output by the first power supply line VDD.

[0080] From the derivation of the current formula above, it is evident that in the light-emitting stage, the driving current of the third transistor M3 is not influenced by the threshold voltage of the third transistor M3. Therefore, the influence of the threshold voltage of the third transistor M3 on the driving current is eliminated, which ensures the uniformity of the display brightness and improves the overall display performance.

[0081] With the continuous advancement of display technologies, the market has placed higher demands on cost-effective, narrow bezels and thin, lightweight designs for display devices. In this context, Gate Driver on Array (GOA) technology, due to its advantages such as narrow bezels and thin, lightweight designs, has become a key research focus for major manufacturers.

[0082] GOA technology integrates a gate driver circuit onto an array substrate equipped with a pixel array. This allows the gate driver circuit to provide gate driver signals directly to the pixel array, eliminating the need for an additional gate driver chip and bonding structure. This reduces costs and the required bezel width. The gate driver circuit is electrically connected to a first sampling signal line, a second sampling signal line, a reset signal line, and a light emission signal line.

[0083] The gate driver circuit includes a variety of shift registers. Fig. Figure 6 is an equivalent circuit diagram of a shift register. As in Fig. As shown in Figure 6, the shift register comprises a gating sub-circuit 10, a node setting sub-circuit 20, a preprocessing sub-circuit 30, an input sub-circuit 40, a node separation sub-circuit 50, an output sub-circuit 60, a noise reduction sub-circuit 70, and a reset sub-circuit 80. The gating sub-circuit 10 is electrically connected to a first gating signal terminal D0 through eighth gating signal terminal D7, a second control clock terminal CKB, and a second node N2, and is configured to provide a signal from the second control clock terminal CKB to the second node N2 by controlling signals from the first gating signal terminal D0 through eighth gating signal terminal D7. The node setting sub-circuit 20 is connected to at least a second high-level power supply terminal GVDD2, a second low-level power supply terminal LVGL, and the second control clock terminal CKB.The input sub-circuit is electrically connected to a third control clock terminal CKC, the first node N1, and the third node N3, and is configured to provide a signal from the second high-level power supply terminal GVDD2 or the second low-level power supply terminal LVGL to the first node N1, controlling signals from the second control clock terminal CKB, the third control clock terminal CKC, and the third node N3. The input sub-circuit is electrically connected to at least the third control clock terminal CKC, the third node N3, and a fifth node N5, and is configured to provide a signal from the third control clock terminal CKC to the fifth node N3, controlling signals from the third node N3 and the third control clock terminal CKC. The preprocessing sub-circuit is electrically connected to at least the second node N2, the third node N3, a fourth node N4, andThe node separation sub-circuit is electrically connected to a first high-level power supply terminal GVDD1 and a first control clock terminal CKA and is configured to provide a signal from the first control clock terminal CKA or the first high-level power supply terminal GVDD1 to the third node N3 and the fourth node N4, controlling signals from the second node N2 and the first control clock terminal CKA. The node separation sub-circuit is electrically connected to the third control clock terminal CKC, the first high-level power supply terminal GVDD1, the second low-level power supply terminal LVGL, the first node N1, the fifth node N5, a sixth node N6, a seventh node N7, an eighth node N8, and a ninth node N9, and is configured tothat it provides a signal from the fifth node N5 to each of the sixth nodes N6 to ninth nodes N9 under control of signals from the third control clock terminal CKC and the first node N1, or provides a signal from the first high-level power supply terminal GVDD2 to the fifth node N5 under control of a signal from the sixth node N6. The output sub-circuit is electrically connected to at least one first output clock terminal CKE1 to fourth output clock terminal CKE4, one first low-level power supply terminal VGL, and one first signal output terminal OUT1 to fourth signal output terminal OUT4, and is configured to output a signal from the first output clock terminal CKE1 or the first low-level power supply terminal VGL to the first signal output terminal OUT1.to output a signal from the second output clock terminal CKE2 or the first low-level power supply terminal VGL to the second signal output terminal OUT2, to output a signal from the third output clock terminal CKE3 or the first low-level power supply terminal VGL to the third signal output terminal OUT3, and to output a signal from the fourth output clock terminal CKE4 or the first low-level power supply terminal VGL to the fourth signal output terminal OUT4.

[0084] In an exemplary implementation, as in Fig. As shown in Figure 6, the gating sub-circuit 10 comprises at least one second transistor T2 up to a ninth transistor T9. A gate electrode of the second transistor T2 is electrically connected to the first gating signal terminal D0, a first electrode of the second transistor T2 is electrically connected to the second control clock terminal CKB, a second electrode of the second transistor T2 is electrically connected to the second node N2, a gate electrode of the third transistor T3 is electrically connected to the second gating signal terminal D1, a first electrode of the third transistor T3 is electrically connected to the second control clock terminal CKB, a second electrode of the third transistor T3 is electrically connected to the second node N2, and a gate electrode of the fourth transistor T4 is electrically connected to the third gating signal terminal D2.A first electrode of the fourth transistor T4 is electrically connected to the second control clock terminal CKB, a second electrode of the fourth transistor T4 is electrically connected to the second node N2, a gate electrode of the fifth transistor T5 is electrically connected to the fourth gating signal terminal D3, a first electrode of the fifth transistor T5 is electrically connected to the second control clock terminal CKB, a second electrode of the fifth transistor T5 is electrically connected to the second node N2, a gate electrode of the sixth transistor T6 is electrically connected to the fifth gating signal terminal D4, a first electrode of the sixth transistor T6 is electrically connected to the second control clock terminal CKB, a second electrode of the sixth transistor T6 is electrically connected to the second node N2, a gate electrode of the seventh transistor T7 is electrically connected to the sixth gating signal terminal D5,a first electrode of the seventh transistor T7 is electrically connected to the second control clock terminal CKB, a second electrode of the seventh transistor T7 is electrically connected to the second node N2, a gate electrode of the eighth transistor T8 is electrically connected to the seventh gating signal terminal D6, a first electrode of the eighth transistor T8 is electrically connected to the second control clock terminal CKB, a second electrode of the eighth transistor T8 is electrically connected to the second node N2, a gate electrode of the ninth transistor T9 is electrically connected to the eighth gating signal terminal D7, a first electrode of the ninth transistor T9 is electrically connected to the second control clock terminal CKB, and a second electrode of the ninth transistor T9 is electrically connected to the second node N2.

[0085] In an exemplary implementation, as in Fig. As shown in Figure 6, the node setting sub-circuit 20 comprises at least a first transistor T1, a fifteenth transistor T15 and a sixteenth transistor T16.A gate electrode of the first transistor T1 is electrically connected to the second control clock terminal CKB, a first electrode of the first transistor T1 is electrically connected to the second high-level power supply terminal GVDD2, a second electrode of the first transistor T1 is electrically connected to the first node N1, a gate electrode of the fifteenth transistor T15 is electrically connected to the third node N3, a first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, a second electrode of the fifteenth transistor T15 is electrically connected to a first electrode of the sixteenth transistor T16, a gate electrode of the sixteenth transistor T16 is electrically connected to the third control clock terminal, and a second electrode of the sixteenth transistor T16 is electrically connected to the second low-level power supply terminal LVGL.

[0086] In an exemplary implementation, as in Fig. As shown in Figure 6, the preprocessing sub-circuit 30 comprises at least an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a tenth transistor T14, and a second capacitor C2. A gate electrode of the eleventh transistor T11 is electrically connected to the second node N2, a first electrode of the eleventh transistor T11 is electrically connected to the first control clock terminal CKA, a second electrode of the eleventh transistor T11 is electrically connected to the fourth node N4, a gate electrode of the twelfth transistor T12 is electrically connected to the second node N2, a first electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, a second electrode of the twelfth transistor T12 is electrically connected to the third node N3, and a gate electrode of the thirteenth transistor T13 is electrically connected to the first control clock terminal CKA.a first electrode of the thirteenth transistor T13 is electrically connected to the third node N3, a second electrode of the thirteenth transistor T13 is electrically connected to the first high-level power supply terminal GVDD1, a gate electrode of the fourteenth transistor T14 is electrically connected to the third node N3, a first electrode of the fourteenth transistor T14 is electrically connected to the fourth node N4, a first electrode of the fourteenth transistor T14 is electrically connected to the fourth node N4, a second electrode of the fourteenth transistor T14 is electrically connected to the first high-level power supply terminal GVDD1, a first terminal of the second capacitor C2 is electrically connected to the third node N3, and a second terminal of the second capacitor C2 is electrically connected to the first high-level power supply terminal GVDD1.

[0087] In an exemplary implementation, as in Fig. As shown in Figure 6, the input subcircuit 40 comprises at least one twenty-first transistor T21 and one twenty-second transistor T22. A gate electrode of the twenty-first transistor T21 is electrically connected to the third node N3, a first electrode of the twenty-first transistor T21 is electrically connected to the third control clock terminal CKC, a second electrode of the twenty-first transistor T21 is electrically connected to a first electrode of the twenty-second transistor T22, a gate electrode of the twenty-second transistor T22 is electrically connected to the third control clock terminal CKC, and a second electrode of the twenty-second transistor T22 is electrically connected to the fifth node N5.

[0088] In an exemplary implementation, as in Fig. As shown in Figure 6, the node separation subcircuit 50 comprises at least a twenty-third transistor T23 to a thirty-fifth transistor T35. A control electrode of the twenty-third transistor T23 is electrically connected to the third control clock terminal CKC, a first electrode of the twenty-third transistor T23 is electrically connected to the fifth node N5, a second electrode of the twenty-third transistor T23 is electrically connected to the sixth node N6, a control electrode of the twenty-fourth transistor T24 is electrically connected to the third control clock terminal CKC, a first electrode of the twenty-fourth transistor T24 is electrically connected to the fifth node N5, a second electrode of the twenty-fourth transistor T24 is electrically connected to the seventh node N7, and a control electrode of the twenty-fifth transistor T25 is electrically connected to the third control clock terminal CKC.A first electrode of the twenty-fifth transistor T25 is electrically connected to the fifth node N5, a second electrode of the twenty-fifth transistor T25 is electrically connected to the eighth node N8, a control electrode of the twenty-sixth transistor T26 is electrically connected to the third control clock terminal CKC, a first electrode of the twenty-sixth transistor T26 is electrically connected to the fifth node N5, a second electrode of the twenty-sixth transistor T26 is electrically connected to the ninth node N9, a control electrode of the twenty-seventh transistor T27 is electrically connected to the first node N1, a first electrode of the twenty-seventh transistor T27 is electrically connected to the sixth node N6, a second electrode of the twenty-seventh transistor T27 is electrically connected to the fifth node N5,a control electrode of the twenty-eighth transistor T28 is electrically connected to the first node N1, a first electrode of the twenty-eighth transistor T28 is electrically connected to the fifth node N5, a second electrode of the twenty-eighth transistor T28 is electrically connected to the second low-level power supply terminal LVGL, a control electrode of the twenty-ninth transistor T29 is electrically connected to the first node N1, a first electrode of the twenty-ninth transistor T29 is electrically connected to the seventh node N7, a second electrode of the twenty-ninth transistor T29 is electrically connected to the fifth node N5, a control electrode of the thirtieth transistor T30 is electrically connected to the first node N1, a first electrode of the thirtieth transistor T30 is electrically connected to the fifth node N5,a first electrode of the thirtieth transistor T30 is electrically connected to the fifth node N5, a second electrode of the thirtieth transistor T30 is electrically connected to the second low-level power supply terminal LVGL, a control electrode of the thirty-first transistor T31 is electrically connected to the first node N1, a first electrode of the thirty-first transistor T31 is electrically connected to the sixth node N6, a second electrode of the thirty-first transistor T31 is electrically connected to the eighth node N8, a control electrode of the thirty-second transistor T32 is electrically connected to the first node N1, a first electrode of the thirty-second transistor T32 is electrically connected to the fifth node N5, a second electrode of the thirty-second transistor T32 is electrically connected to the second low-level power supply terminal LVGL,A control electrode of the thirty-third transistor T33 is electrically connected to the first node N1, a first electrode of the thirty-third transistor T33 is electrically connected to the ninth node N9, a second electrode of the thirty-third transistor T33 is electrically connected to the fifth node N5, a control electrode of the thirty-fourth transistor T34 is electrically connected to the first node N1, a first electrode of the thirty-fourth transistor T34 is electrically connected to the fifth node N5, a second electrode of the thirty-fourth transistor T34 is electrically connected to the second low-level power supply terminal LVGL, a gate electrode of the thirty-fifth transistor T35 is electrically connected to the sixth node N6, a first electrode of the thirty-fifth transistor T35 is electrically connected to the first high-level power supply terminal GVDD1,and a second electrode of the thirty-fifth transistor T35 is electrically connected to the fifth node N5.

[0089] In an exemplary implementation, as described in Fig. As shown in Figure 6, the output sub-circuit 60 comprises at least a thirty-sixth transistor T36, a thirty-seventh transistor T37, a thirty-eighth transistor T38, a thirty-ninth transistor T39, a fortieth transistor T40, a forty-first transistor T41, a forty-second transistor T42, a forty-third transistor T43, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. A gate electrode of the thirty-sixth transistor T36 is electrically connected to the ninth node N9, a first electrode of the thirty-sixth transistor T36 is electrically connected to the first output clock terminal CKE1, a second electrode of the thirty-sixth transistor T36 is electrically connected to the first output terminal OUT1, and a gate electrode of the thirty-seventh transistor T37 is electrically connected to the first node N1.A first electrode of the thirty-seventh transistor T37 is electrically connected to the first output terminal OUT1, a second electrode of the thirty-seventh transistor T37 is electrically connected to the first low-level power supply terminal VGL, a gate electrode of the thirty-eighth transistor T38 is electrically connected to the eighth node N8, a first electrode of the thirty-eighth transistor T38 is electrically connected to the second output clock terminal CKE2, a first electrode of the thirty-eighth transistor T38 is electrically connected to the second output clock terminal CKE2, a second electrode of the thirty-eighth transistor T38 is electrically connected to the second output terminal OUT2, a gate electrode of the thirty-ninth transistor T39 is electrically connected to the first node N1, a first electrode of the thirty-ninth transistor T39 is electrically connected to the second output terminal OUT2,a second electrode of the thirty-ninth transistor T39 is electrically connected to the first low-level power supply terminal VGL, a gate electrode of the fortieth transistor T40 is electrically connected to the seventh node N7, a first electrode of the fortieth transistor T40 is electrically connected to the third output clock terminal CKE3, a second electrode of the fortieth transistor T40 is electrically connected to the third output terminal OUT3, a gate electrode of the forty-first transistor T41 is electrically connected to the first node N1, a first electrode of the forty-first transistor T41 is electrically connected to the third output terminal OUT3, a second electrode of the forty-first transistor T41 is electrically connected to the first low-level power supply terminal VGL, a gate electrode of the forty-second transistor T42 is electrically connected to the sixth node N6,A first electrode of the forty-second transistor T42 is electrically connected to the fourth output clock terminal CKE4, a second electrode of the forty-second transistor T42 is electrically connected to the fourth output terminal OUT4, a gate electrode of the forty-third transistor T43 is electrically connected to the first node N1, a first electrode of the forty-third transistor T43 is electrically connected to the fourth output terminal OUT4, a second electrode of the forty-third transistor T43 is electrically connected to the first low-level power supply terminal VGL, a first terminal of the third capacitor C3 is electrically connected to the ninth node N9, a second terminal of the third capacitor C3 is electrically connected to the first output terminal OUT1, a first terminal of the fourth capacitor C4 is electrically connected to the eighth node N8,A second terminal of the fourth capacitor C4 is electrically connected to the second output terminal OUT2, a first terminal of the fifth capacitor C5 is electrically connected to the seventh node N7, a second terminal of the fifth capacitor C5 is electrically connected to the third output terminal OUT3, a first terminal of the sixth capacitor C6 is electrically connected to the sixth node N6, and a second terminal of the sixth capacitor C6 is electrically connected to the fourth output terminal OUT4.

[0090] In an exemplary implementation, as in Fig. As shown in Figure 6, the noise reduction sub-circuit 70 comprises at least one tenth transistor T10, one seventeenth transistor T17 and one first capacitor C1.A gate electrode of the tenth transistor T10 is electrically connected to the first control clock terminal CKA, a first electrode of the tenth transistor T10 is electrically connected to the second control clock terminal CKB, a second electrode of the tenth transistor T10 is electrically connected to the second node N2, a gate electrode of the seventeenth transistor T17 is electrically connected to the ninth node N9, a first electrode of the seventeenth transistor T17 is electrically connected to the first node N1, a second electrode of the seventeenth transistor T17 is electrically connected to the second low-level power supply terminal LVGL, a first terminal of the first capacitor C1 is electrically connected to the first node N1, and a second terminal of the first capacitor C1 is electrically connected to the second low-level power supply terminal LVGL.

[0091] In an exemplary implementation, as in Fig. As shown in Figure 6, the reset sub-circuit 80 comprises at least one eighteenth transistor T18, one nineteenth transistor T19, and one twentieth transistor T20. A gate electrode of the eighteenth transistor T18 is electrically connected to a global reset signal terminal TRS, a first electrode of the eighteenth transistor T18 is electrically connected to the third node N3, a second electrode of the eighteenth transistor T18 is electrically connected to the fourth node N4, a gate electrode of the nineteenth transistor T19 is electrically connected to the global reset signal terminal TRS, a first electrode of the nineteenth transistor T19 is electrically connected to the first high-level power supply terminal GVDD1, a second electrode of the nineteenth transistor T19 is electrically connected to the first node N1, and a gate electrode of the twentieth transistor T20 is electrically connected to the global reset signal terminal TRS.A first electrode of the twentieth transistor T20 is electrically connected to the fourth node N4, and a second electrode of the twentieth transistor T20 is electrically connected to the second low-level power supply terminal LVGL.

[0092] In an exemplary implementation, all transistors in the shift register, i.e., the first transistor T1 to the forty-third transistor T43, can be N-type transistors. Using the same transistor type in the shift register can simplify process flows, reduce the process difficulties of the display panel, and improve product yield.

[0093] In an exemplary implementation, a gate driver circuit that implements the in Fig. The present disclosure comprises 6 shift registers arranged in a large-format display product, and the pixel driver circuitry in a large-format display product may have a 3T1C structure. The present disclosure is not limited in this respect.

[0094] In an exemplary implementation, the signals of the first high-level power supply terminal GVDD1 and the second high-level power supply terminal GVDD2 are DC signals and are high-level signals.

[0095] In an exemplary implementation, the signals of the first low-level power supply terminal VGL and the second low-level power supply terminal LVGL are DC signals and are low-level signals, and an absolute value of a voltage value of the signal of the second low-level power supply terminal LVGL is greater than an absolute value of a voltage value of the signal of the first low-level power supply terminal VGL.

[0096] In an example implementation, a signal from any signal terminal of the first control clock terminal CKA to the third control clock terminal CKC and from the first output clock terminal CK1 to the fourth output clock terminal CK4 is a square wave that repeats a high voltage and a low voltage. For example, signals from any two signal terminals of the first control clock terminal CKA to the third control clock terminal CKC can have the same cycle and be configured as phase-shifted signals. Signals from any two signal terminals of the first output clock terminal CK1 to the fourth output clock terminal CK4 can have the same cycle and be configured as phase-shifted signals.

[0097] In an exemplary implementation, a high-voltage period of a signal from the first control clock terminal CKA can overlap with part of a low-voltage period of a signal from the second control clock terminal CKB and part of a low-level period of a signal from the third control clock terminal CKC. A high-voltage period of the signal from the second control clock terminal CKB can overlap with part of a low-voltage period of the signal from the first control clock terminal CKA and part of the low-level period of the signal from the third control clock terminal CKC. A high-voltage period of a signal from the third control clock terminal CKC can overlap with part of the low-voltage period of the signal from the first control clock terminal CKA and part of a low-level period of the signal from the second control clock terminal CKB.

[0098] In an exemplary implementation, a high-voltage period of a signal from the first output clock terminal CKE1 may partially overlap with a high-voltage period of a signal from the second output clock terminal CKE2, the high-voltage period of the signal from the second output clock terminal CKE2 may partially overlap with a high-voltage period of a signal from the third output clock terminal CKE3, the high-voltage period of the signal from the third output clock terminal CKE3 may partially overlap with a high-voltage period of a signal from the fourth output clock terminal CKE4, and the high-voltage period of the signal from the first output clock terminal CKE1 does not overlap with the high-voltage period of the signal from the fourth output clock terminal CKE4.

[0099] In an exemplary implementation, any one of the capacitors from the first C1 to the sixth C6 can be a capacitor device fabricated by a process, e.g., the capacitor device can be implemented by fabricating a special capacitor electrode, and a variety of capacitor electrodes of the capacitor can be implemented by metal layers, semiconductor layers (e.g., doped polysilicon), or the like. Alternatively, any one of the capacitors from the first C1 to the sixth C6 can be a parasitic capacitance between a variety of components and can be implemented by the transistor itself and other components or wires.The connection mode of any one of the first capacitor C1 to the sixth capacitor C6 includes the mode described above, but is not limited to it, and may be another suitable connection mode capable of storing the level of the corresponding node. The exemplary embodiments of the present disclosure are not limited to these.

[0100] In an exemplary implementation, the shift register can contain a variety of gating signal connections. Fig. Figure 6 illustrates this using the example of eight gating signal connections. In an exemplary implementation, the gating signals available for access at any gating signal connection in the shift register comprise two gating signals, and these two gating signals are inverted signals. The two gating signals accessed at different gating signal connections are distinct, and there is no output from the shift register only if the signals at all gating signal connections are ineffective levels. By configuring the multiple gating signal connections, it is possible to ensure that at least some of the shift registers in the gate driver circuit can operate independently, and there is no cascade relationship between adjacent shift registers. If the gating sub-circuit comprises 8 transistors, the independent operation of 2^8 = 256 shift registers can be achieved.

[0101] In an exemplary implementation, the shift register can contain a multitude of output pins, each of which is connected to a set of subpixels. The in Fig. The shift register shown comprises four output terminals, meaning four rows of subpixels are connected. Therefore, if the gating subcircuit comprises 8 transistors, independent operation of 2^10 = 1024 rows of subpixels can be achieved. If the number of rows of subpixels that can operate independently is to be increased, this can be achieved by increasing the number of transistors in the gating subcircuit or by increasing the number of output terminals. For example, the gating subcircuit can contain 10 transistors, which is not limited in the present disclosure.

[0102] The shift register provided by the present disclosure can ensure that a large number of shift registers do not need to be cascaded, allowing the shift registers to operate independently. This allows the gate driver circuit, which is described in the disclosure, to operate independently. Fig. The 6 shift registers shown are used to randomly gate a specific series of subpixels. This allows, on the one hand, the gate driver circuit, which is located in Fig. The 6 provided shift registers are used to perform local refreshes of a display image without performing line-by-line sampling, thereby significantly increasing the refresh rate; for example, if only part of the display image needs to be refreshed, only that part of the display image can be selectively refreshed, thereby significantly improving the refresh rate.

[0103] Fig. 7 is a work time sequence diagram of the in Fig. 6 provided sliding registers. As in Fig. As shown in Figure 7, an exemplary embodiment of the present disclosure is described below by a work process of the Fig. The shift register shown in Figure 6 is described, comprising 43 transistors (the first transistor T1 to the forty-third transistor T43) and six capacitors C (the first capacitor C1 to the sixth capacitor C6), and the 43 transistors are all P-type transistors.

[0104] In an exemplary implementation, the shift register's operation can include a display stage and a non-display stage, where a signal from the global reset signal terminal TRS is a high-level signal in part of the non-display stage and a low-level signal in the display stage. Signals from the first control clock terminal CKA to the third control clock terminal CKC and from the first output clock terminal CKE1 to the fourth output clock terminal CKE4 are low-level signals, and signals from the first gating signal terminal D0 to the eighth gating signal terminal D7 are high-level signals. According to the gating principle, the shift register is not gated if the signals at all gating signal terminals are high-level signals.

[0105] In the non-display stage, the signal from the global reset signal terminal TRS is a high-level signal, and the signals from the first gating signal terminal D0 to the eighth gating signal terminal D7 are high-level signals. The signal from the global reset signal terminal TRS is a high-level signal; the eighteenth transistor T18 and the twentieth transistor T20 are turned on; the signals from the third node N3 and the fourth node N4 are pulled down to low-level signals by the second low-level power supply terminal LVGL; the nineteenth transistor T19 is turned on; the first node N1 is pulled high by the high-level signal from the first high-level power supply GVDD1; the twenty-seventh transistor T27 to the thirty-fourth transistor T34 are turned on; and the thirty-seventh transistor T37, the thirty-ninth transistor T39, the forty-first transistor T41, and the forty-third transistor T43 are also turned on.Signals from the sixth node N6, the seventh node N7, the eighth node N8, and the ninth node N9 are pulled low by the second low-level power supply terminal LVGL, and signals from the first output terminal OUT1 to the fourth output terminal OUT4 are pulled low by the first low-level power supply terminal VGL. Signals from the first gating signal terminal D0 to the eighth gating signal terminal D7 are high-level signals, transistors T2 to T9 are turned on, and a signal from the second node N2 is pulled low by the second control clock terminal CKB.

[0106] In an exemplary implementation, the work process of the shift register in the display stage can include the following stages.

[0107] In a first stage P1, signals from the first control clock terminal CKA and the first gating signal terminal D0 to the eighth gating signal terminal D7 are high-level signals, and signals from the second control clock terminal CKB and the third control clock terminal CKC are low-level signals. Under the influence of the first capacitor C1, the first node N1 maintains a high-level signal; the twenty-seventh transistor T27 to the thirty-fourth transistor T34 are switched on; the thirty-seventh transistor T37, the thirty-ninth transistor T39, the forty-first transistor T41, and the forty-third transistor T43 are continuously switched on; signals from the sixth node N6, the seventh node N7, the eighth node N8, and the ninth node N9 are continuously pulled down by the second low-level power supply terminal LVGL to become low-level signals.and signals from the first output terminal OUT1 to the fourth output terminal OUT4 are continuously pulled down by the first low-level power supply terminal VGL. The signals from the first gating signal terminal D0 to the eighth gating signal terminal D7 are high-level signals; the second transistor T2 to the ninth transistor T9 are turned on; the signal from the second node N2 is pulled down by the second control clock terminal CKB; and the signal from the second node N2 is a low-level signal. The signal from the first control clock terminal CKA is a high-level signal; the thirteenth transistor T13 is turned on; the third node N3 is pulled high by the signal from the first high-level power supply terminal GVDD1; a signal from the third node N3 is a high-level signal; a signal from the twenty-first transistor T21 is turned on; and a signal from the third control clock terminal CKC is a low-level signal.The twenty-second transistor T22 to the twenty-sixth transistor T26 are switched off, the fourteenth transistor T14 is switched on, a signal from the fourth node N4 is pulled high by the signal from the first high-level power supply terminal GVDD1, the signal from the fourth node N4 is a high-level signal, in this stage a signal from the first node N1 is a high-level signal, the signal from the second node N2 is a low-level signal, the signal from the third node N3 is a high-level signal, the signal from the fourth node N4 is a high-level signal, and the first output terminal OUT1 to the fourth output terminal OUT4 have no output.

[0108] In a second stage P2, the signal of the second control clock terminal CKB is a high-level signal, and signals from the first gating signal terminal D0 to the eighth gating signal terminal D7, the second control clock terminal CKB and the third control clock terminal CKC are low-level signals.The signal from the second control clock terminal CKB is a high-level signal; the first transistor T1 is switched on; the signal from the first node N1 is pulled high by the high-level signal from the second high-level power supply terminal GVDD2; the twenty-seventh transistor T27 to the thirty-fourth transistor T34 are switched on; the thirty-seventh transistor T37, the thirty-ninth transistor T39, the forty-first transistor T41, and the forty-third transistor T43 are continuously switched on; signals from the sixth node N6, the seventh node N7, the eighth node N8, and the ninth node N9 are continuously pulled down by the second low-level power supply terminal LVGL to become low-level signals; and signals from the first output terminal OUT1 to the fourth output terminal OUT4 are continuously pulled down by the first low-level power supply terminal VGL.Since the signals from the first gating signal terminal D0 to the eighth gating signal terminal D7 are low-level signals, the second transistor T2 to the ninth transistor T9 are switched off, the high-level signal from the second control clock terminal CKB cannot be written to the second node N2, and the third node N3 and the fourth node N4 retain high-level signals from a previous stage. In this stage, the signal from the first node N1 is a high-level signal, the signal from the second node N2 is a low-level signal, the signal from the third node N3 is a high-level signal, and the signal from the fourth node N4 is a high-level signal. The first output terminal OUT1 to the fourth output terminal OUT4 have no output.

[0109] In a third stage P3, the signal at the third control clock terminal CKC is a high-level signal. The signals at the first control clock terminal CKA, the second control clock terminal CKB, and the first gating signal terminal D0 through the eighth gating signal terminal D7 are low-level signals. The second node N2 holds a low-level signal from a previous stage, the third node N3 and the fourth node N4 hold high-level signals from a previous stage, the signal at the third control clock terminal CKC is a high-level signal, the fifteenth transistor T15 and the sixteenth transistor T16 are switched on, the signal at the first node N1 is pulled down by the second low-level power supply GVDD2, the twenty-seventh transistor T27 through the thirty-fourth transistor T34 are switched on, the thirty-seventh transistor T37, the thirty-ninth transistor T39,the forty-first transistor T41 and the forty-third transistor T43 are switched off, the twenty-first transistor T21 to the twenty-sixth transistor T26 are switched on, the fifth node N5 is pulled up by the high-level signal of the third control clock terminal CKC, the sixth node N6 to the ninth node N9 are pulled up by a signal from the fifth node N5, the thirty-sixth transistor T36, the thirty-eighth transistor T38, the thirty-eighth transistor T38, the fortieth transistor T40 and the forty-second transistor T42 are pulled up by a signal from the fifth node N5, the thirty-sixth transistor T36, the forty-eighth transistor T38, the fortieth transistor T40 and the forty-second transistor T42 are switched on, since the signals of the first output clock terminal CKE1 to the fourth output clock terminal CKE4 are low-level signals,The signals from the first output terminal OUT1 to the fourth output terminal OUT4 are low-level signals.

[0110] In a fourth stage P4, the signals from the first output clock terminal CKE1 to the fourth output clock terminal CKE4 are high-level signals for part of a time period; the signals from the first control clock terminal CKA to the third control clock terminal CKC and from the first gating signal terminal D0 to the eighth gating signal terminal D7 are low-level signals; under the bootstrapping action of the third capacitor C3, the ninth node N9 is raised, the thirty-sixth transistor T36 is switched on, the high-level signal from the first output clock terminal CKE1 is written to the first output terminal OUT1; under the bootstrapping action of the fourth capacitor C4, the eighth node N8 is raised, the thirty-eighth transistor T38 is switched on, the high-level signal from the second output clock terminal CKE2 is written to the second output terminal OUT2.Under the bootstrapping action of the fifth capacitor C5, the seventh node N7 is raised, the forty-second transistor T40 is switched on, the high-level signal of the third output clock terminal CKE3 is written to the third output terminal OUT3, under the bootstrapping action of the fourth capacitor C4, the sixth node N6 is raised, the forty-second transistor T42 is switched on, the high-level signal of the fourth output clock terminal CKE4 is written to the fourth output terminal OUT4, the thirty-fifth transistor T35 is continuously switched on, the signal of the fifth node N5 is continuously pulled high, in this stage the signals of the first node N1 and the second node N2 are low-level signals, the signals of the third node N3 to the ninth node N9 are high-level signals, and the signals of the first output terminal OUT1 to the fourth output terminal OUT4 are high-level signals.

[0111] In a fifth stage P5, signals from the second control clock terminal CKB and the first gating signal terminal D0 are high-level signals, and signals from the first control clock terminal CKA, the third control clock terminal CKB, the second gating signal terminal D1 to the eighth gating signal terminal D7 are low-level signals.The signal from the second control clock terminal CKB is a high-level signal; the first transistor T1 is switched on; the signal from the first node N1 is pulled high by the high-level signal from the second high-level power supply terminal GVDD2; the twenty-seventh transistor T27 to the thirty-fourth transistor T34 are switched on; the thirty-seventh transistor T37, the thirty-ninth transistor T39, the forty-first transistor T41, and the forty-third transistor T43 are continuously switched on; the signals from the sixth node N6, the seventh node N7, the eighth node N8, and the ninth node N9 are continuously pulled down by the second low-level power supply terminal LVGL to become low-level signals; and the signals from the first output terminal OUT1 to the fourth output terminal OUT4 are continuously pulled down by the first low-level power supply terminal VGL.Since the signal from the first gating signal terminal D0 is a high-level signal, the second transistor T2 is switched on, the high-level signal from the second control clock terminal CKB is written to the second node N2, the eleventh transistor T11 and the twelfth transistor T12 are switched on, and the low-level signal from the first control clock terminal CKA is written to the third node N3 and the fourth node N4. In this stage, the signals from the first node N1 and the second node N2 are high-level signals, the signals from the third node N3 and the fourth node N4 are low-level signals, and the first output terminals OUT1 through the fourth output terminals OUT4 have no output.

[0112] The above explanation is given by assuming the case that the signals of the first gating signal terminal D0 to the eighth gating signal terminal D7 of the shift register in the second stage are all low-level signals as an example.

[0113] For a shift register in which a signal from one of the first gating signal terminals D0 to eighth gating signal terminal D7 is a high-level signal in the second stage, in the second stage the signal of the second control clock terminal CKB is a high-level signal, the first transistor T1 is switched on, the signal of the first node N1 is pulled high by the high level of the second high-level power supply terminal GVDD2, the twenty-seventh transistor T27 to the thirty-fourth transistor T34 are switched on, the thirty-seventh transistor T37, the thirty-ninth transistor T39, the forty-first transistor T41 and the forty-third transistor T43 are continuously switched on, the signals of the sixth node N6, the seventh node N7, the eighth node N8 and the ninth node N9 are continuously pulled down by the second low-level power supply terminal LVGL to become low-level signals,and the signals from the first output terminal OUT1 to the fourth output terminal OUT4 are continuously pulled down by the first low-level power supply terminal VGL. Since a signal from the first gating signal terminal D0 to the eighth gating signal terminal D7 is a high-level signal, one of the second transistors T2 to the ninth transistor T9 is turned on, the high-level signal from the second control clock terminal CKB is written to the second node N2, the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the low-level signal from the first control clock terminal CKA is written to the third node N3 and the fourth node N4. In this stage, the signals from the first node N1 and the second node N2 are high-level signals, the signals from the third node N3 and the fourth node N4 are low-level signals, and the first output terminal OUT1 to the fourth output terminal OUT4 have no output.until all gating signal connections are low-level signals. Only then does the execution of the third stage begin, which initiates the output.

[0114] In summary, the shift register begins outputting when the signals at all gating signal terminals in the shift register are low-level signals, and the shift register does not output when at least one of the signals at all gating signal terminals in the shift register is a high-level signal.

[0115] The display device includes the in Fig. Figure 6 shows the gate driver circuit. Due to the large number of transistors contained in the shift register within the gate driver circuit, the display device is unable to achieve a narrow bezel.

[0116] Fig. Figure 8 is a first schematic structure diagram of a display substrate according to an embodiment of the present disclosure, Fig. Figure 9 is a second schematic structure diagram of a display substrate according to an embodiment of the present disclosure, and Fig. Figure 10 is a top view of a gating sub-circuit. As in the Fig. 8, Fig. 9 to Fig. As shown in Figure 10, a display substrate according to an embodiment of the present disclosure has a display area 100 and a non-display area 200, which is provided on at least one side of the display area 100 and surrounds it. The display area 100 is provided with pixel driver circuits PE arranged in an array, and the non-display area 200 is provided with a gate driver circuit and a gating signal line group DL. The gating signal line group DL comprises a plurality of gating signal lines, and the gate driver circuit is electrically connected to the pixel driver circuits and the gating signal line group DL. A gating signal line extends along a first direction D1, and the plurality of gating signal lines are arranged along a second direction D2, with the first direction D1 and the second direction D2 intersecting.

[0117] For example, the first direction D1 could be a column direction and the second direction D2 a row direction. The first direction intersecting the second direction means that the angle between the first and second directions is approximately 70 to 90 degrees. The first and second directions can lie in the same plane.

[0118] Fig. 8 and Fig. Figure 9 is shown for the case where there are sixteen gating signal lines: a first gating signal line DL0, a second gating signal line DLN0, a third gating signal line DL1, a fourth gating signal line DLN1, a fifth gating signal line DL2, a sixth gating signal line DLN2, a seventh gating signal line DL3, an eighth gating signal line DLN3, a ninth gating signal line DL4, a tenth gating signal line DLN4, an eleventh gating signal line DL5, a twelfth gating signal line DLN5, a thirteenth gating signal line DL6, a fourteenth gating signal line DLN6, a fifteenth gating signal line DL7, and a sixteenth gating signal line DLN7, as an example.

[0119] As in Fig. 8, Fig. 9 to Fig. As shown in Figure 10, the gate driver circuit comprises a plurality of shift registers, and each shift register comprises a gating sub-circuit 10. The gating sub-circuit is electrically connected to a portion of the gating signal lines in the gating signal line group DL. The gating sub-circuit can contain a plurality of gating transistors, and for each of the shift registers, the plurality of gating transistors in the gating sub-circuit are arranged along the first direction D1. By way of example, the plurality of gating transistors are the second transistor T2 to the ninth transistor T9 in Figure 10. Fig. 6, i.e. the second transistor T2 to the ninth transistor T9 are arranged along the first direction D1. Fig. 8 and Fig. Figure 9 shows only one shift register.

[0120] In an exemplary implementation, the gate driver circuit can be located on at least one side of the display area 200, which is not restricted in the present disclosure.

[0121] The display substrate according to an embodiment of the present disclosure has a display area and a non-display area, which is provided on and surrounds at least one side of the display area, wherein the display area is provided with pixel driver circuits arranged in an array, and the non-display area is provided with a gate driver circuit and a gating signal line group, wherein the gating signal line group comprises: a plurality of gating signal lines, and the gate driver circuit is electrically connected to each of the pixel driver circuits and the gating signal line group; a gating signal line extends along a first direction, the plurality of gating signal lines are arranged along a second direction, and signals from at least two gating signal lines are mutually inverted signals; the gate driver circuit comprises a plurality of shift registers.A shift register comprises: a gating sub-circuit, wherein the gating sub-circuit is electrically connected to a portion of the gating signal lines in the gating signal line group; the gating sub-circuit comprises a plurality of gating transistors; for each shift register, the plurality of gating transistors in the gating sub-circuit are arranged along the first direction. By arranging the plurality of gating transistors in the gating sub-circuit in any shift register along the first direction, the present disclosure can reduce the length of the gate driver circuit along the second direction, thereby realizing a narrow border of the display substrate.

[0122] In an exemplary implementation, the signals from at least two gating signal lines are mutually inverted signals for part of a period of time.

[0123] In an exemplary implementation, Fig. Figure 11 shows a schematic diagram of a connection of a plurality of shift registers. A shift register GOA comprises: M gating signal terminals, and the gating signal line group comprises: 2M gating signal lines. An m-th gating signal terminal is electrically connected to a (2m-1)-th gating signal line or a 2m-th gating signal line, and a signal of the (2m-1)-th gating signal line and a signal of the 2m-th gating signal line are mutually inverted signals, 1 ≤ m ≤ M. Taking M = 8 as an example in conjunction with Fig. 6, Fig. 8 and Fig. 9 a first gating signal terminal D0 is electrically connected to a first gating signal line DL0 or a second gating signal line DLN0, a second gating signal terminal D1 is electrically connected to a third gating signal line DL1 or a fourth gating signal line DLN1, a third gating signal terminal D2 is electrically connected to a fifth gating signal line DL2 or a sixth gating signal line DLN2, a fourth gating signal terminal D3 is electrically connected to a seventh gating signal line DL3 or an eighth gating signal line DLN3, a fifth gating signal terminal D4 is electrically connected to a ninth gating signal line DL4 or a tenth gating signal line DLN4, a sixth gating signal terminal D5 is electrically connected to an eleventh gating signal line DL5 or a twelfth gating signal line DLN5,A seventh gating signal terminal D6 is electrically connected to a thirteenth gating signal line DL6 or a fourteenth gating signal line DLN6, and an eighth gating signal terminal D7 is electrically connected to a fifteenth gating signal line DL7 or a sixteenth gating signal line DLN7.

[0124] In an exemplary implementation, the frequencies of the signals from the first gating signal port D0 to the eighth gating signal port D7 can be sequentially reduced, i.e., the signal pulses from the first gating signal port D0 to the eighth gating signal port D7 can be sequentially increased. For example, the signal frequency of a gating signal at the first gating signal port D0 is the highest, the signal frequency of a gating signal at the second gating signal port D1 is half the signal frequency of the gating signal at the first gating signal port D0, the signal frequency of a gating signal at the third gating signal port D2 is half the signal frequency of the gating signal at the second gating signal port D1, and the signal frequency of a gating signal at the fourth gating signal port D3 is half the signal frequency of the gating signal at the third gating signal port D2.A signal frequency of a gating signal of the fifth gating signal port D4 is half the signal frequency of the gating signal of the fourth gating signal port D3, a signal frequency of a gating signal of the sixth gating signal port D5 is half the signal frequency of the gating signal of the fifth gating signal port D4, a signal frequency of a gating signal of the seventh gating signal port D6 is half the signal frequency of the gating signal of the sixth gating signal port D5, and a signal frequency of a gating signal of the eighth gating signal port D7 is half the signal frequency of the gating signal of the seventh gating signal port D6. The signal pulse width of the gating signal at the first gating signal terminal D0 is the smallest, while the signal pulse width of the gating signal at the second gating signal terminal D1 is twice as large as the signal pulse width of the gating signal at the first gating signal terminal D0.The signal pulse width of the gating signal at the third gating signal port D2 is twice the signal pulse width of the gating signal at the second gating signal port D1; the signal pulse width of the gating signal at the fourth gating signal port D3 is twice the signal pulse width of the gating signal at the third gating signal port D2; the signal pulse width of the gating signal at the fifth gating signal port D4 is twice the signal pulse width of the gating signal at the fourth gating signal port D3; the signal pulse width of the gating signal at the sixth gating signal port D5 is twice the signal pulse width of the gating signal at the fifth gating signal port D4; and the signal pulse width of the gating signal at the seventh gating signal port D6 is twice the signal pulse width of the gating signal at the sixth gating signal port D5.and the signal pulse width of the gating signal of the eighth gating signal terminal D7 is twice as large as the signal pulse width of the gating signal of the seventh gating signal terminal D6.

[0125] In an exemplary implementation, as in Fig. 8 and Fig. As shown in Figure 9, the non-display area 200 has a signal line area and a component area, and the gate driver circuit is located at least partially within the component area. The signal line area can comprise a first signal line area RS1, a second signal line area RS2, and a third signal line area RS3, arranged sequentially along a direction close to the display area 100, and the component area can comprise a first component area RT1, a second component area RT2, a third component area RT3, and a fourth component area RT4, arranged sequentially along the direction close to the display area 100.The first signal line area RS1 is located on a side of the first component area RT1 that is far from the display area 100, and the third signal line area RS3 is located on a side of the fourth component area RT4 that is close to the display area 100.

[0126] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the gating signal line group DL can be located in the first signal line area RS1.

[0127] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the gating sub-circuit 10 can be located in the first component area RT1.

[0128] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the second signal line area RS2 can be located between the first signal line area RS1 and the first component area RT1, or it can be located between the first component area RT1 and the second component area RT2. Fig. Figure 8 shows as an example the case where the second signal line area RS2 can be located between the first signal line area RS1 and the first component area RT1. Fig. Figure 9 is shown as an example of the case where the second signal line area RS2 is located between the first component area RT1 and the second component area RT2.

[0129] In an exemplary implementation, as in Fig. 8 and Fig. As shown in Figure 9, the length of the first signal line area RS1 along the second direction D2 is greater than the length of the second signal line area RS2 along the second direction D2.

[0130] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the length of the third signal line area RS3 along the second direction D2 is greater than the length of the second signal line area RS2 along the second direction D2.

[0131] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the non-display area 200 is further equipped with a clock signal line group CLK, and the gate driver circuit is electrically connected to the clock signal line group CLK. The clock signal line group CLK is located in the first signal line area RS1 and on the side of the gating signal line group DL furthest from the display area 100.

[0132] In an exemplary implementation, as described in the Fig. 8, Fig. 9 and Fig. As shown in Figure 11, the clock signal line group CLK comprises a control clock signal line group CLK2 and an output clock signal line group CLK1. The control clock signal line group CLK2 comprises a plurality of control clock signal lines, one control clock signal line extending along the first direction D1, and the plurality of control clock signal lines arranged along the second direction D2. The output clock signal line group CLK1 comprises a plurality of output clock signal lines, one output clock signal line extending along the first direction D1, and the plurality of output clock signal lines arranged along the second direction D2. The line width of an output clock signal line is larger than the line width of a control clock signal line and the line width of a gating signal line. Fig. 8, Fig. 9 and Fig. 11 are illustrated using the example of 16 output clock signal lines and 4 control clock signal lines.

[0133] In an exemplary implementation, as in Fig. As shown in Figure 11, the shift register comprises a plurality of control clock terminals and a plurality of output clock terminals, each of the plurality of control clock terminals being electrically connected to one of the control clock signal lines in the control clock signal line group CLK2, and each of the plurality of output clock terminals being electrically connected to one of the output clock signal lines in the output clock signal line group CLK1. For each shift register, the plurality of control clock terminals are electrically connected to a portion of the signal lines in the control clock signal group CLK2, and the plurality of output clock terminals are electrically connected to a portion of the signal lines in the output clock signal line group CLK1. Fig. 11 is illustrated by assuming the case that the shift register includes, as an example, three control clock connections, such as the first control clock connection CKA to the third control clock connection CKC, and four output clock connections, such as the first output clock connection CKE1 to the fourth output clock connection CKE4.

[0134] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the output clock signal line group CLK1 can be located on a side of the control clock signal line group CLK2 that is away from the display area 100.

[0135] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the non-display area 200 is further equipped with a first high-level power supply line VDDL1 and a second high-level power supply line VDDL2. The shift register comprises a first high-level power supply connection and a second high-level power supply connection. For each shift register, the first high-level power supply connection is electrically connected to the first high-level power supply line VDDL1, and the second high-level power supply connection is electrically connected to the second high-level power supply line VDDL2.

[0136] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the first high-level power supply line VDDL1 and the second high-level power supply line VDDL2 can be located in the second signal line area RS2.

[0137] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the line width of any power supply line of the first high-level power supply line VDDL1 and the second high-level power supply line VDDL2 is greater than the line width of any signal line located in the first signal line area RS1.

[0138] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the non-display area 200 is further equipped with a first low-level power supply line VGL1 and a second low-level power supply line VGL2. The shift register comprises a first low-level power supply connection and a second low-level power supply connection. For each shift register, the first low-level power supply connection is electrically connected to the first low-level power supply line VGL1, and the second low-level power supply connection is electrically connected to the second low-level power supply line VGL2.

[0139] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the first low-level power supply line VGL1 and the second low-level power supply line VGL2 are located in the third signal line area RS3, and the first low-level power supply line VGL1 is located on one side of the second low-level power supply line VGL2 that is away from the display area.

[0140] In an exemplary implementation, as in Fig. 8 and Fig. As shown in Figure 9, the line width of any power supply line of the first low-level power supply line VGL1 and the second low-level power supply line VGL2 is greater than the line width of any signal line located in the first signal line area RS1, and the line width of the first low-level power supply line VGL1 is less than the line width of the second low-level power supply line VGL2.

[0141] In an exemplary implementation, as in Fig. 8 and Fig. As shown in Figure 9, the length of the second component area RT2 along the second direction D2 is greater than the length of the first component area RT1 along the second direction D2, the length of the third component area RT3 along the second direction D2 is greater than or equal to the length of the second component area RT2 along the second direction D2, and the length of the fourth component area RT4 along the second direction D2 is greater than the length of the third component area RT3 along the second direction D2.

[0142] In an exemplary implementation, as used in conjunction with the Fig. 6, Fig. 8 and Fig. As shown in Figure 9, the shift register further comprises an input sub-circuit 40, a node-setting sub-circuit 20, and a preprocessing sub-circuit 30; the plurality of control clock connections includes: a first control clock connection to a third control clock connection. The node-setting sub-circuit 20 is electrically connected at least to the second high-level power supply connection, the second low-level power supply connection, the second control clock connection, the third control clock connection, the first node, and the third node, and is configured to provide a signal from the second high-level power supply connection or the second low-level power supply connection to the first node, controlling signals from the second control clock connection, the third control clock connection, and the third node.the input sub-circuit 40 is electrically connected at least to the third control clock terminal, the third node and the fifth node and is configured to provide a signal from the third control clock terminal to the fifth node under control of signals from the third node and the third control clock terminal; the preprocessing sub-circuit 30 is electrically connected at least to the second node, the third node, the fourth node, the first high-level power supply terminal and the first control clock terminal and is configured to provide a signal from the first control clock terminal or the first high-level power supply terminal to the third node and the fourth node under control of signals from the second node and the first control clock terminal;The gating sub-circuit 10 is furthermore electrically connected to the second control clock terminal and the second node and is configured to provide a signal from the second control clock terminal to the second node under control of signals from the plurality of gating signal terminals;

[0143] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the input subcircuit 40, the node setting subcircuit 20, and the preprocessing subcircuit 30 can be located in the second component area RT2 and arranged along the first direction D1, with the preprocessing subcircuit 30 located between the input subcircuit 40 and the node setting subcircuit 20. Locating the input subcircuit 40, the node setting subcircuit 20, and the preprocessing subcircuit 30 in the second component area RT2 and arranging them along the first direction D1 can reduce the length of the gate driver circuit along the second direction, thereby achieving a narrow border around the display substrate.

[0144] In an exemplary implementation, the preprocessing subcircuit 30 comprises a plurality of preprocessing transistors and a preprocessing capacitor. The preprocessing capacitor can replace the second capacitor C2 in Fig. 6 comprise, and the multitude of preprocessing transistors can include the eleventh transistor T11 to the fourteenth transistor T14 in Fig. The circuit comprises 6 components. The preprocessing capacitor is located on a side of the multitude of preprocessing transistors close to the node setting subcircuit 20. The preprocessing capacitor occupies a large area, which ensures the storage capacity of the preprocessing capacitor, thereby improving the reliability of the gate driver circuit.

[0145] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the shift register can also include a node separation subcircuit 50. The node separation subcircuit 50 is electrically connected to the third control clock terminal, the first high-level power supply terminal, the second low-level power supply terminal, the first node, the fifth node, the sixth node, the seventh node, the eighth node, and the ninth node, and is configured to provide a signal from the fifth node to the sixth node and the ninth node by controlling signals from the third control clock terminal and the first node, or to provide a signal from the first high-level power supply terminal to the fifth node by controlling a signal from the sixth node.

[0146] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the node separation sub-circuit 50 can be located in the third component area RT3.

[0147] In an exemplary implementation, the shift register further comprises an output sub-circuit 60. The output sub-circuit 60 is electrically connected at least to the plurality of output clock terminals, the first low-level power supply terminal, and the plurality of signal output terminals, and is configured to output a signal from a corresponding output clock terminal or the first low-level power supply terminal to the plurality of signal output terminals.

[0148] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the output sub-circuit 60 can be located in the fourth component area RT4.

[0149] In an exemplary implementation, the output sub-circuit 60 further comprises a plurality of output capacitors arranged in an array along the first direction D1 and the second direction D2. Arranging the plurality of output capacitors in an array along the first direction D1 and the second direction D2 can reduce the length of the gate driver circuitry along the second direction D2, thereby achieving a narrow border around the display substrate.

[0150] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the shift register further comprises a reset sub-circuit 80 and a noise reduction sub-circuit (not shown), and the plurality of control clock connections includes a first control clock connection through a third control clock connection. The reset sub-circuit 80 is electrically connected at least to the global reset signal connection, the third node, the fourth node, the first high-level power supply connection, and the second low-level power supply connection, and is configured to provide an electrical connection from the second low-level power supply connection to the third node, the fourth node, and the first high-level power supply connection under control of a signal from the global reset signal connection.The noise reduction sub-circuit is electrically connected at least to the first node, the second node, the ninth node, the first control clock terminal, the second control clock terminal, and the second low-level power supply terminal, and is configured to provide a signal from the second control clock terminal to the second node by controlling a signal from the first control clock terminal, and to provide a signal from the second low-level power supply terminal to the first node by controlling a signal from the ninth node.

[0151] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the reset sub-circuit 80 can be located in the second component area RT2, and the reset sub-circuit 80 and the preprocessing sub-circuit 30 are arranged along the second direction D2.

[0152] In an exemplary implementation, the noise reduction sub-circuit can be located in the second component area RT2, transistors in the noise reduction sub-circuit are small in size, and the position at which the noise reduction sub-circuit is placed can be any position, for example, the noise reduction sub-circuit can be placed between the reset sub-circuit 80 and the node separation sub-circuit 50, and arranged along the second direction D2 with the reset sub-circuit 80 and the node separation sub-circuit 50, or placed between the reset sub-circuit 80 and the node setting sub-circuit 20 and arranged along the first direction D1 with the reset sub-circuit 80 and the node setting sub-circuit 20, which is not limited in the present disclosure.

[0153] In an exemplary implementation, the non-display area 200 is further equipped with a reset signal line. The global reset signal connection of the shift register is electrically connected to the reset signal line.

[0154] In an exemplary implementation, the reset signal line can be located in the first signal line area RS1.

[0155] In an exemplary implementation, Fig. 12 A schematic diagram of a connection of a multitude of shift register groups. As in the Fig. 11 and Fig. As shown in Figure 12, the gate driver circuit comprises a plurality of shift register groups (hereinafter referred to as GOA groups), a shift register group comprises N1 shift register units (hereinafter referred to as GOA units), and a GOA unit comprises N2 shift registers GOA, N1, N2≥2. Fig. 11 shows as an example the case where one GOA unit comprises four GOAs, Fig. Figure 11 shows a GOA unit with a first shift register GOA(1) to a fourth shift register GOA(4), each GOA being connected to four rows of subpixels. GOA(1) is connected to a first row of subpixels R1 to a fourth row of subpixels R4, GOA(2) is connected to a fifth row of subpixels R5 to an eighth row of subpixels R8, GOA(3) is connected to a ninth row of subpixels R9 to a twelfth row of subpixels R12, and GOA(3) is connected to a thirteenth row of subpixels R13 to a sixteenth row of subpixels T16. Fig. Figure 12 shows a case in which the gate driver circuit is connected to 2160 rows of subpixels and the gate driver circuit comprises 17 GOA groups, such as GOA group (1) to GOA group (17).

[0156] In an exemplary implementation, as in Fig. As shown in Figure 11, a portion of the gating signal lines connected to a plurality of gating signal terminals of a shift register are called gating signal line units; gating signal lines contained in gating signal line units connected to any two shift registers located in the same shift register unit are the same, and at least one of the gating signal lines contained in gating signal line units connected to any two shift register units located in the same shift register group is different; and gating signal lines contained in gating signal line units connected to n1th shift register units located in different shift register groups are the same, 1 ≤ n1 ≤ n1. Fig. Figure 11 is shown for the case where, for all shift registers located in the same GOA unit, first gating signal connections D0 are electrically connected to a first gating signal line DL0, second gating signal connections D1 are electrically connected to a third gating signal line DL1, third gating signal connections D2 are electrically connected to a fifth gating signal line DL2, fourth gating signal connections D3 are electrically connected to a seventh gating signal line DL3, fifth gating signal connections D4 are electrically connected to a ninth gating signal line DL4, sixth gating signal connections D5 are electrically connected to an eleventh gating signal line DL5, seventh gating signal connections D6 are electrically connected to a thirteenth gating signal line DL6, and eighth gating signal connections D7 are electrically connected to a fifteenth gating signal line DL7 (example). Fig. Figure 12 is shown for the case where, for all shift registers in a GOA unit (1) of a first GOA group, the first gating signal connections D0 are electrically connected to a first gating signal line DL0, the second gating signal connections D1 are electrically connected to a third gating signal line DL1, the third gating signal connections D2 are electrically connected to a fifth gating signal line DL2, the fourth gating signal connections D3 are electrically connected to a seventh gating signal line DL3, the fifth gating signal connections D4 are electrically connected to a ninth gating signal line DL4, the sixth gating signal connections D5 are electrically connected to an eleventh gating signal line DL5, the seventh gating signal connections D6 are electrically connected to a thirteenth gating signal line DL6, and the eighth gating signal connections D7 are electrically connected to a fifteenth gating signal line DL7.and for a GOA unit (8) first gating signal terminals D0 are electrically connected to a second gating signal line DLN0, second gating signal terminals D1 are electrically connected to a fourth gating signal line DLN1, third gating signal terminals D2 are electrically connected to a sixth gating signal line DLN2, fourth gating signal terminals D3 are electrically connected to a seventh gating signal line DL3, fifth gating signal terminals D4 are electrically connected to a ninth gating signal line DL4, sixth gating signal terminals D5 are electrically connected to an eleventh gating signal line DL5, seventh gating signal terminals D6 are electrically connected to a thirteenth gating signal line DL6, and eighth gating signal terminals D7 are electrically connected to a fifteenth gating signal line DL7, to give an example. The present disclosure is not limited in this respect.

[0157] In an exemplary implementation, a portion of the control clock signal lines connected to a plurality of control clock terminals of a shift register are referred to as control clock signal line units, and a portion of the output clock signal lines connected to a plurality of output clock terminals of a shift register are referred to as output clock signal line units; at least one of the control clock signal lines contained in control clock signal line units connected to any two shift registers located in the same shift register unit is different, and at least one of the output clock signal lines contained in output clock signal line units connected to any two shift registers located in the same shift register unit is different;Control clock signal lines contained in control clock signal line units connected to n²-th shift registers located in different shift register units are equal, and output clock signal lines contained in output clock signal line units connected to n²-th shift registers located in different shift register units are equal, 1 ≤ n² ≤ n². In an exemplary implementation, ; Fig. 11 a case is presented in which, for GOA (1) a first control clock connection CKA is electrically connected to a first control clock signal line CLKA, a second control clock connection CKB is electrically connected to a second control clock signal line CLKB, a third control clock connection CKC is electrically connected to a third control clock signal line CLKC, a first output clock connection CKE1 is electrically connected to a first output clock signal line CLKE1, a second output clock connection CKE2 is electrically connected to a second output clock signal line CLKE2, a third output clock connection CKE3 is electrically connected to a third output clock signal line CLKE3, a fourth output clock connection CKE4 is electrically connected to a fourth output clock signal line CLKE4, for GOA (2) a first control clock connection CKA is electrically connected to the second control clock signal line CLKB,a second control clock connection CKB is electrically connected to the third control clock signal line CLKC, a third control clock connection CKC is electrically connected to a fourth control clock signal line CLKD, a first output clock connection CKE1 is electrically connected to a fifth output clock signal line CLKE5, a second output clock connection CKE2 is electrically connected to a sixth output clock signal line CLKE6, a third output clock connection CKE3 is electrically connected to a seventh output clock signal line CLKE7, a fourth output clock connection CKE4 is electrically connected to an eighth output clock signal line CLKE8, for GOA (3) a first control clock connection CKA is electrically connected to the third control clock signal line CLKC, a second control clock connection CKB is electrically connected to the fourth control clock signal line CLKD,a third control clock terminal CKC is electrically connected to the first control clock signal line CLKA, a first output clock terminal CKE1 is electrically connected to a ninth output clock signal line CLKE9, a second output clock terminal CKE2 is electrically connected to a tenth output clock signal line CLKE10, a third output clock terminal CKE3 is electrically connected to an eleventh output clock signal line CLKE11, a fourth output clock terminal CKE4 is electrically connected to a twelfth output clock signal line CLKE12, and for GOA (4), a first control clock terminal CKA is electrically connected to the fourth control clock signal line CLKD, a second control clock terminal CKB is electrically connected to the first control clock signal line CLKA, a third control clock terminal CKC is electrically connected to the second control clock signal line CLKB,For example, a first output clock terminal CKE1 is electrically connected to a thirteenth output clock signal line CLKE13, a second output clock terminal CKE2 is electrically connected to a fourteenth output clock signal line CLKE14, a third output clock terminal CKE3 is electrically connected to a fifteenth output clock signal line CLKE15, and a fourth output clock terminal CKE4 is electrically connected to a sixteenth output clock signal line CLKE16.

[0158] In an exemplary implementation, the number of shift registers contained in a shift register unit can be determined according to the number of combinations of gating signals available for access. If a shift register has two gating signal terminals, the shift register is accessed using those two gating signals. If four gating signals are available for access, two of which are mutually inverted signals, and the other two are mutually inverted signals, then the four gating signals can form four combinations for accessing shift registers, thus creating four shift register groups, and each shift register in each shift register group is accessed using the same combination of gating signals.

[0159] In an exemplary implementation, the number of shift registers contained in a shift register unit can be determined depending on the number of clock signals provided.

[0160] In an exemplary implementation, Fig. 13 A schematic cross-sectional view of a display substrate. As in Fig. As shown in Figure 13, the display substrate comprises a base substrate 11 and a driver structure layer provided on the base substrate, and the shift register comprises a plurality of transistors. The driver structure layer comprises a first conductive layer, a first insulating layer 12, a semiconductor layer, a second insulating layer 13, and a second conductive layer stacked on the base substrate. Fig. Figure 13 shows only one of the transistors. The transistor comprises an active pattern 21, a gate electrode 22, a first electrode 23, and a second electrode 24.

[0161] In an exemplary implementation, the semiconductor layer includes at least the active patterns of the multitude of transistors in the shift register.

[0162] In an exemplary implementation, the second conductive layer comprises at least gate electrodes, first electrodes and second electrodes of the plurality of transistors in the shift register.

[0163] In an exemplary implementation, the driver structure layer can also include a third insulation layer 14 and a planarization layer 15.

[0164] In an exemplary implementation, the first conductive layer includes at least one signal line L to which the transistors are connected. The signal line L can be any of the following: a gating signal line, a control clock signal line, an output clock signal line, a first high-level power supply line VDDL1, a second high-level power supply line VDDL2, a first low-level power supply line VGL1, and a second low-level power supply line VGL2.

[0165] In an exemplary implementation, any one of the gating signal line, control clock signal line, output clock signal line, first high-level power supply line VDDL1, second high-level power supply line VDDL2, first low-level power supply line VGL1 and second low-level power supply line VGL2 is of single-layer structure and is located in the first conductive layer, or is of two-layer structure and is located in the first conductive layer and the second conductive layer.

[0166] In an exemplary implementation, as in Fig. As shown in Figure 10, the non-display area is further provided with a first connecting line L1 and a second connecting line L2, and the first connecting line L1 and the second connecting line L2 may be located in the first conductive layer.

[0167] In an exemplary implementation, as in Fig. As shown in Figure 10, the first electrodes of all gating transistors located in the same gating sub-circuit are electrically connected to the first connecting line L1, and the second electrodes of a plurality of gating transistors located in the same gating sub-circuit are electrically connected to the second connecting line L2.

[0168] In an exemplary implementation, as in Fig. As shown in Figure 10, any gate electrode, first electrode or second electrode in any gating transistor extends at least partially along the second direction D2, and the first connecting line L1 and the second connecting line L2 extend along the first direction D1.

[0169] In an exemplary implementation, Fig. 14 A schematic partial view of a non-display area of ​​a display substrate. As in Fig. As shown in Figure 14, the non-display area 200 is further equipped with a plurality of control clock connection lines and a plurality of control clock electrostatic release circuits; the plurality of control clock connection lines correspond one-to-one to the plurality of control clock signal lines, and the plurality of control clock connection lines correspond one-to-one to the plurality of control clock electrostatic release circuits. Fig. Figure 14 shows the case in which the plurality of control clock connecting lines includes a first control clock connecting line AL1 to a fourth control clock connecting line AL4, and the plurality of control clock electrostatic release circuits includes a first control clock electrostatic release circuit A-ESD1 to a fourth control clock electrostatic release circuit A-ESD4.The first control clock connection line AL1 corresponds to the first control clock signal line CLKA, the second control clock connection line AL2 corresponds to the second control clock signal line CLKB, the third control clock connection line AL3 corresponds to the third control clock signal line CLKC, the fourth control clock connection line AL4 corresponds to the fourth control clock signal line CLKD, the first control clock connection line AL1 corresponds to the first control clock electrostatic release circuit A-ESD1, the second control clock connection line AL2 corresponds to the second control clock electrostatic release circuit A-ESD2, the third control clock connection line AL3 corresponds to the third control clock electrostatic release circuit A-ESD3, and the fourth control clock connection line AL4 corresponds to the fourth control clock electrostatic release circuit A-ESD4.

[0170] In an exemplary implementation, as in Fig. As shown in Figure 14, each control clock connection line is electrically connected to a corresponding control clock signal line and a corresponding control clock electrostatic release circuit. For example, the first control clock connection line AL1 is electrically connected to the first control clock signal line CLKA and the first control clock electrostatic release circuit A-ESD1; the second control clock connection line AL2 is electrically connected to both the second control clock signal line CLKB and the second control clock electrostatic release circuit A-ESD2; the third control clock connection line AL3 is electrically connected to both the third control clock signal line CLKC and the third control clock electrostatic release circuit A-ESD3; and the fourth control clock connection line AL4 is electrically connected to both the fourth control clock signal line CLKD and the fourth control clock electrostatic release circuit A-ESD4.

[0171] In an exemplary implementation, as in Fig. As shown in Figure 14, a control clock connection line comprises a first control clock connection part ALA extending along the second direction D2, and a second control clock connection part ALB extending along the first direction D1. In each control clock connection line, the first control clock connection part ALA is electrically connected to a corresponding control clock signal line and to the second control clock connection part ALB, and the second control clock connection part is electrically connected to a corresponding control clock electrostatic enable circuit.For example, the first control clock connection part ALA of the first control clock connection line AL1 is electrically connected to the first control clock signal line CLKA and the second control clock connection part ALB of the first control clock connection line AL1, and the second control clock connection part ALB of the first control clock connection line AL1 is electrically connected to the first control clock electrostatic release circuit A-ESD1.The first control clock connection part ALA of the second control clock connection line AL2 is electrically connected to the second control clock signal line CLKB and the second control clock connection part ALB of the second control clock connection line AL2, the second control clock connection part ALB of the second control clock connection line AL2 is electrically connected to the second control clock electrostatic release circuit A-ESD2, the first control clock connection part ALA of the third control clock connection line AL3 is electrically connected to the third control clock signal line CLKC and the second control clock connection part ALB of the third control clock connection line AL3, and the second control clock connection part ALB of the third control clock connection line AL3 is electrically connected to the third control clock electrostatic release circuit A-ESD3.The first control clock connection part ALA of the fourth control clock connection line AL4 is electrically connected to the fourth control clock signal line CLKD and the second control clock connection part ALB of the fourth control clock connection line AL4, and the second control clock connection part ALB of the fourth control clock connection line AL4 is electrically connected to the fourth control clock electrostatic release circuit A-ESD4.

[0172] In an exemplary implementation, as in Fig. As shown in Figure 14, the first control clock connection parts ALA are located in the second conductive layer, and the second control clock connection parts ALB are located in the first conductive layer.

[0173] In an exemplary implementation, as in Fig. As shown in Figure 14, the non-display area 200 is further equipped with a plurality of output clock connection lines and a plurality of output clock electrostatic release circuits; the plurality of output clock connection lines correspond one-to-one to the plurality of output clock signal lines, and the plurality of output clock connection lines correspond one-to-one to the plurality of output clock electrostatic release circuits. Fig. Figure 14 illustrates the case where the plurality of output clock interconnect lines includes a first output clock interconnect line EL1 to a sixteenth output clock interconnect line EL16, and the plurality of output clock electrostatic release circuits includes a first output clock electrostatic release circuit ESD1 to a sixteenth output clock electrostatic release circuit ESD16, as an example.The first output clock connection line EL1 corresponds to the first output clock signal line CLKE1, the second output clock connection line EL2 corresponds to the second output clock signal line CLKE2, the third output clock connection line EL3 corresponds to the third output clock signal line CLKE3, the fourth output clock connection line EL4 corresponds to the fourth output clock signal line CLKE4, etc. The first output clock connection line EL1 corresponds to the first output clock electrostatic release circuit ESD1, the second output clock connection line EL2 corresponds to the second output clock electrostatic release circuit ESD2, the third output clock connection line EL3 corresponds to the third output clock electrostatic release circuit ESD3, and the fourth output clock connection line EL4 corresponds to the fourth output clock electrostatic release circuit ESD4, and so on.

[0174] In an exemplary implementation, as in Fig. As shown in Figure 14, each output clock connection line is electrically connected to a corresponding output clock signal line and a corresponding output clock electrostatic release circuit. The first output clock connection line EL1 is electrically connected to the first output clock signal line CLKE1 and the first output clock electrostatic release circuit ESD1, the second output clock connection line EL2 is electrically connected to the second output clock signal line CLKE2 and the second output clock electrostatic release circuit ESD2, the third output clock connection line EL3 is electrically connected to the third output clock signal line CLKE3 and the third output clock electrostatic release circuit ESD3, the fourth output clock connection line EL4 is electrically connected to the fourth output clock signal line CLKE4 and the fourth output clock electrostatic release circuit ESD4, and so on.

[0175] In an exemplary implementation, as in Fig. As shown in Figure 14, an output clock connection line comprises a first output clock connection section ELA extending along the second direction D2, and a second output clock connection section ELB extending along the first direction D1. In each output clock connection line, the first output clock connection section is electrically connected to a corresponding output clock signal line and the second output clock connection section, and the second output clock connection section is electrically connected to a corresponding output clock electrostatic enable circuit. For example, the first output clock connection section ELA of the first output clock connection line EL1 is electrically connected to both the first output clock signal line CLKE1 and the second output clock connection section ELB of the first output clock connection line EL1.The second output clock connection part ELB of the first output clock connection line EL1 is electrically connected to the first output clock electrostatic release circuit ESD1; the first output clock connection part ELA of the second output clock connection line EL2 is electrically connected to both the second output clock signal line CLKE2 and the second output clock connection part ELB of the second output clock connection line EL2; the second output clock connection part ELB of the second output clock connection line EL2 is electrically connected to the second output clock electrostatic release circuit ESD2; the first output clock connection part ELA of the third output clock connection line EL3 is electrically connected to both the third output clock signal line CLKE3 and the second output clock connection part ELB of the third output clock connection line EL3.The second output clock connection part ELB of the third output clock connection line EL3 is electrically connected to the third output clock electrostatic release circuit ESD3, the first output clock connection part ELA of the fourth output clock connection line EL4 is electrically connected to the fourth output clock signal line CLKE4 and the second output clock connection part ELB of the fourth output clock connection line EL4, the second output clock connection part ELB of the fourth output clock connection line EL4 is electrically connected to the fourth output clock electrostatic release circuit ESD4, and so on.

[0176] In an exemplary implementation, as in Fig. As shown in Figure 14, first output clock interconnects ELA can be located in the second conductive layer, and second output clock interconnects ELB can be located in the first conductive layer.

[0177] In an exemplary implementation, as in Fig. As shown in Figure 14, the non-display area 200 is further equipped with four power supply connection lines and four power supply electrostatic release circuits.A first power supply connection line SL1 is electrically connected to the first high-level power supply line VDDL1 and a first power supply electrostatic release circuit S-ESD1; a second power supply connection line SL2 is electrically connected to the second high-level power supply line VDDL2 and a second power supply electrostatic release circuit S-ESD2; a third power supply connection line SL3 is electrically connected to the first low-level power supply line VGL1 and a third power supply electrostatic release circuit S-ESD3; a fourth power supply connection line SL4 is electrically connected to the second low-level power supply line VGL2 and a fourth power supply electrostatic release circuit S-ESD4.

[0178] In an exemplary implementation, as in Fig. As shown in Figure 14, a power supply connection line comprises a first power supply connection part SLA extending along the second direction D2, and a second power supply connection part SLB extending along the first direction D1.

[0179] In an exemplary implementation, as in Fig. As shown in Figure 14, for each power supply connection line, the first power supply connection part SLA is electrically connected to a connected power supply line and to the second power supply connection part SLB, and the second power supply connection part SLB is electrically connected to a connected power supply electrostatic release circuit. For example, the first power supply connection part SLA of the first power supply connection line SL1 is electrically connected to the first high-level power supply line VDDL1 and to the second power supply connection part SLB of the first power supply connection line SL1, and the second power supply connection part SLB of the first power supply connection line SL1 is electrically connected to the first power supply electrostatic release circuit S-ESD1.the first power supply connection part SLA of the second power supply connection line SL2 is electrically connected to the second high-level power supply line VDDL2 and the second power supply connection part SLB of the second power supply connection line SL2, the second power supply connection part SLB of the second power supply connection line SL2 is electrically connected to the second power supply electrostatic release circuit S-ESD2, the first power supply connection part SLA of the third power supply connection line SL3 is electrically connected to the first low-level power supply line VGL1 and the second power supply connection part SLB of the third power supply connection line SL3, the second power supply connection part SLB of the third power supply connection line SL3 is electrically connected to the third power supply electrostatic release circuit S-ESD3,the first power supply connection part SLA of the fourth power supply connection line SL4 is electrically connected to the second low-level power supply line VGL2 and the second power supply connection part SLB of the fourth power supply connection line SL4, and the second power supply connection part SLB of the fourth power supply connection line SL4 is electrically connected to the fourth power supply electrostatic release circuit S-ESD4.

[0180] In an exemplary implementation, as in Fig. As shown in Figure 14, the first power supply connection part SLA can be located in the second conductive layer, and the second power supply connection part SLB can be located in the first conductive layer.

[0181] In an exemplary implementation, as in the Fig. 8 and Fig. As shown in Figure 9, the distance H between a boundary of a first signal line located away from the display area and a boundary of a second signal line located near the display area is approximately 3,400 to 3,450 micrometers. The first signal line is a signal line in the first signal line area RS1 that is furthest from a boundary of the display area, as shown in Figure 9. Fig. 8 and Fig. As shown in Figure 9, the first signal line is the first output clock signal line CLKE1, and the second signal line is a signal line in the third signal line area RS3, which is closest to the edge of the display area, as shown in Figure 9. Fig. 8 and Fig. As shown in Figure 9, the second signal line is the second low-level power supply line VGL2.

[0182] For example, a distance H between a boundary of the first signal line, which is away from the display area, and a boundary of the second signal line, which is near the display area, is approximately 3430 micrometers.

[0183] In an exemplary implementation, the display substrate according to the present disclosure can be applied to a display device with a pixel driver circuit, such as an OLED, a quantum dot display (QLED), a light-emitting diode display (micro-LED or mini-LED) or a quantum dot light-emitting diode display (QDLED), which is not limited in the present disclosure.

[0184] In an exemplary implementation, the display substrate can further include a light-emitting structure layer located on a side of the driver structure layer furthest from the base substrate. The light-emitting structure layer can comprise an anode, a pixel definition layer, an organic light-emitting layer, and a cathode, wherein the anode is connected to one of the transistors in the driver structure layer via a through-hole, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of a corresponding color when the anode and cathode are driven.

[0185] In an exemplary implementation, the organic light emission layer can comprise an emission layer (EML) and one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary implementation, one or more of the hole injection layers, hole transport layers, electron block layers, hole block layers, electron transport layers, and electron injection layers of all subpixels can be connected to form a common, connected layer. The emitting layers of adjacent subpixels can slightly overlap or be isolated from each other.

[0186] In an exemplary implementation, the display substrate can further include an encapsulation layer located on the side of the light-emitting structure layer furthest from the base substrate. The encapsulation layer can comprise a first, second, and third encapsulation layer stacked on top of each other. The first and third encapsulation layers can be made of an inorganic material, the second encapsulation layer can be made of an organic material, and the second encapsulation layer is positioned between the first and third encapsulation layers, thus ensuring that no water vapor can penetrate the light-emitting structure layer from the outside.

[0187] In an exemplary implementation, the display substrate may further include a contact structure layer located on a side of the encapsulation structure layer away from the base substrate.The contact structure layer can comprise a first contact insulating layer arranged on the encapsulation structure layer, a first contact metal layer arranged on the first contact insulating layer, a second contact insulating layer covering the first contact metal layer, a second contact metal layer arranged on the second contact insulating layer, and a contact protection layer covering the second contact metal layer, wherein the first contact metal layer can comprise a plurality of bridge electrodes, the second contact metal layer can comprise a plurality of first contact electrodes and second contact electrodes, and a first contact electrode or a second contact electrode can be connected to a bridge electrode by a through-hole.

[0188] The following describes, by way of example, a manufacturing process for an indicator substrate. A “patterning process” mentioned in the present disclosure includes coating with photoresist, exposure with a mask, development, etching, removal of the photoresist, etc., for a metallic material, an inorganic material, or a transparent conductive material, and includes coating with organic material, exposure with a mask, development, etc., for an organic material. Deposition may be carried out by one or more of the methods sputtering, evaporation, and chemical vapor deposition; coating by one or more of the methods spray coating, centrifugal coating, and inkjet printing; and etching by one or more of the methods dry etching and wet etching, the present disclosure being no longer limited to these.A "thin film" refers to a layer of a thin film produced from a specific material on a base substrate by deposition, coating, or other processes. If the "thin film" does not require any patterning process during its manufacture, it may also be referred to as a "layer." If the "thin film" does require patterning during its manufacture, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. At least one "pattern" is contained within the layer that has undergone the patterning process.In the present disclosure, “A and B are arranged in the same layer” means that A and B are formed simultaneously by the same patterning process, and a “thickness” of a film layer is a dimension of the film layer in a direction perpendicular to a display substrate. In an exemplary implementation of the present disclosure, “an orthographic projection of B lying within a region of an orthographic projection of A” or “an orthographic projection of A encompassing an orthographic projection of B” means that a boundary of the orthographic projection of B falls within a region of a boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0189] (1) A pattern of a first conductive layer is formed. In an exemplary implementation, forming the pattern of the first conductive layer may involve depositing a first conductive thin film onto a base substrate, patterning the first conductive thin film by a patterning process to form the pattern of the first conductive layer, as described in Fig. 15 shown, include, and Fig. Figure 15 is a schematic diagram of a pattern of a first conductive layer in Fig. 10.

[0190] In an exemplary implementation, as in Fig. As shown in Figure 15, the pattern of the first conductive layer can include at least the following: a second high-level power supply line GVDD2; a first interconnecting line L1 and a second interconnecting line L2 located in each shift register.

[0191] In an exemplary implementation, as in Fig. As shown in Figure 15, the second high-level power supply line GVDD2 is located on one side of the first connecting line L1 that is away from the display area, and the second connecting line L2 is located on one side of the first connecting line L1 that is close to the display area.

[0192] In an exemplary implementation, as in Fig. As shown in Figure 15, the second high-level power supply line GVDD2 can have the form of a line with a main body section extending along the first direction D1. The second high-level power supply line GVDD2 is provided with a through-hole V0, which can reduce the coupling capacitance in the gate driver circuit and improve the reliability of the gate driver circuit.

[0193] In an exemplary implementation, as in Fig. As shown in Figure 15, the first connecting line L1 can have the form of a line with a main body section extending along the first direction D1.

[0194] In an exemplary implementation, as in Fig. As shown in Figure 15, the second connecting line L2 can have the form of a line with a main body section extending along the first direction D1. A groove K is provided on one side of the second connecting line L2 near the first connecting line L1.

[0195] In an exemplary implementation, the first connecting lines L1 and the second connecting lines L2 can be of equal or unequal width, straight or bent, which not only simplifies the layout of the shift register but can also reduce the parasitic capacitance between the signal lines, which is not limited here in the present disclosure.

[0196] (2) A pattern of semiconductor layer is formed. In an exemplary implementation, forming the pattern of the semiconductor layer may include: successively depositing a first insulating thin film and a semiconductor thin film onto the base substrate, and patterning the semiconductor thin film by a patterning process to form a first insulating layer covering the first conductive layer, and the pattern of the semiconductor layer arranged on the first insulating layer, as shown in Fig. 16 and Fig. As shown in 17, Fig. 16 A schematic view of a pattern of a semiconductor layer in Fig. 10 and Fig. Figure 17 is a schematic diagram, based on a pattern of a semiconductor in Fig. 10 was formed.

[0197] In an exemplary implementation, as in the Fig. 16 and Fig. As shown in Figure 17, the semiconductor layer pattern can contain at least one active pattern ACT21 of the second transistor up to one active pattern ACT91 of the ninth transistor, which are located in each shift register.

[0198] In an exemplary implementation, orthographic projections of the active pattern ACT21 of the second transistor to the active pattern ACT91 of the ninth transistor are located on the base substrate between an orthographic projection of the first interconnection line L1 on the base substrate and an orthographic projection of the second interconnection line L2 on the base substrate.

[0199] In an exemplary implementation, the active pattern ACT21 of the second transistor up to the active pattern ACT91 of the ninth transistor are individually provided and arranged sequentially along the first direction D1.

[0200] In an exemplary implementation, each active pattern of the active pattern ACT21 of the second transistor extends to the active pattern ACT91 of the ninth transistor along the first direction D1.

[0201] In an exemplary implementation, an active sample ACT81 of the eighth transistor is located within the groove of the first connecting line.

[0202] In an exemplary implementation, an active pattern of each transistor can include a first region, a second region, and a channel region located between the first region and the second region.In an exemplary implementation, the first region ACT21-1 and the second region ACT21-2 of the active pattern ACT21 of the second transistor, the first region ACT31-1 and the second region ACT31-2 of the active pattern ACT31 of the third transistor, the first region ACT41-1 and the second region ACT41-2 of the active pattern ACT41 of the fourth transistor, the first region ACT51-1 and the second region ACT51-2 of the active pattern ACT51 of the fifth transistor, the first region ACT61-1 and the second region ACT61-2 of the active pattern ACT61 of the sixth transistor, the first region ACT71-1 and the second region ACT71-2 of the active pattern ACT71 of the seventh transistor, the first region ACT81-1 and the second region ACT81-2 of the active pattern ACT81 of the eighth transistor, and the first region ACT91-1 and the second Area ACT91-2 of the active pattern ACT91 of the ninth transistor are provided individually.

[0203] (3) A pattern of a second insulating layer is formed. In an exemplary implementation, forming the pattern of the second insulating layer may include: depositing a second insulating thin film onto the base substrate on which the patterns mentioned above are formed; patterning the second insulating thin film using a patterning process to form a second insulating layer covering the pattern of the semiconductor layer; and a plurality of through holes provided on the second insulating layer, as shown in Fig. 18 shown, and Fig. 18 is a schematic diagram, based on a pattern of a second insulating layer in Fig. 10 was formed.

[0204] In an exemplary implementation, as in Fig. As shown in Figure 18, the plurality of through holes of the pattern of the second insulating layer includes at least a first through hole V1 to an eighteenth through hole V18, which are located in the shift register.

[0205] In an exemplary implementation, an orthographic projection of the first through-hole V1 on the base substrate lies within an area of ​​an orthographic projection of the first interconnection line on the base substrate, the first insulating layer and the second insulating layer within the first through-hole V1 are etched away to expose a surface of the first interconnection line, and the first through-hole V1 is configured such that a first electrode of the subsequently formed second transistor up to a first electrode of the subsequently formed ninth transistor is connected to the first interconnection line via the through-hole.

[0206] In an exemplary implementation, an orthographic projection of the second through-hole V2 on the base substrate lies within an area of ​​an orthographic projection of the second interconnect on the base substrate, the first insulating layer and the second insulating layer within the second through-hole V2 are etched away to expose a surface of the second interconnect, and the second through-hole V2 is configured such that a second electrode of the subsequently formed second transistor up to a second electrode of the subsequently formed ninth transistor is connected to the second interconnect via the through-hole.

[0207] In an exemplary implementation, an orthographic projection of the third through-hole V3 on the base substrate lies within a region of an orthographic projection of a first region of the active pattern of the second transistor on the base substrate, the third through-hole V3 exposes a surface of the first region of the active pattern of the second transistor, and the third through-hole V3 is configured such that a first electrode of the subsequently formed second transistor is connected to the first region of the active pattern of the second transistor via the through-hole.

[0208] In an exemplary implementation, an orthographic projection of the fourth through-hole V4 on the base substrate lies within a region of an orthographic projection of a second region of the active pattern of the second transistor on the base substrate, the fourth through-hole V4 exposes a surface of the second region of the active pattern of the second transistor, and the fourth through-hole V4 is configured such that a second electrode of the subsequently formed second transistor is connected via the through-hole to the second region of the active pattern of the second transistor.

[0209] In an exemplary implementation, an orthographic projection of the fifth through-hole V5 on the base substrate lies within a region of an orthographic projection of a first region of the active pattern of the third transistor on the base substrate, the fifth through-hole V5 exposes a surface of the first region of the active pattern of the third transistor, and the fifth through-hole V5 is configured such that a first electrode of the subsequently formed third transistor is connected via the through-hole to the first region of the active pattern of the third transistor.

[0210] In an exemplary implementation, an orthographic projection of the sixth through-hole V6 on the base substrate lies within a region of an orthographic projection of a second region of the active pattern of the third transistor on the base substrate, the sixth through-hole V6 exposes a surface of the second region of the active pattern of the third transistor, and the sixth through-hole V6 is configured such that a second electrode of the subsequently formed third transistor is connected via the through-hole to the second region of the active pattern of the third transistor.

[0211] In an exemplary implementation, an orthographic projection of the seventh through-hole V7 on the base substrate lies within a region of an orthographic projection of a first region of the active pattern of the fourth transistor on the base substrate, the seventh through-hole V7 exposes a surface of the first region of the active pattern of the fourth transistor, and the seventh through-hole V7 is configured such that a first electrode of the subsequently formed fourth transistor is connected via the through-hole to the first region of the active pattern of the fourth transistor.

[0212] In an exemplary implementation, an orthographic projection of the eighth through-hole V8 on the base substrate lies within a region of an orthographic projection of a second region of the active pattern of the fourth transistor on the base substrate, the eighth through-hole V8 exposes a surface of the second region of the active pattern of the fourth transistor, and the eighth through-hole V8 is configured such that a second electrode of the subsequently formed fourth transistor is connected to the second region of the active pattern of the fourth transistor via the through-hole.

[0213] In an exemplary implementation, an orthographic projection of the ninth through-hole V9 on the base substrate lies within a region of an orthographic projection of a first region of the active pattern of the fifth transistor on the base substrate, the ninth through-hole V9 exposes a surface of the first region of the active pattern of the fifth transistor, and the ninth through-hole V9 is configured such that a first electrode of the subsequently formed fifth transistor is connected via the through-hole to the first region of the active pattern of the fifth transistor.

[0214] In an exemplary implementation, an orthographic projection of the tenth through-hole V10 on the base substrate lies within a region of an orthographic projection of a second region of the active pattern of the fifth transistor on the base substrate, the tenth through-hole V10 exposes a surface of the second region of the active pattern of the fifth transistor, and the tenth through-hole V10 is configured such that a second electrode of the subsequently formed fifth transistor is connected via the through-hole to the second region of the active pattern of the fifth transistor.

[0215] In an exemplary implementation, an orthographic projection of the eleventh through-hole V11 on the base substrate lies within a region of an orthographic projection of a first region of the active pattern of the sixth transistor on the base substrate, the eleventh through-hole V11 exposes a surface of the first region of the active pattern of the sixth transistor, and the eleventh through-hole V11 is configured such that a first electrode of the subsequently formed sixth transistor is connected to the first region of the active pattern of the sixth transistor via the through-hole.

[0216] In an exemplary implementation, an orthographic projection of the twelfth through-hole V12 on the base substrate lies within a region of an orthographic projection of a second region of the active pattern of the sixth transistor on the base substrate, the twelfth through-hole V12 exposes a surface of the second region of the active pattern of the sixth transistor, and the twelfth through-hole V12 is configured such that a second electrode of the subsequently formed sixth transistor is connected via the through-hole to the second region of the active pattern of the sixth transistor.

[0217] In an exemplary implementation, an orthographic projection of the thirteenth through-hole V13 on the base substrate lies within a region of an orthographic projection of a first region of the active pattern of the seventh transistor on the base substrate, the thirteenth through-hole V13 exposes a surface of the first region of the active pattern of the seventh transistor, and the thirteenth through-hole V13 is configured such that a first electrode of the subsequently formed seventh transistor is connected via the through-hole to the first region of the active pattern of the seventh transistor.

[0218] In an exemplary implementation, an orthographic projection of the fourteenth through-hole V14 on the base substrate lies within a region of an orthographic projection of a second region of the active pattern of the seventh transistor on the base substrate, the fourteenth through-hole V14 exposes a surface of the second region of the active pattern of the seventh transistor, and the fourteenth through-hole V14 is configured such that a second electrode of the subsequently formed seventh transistor is connected via the through-hole to the second region of the active pattern of the seventh transistor.

[0219] In an exemplary implementation, an orthographic projection of the fifteenth through-hole V15 on the base substrate lies within a region of an orthographic projection of a first region of the active pattern of the eighth transistor on the base substrate, the fifteenth through-hole V15 exposes a surface of the first region of the active pattern of the eighth transistor, and the fifteenth through-hole V15 is configured such that a first electrode of the subsequently formed eighth transistor is connected via the through-hole to the first region of the active pattern of the eighth transistor.

[0220] In an exemplary implementation, an orthographic projection of the sixteenth through-hole V16 on the base substrate lies within a region of an orthographic projection of a second region of the active pattern of the eighth transistor on the base substrate, the sixteenth through-hole V16 exposes a surface of the second region of the active pattern of the eighth transistor, and the sixteenth through-hole V16 is configured such that a second electrode of the subsequently formed eighth transistor is connected to the second region of the active pattern of the eighth transistor via the through-hole.

[0221] In an exemplary implementation, an orthographic projection of the seventeenth through-hole V17 on the base substrate lies within a region of an orthographic projection of a first region of the active pattern of the ninth transistor on the base substrate, the seventeenth through-hole V17 exposes a surface of the first region of the active pattern of the ninth transistor, and the seventeenth through-hole V17 is configured such that a first electrode of the subsequently formed ninth transistor is connected to the first region of the active pattern of the ninth transistor via the through-hole.

[0222] In an exemplary implementation, an orthographic projection of the eighteenth through-hole V18 on the base substrate lies within a region of an orthographic projection of a second region of the active pattern of the ninth transistor on the base substrate, the eighteenth through-hole V18 exposes a surface of the second region of the active pattern of the ninth transistor, and the eighteenth through-hole V18 is configured such that a second electrode of the subsequently formed ninth transistor is connected to the second region of the active pattern of the ninth transistor via the through-hole.

[0223] In an exemplary implementation, as in Fig. As shown in Figure 18, the number of first through holes V1 is multiple, and several first through holes are arranged along the first direction D1. The number of second through holes V2 is multiple, and at least some of the second through holes V2 are arranged along the first direction D1. Some of the second through holes are arranged along the first direction D1, including the fifteenth and sixteenth through holes.

[0224] In an exemplary implementation, as in Fig. As shown in Figure 18, the third through hole V3 to the eighteenth through hole V18 are arranged along the first direction D1, and the number of each of the third through hole V3 to the eighteenth through hole V18 can be one.

[0225] (4) A pattern of a second conductive layer is formed. In an exemplary implementation, forming the pattern of the second conductive layer may involve: depositing a second conductive thin film onto the base substrate, patterning the second conductive thin film by a patterning process to form the pattern of the second conductive layer, as shown in Fig. 19 and Fig. 20 is shown, is Fig. 19 a schematic diagram of a pattern of a second conductive layer in Fig. 10, and Fig. Figure 20 is a schematic diagram, based on a pattern of a second conductive layer in Fig. 10 is formed.

[0226] In an exemplary implementation, as in the Fig. 19 and Fig.As shown in Figure 20, the pattern of the second conductive layer comprises at least one gate electrode Gate22, one first electrode SD23 and one second electrode S24 of the second transistor, one gate electrode Gate32, one first electrode SD33 and one second electrode SD34 of the third transistor, one gate electrode SD42, one first electrode SD43 and one second electrode S44 of the fourth transistor, one gate electrode SD52, one first electrode SD53 and one second electrode S54 of the fifth transistor, one gate electrode SD62, one first electrode SD63 and one second electrode S64 of the sixth transistor, one gate electrode SD72, one first electrode SD73 and one second electrode S74 of the seventh transistor, one gate electrode SD82, one first electrode SD83 and one second electrode S84 of the eighth transistor, one gate electrode SD92, one first electrode SD93 and one second electrode S94 of the ninth transistor in each shift register.

[0227] In an exemplary implementation, each gate electrode, from the gate electrode Gate22 of the second transistor to the gate electrode Gate82 of the eighth transistor, has the shape of a strip and extends along the second direction D2.

[0228] In an exemplary implementation, the gate electrode Gate92 of the ninth transistor can have the shape of a bend curve and be in a “┘” shape.

[0229] In an exemplary implementation, the first electrode SD23 of the second transistor can be in the form of a strip and extend at least partially along the second direction D2. The first electrode SD23 of the second transistor is connected to the first interconnect via the first through-hole and to the first region of the active structure of the second transistor via the third through-hole.

[0230] In an exemplary implementation, the second electrode SD24 of the second transistor can have the shape of a “┐”. The second electrode SD24 of the second transistor is connected to the second interconnect via the second through-hole and to the second region of the active structure of the second transistor via the fourth through-hole.

[0231] In an exemplary implementation, the first electrode SD33 of the third transistor can be in the form of a strip and extend at least partially along the second direction D2. The first electrode SD33 of the third transistor is connected to the first interconnect via the first through-hole and to the first region of the active structure of the third transistor via the fifth through-hole.

[0232] In an exemplary implementation, the second electrode SD34 of the third transistor can have the shape of a “┐”. The second electrode SD34 of the third transistor is connected to the second interconnect via the second through-hole and to the second region of the active structure of the third transistor via the sixth through-hole.

[0233] In an exemplary implementation, the first electrode SD43 of the fourth transistor can be in the form of a strip and extend at least partially along the second direction D2. The first electrode SD43 of the fourth transistor is connected to the first interconnect via the first through-hole and to the first region of the active pattern of the fourth transistor via the seventh through-hole.

[0234] In an exemplary implementation, a second electrode SD44 of the fourth transistor can have the shape of a bending curve.The second electrode SD44 of the fourth transistor comprises a first electrode junction SD441, a second electrode junction SD442 and a third electrode junction SD443, wherein the first electrode junction SD441 and the third electrode junction SD443 extend along the second direction D2, the second electrode junction SD442 extends along the first direction D1, the first electrode junction SD441 and the third electrode junction SD443 are located on opposite sides of the second electrode junction SD442, the first electrode junction SD441 is provided at a right angle to the second electrode junction SD442 and the third electrode junction SD443 is provided at a right angle to the second electrode junction SD442.The second electrode SD44 of the fourth transistor is connected to the second connecting line via the second through-hole and to the second area of ​​the active pattern of the fourth transistor via the eighth through-hole.

[0235] In an exemplary implementation, the first electrode SD53 of the fifth transistor can be in the form of a strip and extend at least partially along the second direction D2. The first electrode SD53 of the fifth transistor is connected to the first interconnect via the first through-hole and to the first region of the active structure of the fifth transistor via the ninth through-hole.

[0236] In an exemplary implementation, a second electrode SD54 of the fifth transistor comprises a fourth electrode junction SD541, a fifth electrode junction SD542, and a sixth electrode junction SD543, wherein the fourth electrode junction SD541 and the sixth electrode junction SD543 extend along the second direction D2, the fifth electrode junction SD542 extends along the first direction D1, the fourth electrode junction SD541 is located on one side of the fifth electrode junction SD542 away from the display area, the sixth electrode junction SD543 is located on one side of the fifth electrode junction SD542 near the display area, and the fourth electrode junction SD541 is provided at a right angle to the fifth electrode junction SD542.and one end of the sixth electrode connection SD543 is connected to the center of the fifth electrode connection SD542. The second electrode SD54 of the fifth transistor is connected via the second through-hole to the second connection line and via the tenth through-hole to the second area of ​​the active structure of the fifth transistor.

[0237] In an exemplary implementation, the first electrode SD63 of the sixth transistor can be in the form of a strip and extend at least partially along the second direction D2. The first electrode SD63 of the sixth transistor is connected to the first interconnect via the first through-hole and to the first region of the active structure of the sixth transistor via the eleventh through-hole.

[0238] In an exemplary implementation, the second electrode SD64 of the sixth transistor can have the shape of a “┐”. The second electrode SD64 of the sixth transistor is connected to the second interconnect via the second through-hole and to the second region of the active pattern of the sixth transistor via the twelfth through-hole.

[0239] In an exemplary implementation, the first electrode SD73 of the seventh transistor can be in the form of a strip and extend at least partially along the second direction D2. The first electrode SD73 of the seventh transistor is connected to the first interconnect via the first through-hole and to the first region of the active structure of the seventh transistor via the thirteenth through-hole.

[0240] In an exemplary implementation, the second electrode SD74 of the seventh transistor can have the shape of a “┐”. The second electrode SD74 of the seventh transistor is connected to the second interconnect via the second through-hole and to the second region of the active pattern of the seventh transistor via the fourteenth through-hole.

[0241] In an exemplary implementation, the first electrode SD83 of the eighth transistor can have the form of a strip and extends at least partially along the second direction D2. The first electrode SD83 of the eighth transistor is connected to the first interconnect via the first through-hole and to the first region of the active structure of the eighth transistor via the fifteenth through-hole.

[0242] In an exemplary implementation, the second electrode SD84 of the eighth transistor can be block-shaped and extend along the second direction D2. The second electrode SD84 of the eighth transistor is connected to the second interconnect via the second through-hole and to the second region of the eighth transistor's active pattern via the sixteenth through-hole.

[0243] In an exemplary implementation, the first electrode SD93 of the ninth transistor can have the shape of a "┘". The first electrode SD93 of the ninth transistor is connected to the first interconnect via the first through-hole and to the first active region of the ninth transistor via the seventeenth through-hole.

[0244] In an exemplary implementation, the second electrode SD94 of the ninth transistor can be block-shaped and extend along the second direction D2. The second electrode SD94 of the ninth transistor is connected to the second interconnect via the second through-hole and to the second region of the ninth transistor's active pattern via the eighteenth through-hole.

[0245] (5) A pattern of planarization layer is formed. In an exemplary implementation, forming the planarization layer pattern may include: depositing a third insulating thin film onto the base substrate on which the above-mentioned patterns are formed, and coating a planarization thin film, patterning the third insulating thin film and the planarization thin film by a patterning process to form a pattern of a third insulating layer and the planarization layer pattern.

[0246] In an exemplary implementation, the semiconductor layer can be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, a tungsten and indium oxide, a tungsten, indium, and zinc oxide, a titanium and indium oxide, a titanium, indium, and tin oxide, an indium and zinc oxide, a silicon, indium, and tin oxide, or an indium or gallium and zinc oxide. The metal oxide layer can be a single layer, a double layer, or a multiple layer.

[0247] In an exemplary implementation, the first conductive layer and the second conductive layer can consist of a metallic material, such as one or more of the metals silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), and can have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0248] In an exemplary implementation, the first insulating layer, the second insulating layer, and the third insulating layer can consist of one or more of the following materials: silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer.

[0249] In one exemplary implementation, the planarization layer can be made from an organic material, such as resin.

[0250] In an exemplary implementation, after the preparation of the driver structure layer is complete, a light-emitting structure layer is prepared on the driver structure layer, and a preparation process of the light-emitting structure layer may include the following operations.

[0251] Deposition of a conductive anode thin film onto the base substrate on which the aforementioned patterns are formed; patterning of the conductive anode thin film using a patterning process to form a pattern of a conductive anode layer arranged on a second planarization layer; deposition of a pixel definition thin film onto the base substrate on which the aforementioned patterns are formed; patterning of the pixel definition thin film by a patterning process to form a pixel definition layer pattern that exposes the pattern of the conductive anode layer; coating of the base substrate on which the pixel definition layer pattern is formed with an organic light-emitting material; patterning of the organic light-emitting material by a patterning process to form an organic structural layer pattern; deposition of a conductive cathode thin film onto the base substrate.on which the organic material layer pattern is formed, and patterns of the conductive cathode thin film through a patterning process to form the conductive cathode layer.

[0252] Up to now, the light-emitting structural layer has been produced on the base substrate.

[0253] In an exemplary implementation, the conductive anode layer comprises at least a plurality of anode patterns. The plurality of anode patterns can include an anode of a first light-emitting device, an anode of a second light-emitting device, an anode of a third light-emitting device, and an anode of a fourth light-emitting device, wherein the anode of the first light-emitting device is located at a red subpixel that emits red light, the anode of the second light-emitting device can be located at a blue subpixel that emits blue light, the anode of the third light-emitting device can be located at a first green subpixel that emits green light, and the anode of the fourth light-emitting device can be located at a second green subpixel that emits green light.

[0254] In an exemplary implementation, the anode of the first light-emitting device and the anode of the second light-emitting device can be arranged alternately in the first direction, and the anode of the third light-emitting device and the anode of the fourth light-emitting device can be arranged alternately in the first direction. Alternatively, the anode of the first light-emitting device and the anode of the second light-emitting device can be arranged alternately in the second direction, and the anode of the third light-emitting device and the anode of the fourth light-emitting device can be arranged alternately in the second direction.

[0255] In an exemplary implementation, the conductive anode layer can consist of a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can consist of a multi-layer composite structure, such as ITO / Ag / ITO.

[0256] In an exemplary implementation, the organic structural layer may contain at least: an organic light-emitting layer of the light-emitting device.

[0257] In an exemplary implementation, the conductive cathode layer can include at least the cathodes of a variety of light-emitting devices.

[0258] In an exemplary implementation, the cathode layer can be made of a metallic material, such as one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy of the aforementioned metals, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), and can have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the fourth conductive layer can consist of a three-layer stacked structure of titanium, aluminum, and titanium.

[0259] In an exemplary implementation, the subsequent preparation process may include: the formation of an encapsulation structure layer on the conductive cathode layer. This encapsulation structure layer may comprise a first, second, and third encapsulation layer stacked on top of each other. The first and third encapsulation layers may be made of an inorganic material, while the second encapsulation layer may be made of an organic material. The second encapsulation layer is positioned between the first and third encapsulation layers to ensure that no water vapor from the outside can penetrate the light-emitting structure layer.

[0260] The display substrate according to the embodiment of the present disclosure can be applied to a display product with any resolution.

[0261] One embodiment of the present disclosure further provides a display device which may include: a display substrate.

[0262] The display substrate is the display substrate according to one of the aforementioned embodiments and has similar implementation principles and implementation effects, which are not repeated here.

[0263] In an exemplary implementation, the display device can be any product or component with a display function, such as a portable device, a mobile phone, a tablet computer, a television, a display, a laptop, a digital photo frame, and a navigation device.

[0264] The drawings of the embodiments of the present disclosure relate only to structures included in the embodiments of the present disclosure, and other structures may refer to a general design.

[0265] For clarity, the thickness and size of a layer or microstructure in the accompanying drawings used to describe the embodiments of this disclosure have been enlarged. When an element, such as a layer, film, region, or substrate, is described as lying "on" or "under" another element, the element may lie "directly" on or "under" the other element, or an intermediate element may be present.

[0266] Although the implementations of the present disclosure are disclosed above, the contents are merely implementations intended to aid in understanding the present disclosure and are not meant to limit it. Any person skilled in the art in the field of the present disclosure may make any modifications and variations in the manner and details of the implementation without departing from the spirit and scope of the present disclosure. However, the scope of protection of the present disclosure should be limited to the scope defined by the attached claims.

Claims

Display substrate with a display area and a non-display area, the latter being provided on and surrounding at least one side of the display area, wherein the display area is provided with pixel driver circuits arranged in an array, and the non-display area is provided with a gate driver circuit and a gating signal line group, the gating signal line group comprising: a plurality of gating signal lines, and the gate driver circuit is electrically connected to each of the pixel driver circuits and the gating signal line group; one gating signal line extends along a first direction, the plurality of gating signal lines are arranged along a second direction, and the first direction and the second direction intersect;The gate driver circuit comprises a plurality of shift registers; a shift register comprises: a gating sub-circuit, wherein the gating sub-circuit is electrically connected to a portion of the gating signal lines in the gating signal line group; the gating sub-circuit comprises a plurality of gating transistors; for each shift register, the plurality of gating transistors in the gating sub-circuit are arranged along the first direction. Display substrate according to claim 1, wherein the shift register comprises M gating signal terminals, and the gating signal line group comprises 2M gating signal lines; an m-th gating signal terminal is electrically connected to a (2m-1)-th gating signal line or a 2m-th gating signal line, and a signal of the (2m-1)-th gating signal line and a signal of the 2m-th gating signal line are mutually inverted signals, wherein 1≤m≤M. Display substrate according to claim 1, wherein the non-display area comprises a signal line area and a component area, the gate driver circuit is located at least partially in the component area, the signal line area comprises a first signal line area, a second signal line area and a third signal line area arranged successively along a direction close to the display area, and the component area comprises a first component area, a second component area, a third component area and a fourth component area arranged successively along the direction close to the display area; the first signal line area is located on a side of the first component area furthest from the display area, and the third signal line area is located on a side of the fourth component area close to the display area;The gating signal line group is located in the first signal line area, and the gating sub-circuit is located in the first component area. Display substrate according to claim 3, wherein the second signal line area is located between the first signal line area and the first component area or between the first component area and the second component area. Display substrate according to claim 3 or 4, wherein a length of the first signal line area along the second direction is greater than a length of the second signal line area along the second direction, and a length of the third signal line area along the second direction is greater than the length of the second signal line area along the second direction. Display substrate according to claim 3 or 4, wherein the non-display area is further provided with a clock signal line group, and the gate driver circuit is electrically connected to the clock signal line group; the clock signal line group is located in the first signal line area and is located on a side of the gating signal line group away from the display area. Display substrate according to claim 3 or 4, wherein the clock signal line group comprises a control clock signal line group and an output clock signal line group; the control clock signal line group comprises a plurality of control clock signal lines, one control clock signal line extends along the first direction, the plurality of control clock signal lines are arranged along the second direction, the output clock signal line group comprises a plurality of output clock signal lines, one output clock signal line extends along the first direction, the plurality of output clock signal lines are arranged along the second direction, and the line width of the output clock signal line is greater than the line width of the control clock signal line and the line width of the gating signal line;The shift register comprises a plurality of control clock terminals and a plurality of output clock terminals; each of the plurality of control clock terminals is electrically connected to one of the control clock signal lines in the control clock signal line group; and each of the plurality of output clock terminals is electrically connected to one of the output clock signal lines in the output clock signal line group; for each shift register, the plurality of control clock terminals are electrically connected to a portion of the signal lines in a control clock signal group, and the plurality of output clock terminals are electrically connected to a portion of the signal lines in the output clock signal line group; the output clock signal line group is located on a side of the control clock signal line group away from the display area. Display substrate according to claim 3 or 4, wherein the non-display area is further provided with a first high-level power supply line and a second high-level power supply line; the shift register comprises: a first high-level power supply connection and a second high-level power supply connection; for each shift register, the first high-level power supply connection is electrically connected to the first high-level power supply line, and the second high-level power supply connection is electrically connected to the second high-level power supply line; the first high-level power supply line and the second high-level power supply line are located in the second signal line area; a line width of one of the first high-level power supply lines and the second high-level power supply line is greater than a line width of a signal line located in the first signal line area. Display substrate according to claim 3 or 4, wherein the non-display area is further provided with a first low-level power supply line and a second low-level power supply line; the shift register comprises: a first low-level power supply connection and a second low-level power supply connection; for each shift register, the first low-level power supply connection is electrically connected to the first low-level power supply line, and the second low-level power supply connection is electrically connected to the second low-level power supply line; the first low-level power supply line and the second low-level power supply line are located in the third signal line area, and the first low-level power supply line is located on a side of the second low-level power supply line remote from the display area;a conductor width of one of the first low-level power supply lines and the second low-level power supply line is greater than a conductor width of any signal line located in the first signal line area, and a conductor width of the first low-level power supply line is less than a conductor width of the second low-level power supply line. Display substrate according to claim 3 or 4, wherein a length of the second component area along the second direction is greater than a length of the first component area along the second direction, a length of the third component area along the second direction is greater than the length of the second component area along the second direction, and a length of the fourth component area along the second direction is greater than the length of the third component area along the second direction. Display substrate according to claim 3 or 4, wherein the shift register further comprises an input sub-circuit, a node setting sub-circuit and a preprocessing sub-circuit; the plurality of control clock connections comprise: a first control clock connection to a third control clock connection; the node setting sub-circuit is electrically connected at least to a second high-level power supply connection, a second low-level power supply connection, a second control clock connection, a third control clock connection, a first node and a third node and is configured to provide a signal from the second high-level power supply connection or the second low-level power supply connection to the first node by controlling signals from the second control clock connection, the third control clock connection and the third node;the input sub-circuit is electrically connected at least to the third control clock terminal, the third node, and a fifth node, and is configured to provide a signal from the third control clock terminal to the fifth node while controlling signals from the third node and the third control clock terminal; the preprocessing sub-circuit is electrically connected at least to a second node, the third node, a fourth node, a first high-level power supply terminal, and the first control clock terminal, and is configured to provide a signal from the first control clock terminal to the fourth node and a signal from the fourth node to the first high-level power supply terminal while controlling a signal from the second node;the gating sub-circuit is furthermore electrically connected to the second control clock terminal and the second node and is configured to provide a signal from the second control clock terminal to the second node while controlling signals from a plurality of gating signal terminals; and the input sub-circuit, the node setting sub-circuit, and the preprocessing sub-circuit are located in the second component area and are arranged along the first direction, with the preprocessing sub-circuit located between the input sub-circuit and the node setting sub-circuit. Display substrate according to claim 11, wherein the preprocessing sub-circuit comprises a plurality of preprocessing transistors and a preprocessing capacitor; the preprocessing capacitor is located on a side of the plurality of preprocessing transistors close to the node setting sub-circuit. Display substrate according to claim 3 or 4, wherein the shift register further comprises a node separation subcircuit; the node separation subcircuit is electrically connected to a third control clock terminal, a first high-level power supply terminal, a second low-level power supply terminal, a first node, a fifth node, a sixth node, a seventh node, an eighth node and a ninth node, and is configured to provide a signal from the fifth node to each of the sixth nodes through the ninth node under control of signals from the third control clock terminal and the first node, or to provide a signal from the first high-level power supply terminal to the fifth node under control of a signal from the sixth node; and the node separation subcircuit is located in the third component area. Display substrate according to claim 3 or 4, wherein the shift register further comprises an output sub-circuit; the output sub-circuit is at least electrically connected to a plurality of output clock terminals, a first low-level power supply terminal and a plurality of signal output terminals, and is configured to output a signal from a corresponding output clock terminal or the first low-level power supply terminal to the plurality of signal output terminals; and the output sub-circuit is located in the fourth component area. Display substrate according to claim 14, wherein the output sub-circuit further comprises a plurality of output capacitors arranged in an array along the first direction and the second direction. Display substrate according to claim 3 or 4, wherein the shift register further comprises a reset sub-circuit and a noise reduction sub-circuit, and the plurality of control clock connections comprise: a first control clock connection to a third control clock connection; the reset sub-circuit is electrically connected at least to a global reset signal connection, a third node, a fourth node, a first high-level power supply connection and a second low-level power supply connection and is configured to provide an electrical connection from the second low-level power supply connection to the third node, the fourth node and the first high-level power supply connection under control of a signal from the global reset signal connection;The noise reduction sub-circuit is electrically connected to at least one first node, one second node, one ninth node, one first control clock terminal, one second control clock terminal, and one second low-level power supply terminal, and is configured to provide a signal from the second control clock terminal to the second node by controlling a signal from the first control clock terminal, and to provide a signal from the second low-level power supply terminal to the first node by controlling a signal from the ninth node; and the reset sub-circuit and the noise reduction sub-circuit are located in the second component area, and the reset sub-circuit and the preprocessing sub-circuit are arranged along the second direction. Display substrate according to claim 16, wherein the non-display area is further provided with a reset signal line; a global reset signal connection of the shift register is electrically connected to the reset signal line, and the reset signal line is located in the first signal line area. Display substrate according to claim 3 or 4, wherein the gate driver circuit comprises: a plurality of shift register groups, a shift register group comprising N1 shift register units, and a shift register unit comprising N2 shift registers, wherein N1, N2 ≥ 2; a portion of the gating signal lines connected to a plurality of gating signal terminals of a shift register being called gating signal line units; gating signal lines contained in gating signal line units connected to any two shift registers located in an identical shift register unit are identical, and at least one of the gating signal lines contained in gating signal line units connected to any two shift register units located in an identical shift register group is different;and gating signal lines contained in gating signal line units connected to n1th shift register units located in different shift register groups are equal, where 1≤n1≤N1.; Display substrate according to claim 18, wherein a portion of the control clock signal lines connected to a plurality of control clock terminals of a shift register are called control clock signal line units, and a portion of the output clock signal lines connected to a plurality of output clock terminals of a shift register are called output clock signal line units; at least one of the control clock signal lines contained in control clock signal line units connected to any two shift registers located in an identical shift register unit is different, and at least one of the output clock signal lines contained in output clock signal line units connected to any two shift registers located in an identical shift register unit is different;Control clock signal lines contained in control clock signal line units connected to n2-th shift registers located in different shift register units are identical, and output clock signal lines contained in output clock signal line units connected to n2-th shift registers located in different shift register units are identical, where 1≤n2≤N2.; Display substrate according to claim 1, comprising: a base substrate and a driver structure layer arranged on the base substrate, wherein the shift register comprises a plurality of transistors; the driver structure layer comprises: a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer and a second conductive layer stacked on the base substrate; the semiconductor layer comprises at least: active patterns of a plurality of transistors in the shift register; and the second conductive layer comprises at least: gate electrodes, first electrodes and second electrodes of the plurality of transistors in the shift register. Display substrate according to claim 20, further comprising: a gating signal line, a control clock signal line, an output clock signal line, a first high-level power supply line, a second high-level power supply line, a first low-level power supply line and a second low-level power supply line, wherein each signal line of the gating signal line, the control clock signal line, the output clock signal line, the first high-level power supply line, the second high-level power supply line, the first low-level power supply line and the second low-level power supply line consists of a single-layer structure and is located in the first conductive layer, or consists of a double-layer structure and is located in the first conductive layer and the second conductive layer. Display substrate according to claim 20, wherein the non-display area is further provided with a first connecting line and a second connecting line, and the first connecting line and the second connecting line are located in the first conductive layer; first electrodes of all gating transistors located in an identical gating sub-circuit are electrically connected to the first connecting line, and second electrodes of a plurality of gating transistors located in an identical gating sub-circuit are electrically connected to the second connecting line; and each electrode of a gate electrode, a first electrode, and a second electrode in each gating transistor extends at least partially along the second direction, and the first connecting line and the second connecting line extend along the first direction. Display substrate according to claim 20, wherein the non-display area is further provided with a plurality of control clock connection lines and a plurality of control clock electrostatic release circuits; the plurality of control clock connection lines correspond one-to-one with a plurality of control clock signal lines, and the plurality of control clock connection lines correspond one-to-one with the plurality of control clock electrostatic release circuits; each control clock connection line is electrically connected to a corresponding control clock signal line and a corresponding control clock electrostatic release circuit. Display substrate according to claim 23, wherein the control clock connection line comprises a first control clock connection part extending along the second direction and a second control clock connection part extending along the first direction; for each control clock connection line, the first control clock connection part is electrically connected to a corresponding control clock signal line and the second control clock connection part, and the second control clock connection part is electrically connected to a corresponding control clock electrostatic release circuit; and the first control clock connection part is located in the second conductive layer, and the second control clock connection part is located in the first conductive layer. Display substrate according to claim 20, wherein the non-display area is further provided with a plurality of output clock connection lines and a plurality of output clock electrostatic release circuits; the plurality of output clock connection lines correspond one-to-one with a plurality of output clock signal lines, and the plurality of output clock connection lines correspond one-to-one with the plurality of output clock electrostatic release circuits; each output clock connection line is electrically connected to a corresponding output clock signal line and a corresponding output clock electrostatic release circuit. Display substrate according to claim 25, wherein the output clock interconnect comprises a first output clock interconnect extending along the second direction and a second output clock interconnect extending along the first direction; for each output clock interconnect, the first output clock interconnect is electrically connected to a corresponding output clock signal line and the second output clock interconnect, and the second output clock interconnect is electrically connected to a corresponding output clock electrostatic release circuit; and the first output clock interconnect is located in the second conductive layer, and the second output clock interconnect is located in the first conductive layer. Display substrate according to claim 20, wherein the non-display area is further provided with four power supply connection lines and four power supply electrostatic release circuits, a first power supply connection line being electrically connected to a first high-level power supply line and a first power supply electrostatic release circuit; a second power supply connection line being electrically connected to a second high-level power supply line and a second power supply electrostatic release circuit; a third power supply connection line being electrically connected to a first low-level power supply line and a third power supply electrostatic release circuit; and a fourth power supply connection line being electrically connected to a second low-level power supply line and a fourth power supply electrostatic release circuit. Display substrate according to claim 27, wherein a power supply connection line comprises a first power supply connection part extending along the second direction and a second power supply connection part extending along the first direction; for each power supply connection line, the first power supply connection part is electrically connected to an attached power supply line and the second power supply connection part, and the second power supply connection part is electrically connected to an attached power supply electrostatic release circuit; and the first power supply connection part is located in the second conductive layer, and the second power supply connection part is located in the first conductive layer. Display substrate according to claim 2, wherein the distance between a boundary of a first signal line located farther from the display area and a boundary of a second signal line located near the display area is approximately 3400 micrometers to 3450 micrometers; the first signal line is a signal line in a first signal line area that is furthest from a boundary of the display area, and the second signal line is a signal line in a third signal line area that is closest to the boundary of the display area. Display substrate according to claim 1, wherein signals from at least two gating signal lines are mutually inverted signals during part of a time period. Display device comprising: the display substrate according to any one of claims 1 to 30.

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