Power amplification system, power amplifier circuit and power amplification method

Abstract

A power amplification system (20) has the following features: a power amplifier (11) configured to amplify a first WLAN signal in a first frequency band; a power amplifier (12) configured to amplify a second WLAN signal in a second frequency band higher than the first frequency band; and a (DPD) circuit (311) configured to pre-distort the second WLAN signal without pre-distorting the first WLAN signal.

Description

Technical field

[0001] The present invention relates to a power amplification system, a power amplifier circuit and a power amplification method. background

[0002] Patent document 1 discloses a circuit for amplifying 2.4 GHz band signals and 5 GHz band signals of a wireless local area network (WLAN). Citation list patent document

[0003] Patent document 1: Unexamined Japanese patent application publication no. 2019-140671 Brief description of the invention: Technical problem

[0004] In WLAN, the modulation bandwidth (channel bandwidth) and bit rate of digital modulation techniques are increasing, and the next-generation standard (IEEE 802.11be) plans to use a modulation bandwidth of 320 MHz and a modulation technique of 4096 quadrature amplitude modulation (QAM). As the modulation bandwidth and bit rate of modulation techniques increase, so does the performance index (e.g., error vector magnitude (EVM)) required for communication devices, and it is difficult to meet the required performance with state-of-the-art technologies. Furthermore, it is also desirable to reduce the power consumption of communication devices.

[0005] Accordingly, the present invention provides a power amplification system, a power amplifier circuit and a power amplification method that can effectively improve the quality of a transmission signal while suppressing an increase in power consumption. Solution to the problem

[0006] According to an embodiment of the present invention, a power amplification system comprises a first power amplifier configured to amplify a first wireless local area network signal in a first frequency band, a second power amplifier configured to amplify a second wireless local area network signal in a second frequency band higher than the first frequency band, and a first digital pre-distortion circuit configured to pre-distort the second wireless local area network signal and not to pre-distort the first wireless local area network signal.

[0007] According to an embodiment of the present invention, a power amplifier circuit comprises a first power amplifier configured to amplify a first wireless local area network (WINO) signal in a first frequency band, and a second power amplifier configured to amplify a second WINO signal in a second frequency band higher than the first frequency band. The second WINO signal is pre-distorted, and the first WINO signal is not pre-distorted.

[0008] According to an embodiment of the present invention, a power amplification method comprises amplifying a first wireless local area network signal in a first frequency band that is not pre-distorted, pre-distorting a second wireless local area network signal in a second frequency band that is higher than the first frequency band, and amplifying the pre-distorted second wireless local area network signal. Advantageous effects of the invention

[0009] According to the power amplification system and so forth of an embodiment of the present invention, the quality of a transmission signal can be effectively improved while suppressing an increase in power consumption. Brief description of the drawings Fig. Figure 1A is a graph illustrating an example of changes in a power supply voltage in an Average Power Tracking (APT) mode. Fig. Figure 1B is a graph illustrating an example of changes in a power supply voltage in an analog envelope tracking (A-ET) mode. Fig. 1C is a graph illustrating an example of changes in a power supply voltage in a digital envelope tracking (D-ET) mode. Fig. Figure 2 is a circuit configuration diagram of a communication device according to an exemplary embodiment. Fig. Figure 3 is a circuit configuration diagram of a digital envelope tracer according to an exemplary embodiment. Fig. Figure 4 is a flowchart illustrating a power amplification method according to an exemplary embodiment. Description of exemplary implementations

[0010] Exemplary embodiments of the present invention are described in detail below with reference to the drawings. The exemplary embodiments described below each illustrate a comprehensive or specific example of the present invention. The numerical values, shapes, materials, components, arrangements of the components, the ways in which the components are connected, and so on, described in the following exemplary embodiments are merely examples and are not intended to limit the present invention.

[0011] It is noted that the drawings are schematic drawings in which certain elements are emphasized or omitted, or their proportions are suitably adjusted to illustrate the present invention. The drawings are not necessarily illustrative in a strictly accurate manner, and the actual shapes, positional relationships, and proportions may differ from those shown in the drawings. Configurations that are essentially the same may be designated by the same symbols in the drawings, and any repeated description thereof may be omitted or simplified.

[0012] In the circuit configuration of the present invention, the meaning of "connected" includes not only direct connections via connection terminals and / or wiring conductors, but also electrical connections realized through other circuit elements. "Directly connected" means a direct connection through a connection terminal and / or a wiring conductor, without the insertion of another circuit element. "C is connected between A and B" means that one end of C is connected to A and the other end of C is connected to B, and C is arranged in series in a path connecting A and B. A "path connecting A and B" means a path consisting of a conductor that electrically connects A and B.

[0013] In the following description, "termination" means a point where a conductor ends within an element. If the impedance of a conductor between elements is sufficiently low, a termination is also interpreted not only as a single point, but also as any point along the conductor between elements, or even the entire conductor.

[0014] Furthermore, expressions that specify the relationships between elements, such as "parallel" and "perpendicular", expressions that specify the shape of elements, such as "rectangular", and numerical ranges do not only express a strict meaning, but are intended to encompass essentially equivalent ranges, for example, differences of about a few percent.

[0015] First, a tracking mode is described as a technology for amplifying a high-frequency signal with high efficiency. In this mode, a power amplifier is supplied with a power supply voltage that is dynamically adjusted over time based on the high-frequency signal. Unlike a fixed-voltage mode, the tracking mode is a mode in which the power supply voltage applied to the power amplifier is dynamically adjusted. Furthermore, the fixed-voltage mode is a mode in which the power supply voltage applied to the power amplifier is not dynamically adjusted. There are several types of tracking modes, but here the APT mode, the A-ET mode, and the D-ET mode are discussed with reference to... Fig. 1A to 1C described. In Fig. From 1A to 1C, the horizontal axis represents time and the vertical axis represents voltage. Furthermore, the thick solid line represents the power supply voltage and the thin solid line (waveform) represents the modulated signal.

[0016] Fig. Figure 1A is a graph illustrating an example of power supply voltage changes in APT mode. APT mode is a mode in which the power supply voltage is varied to several discrete voltage levels in units of a frame, based on the average power.

[0017] A frame is a unit representing a high-frequency signal (modulated signal). For example, in fifth-generation New Radio (5G NR) and Long Term Evolution (LTE), a frame comprises ten subframes, each subframe contains multiple slots, and each slot consists of multiple symbols. The subframe length is 1 ms, and the frame length is 10 ms.

[0018] It is noted that a mode in which the voltage level is changed in units of a frame or in units larger than a frame based on average power is referred to as an APT mode and is distinguished from a mode in which the voltage level is changed in units smaller than a frame (for example, in units of subframes, slots, or symbols).

[0019] Fig. Figure 1B is a graph illustrating an example of power supply voltage changes in A-ET mode. A-ET mode is a mode in which the power supply voltage is continuously changed based on an envelope signal. In A-ET mode, the envelope of the modulated signal is tracked.

[0020] The envelope signal is a signal that represents the envelope of the modulated signal. The envelope value is expressed, for example, as the square root of (I). 2 + Q 2 ) expressed here. Here, (I, Q) represents a constellation point. A constellation point is a point that represents a digitally modulated signal in a constellation diagram. (I, Q) is determined, for example, by a baseband integrated circuit (BBIC) based on transmission information.

[0021] Fig. Figure 1C is a graph illustrating an example of power supply voltage changes in D-ET mode. D-ET mode is a mode in which the power supply voltage is changed to multiple discrete voltage levels within a frame based on an envelope signal. In D-ET mode, the envelope of the modulated signal is tracked. Examples of implementation

[0022] Examples of implementation are described below. 1 Circuit configuration of the communication device 60

[0023] First, the circuit configuration of a communication device 60 according to this embodiment is described with reference to Fig. 2 described. Fig. Figure 2 is a circuit configuration diagram of the communication device 60 according to this embodiment.

[0024] It is noted that Fig. 2 is an exemplary circuit configuration and the communication device 60 can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the communication device 60 provided below should not be interpreted as limiting.

[0025] The communication device 60 according to this embodiment corresponds to a user equipment (UE) in a cellular network and is typically a mobile phone, a smartphone, a tablet computer, a wearable device, or the like. The communication device 60 can be an Internet of Things (IoT) sensor device, a medical / healthcare device, a car, an unmanned aerial vehicle (UAV) (a so-called drone), or an automated guided vehicle (AGV). The communication device 60 can also function as a base station (BS) in a cellular network.

[0026] As in Fig. As illustrated in Figure 2, the communication device 60 comprises a power amplifier circuit 10, radio frequency integrated circuits (RFICs) 31 to 33, BBICs 41 to 43, antennas 51 to 55, a DC power source 70, a digital envelope tracker (D-ET) 71, and an average power tracker (APT) 72. A power amplification system 20 comprises the power amplifier circuit 10, the RFICs 31 to 33, the DC power source 70, the digital envelope tracker 71, and the average power tracker 72.

[0027] The power amplifier circuit 10 is connected between the RFICs 31 to 33 and the antennas 51 to 55. The power amplifier circuit 10 is further connected to the DC power source 70, the digital envelope follower 71, and the average power follower 72. In particular, the power amplifier circuit 10 comprises power amplifiers 11 to 15.

[0028] Power amplifier 11 is an example of a first power amplifier and is connected between RFIC 31 and antenna 51. Power amplifier 11 is also connected to DC power source 70 and is supplied with a fixed power supply voltage Vcc1. This means that a fixed-voltage mode is applied to power amplifier 11. This allows power amplifier 11 to amplify a 2.4 GHz band WLAN radio frequency signal received by RFIC 31 using the power supply voltage Vcc1 provided by DC power source 70.

[0029] Power amplifier 12 is an example of a second power amplifier and is connected between RFIC 31 and antenna 52. Furthermore, power amplifier 12 is connected to DC power source 70, and a fixed power supply voltage Vcc2 is supplied to power amplifier 12. This means that a fixed-voltage mode is applied to power amplifier 12. This allows power amplifier 12 to amplify a 5-7 GHz band WLAN radio frequency signal received by RFIC 31 using the power supply voltage Vcc2 provided by DC power source 70.

[0030] Power amplifier 13 is an example of a third power amplifier and is connected between RFIC 31 and antenna 53. Furthermore, power amplifier 13 is connected to a DC power source 70 and is supplied with a fixed power supply voltage Vcc3. This means that a fixed-voltage mode is applied to power amplifier 13. This allows power amplifier 13 to amplify a 60 GHz WLAN radio frequency signal received by RFIC 31 using the power supply voltage Vcc3 provided by the DC power source 70. It should be noted that power amplifier 13 is not necessarily included in power amplifier circuit 10.

[0031] Power amplifier 14 is an example of a fourth power amplifier and is connected between RFIC 32 and antenna 54. Furthermore, power amplifier 14 is connected to digital envelope follower 71 and is supplied with a power supply voltage Vcc4 that dynamically changes to several discrete voltages. This means that a D-ET mode is applied to power amplifier 14. This allows power amplifier 14 to amplify a high-frequency signal from frequency range 1 (FR1) of a cellular network, received by RFIC 32, using the power supply voltage Vcc4 provided by digital envelope follower 71. FR1 is a frequency range of 410 to 7125 MHz and can be described as a sub-6 band. It should be noted that power amplifier 14 is not necessarily included in power amplifier circuit 10.

[0032] Power amplifier 15 is an example of a fourth power amplifier and is connected between RFIC 33 and antenna 55. Power amplifier 15 is further connected to average power follower 72 and is supplied with a power supply voltage Vcc5 that dynamically changes to several discrete voltages. This means that an APT mode is applied to power amplifier 15. This allows power amplifier 15 to amplify a high-frequency signal from frequency range 2 (FR2) of a cellular network, received by RFIC 33, using the power supply voltage Vcc5 provided by average power follower 72. FR2 is a frequency range from 24250 to 52600 MHz and can be described as a millimeter-wave band. It should be noted that power amplifier 15 is not necessarily included in power amplifier circuit 10.

[0033] RFICs 31 to 33 are examples of signal processing circuits that process high-frequency signals (WLAN signals and cellular network signals). RFIC 31 can receive digital IQ signals from BBIC 41 and supply WLAN signals to power amplifiers 11 to 13. Specifically, RFIC 31 can supply a 2.4 GHz WLAN signal (for example, a first WLAN signal) to power amplifier 11, can supply at least one WLAN signal (an example of a second WLAN signal) in the 5 GHz, 6 GHz, or 7 GHz band to power amplifier 12, and can supply a 60 GHz WLAN signal (an example of a third WLAN signal) to power amplifier 13. RFIC 32 can receive digital IQ signals from BBIC 42 and supply a cellular network FR1 signal to power amplifier 14. The RFIC 33 can receive digital IQ signals from the BBIC 43 and deliver a cellular network FR2 signal to the power amplifier 15.It is noted that RFICs 32 and 33 are not necessarily included in the power amplification system 20.

[0034] BBICs 41 to 43 are baseband signal processing circuits that perform signal processing using a frequency band lower than that of the high-frequency signals. For example, BBICs 41 to 43 can digitally modulate an image signal for display and / or a bit sequence representing an audio signal for communication via a loudspeaker, generating digital IQ signals. The generated digital IQ signals are supplied to RFICs 31 to 33. It should be noted that BBICs 41 to 43 are not necessarily included in the communication device 60.

[0035] Antennas 51 to 55 can transmit the high-frequency signals, which are amplified by the power amplifier circuit 10, to outside the communication device 60. Some or all of antennas 51 to 55 are not necessarily contained within the communication device 60.

[0036] The DC power source 70 can supply a DC voltage to the power amplifiers 11 to 13, the digital envelope follower 71, and the average power follower 72. The DC power source 70 can be, for example, a rechargeable battery, but is not limited to this. The DC power source 70 is not necessarily included in the power amplification system 20.

[0037] The digital envelope follower 71 can supply the power supply voltage Vcc4 to the power amplifier 14 in D-ET mode. Specifically, the digital envelope follower 71 can generate several discrete voltages from the input voltage provided by the DC power source 70 and selectively supply at least one of the generated discrete voltages to the power amplifier 14. At this time, at least one of the discrete voltages is selected based on the envelope of the FR1 signal of the cellular network. This allows the digital envelope follower 71 to dynamically change the power supply voltage Vcc4, for example, within a frame, based on the envelope of the FR1 signal of the cellular network. It should be noted that the digital envelope follower 71 is not necessarily included in the power amplification system 20.

[0038] The average power tracker 72 can supply the power amplifier 15 with the power supply voltage Vcc5 in D-APT mode. Specifically, the average power tracker 72 can convert the input voltage provided by the DC power source 70 into a modified voltage and supply the modified voltage to the power amplifier 15. At this time, the level of the modified voltage is determined based on the average power of the FR2 signal of the cellular network. This allows the average power tracker 72 to dynamically change the power supply voltage Vcc5, for example, in units of one or more frames, based on the average power of the FR2 signal of the cellular network. It should be noted that the average power tracker 72 is not necessarily included in the power amplification system 20. 2 Internal configuration of RFICs 31 to 33

[0039] The internal configurations of RFICs 31 to 33 are described with reference to Fig. 2 described.

[0040] The RFIC 31 includes a digital pre-distortion (DPD) circuit 311, a digital-to-analog converter (DAC) 312 and a quadrature modulator 313.

[0041] The DPD circuit 311 is an example of a first DPD circuit and can pre-distort digital IQ signals provided by the BBIC 41 using a mathematical model for DPD. For example, the DPD circuit 311 can generate pre-distorted digital IQ signals from the digital IQ signals. The pre-distorted digital IQ signals are supplied to the DAC 312.

[0042] It is noted that the DPD circuit 311 can skip the DPD processing. In this case, the DPD circuit 311 can supply the digital IQ signals provided by the BBIC 41 (that is, digital IQ signals that have not been pre-distorted) to the DAC 312.

[0043] In this embodiment, the DPD circuit 311 performs DPD processing on the digital IQ signals for WLAN signals in the 5-7 GHz and 60 GHz bands and skips DPD processing on the digital IQ signals for WLAN signals in the 2.4 GHz band. In other words, the DPD circuit 311 does not pre-distort a WLAN signal in the 2.4 GHz band, but it does pre-distort WLAN signals in the 5-7 GHz and 60 GHz bands.

[0044] The DAC 312 can convert digital IQ signals provided by the DPD circuit 311 into analog IQ signals. The converted analog IQ signals are supplied to the quadrature modulator 313. It should be noted that the DAC 312 can be a state-of-the-art DAC and need not be specifically limited.

[0045] The quadrature modulator 313 can generate WLAN signals by performing quadrature modulation and upconversion on analog IQ signals provided by the DAC 312. The generated WLAN signals are supplied to the power amplifiers 11 to 13. The quadrature modulator 313 can be a state-of-the-art quadrature modulator and does not need to be specifically limited.

[0046] The RFIC 32 comprises a DPD circuit 321, a DAC 322, and a quadrature modulator 323. The RFIC 32 may also include a (not illustrated) control unit that controls the digital envelope follower 71. Some or all of the functions of the RFIC 32 as a control unit can be implemented outside the RFIC 32.

[0047] The DPD circuit 321 is an example of a second DPD circuit and can pre-distort digital IQ signals provided by the BBIC 42 using a mathematical model for DPD. For example, the DPD circuit 321 can generate pre-distorted digital IQ signals from the digital IQ signals. The pre-distorted digital IQ signals are then supplied to the DAC 322.

[0048] The DAC 322 can convert the digital IQ signal provided by the DPD circuit 321 into analog IQ signals. These converted analog IQ signals are then supplied to the quadrature modulator 323. The DAC 322 can be a state-of-the-art DAC and does not need to be specifically limited.

[0049] The quadrature modulator 323 can generate the FR1 signal of the cellular network by performing quadrature modulation and upconversion on the analog IQ signals provided by the DAC 322. The generated FR1 signal is supplied to the power amplifier 14. The quadrature modulator 323 can be a state-of-the-art quadrature modulator and need not be specifically limited.

[0050] The RFIC 33 comprises a DPD circuit 331, a DAC 332, and a quadrature modulator 333. The RFIC 33 may also include a control unit (not illustrated) that controls the average power tracker 72. Some or all of the functions of the RFIC 33 as a control unit may be implemented outside the RFIC 33.

[0051] The DPD circuit 331 is an example of a second DPD circuit and can pre-distort digital IQ signals provided by the BBIC 43 using a mathematical model for DPD. For example, the DPD circuit 331 can generate pre-distorted digital IQ signals from the digital IQ signals. The pre-distorted digital IQ signals are then supplied to the DAC 332.

[0052] The DAC 332 can convert the digital IQ signals provided by the DPD circuit 331 into analog IQ signals. These converted analog IQ signals are then supplied to the quadrature modulator 333. It should be noted that the DAC 332 can be a state-of-the-art DAC and need not be specifically limited in its functionality.

[0053] The quadrature modulator 333 can generate the FR2 signal of the cellular network by performing quadrature modulation and upconversion on the analog IQ signals provided by the DAC 332. The generated FR2 signal is supplied to the power amplifier 15. It is noted that the quadrature modulator 333 can be a state-of-the-art quadrature modulator and need not be specifically limited.

[0054] The circuit configurations of RFICs 31 to 33, which are in Fig. The circuits illustrated in Figure 2 are merely examples, and RFICs 31 to 33 are not limited to these configurations. For example, some or all of the DPD circuit 311, the DAC 312, and the quadrature modulator 313 are not necessarily included in RFIC 31. For example, the DPD circuit 311 may be included in BBIC 41. Likewise, RFICs 32 and 33 do not necessarily include some or all of the DPD circuit, the DAC, and the quadrature modulator.

[0055] Next, mathematical models used for DPD in DPD circuits 311, 321, and 331 are described. In this embodiment, the mathematical model used for DPD can be a first mathematical model that incorporates a memory effect, or a second mathematical model that does not.

[0056] The memory effect is defined as a change in the distortion of a power amplifier caused by a past input signal. Therefore, the first mathematical model models not only the distortion caused by a current input signal, but also the change in distortion caused by a past input signal. Consequently, nonlinear distortion can be reduced more effectively with the first mathematical model than with the second, but the computational load is increased.

[0057] Therefore, in this embodiment, to effectively reduce nonlinear distortion with a lower computational load, switching between the first and second mathematical models is performed depending on a predetermined condition. For example, switching between the first and second mathematical models is based on the bit rate of the modulation scheme and / or the modulation bandwidth. The bit rate of the modulation scheme refers to the number of bits per symbol. For example, the bit rate of 256QAM is 8 bits / symbol. It should be noted that switching between the first and second mathematical models is not critical, and either the first or the second mathematical model can be used in a fixed manner.

[0058] Next, a specific example of the second mathematical model, which does not include the memory effect, will be described. [Equation 1] x[n]=∑i=0N−1cir[n]|r[n]|i x[n]: pre-distorted signal r[n]: original input signal c i : DPD coefficients N: Polynomial order

[0059] Equation (1) above is an example of a polynomial used in the second mathematical model. The mathematical model using equation (1) is referred to as a non-memory polynomial model. In equation (1), for a current input signal r[n], the input signal is multiplied by a power of the input signal. The polynomial order N and the DPD coefficient c iare parameters of the polynomial model without memory effect and can be determined experimentally and / or empirically in advance and are stored in advance in (not illustrated) memories, which are contained in, for example, RFICs 31 to 33.

[0060] In equation (1), increasing the polynomial order N is expected to reduce the nonlinear distortion, but there are concerns that this will increase the computational load. It is noted that equation (1) does not account for the memory effect, and therefore there is a limit to the reduction of nonlinear distortion in the polynomial model without the memory effect.

[0061] Next, a specific example of a first mathematical model that incorporates the memory effect will be described. [Equation 2] x[n]=∑i=0N−1∑q=0Qcqir[n−q]|r[n−q]|i x[n]: pre-distorted signal r[n]: original input signal c qi: DPD coefficients Q: Memory depth N: Polynomial order

[0062] Equation (2) above is an example of a polynomial used in the first mathematical model. The mathematical model using equation (2) is called a memory polynomial model (MPM). In equation (2), for each of the input signals r[nq] from past Q to current 0, the input signal is multiplied by a power of the input signal. The polynomial order N, the memory depth Q, and the DPD coefficient c are given by... qi These are parameters of the MPM and can be determined experimentally and / or empirically in advance and are stored in advance in (not illustrated) memories, which are contained, for example, in RFICs 31 to 33.

[0063] In equation (2), increasing the polynomial order N and memory depth Q is expected to reduce nonlinear distortion, but there are concerns about an increase in the number of parameters, an increase in computational load, and a decrease in convergence if the DPD coefficient c qi is determined. [Equation 3] x[n]=∑i=0N−1∑q=0Qcqir[n−q]|r[n−q]|i⋯(3−1) +∑i=1Nd∑m=1Md∑q=0QDdqmir[n−q]|r[n−q−m]|i⋯(3−2) +∑i=1Ne∑m=1Me∑q=0Qeeqmir[n−q]|r[n−q+m]|i⋯(3−3) x[n]: pre-distorted signal r [n]: original input signal c qi , d qmi , e qmi : DPD coefficients Q: Synchronization memory depth N: Synchronization order Q d : Wake memory depth M d Maximum overrun N d : Follow-up order Q e Lead-in memory depth M e Maximum lead time N e Preliminary order

[0064] Equation (3) above is an example of a polynomial used in the first mathematical model. The mathematical model in which equation (3) is used is called a generalized memory polynomial model (GMP). In equation (3), a synchronization term (3-1) is combined with a lagging term (3-2) and an antecedent term (3-3). The synchronization term (3-1) is the same as the term in equation (2) for MPM. In the lagging term (3-2), the input signal is multiplied by a power raised to a previous input signal. In the antecedent term (3-3), the input signal is multiplied by a power raised to a future input signal. The orders N, N d and N e , the memory depth Q and the DPD coefficient c qi , d qmi and e qmiThe respective terms are parameters of the GMP and can be determined in advance experimentally and / or empirically and are stored in advance in (not illustrated) memories, which are contained, for example, in RFICs 31 to 33.

[0065] In equation (3), if the storage depths Q, Q d , Q e and the cross-sections M d and M e Increasing the respective terms is expected to reduce the nonlinear distortion.

[0066] However, there are concerns regarding an increase in the number of parameters, an increase in the computational load, and a decrease in convergence when the DPD coefficients c qi , d qmi and e qmi be determined.

[0067] The reduction of nonlinear distortion increases in order of the no-memory polynomial model, the MPM, and the GMP, but the number of parameters and the computational load (i.e., the power consumption) also increase with each reduction. In other words, the GMP can reduce nonlinear distortion more effectively than the MPM and the no-memory polynomial model, and the MPM can reduce nonlinear distortion more effectively than the no-memory polynomial model. Conversely, the no-memory polynomial model can reduce the computational load more effectively than the MPM and GMP, and the MPM can reduce the computational load more effectively than the GMP. Furthermore, the no-memory polynomial model can reduce the amount of memory used to store parameters more effectively than the MPM and GMP, and the MPM can reduce the amount of memory used to store parameters more effectively than the GMP.

[0068] It is noted that the first mathematical model is not restricted to the MPM and GMP. This means that the first mathematical model can use any mathematical expression other than equations (2) and (3) above. Furthermore, the second mathematical model is not restricted to the polynomial model without memory effect. This means that the second mathematical model can use any mathematical expression other than equation (1) above. 3 Circuit configuration of the digital envelope tracer 71

[0069] Next, the circuit configuration of the digital envelope tracer 71 will be described with reference to Fig. 3 described. Fig. Figure 3 is a circuit configuration diagram of the digital envelope follower 71 according to this embodiment.

[0070] It is noted that Fig. Figure 3 illustrates an exemplary circuit configuration, and the digital envelope tracker 71 can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the digital envelope tracker 71 provided below should not be interpreted as limiting.

[0071] The digital envelope follower 71 includes a pre-regulator circuit 710, a switching capacitor circuit 720, a supply modulator 730, filter circuits 741 and 742, switches S56 and S57 and a digital control circuit 760.

[0072] The 710 pre-regulator circuit can convert an input voltage provided by a (not illustrated) DC power source into a matched voltage using a power inductor. The 710 pre-regulator circuit includes a power inductor and switches. The power inductor is an inductor used to boost and / or reduce a direct current (DC) voltage. The power inductor is connected in series with a DC path. The power inductor can also be connected between the DC path and ground (i.e., in parallel with the DC path). Such a 710 pre-regulator circuit can be called a magnetic regulator or a DC / DC converter. It should be noted that the 710 pre-regulator circuit does not necessarily include a power inductor.

[0073] The switching capacitor circuit 720 comprises several capacitors and several switches and can generate several discrete voltages, each with a discrete voltage level, from the voltage provided by the pre-regulator circuit 710. The switching capacitor circuit 720 can also be referred to as a switching capacitor voltage ladder.

[0074] The supply modulator 730 can selectively output at least one of the several discrete voltages generated by the switching capacitor circuit 720 to the power amplifier 14.

[0075] Filter circuits 741 and 742 can attenuate noise from the several discrete voltages supplied to power amplifier 14. Filter circuits 741 and 742 can also be called pulse-shaping networks or transition-shaping filters.

[0076] Switches S56 and S57 are on / off switches for filter circuits 741 and 742, respectively. Switch S56 is connected between power supply modulator 730 and filter circuit 741. Switch S57 is connected between power supply modulator 730 and filter circuit 742.

[0077] The digital control circuit 760 can control the pre-regulator circuit 710, the switching capacitor circuit 720, the supply modulator 730 and the switches S56 and S57 based on digital control signals from the RFIC 32.

[0078] It is noted that the digital envelope follower 71 does not necessarily include all of the pre-regulator circuit 710, the switching capacitor circuit 720, the power supply modulator 730, the filter circuits 741 and 742, the switches S56 and S57, and the digital control circuit 760. For example, the digital envelope follower 71 does not necessarily include the pre-regulator circuit 710. Furthermore, the digital envelope follower 71 does not necessarily include the filter circuits 741 and 742 and the switches S56 and S57. In addition, any combination of the pre-regulator circuit 710, the switching capacitor circuit 720, the power supply modulator 730, the filter circuits 741 and 742, and the switches S56 and S57 can be integrated into a single circuit. Furthermore, the digital envelope follower 71 can include several pre-regulator circuits instead of the pre-regulator circuit 710 and the switching capacitor circuit 720.In this case, the 730 supply modulator can be configured to select at least one of the several pre-regulator circuits.

[0079] Next, the circuit configuration of each circuit contained in the digital envelope tracer 71 will be described with reference to Fig. 3 described. 3.1 Circuit configuration of the switching capacitor circuit 720

[0080] First, the circuit configuration of the switching capacitor circuit 720 is described. The switching capacitor circuit 720 comprises capacitors C11 to C16, capacitors C10, C20, C30, and C40, and switches S11 to S14, S21 to S24, S31 to S34, and S41 to S44. Energy and charge are input from the pre-regulator circuit 710 at nodes N1 to N4 into the switching capacitor circuit 720 and are extracted from the switching capacitor circuit 720 at nodes N1 to N4 to the supply modulator 730.

[0081] Each of the capacitors C11 through C16 acts as a flying capacitor (sometimes called a transfer capacitor). This means that each of the capacitors C11 through C16 is used to increase or decrease the adjusted voltage supplied by the 710 pre-regulator circuit. Specifically, capacitors C11 through C16 transfer charges between themselves and nodes N1 through N4, so that voltages V1 through V4 (voltages relative to ground potential), satisfying V1:V2:V3:V4 = 1:2:3:4, are maintained at the four nodes N1 through N4. These voltages V1 through V4 correspond to several discrete voltages with several discrete voltage levels.

[0082] Capacitor C11 has two electrodes. One of the two electrodes of capacitor C11 is connected to one end of switch S11 and one end of switch S12. The other of the two electrodes of capacitor C11 is connected to one end of switch S21 and one end of switch S22.

[0083] Capacitor C12 has two electrodes. One of the two electrodes of capacitor C12 is connected to one end of switch S21 and one end of switch S22. The other of the two electrodes of capacitor C12 is connected to one end of switch S31 and one end of switch S32.

[0084] Capacitor C13 has two electrodes. One of the two electrodes of capacitor C13 is connected to one end of switch S31 and one end of switch S32. The other of the two electrodes of capacitor C13 is connected to one end of switch S41 and one end of switch S42.

[0085] Capacitor C14 has two electrodes. One of the two electrodes of capacitor C14 is connected to one end of switch S13 and one end of switch S14. The other of the two electrodes of capacitor C14 is connected to one end of switch S23 and one end of switch S24.

[0086] Capacitor C15 has two electrodes. One of the two electrodes of capacitor C15 is connected to one end of switch S23 and one end of switch S24. The other of the two electrodes of capacitor C15 is connected to one end of switch S33 and one end of switch S34.

[0087] Capacitor C16 has two electrodes. One of the two electrodes of capacitor C16 is connected to one end of switch S33 and one end of switch S34. The other of the two electrodes of capacitor C16 is connected to one end of switch S43 and one end of switch S44.

[0088] The set of capacitors C11 and C14, the set of capacitors C12 and C15, and the set of capacitors C13 and C16 can be charged and discharged in a complementary manner by repeating a first phase and a second phase.

[0089] In particular, during the first phase, switches S12, S13, S22, S23, S32, S33, S42, and S43 are switched on. As a result, for example, one of the two electrodes of capacitor C12 is connected to node N3, the other of the two electrodes of capacitor C12 and one of the two electrodes of capacitor C15 are connected to node N2, and the other of the two electrodes of capacitor C15 is connected to node N1.

[0090] On the other hand, in the second phase, switches S11, S14, S21, S24, S31, S34, S41, and S44 are switched on. As a result, for example, one of the two electrodes of capacitor C15 is connected to node N3, the other of the two electrodes of capacitor C15 and one of the two electrodes of capacitor C12 are connected to node N2, and the other of the two electrodes of capacitor C12 is connected to node N1.

[0091] By repeating the first and second phases, if, for example, one of the capacitors C12 and C15 is charged by node N2, the other of the capacitors C12 and C15 can be discharged to capacitor C30. That is, capacitors C12 and C15 can be charged and discharged in a complementary manner.

[0092] By repeating the first phase and the second phase, each of the set of capacitors C11 and C14 and the set of capacitors C13 and C16 can be charged and discharged in a complementary way, similar to the set of capacitors C12 and C15.

[0093] Each of the capacitors C10, C20, C30, and C40 acts as a smoothing capacitor. This means that each of the capacitors C10, C20, C30, and C40 is used to hold and smooth the voltages V1 to V4 at nodes N1 to N4.

[0094] Capacitor C10 is connected between node N1 and ground. Specifically, one of the two electrodes of capacitor C10 is connected to node N1.

[0095] Meanwhile, the other of the two electrodes of capacitor C10 is connected to ground.

[0096] Capacitor C20 is connected between nodes N2 and N1. Specifically, one of the two electrodes of capacitor C20 is connected to node N2, while the other electrode is connected to node N1.

[0097] Capacitor C30 is connected between nodes N3 and N2. Specifically, one of the two electrodes of capacitor C30 is connected to node N3, while the other electrode is connected to node N2.

[0098] Capacitor C40 is connected between nodes N4 and N3. Specifically, one of the two electrodes of capacitor C40 is connected to node N4, while the other electrode is connected to node N3.

[0099] Switch S11 is connected between one of the two electrodes of capacitor C11 and node N3. Specifically, one end of switch S11 is connected to one of the two electrodes of capacitor C11, while the other end is connected to node N3.

[0100] Switch S12 is connected between one of the two electrodes of capacitor C11 and node N4. Specifically, one end of switch S12 is connected to one of the two electrodes of capacitor C11, while the other end is connected to node N4.

[0101] Switch S21 is connected between one of the two electrodes of capacitor C12 and node N2. Specifically, one end of switch S21 is connected to one of the two electrodes of capacitor C12 and the other end of the two electrodes of capacitor C11. Meanwhile, the other end of switch S21 is connected to node N2.

[0102] Switch S22 is connected between one of the two electrodes of capacitor C12 and node N3. Specifically, one end of switch S22 is connected to one of the two electrodes of capacitor C12 and the other end of the two electrodes of capacitor C11. Meanwhile, the other end of switch S22 is connected to node N3.

[0103] Switch S31 is connected between the other of the two electrodes of capacitor C12 and node N1. Specifically, one end of switch S31 is connected to the other of the two electrodes of capacitor C12 and to one of the two electrodes of capacitor C13. Meanwhile, the other end of switch S31 is connected to node N1.

[0104] Switch S32 is connected between the other of the two electrodes of capacitor C12 and node N2. Specifically, one end of switch S32 is connected to the other of the two electrodes of capacitor C12 and to one of the two electrodes of capacitor C13. Meanwhile, the other end of switch S32 is connected to node N2. That is to say, the other end of switch S32 is connected to the other end of switch S21.

[0105] Switch S41 is connected between the other of the two electrodes of capacitor C13 and ground. Specifically, one end of switch S41 is connected to the other of the two electrodes of capacitor C13, while the other end is connected to ground.

[0106] Switch S42 is connected between the other of the two electrodes of capacitor C13 and node N1. Specifically, one end of switch S42 is connected to the other of the two electrodes of capacitor C13. Meanwhile, the other end of switch S42 is connected to node N1. That is to say, the other end of switch S42 is connected to the other end of switch S31.

[0107] Switch S13 is connected between one of the two electrodes of capacitor C14 and node N3. Specifically, one end of switch S13 is connected to one of the two electrodes of capacitor C14. Meanwhile, the other end of switch S13 is connected to node N3. This means that the other end of switch S13 is connected to the other end of switch S11 and the other end of switch S22.

[0108] Switch S14 is connected between one of the two electrodes of capacitor C14 and node N4. Specifically, one end of switch S14 is connected to one of the two electrodes of capacitor C14, while the other end of switch S14 is connected to node N4. This means that the other end of switch S14 is connected to the other end of switch S12.

[0109] Switch S23 is connected between one of the two electrodes of capacitor C15 and node N2. Specifically, one end of switch S23 is connected to one of the two electrodes of capacitor C15 and the other of the two electrodes of capacitor C14. Meanwhile, the other end of switch S23 is connected to node N2. This means that the other end of switch S23 is connected to the other end of switch S21 and the other end of switch S32.

[0110] Switch S24 is connected between one of the two electrodes of capacitor C15 and node N3. Specifically, one end of switch S24 is connected to one of the two electrodes of capacitor C15 and the other of the two electrodes of capacitor C14. Meanwhile, the other end of switch S24 is connected to node N3. This means that the other end of switch S24 is connected to the other end of switch S11, the other end of switch S22, and the other end of switch S13.

[0111] Switch S33 is connected between the other of the two electrodes of capacitor C15 and node N1. Specifically, one end of switch S33 is connected to the other of the two electrodes of capacitor C15 and to one of the two electrodes of capacitor C16. Meanwhile, the other end of switch S33 is connected to node N1. This means that the other end of switch S33 is connected to the other end of switch S31 and the other end of switch S42.

[0112] Switch S34 is connected between the other of the two electrodes of capacitor C15 and node N2. Specifically, one end of switch S34 is connected to the other of the two electrodes of capacitor C15 and to one of the two electrodes of capacitor C16. Meanwhile, the other end of switch S34 is connected to node N2. This means that the other end of switch S34 is connected to the other end of switch S21, the other end of switch S32, and the other end of switch S23.

[0113] Switch S43 is connected between the other of the two electrodes of capacitor C16 and ground. Specifically, one end of switch S43 is connected to the other of the two electrodes of capacitor C16, while the other end is connected to ground.

[0114] Switch S44 is connected between the other of the two electrodes of capacitor C16 and node N1. Specifically, one end of switch S44 is connected to the other of the two electrodes of capacitor C16. Meanwhile, the other end of switch S44 is connected to node N1. This means that the other end of switch S44 is connected to the other end of switch S31, the other end of switch S42, and the other end of switch S33.

[0115] A first set of switches, comprising switches S12, S13, S22, S23, S32, S33, S42, and S43, and a second set of switches, comprising switches S11, S14, S21, S24, S31, S34, S41, and S44, are switched on and off in a complementary manner based on a control signal S2. Specifically, in the first phase, the first set of switches is switched on and the second set of switches is switched off. Conversely, in the second phase, the first set of switches is switched off and the second set of switches is switched on.

[0116] For example, in one of the first and second phases, capacitors C10 to C40 are charged by capacitors C11 to C13, and in the other of the first and second phases, capacitors C10 to C40 are charged by capacitors C14 to C16. This means that, since capacitors C10 to C40 are always charged by capacitors C11 or C13 or capacitors C14 to C16, even if a current flows rapidly from nodes N1 to N4 to the supply modulator 730, nodes N1 to N4 are quickly recharged, thus suppressing potential fluctuations at nodes N1 to N4.

[0117] By operating in this manner, the switching capacitor circuit 720 can maintain approximately equal voltages at both ends of each of the capacitors C10, C20, C30, and C40. Specifically, at the four nodes labeled V1 to V4, voltages V1 to V4 (voltages relative to ground potential) are maintained, satisfying the ratio V1:V2:V3:V4 = 1:2:3:4. The voltage levels of V1 to V4 correspond to several discrete voltage levels that can be supplied to the supply modulator 730 by the switching capacitor circuit 720.

[0118] It is noted that the voltage ratio (V1:V2:V3:V4) is not limited to (1:2:3:4). The voltage ratio (V1:V2:V3:V4) can, for example, be (1:2:4:8).

[0119] It is noted that the configuration of the in Fig. The 3 illustrated switching capacitor circuit 720 is merely an example and the configuration is not limited to this example. Fig. The switching capacitor circuit 720 is configured to provide four discrete voltages, but the number of discrete voltages is not limited to this. The switching capacitor circuit 720 can be configured to provide any number of two or more discrete voltages. For example, if two discrete voltages are provided, it is sufficient for the switching capacitor circuit 720 to include at least capacitors C12 and C15 and switches S21 to S24 and S31 to S34. 3.2 Circuit configuration of the 730 power supply modulator

[0120] Next, the circuit configuration of the 730 power supply modulator is described. The 730 power supply modulator includes input terminals 131 to 134, switches S51 to S54, and one output terminal 130.

[0121] Output terminal 130 is connected to filter circuits 741 and 742. Output terminal 130 is a connection for supplying a power supply voltage, selected from voltages V1 to V4, to the power amplifier 14 via filter circuit 741 and / or filter circuit 742.

[0122] Input terminals 131 to 134 are each connected to nodes N4 to N1 of the switching capacitor circuit 720. Input terminals 131 to 134 are for receiving the voltages V4 to V1 from the switching capacitor circuit 720.

[0123] Switch S51 is connected between input port 131 and output port 130. Specifically, switch S51 has one terminal connected to input port 131 and one terminal connected to output port 130. In this connection configuration, switch S51 can be toggled between connecting and disconnecting input port 131 and output port 130 by being turned on / off by a control signal S3.

[0124] Switch S52 is connected between input port 132 and output port 130. Specifically, switch S52 has one terminal connected to input port 132 and one terminal connected to output port 130. In this connection configuration, switch S52 can be toggled between connecting and disconnecting input port 132 and output port 130 by being turned on / off by control signal S3.

[0125] Switch S53 is connected between input port 133 and output port 130. Specifically, switch S53 has one terminal connected to input port 133 and one terminal connected to output port 130. In this connection configuration, switch S53 can be toggled between connecting and disconnecting input port 133 and output port 130 by being turned on / off by control signal S3.

[0126] Switch S54 is connected between input port 134 and output port 130. Specifically, switch S54 has one terminal connected to input port 134 and one terminal connected to output port 130. In this connection configuration, switch S54 can be toggled between connecting and disconnecting input port 134 and output port 130 by being turned on / off by control signal S3.

[0127] These switches S51 to S54 are controlled to be switched on in an exclusive manner. This means that only one of the switches S51 to S54 is switched on, and the remaining switches S51 to S54 are switched off. This allows the supply modulator 730 to output a voltage selected from the voltages V1 to V4.

[0128] It is noted that the configuration of the in Fig. The power supply modulator 730 illustrated in Figure 3 is an example and is not limited to this example. In particular, switches S51 to S54 can have any configuration as long as they can selectively connect at least one of the four input terminals 131 to 134 to the output terminal 130. For example, the power supply modulator 730 can further include a switch connected between switches S51 to S53 and switch S54 and the output terminal 130. For example, the power supply modulator 730 can further include a switch connected between switches S51 and S52 and switches S53 and S54 and the output terminal 130.

[0129] If voltages with two discrete voltage levels are provided by the switching capacitor circuit 720, it is sufficient for the supply modulator 730 to include at least two of the switches S51 to S54. 3.3 Circuit configuration of the pre-regulator circuit 710

[0130] Next, the circuit configuration of the pre-regulator circuit 710 is described. The pre-regulator circuit 710 comprises an input terminal 110, output terminals 111 to 114, switches S61 to S63, S71 and S72, a power inductor L71 and capacitors C61 to C64.

[0131] Input terminal 110 is an input terminal for a DC voltage. In other words, input terminal 110 is a terminal for receiving an input voltage from the DC power source 70.

[0132] Output terminal 111 is the output terminal for voltage V4. This means that output terminal 111 is a connection for supplying voltage V4 to the switching capacitor circuit 720. Output terminal 111 is connected to node N4 of the switching capacitor circuit 720.

[0133] Output terminal 112 is the output terminal for voltage V3. This means that output terminal 112 is a connection for supplying voltage V3 to the switching capacitor circuit 720. Output terminal 112 is connected to node N3 of the switching capacitor circuit 720.

[0134] Output terminal 113 is the output terminal for voltage V2. This means that output terminal 113 is a connection for supplying voltage V2 to the switching capacitor circuit 720. Output terminal 113 is connected to node N2 of the switching capacitor circuit 720.

[0135] Output terminal 114 is the output terminal for voltage V1. This means that output terminal 114 is a connection for supplying voltage V1 to the switching capacitor circuit 720. Output terminal 114 is connected to node N1 of the switching capacitor circuit 720.

[0136] Switch S71 is connected between input terminal 110 and one end of power inductor L71. Specifically, switch S71 has one terminal connected to input terminal 110 and another terminal connected to one end of power inductor L71. In this connection configuration, switch S71 can toggle between connecting and disconnecting input terminal 110 and one end of power inductor L71 by switching between open and closed based on a control signal S1.

[0137] Switch S72 is connected between one end of power inductor L71 and ground. Specifically, switch S72 has one terminal connected to one end of power inductor L71 and one terminal connected to ground. In this connection configuration, switch S72 can toggle between connecting and disconnecting one end of power inductor L71 and ground by switching between open and closed based on the control signal S1.

[0138] Switch S61 is connected between the other end of power inductor L71 and output terminal 111. Specifically, switch S61 has one terminal connected to the other end of power inductor L71 and another terminal connected to output terminal 111. In this connection configuration, switch S61 can toggle between connecting and disconnecting the other end of power inductor L71 and output terminal 111 by switching between open and closed based on the control signal S1.

[0139] Switch S62 is connected between the other end of power inductor L71 and output terminal 112. Specifically, switch S62 has one terminal connected to the other end of power inductor L71 and another terminal connected to output terminal 112. In this connection configuration, switch S62 can toggle between connecting and disconnecting the other end of power inductor L71 and output terminal 112 by switching between open and closed based on the control signal S1.

[0140] Switch S63 is connected between the other end of power inductor L71 and output terminal 113. Specifically, switch S63 has one terminal connected to the other end of power inductor L71 and another terminal connected to output terminal 113. In this connection configuration, switch S63 can toggle between connecting and disconnecting the other end of power inductor L71 and output terminal 113 by switching between open and closed based on the control signal S1.

[0141] One of the two electrodes of capacitor C61 is connected to switch S61 and output terminal 111. The other of the two electrodes of capacitor C61 is connected to switch S62, output terminal 112, and one of the two electrodes of capacitor C62.

[0142] One of the two electrodes of capacitor C62 is connected to switch S62, output terminal 112, and the other of the two electrodes of capacitor C61. The other of the two electrodes of capacitor C62 is connected to a path that links switch S63, output terminal 113, and one of the two electrodes of capacitor C63.

[0143] One of the two electrodes of capacitor C63 is connected to switch S63, output terminal 113, and the other of the two electrodes of capacitor C62. The other of the two electrodes of capacitor C63 is connected to output terminal 114 and one of the two electrodes of capacitor C64.

[0144] One of the two electrodes of capacitor C64 is connected to output terminal 114, and the other of the two electrodes of capacitor C63 is connected to the output terminal 114. The other of the two electrodes of capacitor C64 is connected to ground.

[0145] Switches S61 to S63 are controlled to be switched on sequentially. This means that only one of switches S61 to S63 is switched on, while the remaining switches are off. By switching on only one of switches S61 to S63, the pre-regulator circuit 710 can vary the voltage supplied to the switching capacitor circuit 720 between the voltage levels of voltages V2 to V4.

[0146] The pre-regulator circuit 710 configured in this way can supply a charge to the switching capacitor circuit 720 via at least one of the output terminals 111 to 114.

[0147] If the input voltage only needs to be converted into a suitable voltage, it is sufficient for the pre-regulator circuit 710 to include at least the switches S71 and S72 and the power inductor L71. 3.4 Circuit configurations of the filter circuits 741 and 742

[0148] Next, the circuit configurations of filter circuits 741 and 742 will be described.

[0149] The filter circuit 741 comprises a parallel circuit (LC parallel circuit) consisting of an inductor L51 and a capacitor C51. One end of the parallel circuit, comprising inductor L51 and capacitor C51, is connected to switch S56, and the other end of the parallel circuit, comprising inductor L51 and capacitor C51, is connected to power amplifier 14.

[0150] The filter circuit 742 comprises a parallel circuit consisting of an inductor L52 and a capacitor C52. One end of the parallel circuit, comprising inductor L52 and capacitor C52, is connected to switch S57, and the other end of the parallel circuit, comprising inductor L52 and capacitor C52, is connected to power amplifier 14.

[0151] Filter circuits 741 and 742, connected in this way, are switched on and off by switches S56 and S57. This allows filter circuits 741 and 742 to switch band-stop filters on and off for removing noise from several discrete voltages. For example, by controlling the opening and closing of switches S56 and S57, three types of band-stop filters, described below in (1) to (3), can be implemented. (1) When switch S56 is closed and switch S57 is open, filter circuit 741 is connected between supply modulator 730 and power amplifier 14, and filter circuit 742 is not connected between them. As a result, filter circuit 741 acts as a band-stop filter, and filter circuit 742 does not. (2) When switch S56 is open and switch S57 is closed, filter circuit 742 is connected between supply modulator 730 and power amplifier 14, and filter circuit 741 is not connected between them. As a result, filter circuit 742 acts as a band-stop filter, and filter circuit 741 does not. (3) When switch S56 and switch S57 are closed, filter circuits 741 and 742 are connected between the supply modulator 730 and the power amplifier 14. As a result, filter circuits 741 and 742 function as band-stop filters.

[0152] The opening and closing of switches S56 and S57 can be controlled based on, for example, the modulation bandwidth of the FR1 signal. If the power amplifier 14 is capable of amplifying transmission signals of multiple frequency bands, the opening and closing of switches S56 and S57 can also be controlled based on the frequency band of the transmission signal being amplified by the power amplifier 14. It should be noted that the control of the opening and closing of switches S56 and S57 is not limited to the above description.

[0153] The circuit configurations of the filter circuits 741 and 742, which are in Fig. The illustrations in Figure 3 are examples and are not limited to these. For example, filter circuit 741 and / or filter circuit 742 can be a series circuit (LC series circuit) comprising an inductor and a capacitor. In this case, the LC series circuit can be connected between the path connecting the supply modulator 730 and the power amplifier 14 and ground. 3.5 Circuit configuration of the 760 digital control circuit

[0154] Next, the circuit configuration of the 760 digital control circuit is described. The 760 digital control circuit comprises a first controller 761 and a second controller 762.

[0155] The first controller, 761, can perform processing on a serial data signal (DATA) based on a clock signal (CLK) provided by RFIC 32 and generate the control signals S1 to S4. Here, the serial data signal means a data signal transmitted bit by bit through a signal line or cable.

[0156] Control signal S1 controls the opening and closing of switches S61 to S63, S71, and S72, which are part of the pre-regulator circuit 710. Control signal S2 controls the opening and closing of switches S11 to S14, S21 to S24, S31 to S34, and S41 to S44, which are part of the switching capacitor circuit 720. Control signal S3 controls the opening and closing of switches S51 to S54, which are part of the supply modulator 730, when APT mode is applied to the power amplifier 14. Control signal S4 controls the opening and closing of switches S56 and S57 for the filter circuits 741 and 742.

[0157] A separate signal line, distinct from the one for the serial data signal, is used for the clock signal to process the serial data signal in the first controller 761, but the configuration is not limited to this. For example, the clock signal can be transmitted through the same signal line as the one for the serial data signal.

[0158] Furthermore, in this embodiment, a serial data signal is used to control the pre-regulator circuit 710, the switching capacitor circuit 720, the supply modulator 730 and the switches S56 and S57, but several serial data signals can be used.

[0159] The second controller, 762, can process digital control level (DCL) signals (DCL1, DCL2) provided by RFIC 32 and generate a control signal S5. The DCL signals are an example of parallel data signals. Here, parallel data signals mean signals that are transmitted simultaneously in parallel through multiple signal lines or circuits.

[0160] The DCL signals (DCL1, DCL2) are generated by RFIC 32 based on an envelope signal of a high-frequency signal when the D-ET mode is applied to the power amplifier 14. Accordingly, the control signal S5 is a signal for controlling the opening and closing of switches S51 to S54, which are contained in the supply modulator 730, when the D-ET mode is applied to the power amplifier 14.

[0161] Each of the DCL signals (DCL1, DCL2) is a 1-bit signal. Each of the voltages V1 to V4 is represented by a combination of two 1-bit signals. For example, V1, V2, V3, and V4 are represented by "00", "01", "10", and "11", respectively. Gray code can be used to represent the voltage levels.

[0162] It is noted that in this embodiment, two DCL signals are used to control the supply modulator 730 in D-ET mode, but the number of DCL signals is not limited to two. For example, one or any number of three or more DCL signals can be used, depending on the number of voltage levels that can be selected by each supply modulator 730. Furthermore, the digital control signal used to control the supply modulator 730 is not limited to a single DCL signal. 4 Performance Enhancement Methods

[0163] Next, a power amplification method according to this embodiment will be described with reference to Fig. 4 described. Fig. Figure 4 is a flowchart illustrating the power amplification method according to this embodiment.

[0164] First, RFICs 31 to 33 determine whether the radio frequency signal to be amplified is a WLAN signal (S10). If the radio frequency signal to be amplified is a WLAN signal (Yes in S10), RFIC 31 determines whether the frequency band of the WLAN signal is lower than a threshold band (S20). For example, if the 5 GHz band is used as the threshold band, it is determined that the 2.4 GHz band is lower than the 5 GHz band. The threshold band can be one that is determined experimentally and / or empirically in advance.

[0165] If the frequency band of the WLAN signal is lower than the threshold band (Yes in S20), the power amplifier 11 amplifies the undistorted WLAN signal (S30). This means that the DPD circuit 311 does not pre-distortize the digital IQ signal, and the DAC 312 and the quadrature modulator 313 generate an undistorted WLAN signal from the undistorted digital IQ signals.

[0166] If, on the other hand, the frequency band of the WLAN signal is not lower than the threshold band (No in S20), RFIC 31 determines whether the bit rate of the modulation scheme is higher than a threshold bit rate (S40) and whether the modulation bandwidth is less than a threshold width (S50). The threshold bit rate and the threshold width can be determined experimentally and / or empirically in advance.

[0167] If the bit rate of the modulation method is higher than the threshold bit rate (Yes in S40) or if the modulation bandwidth is not less than the threshold (No in S50), the DPD circuit 311 pre-distorts the WLAN signal using the first mathematical model, which incorporates a memory effect (S60). Conversely, if the bit rate of the modulation method is not higher than the threshold bit rate and the modulation bandwidth is less than the threshold (No in S40 and Yes in S50), the DPD circuit 311 pre-distorts the WLAN signal using the second mathematical model, which does not incorporate a memory effect (S70). Then, the power amplifiers 12 and 13 amplify the pre-distorted WLAN signal (S80).

[0168] It is noted that if the high-frequency signal to be amplified is not a WLAN signal (No in S10), that is, if the high-frequency signal to be amplified is a cellular network signal, the DPD circuit 321 or 331 pre-distorts the cellular network signal based on the first mathematical model or the second mathematical model (S90). Then the power amplifier 14 or 15 amplifies the pre-distorted cellular network signal (S100).

[0169] It is noted that the steps and the order of the steps in Fig. 4 are merely examples and the power amplification method is not based on the flowchart in Fig.4 is limited. For example, the order of steps S40 and S50 can be reversed. Furthermore, if the power amplification system 20 does not include RFICs 32 and 33, step S10 can be skipped. Additionally, steps S40 and S50 can be skipped, and only one of steps S60 and S70 might be performed. 5 effects etc.

[0170] As previously described, the power amplification system 20 according to this embodiment comprises the power amplifier 11, which is configured to amplify a first WLAN signal in a first frequency band, the power amplifier 12, which is configured to amplify a second WLAN signal in a second frequency band that is higher than the first frequency band, and the DPD circuit 311, which is configured to pre-distort the second WLAN signal and not pre-distort the first WLAN signal.

[0171] Furthermore, the power amplifier circuit 10 according to this embodiment comprises the power amplifier 11, which is configured to amplify a first WLAN signal in a first frequency band, and the power amplifier 12, which is configured to amplify a second WLAN signal in a second frequency band that is higher than the first frequency band, and the second WLAN signal is pre-distorted and the first WLAN signal is not pre-distorted.

[0172] The power amplification method according to this embodiment amplifies a first WLAN signal in a first frequency band that is not pre-distorted (S30), pre-distorts a second WLAN signal in a second frequency band that is higher than the first frequency band (S60 or S70), and amplifies the pre-distorted second WLAN signal (S80).

[0173] Accordingly, pre-distorting the second WLAN signal in the higher, second frequency band reduces its nonlinear distortion and improves the transmission signal quality. Conversely, the power consumption for DPD can be reduced by not pre-distorting the lower, first WLAN signal. A wider modulation bandwidth is more likely to be used in the higher, second frequency band than in the first, and the nonlinear distortion due to power amplification is significant. Furthermore, the bit rate of the modulation method is more likely to be higher in the second frequency band than in the first, and there is a strong need to reduce EVM. Therefore, the effect of reducing nonlinear distortion by pre-distorting the second WLAN signal is substantial.Conversely, a modulation method with a smaller modulation bandwidth and a lower bit rate is more likely to be used in the lower, first frequency band than in the second frequency band, and the effect of reducing nonlinear distortion by pre-distorting the first WLAN signal is small. Therefore, by not pre-distorting the lower, first WLAN signal and pre-distorting the second WLAN signal in the higher, second frequency band, the transmission signal quality can be effectively improved while suppressing an increase in power consumption in the WLAN.

[0174] Furthermore, for example in the power amplification system 20, the power amplifier circuit 10 or the power amplification method according to this embodiment, the first frequency band can include the 2.4 GHz band and the second frequency band can include the 5 GHz band, the 6 GHz band and / or the 7 GHz band.

[0175] Accordingly, by not pre-distorting the first WLAN signal of the 2.4 GHz band and pre-distorting the second WLAN signal of the 5 GHz, 6 GHz or 7 GHz band, the quality of the transmission signal can be effectively improved while suppressing an increase in power consumption in the WLAN.

[0176] For example, according to this embodiment, the power amplification system 20 may further include the power amplifier 13, which is configured to amplify a third WLAN signal in a third frequency band higher than the second frequency band, and the DPD circuit 311 may further be configured to pre-distort the third WLAN signal.

[0177] For example, according to this embodiment, the power amplifier circuit 10 may further include the power amplifier 13, which is configured to amplify a third WLAN signal of a third frequency band higher than the second frequency band, and the third WLAN signal may be pre-distorted.

[0178] For example, in the power amplification method, the third WLAN signal in the third frequency band, which is higher than the second frequency band, can be pre-distorted (S60 or S70) and the pre-distorted third WLAN signal can be amplified (S80).

[0179] Accordingly, it is possible to reduce the nonlinear distortion of the third Wi-Fi signal in the higher, third frequency band and improve the quality of the transmission signal by pre-distorting the third Wi-Fi signal. A wider modulation bandwidth is more likely to be used in the third frequency band, which is higher than the second frequency band. Since the nonlinear distortion caused by power amplification is significant in the third frequency band, the effect of reducing this distortion by pre-distorting the third Wi-Fi signal is substantial. Therefore, pre-distorting the third Wi-Fi signal in the third frequency band can effectively improve the quality of a Wi-Fi transmission signal.

[0180] For example, in the power amplification system 20, the power amplifier circuit 10 or the power amplification method according to this embodiment, the third frequency band can include the 60 GHz band.

[0181] Accordingly, by pre-distorting the third WLAN signal of the 60 GHz band, the quality of a transmission signal in the WLAN can be effectively improved.

[0182] For example, according to this embodiment, the power amplification system 20 may further include the power amplifier 14, which is configured to amplify a cellular network signal, and the DPD circuit 321, which is configured to pre-distort the cellular network signal.

[0183] For example, according to this embodiment, the power amplifier circuit 10 may further include the power amplifier 14, which is configured to amplify a cellular network signal, and the cellular network signal may be pre-distorted.

[0184] For example, the power amplification method according to this embodiment can further include pre-distorting a cellular network signal (S90) and amplifying the cellular network signal that has been pre-distorted (S100).

[0185] Accordingly, by pre-distorting a cellular network signal, the quality of the transmission signal can also be effectively improved in a cellular network.

[0186] For example, according to this embodiment, the power amplification system 20 can further comprise the digital envelope follower 71, which is configured to generate several discrete voltages from an input voltage provided by the DC power source 70, and to selectively supply at least one of the several discrete voltages to the power amplifier 14, and the input voltage can be supplied to the power amplifiers 11 and 12 from the DC power source 70.

[0187] Accordingly, the power amplifier 14, which amplifies a cellular network signal, is supplied with several discrete voltages via the digital envelope tracker 71, thereby improving power efficiency. Conversely, since the power amplifiers 11 and 12, which amplify a WLAN signal, are supplied with an input voltage directly from the DC power source 70, the number of components can be reduced, and the size of the communication device 60 can be minimized. Because a higher output power is required for a cellular network signal than for a WLAN signal, the effect of improved power efficiency is particularly significant.

[0188] Furthermore, in the power amplification system 20 according to this embodiment, for example, the DPD circuit 311 can switch the mathematical model used for DPD of the second WLAN signal based on the modulation method and / or the modulation bandwidth of the second WLAN signal.

[0189] Accordingly, by switching the mathematical model depending on the modulation method and bandwidth, it is possible to prioritize either reducing the computational load for DPD (i.e., reducing power consumption) or reducing nonlinear distortion. Since the required value of an EVM and the amount of nonlinear distortion vary depending on the modulation method and bandwidth, switching the mathematical model according to these factors is an effective way to improve the quality of the transmitted signal while suppressing an increase in power consumption.

[0190] For example, in the power amplification system 20 according to this embodiment, the DPD circuit 311 can pre-distort the second WLAN signal using the first mathematical model, which incorporates the memory effect of the power amplifier 12, if the bit rate of the modulation method of the second WLAN signal is higher than a threshold bit rate, and can pre-distort the second WLAN signal using the second mathematical model, which does not incorporate the memory effect of the power amplifier 12, if the bit rate of the modulation method of the second WLAN signal is not higher than the threshold bit rate.

[0191] If the bit rate of the modulation method is higher, the first mathematical model, which incorporates the memory effect, is used. This prioritizes the reduction of nonlinear distortion and effectively improves the quality of the transmitted signal. Conversely, if the bit rate of the modulation method is lower, the second mathematical model, which does not incorporate the memory effect, is used. This prioritizes the reduction of the computational load and suppresses an increase in power consumption. Since the required EVM value is also high when the bit rate of the modulation method is high, it is more effective to use the first mathematical model, which can reduce nonlinear distortion more effectively at high bit rates.

[0192] For example, in the power amplification system 20 according to this embodiment, the DPD circuit 311 can pre-distort the second WLAN signal using the first mathematical model, which incorporates the memory effect of the power amplifier 12, if the modulation bandwidth of the second WLAN signal is greater than a threshold bandwidth, and can pre-distort the second WLAN signal using the second mathematical model, which does not incorporate the memory effect of the power amplifier 12, if the modulation bandwidth of the second WLAN signal is not greater than the threshold bandwidth.

[0193] When the modulation bandwidth is larger, the first mathematical model, which incorporates the memory effect, is used. This prioritizes the reduction of nonlinear distortion and effectively improves the quality of the transmitted signal. Conversely, when the modulation bandwidth is smaller, the second mathematical model, which does not incorporate the memory effect, is used. This prioritizes the reduction of the computational load and suppresses an increase in power consumption. With a larger modulation bandwidth, the peak-to-average power ratio (PAPR) increases, as does the nonlinear distortion. Therefore, it is more effective to use the first mathematical model, which can reduce nonlinear distortion more effectively with a larger modulation bandwidth. Other examples of implementation

[0194] The power amplification system, power amplifier circuit, and power amplification method according to the present invention have been previously described based on exemplary embodiments, but the power amplification system, power amplifier circuit, and power amplification method according to the present invention are not limited to the previously described exemplary embodiments. Other exemplary embodiments realized by combining any of the components of the above exemplary embodiments, modifications obtained by modifying the above exemplary embodiments in various ways that a person skilled in the art might devise without departing from the essence of the present invention, and various devices incorporating the previously described power amplification system or power amplifier circuit are also included in the present invention.

[0195] For example, in the circuit configurations of the various circuits according to the above embodiments, other circuit elements, wiring leads, etc., can be inserted between the paths connecting the circuit elements and the signal paths revealed in the drawings. For example, a filter can be inserted between a DAC and a quadrature modulator. Also, for example, a filter can be inserted between a power amplifier and an antenna.

[0196] It should be noted that in the above embodiments, several discrete voltages are supplied to the supply modulator by the switching capacitor circuit, but the configuration is not limited to this. For example, several discrete voltages can be supplied to the supply modulator by several DC-DC converters. Furthermore, if the voltage levels of the several discrete voltages are evenly spaced, it is preferable to use a switching capacitor circuit, which is effective in reducing the size of a tracer module.

[0197] Furthermore, in each of the above embodiments, the power amplifier circuit does not include a receive path, but the power amplifier circuit may include a receive path. <1> A power amplification system comprising the following features: a first power amplifier configured to amplify a first wireless local area network signal in a first frequency band; a second power amplifier configured to amplify a second wireless local area network signal in a second frequency band higher than the first frequency band; and a first digital pre-distortion circuit configured to pre-distort the second Wireless Local Area Network signal and not to pre-distort the first Wireless Local Area Network signal. <2> The power amplification system according to <1> , the first frequency band comprises a 2.4 GHz band, and the second frequency band includes a 5 GHz band, a 6 GHz band and / or a 7 GHz band. <3> The power amplification system according to <1> or <2> , which also has the following features: a third power amplifier configured to amplify a third wireless local area network signal in a third frequency band that is higher than the second frequency band, wherein the first digital pre-distortion circuit is further configured to pre-distort the third wireless local network signal. <4> The power amplification system according to <3> , the third frequency band comprises a 60 GHz band. <5> The power amplification system according to one of <1> until <4> , wherein the first digital pre-distortion circuit switches a mathematical model used for digital pre-distortion of the second Wireless Local Area Network signal based on a modulation scheme and / or modulation bandwidth of the second Wireless Local Area Network signal. <6> The power amplification system according to <5> , wherein the first digital pre-distortion circuit pre-distorts the second wireless local network signal using a first mathematical model that incorporates a memory effect of the second power amplifier when a bit rate of the modulation method of the second wireless local network signal is higher than a threshold bit rate, and The second Wireless Local Area Network signal is pre-distorted using a second mathematical model that does not incorporate the memory effect of the second power amplifier if the bit rate of the modulation method of the second Wireless Local Area Network signal is not higher than the threshold bit rate. <7> The power amplification system according to <5> , wherein the first digital pre-distortion circuit pre-distorts the second wireless local network signal using a first mathematical model that incorporates a memory effect of the second power amplifier when the modulation bandwidth of the second wireless local network signal is greater than a threshold bandwidth, and The second Wireless Local Area Network signal is pre-distorted using a second mathematical model that does not incorporate the memory effect of the second power amplifier if the modulation bandwidth of the second Wireless Local Area Network signal is not greater than the threshold bandwidth. <8> The power amplification system according to one of <1> until <7> , which also has the following features: a fourth power amplifier configured to amplify a cellular network signal; and a second digital pre-distortion circuit configured to pre-distort the cellular network signal. <9> The power amplification system according to <8> , which also has the following features: a tracer circuit configured to generate several discrete voltages from an input voltage provided by a DC power source, and to selectively supply at least one of the several discrete voltages to the fourth power amplifier, where the first power amplifier and the second power amplifier are supplied with the input voltage from the DC power source. <10> Power amplifier circuit which has the following features: a first power amplifier configured to amplify a first wireless local area network signal in a first frequency band; and a second power amplifier configured to amplify a second wireless local area network signal in a second frequency band that is higher than the first frequency band, where the second wireless local area network signal is pre-distorted, and the first wireless local area network signal is not pre-distorted. <11> The power amplifier circuit according to <10> , the first frequency band comprises a 2.4 GHz band, and the second frequency band includes a 5 GHz band, a 6 GHz band and / or a 7 GHz band. <12> The power amplifier circuit according to <10> or <11> , which also has the following features: a third power amplifier configured to amplify a third wireless local area network signal in a third frequency band that is higher than the second frequency band, where the third wireless local area network signal is pre-distorted. <13> The power amplifier circuit according to <12> , the third frequency band comprises a 60 GHz band. <14> The power amplifier circuit according to one of <10> until <13> , which also has the following features: a fourth power amplifier configured to amplify a cellular network signal, where the cellular network signal is pre-distorted. <15> The power amplifier circuit according to <14> , where a digital envelope tracking (D-ET) mode is applied to the fourth power amplifier, and A fixed voltage mode is applied to the first power amplifier and the second power amplifier. <16> A performance enhancement process that includes the following steps: Amplifying an initial wireless local area network signal in a first frequency band that is not pre-distorted; Pre-distortion of a second wireless local area network signal in a second frequency band that is higher than the first frequency band; and Amplifying the pre-distorted second wireless local area network signal. <17> The performance enhancement procedure according to <16> , the first frequency band comprises a 2.4 GHz band, and the second frequency band includes a 5 GHz band, a 6 GHz band and / or a 7 GHz band. <18> The performance enhancement procedure according to <16> or <17> , which further includes the following steps: Pre-distortion of a third wireless local area network signal in a third frequency band that is higher than the second frequency band; and Amplifying the pre-distorted third wireless local area network signal. <19> The performance enhancement procedure according to <18> , the third frequency band comprises a 60 GHz band. <20> The performance enhancement procedure according to one of <16> until <19> , which further includes the following steps: Pre-distortion of a cellular network signal; and Amplification of the pre-distorted cellular network signal. Industrial applicability

[0198] The present invention can be widely used in communication devices, such as mobile phones, as a power amplification system for amplifying high-frequency signals. Reference symbol list 10 Power amplifier circuit 11, 12, 13, 14, 15 power amplifiers 20 Power amplification system 31, 32, 33 RFIC 41, 42, 43 BBIC 51, 52, 53, 54, 55 Antenna 60 Communication device 70 DC power source 71 Digital Envelope Tracers 72 average performance pursuers 110, 131, 132, 133, 134 Input port 111, 112, 113, 114, 130 Output port 311, 321, 331 DPD switching 312, 322, 332 DAC 313, 323, 333 quadrature modulator 710 Pre-regulator circuit 720 Switching capacitor circuit 730 Supply modulator 741, 742 Filter circuit 760 Digital Control Circuit 761 first control 762 second control QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2019-140671

[0003]

Claims

[1] A power amplification system that has the following features: a first power amplifier configured to amplify a first wireless local area network signal in a first frequency band; a second power amplifier configured to amplify a second wireless local area network signal in a second frequency band higher than the first frequency band; and a first digital pre-distortion circuit configured to pre-distort the second Wireless Local Area Network signal and not to pre-distort the first Wireless Local Area Network signal. [2] The power amplification system according to claim 1, the first frequency band comprises a 2.4 GHz band, and the second frequency band includes a 5 GHz band, a 6 GHz band and / or a 7 GHz band. [3] The power amplification system according to claim 1 or 2, which further comprises the following features: a third power amplifier configured to amplify a third wireless local area network signal in a third frequency band that is higher than the second frequency band, the first digital pre-distortion circuit is further configured to pre-distort the third wireless local network signal. [4] The power amplification system according to claim 3, the third frequency band comprises a 60 GHz band. [5] The power amplification system according to any one of claims 1 to 4, where the first digital pre-distortion circuit a mathematical model that is used to digitally pre-distort the second Wireless Local Area Network signal, based on a modulation technique and / or modulation bandwidth of the second Wireless Local Area Network signal. [6] The power amplification system according to claim 5, wherein the first digital pre-distortion circuit pre-distorts the second wireless local network signal using a first mathematical model that incorporates a memory effect of the second power amplifier when a bit rate of the modulation method of the second wireless local network signal is higher than a threshold bit rate, and The second Wireless Local Area Network signal is pre-distorted using a second mathematical model that does not incorporate the memory effect of the second power amplifier if the bit rate of the modulation method of the second Wireless Local Area Network signal is not higher than the threshold bit rate. [7] The power amplification system according to claim 5, wherein the first digital pre-distortion circuit pre-distorts the second wireless local network signal using a first mathematical model that incorporates a memory effect of the second power amplifier when the modulation bandwidth of the second wireless local network signal is greater than a threshold bandwidth, and The second Wireless Local Area Network signal is pre-distorted using a second mathematical model that does not incorporate the memory effect of the second power amplifier if the modulation bandwidth of the second Wireless Local Area Network signal is not greater than the threshold bandwidth. [8] The power amplification system according to any one of claims 1 to 7, which further comprises the following features: a fourth power amplifier configured to amplify a cellular network signal; and a second digital pre-distortion circuit configured to pre-distort the cellular network signal. [9] The power amplification system according to claim 8, which further comprises the following features: a tracer circuit configured to generate several discrete voltages from an input voltage provided by a DC power source, and to selectively supply at least one of the several discrete voltages to the fourth power amplifier, where the first power amplifier and the second power amplifier are supplied with the input voltage from the DC power source. [10] A power amplifier circuit which has the following features: a first power amplifier configured to amplify a first wireless local area network signal in a first frequency band; and a second power amplifier configured to amplify a second wireless local area network signal in a second frequency band that is higher than the first frequency band, where the second wireless local area network signal is pre-distorted, and the first wireless local area network signal is not pre-distorted. [11] The power amplifier circuit according to claim 10, the first frequency band comprises a 2.4 GHz band, and the second frequency band includes a 5 GHz band, a 6 GHz band and / or a 7 GHz band. [12] The power amplifier circuit according to claim 10 or 11, which further comprises the following features: a third power amplifier configured to amplify a third wireless local area network signal in a third frequency band that is higher than the second frequency band, where the third wireless local area network signal is pre-distorted. [13] The power amplifier circuit according to claim 12, wherein the third frequency band comprises a 60 GHz band. [14] The power amplifier circuit according to one of claims 10 to 13, which further comprises the following features: a fourth power amplifier configured to amplify a cellular network signal, where the cellular network signal is pre-distorted. [15] The power amplifier circuit according to claim 14, where a digital envelope tracking (D-ET) mode is applied to the fourth power amplifier, and A fixed voltage mode is applied to the first power amplifier and the second power amplifier. [16] A power amplification procedure comprising the following steps: Amplifying an initial wireless local area network signal in a first frequency band that is not pre-distorted; Pre-distortion of a second wireless local area network signal in a second frequency band that is higher than the first frequency band; and Amplifying the pre-distorted second wireless local area network signal. [17] The power enhancement method according to claim 16, the first frequency band comprises a 2.4 GHz band, and the second frequency band includes a 5 GHz band, a 6 GHz band and / or a 7 GHz band. [18] The power enhancement method according to claim 16 or 17, which further comprises the following steps: Pre-distortion of a third wireless local area network signal in a third frequency band that is higher than the second frequency band; and Amplifying the pre-distorted third wireless local area network signal. [19] The power amplification method according to claim 18, wherein the third frequency band comprises a 60 GHz band. [20] The power enhancement method according to one of claims 16 to 19, which further comprises the following steps: Pre-distortion of a cellular network signal; and Amplification of the pre-distorted cellular network signal.

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