TIME SYNCHRONIZATION SYSTEM

DE112025000157T5Undetermined Publication Date: 2026-07-02RIGOL TECHNOLOGIES CO LTD
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Patent Information

Application Number
DE112025000157
Authority / Receiving Office
DE · DE
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-06-06
Filing Date
2025-06-05
Publication Date
2026-07-02

AI Technical Summary

Technical Problem

In the existing technology, synchronizing multiple clocks with one SYNC pulse signal can easily lead to phase instability, and inputting multiple individually adjustable SYNC pulse signals into multiple frequency dividers will increase area and power consumption.

Method used

The structure employs a trigger group and a frequency divider group. The trigger group receives N clock signals and one SYNC pulse signal, and transmits them to N frequency dividers respectively. By setting the input and output phase difference threshold of the triggers, combined with the delay adjustment circuit and the inverter, it is ensured that the phase difference between the rising edge of the SYNC pulse signal and the rising edge of the clock signal is greater than the difference threshold, so as to reduce the risk of metastability.

Benefits of technology

While reducing the risk of metastability, power consumption was reduced, and stable synchronization of multi-phase clock signals was achieved.

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Abstract

A clock synchronization system. The clock synchronization system comprises a trigger group (110) and a frequency divider group (120), wherein the trigger group (110) comprises N triggers and the frequency divider group (120) comprises N frequency dividers; and wherein the trigger group (110) receives N clock signals and a SYNC pulse signal, transmits the N clock signals to the N frequency dividers each, and transmits the N pulse signals output by the trigger group (110) to the N frequency dividers each, where N is a positive integer greater than 1.
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Citation Information

Patent Citations

  • Clock synchronization system

    CN121091960A

  • 202410727626.6