Server nodes

Abstract

Server nodes, including: A housing comprising a server node body for accommodating a motherboard; wherein the motherboard comprises: (i) a BIOS / BMC load module, (ii) a first security chip of an ASTXXXX type, and (iii) a second security chip of a CECXXX type; where the first security chip and the second security chip are connected to the BIOS / BMC load module via a switch; the switch is configured to selectively activate operation of the first security chip and the second security chip.

Description

TECHNOLOGY AREA

[0001] The present technology relates to a computer node and, in particular, to a computer node with security microchips. BACKGROUND

[0002] A server is a central computer that typically serves computers in a network environment, providing necessary functions such as storing, processing, and exchanging information to these network computers. Conventional servers can be implemented similarly to conventional personal computers and typically include a central processing unit (CPU), one or more memories, and one or more input / output devices, all of which are internally coupled to communicate via a bus. These internal components of the server, or server hardware, operate according to inherent specifications and can be affected by external factors such as temperature, humidity, pressure, and the like. A server rack may include a plurality of computer nodes.

[0003] A compute node uses firmware related to the node's boot functions. The firmware initially boots the hardware components, checks for driver errors, and so on. In data center-based solutions, it is critical to validate the hardware components and their immutability during boot of the compute node and / or server rack. Especially during boot of the compute node and / or server rack, there is a need to validate that there are no changes in the server firmware that could lead to a security breach, for example, to steal data or generate spurious traffic. SUMMARY

[0004] Embodiments of the present technology have been developed based on developers' recognition of the need for firmware security measures. To this end, security chips can be deployed to provide protection against a wide range of cyber threats. Security chips can incorporate advanced encryption, authentication, and intrusion detection mechanisms. Security chips can also incorporate tamper-evident features to thwart physical attacks on devices incorporating these chips.

[0005] However, developers have also found that security chips lack versatility or interoperability when integrated into a variety of devices and systems, ranging from personal computers and mobile devices to server racks and / or other critical infrastructure components. Embodiments of the present technology were developed based on the developers' findings regarding at least one technical problem related to the prior art solutions.

[0006] In one aspect of the present technology, a server node is provided comprising a chassis having a server node body for receiving a motherboard, the motherboard comprising: (i) a BIOS / BMC load module, (ii) a first security chip of an ASTXXXX type, and (iii) a second security chip of a CECXXX type. The first security chip and the second security chip are connected to the BIOS / BMC load module via a switch. The switch is configured to selectively enable operation of the first security chip and the second security chip.

[0007] In some embodiments of the server node, the switch comprises a first jumper connected to the first security chip and a second jumper connected to the second security chip.

[0008] In some embodiments of the server node, the switch includes a programmable element.

[0009] In some embodiments of the server node, the programmable element is a field programmable gate array (FPGA).

[0010] In some embodiments of the server node, the first jumper is a first hardware jumper and the second jumper is a second hardware jumper.

[0011] In some embodiments of the server node, the first jumper is a first software jumper and the second jumper is a second software jumper. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] These and other features, aspects, and advantages of the present technology will be better understood from the following description, the appended claims, and the accompanying drawings: Fig. 1 is a front left perspective view of a server rack housing a chassis structure; Fig. 2 is a perspective view of the housing structure of Fig. 1 from the front left, with a first and a second computer node in a received position and a plurality of electronic components; Fig. 3 is a perspective view of a housing of the housing structure of Fig. 1 from the front left, with fans and the first and second computer nodes removed; Fig. 4 is an exploded view of the housing and the second computer node of Fig. 2 from the front left, with the electronic components of the second computer node removed, the fans removed, and the first computer node removed; Fig. 5 is a front perspective view of the housing structure of Fig. 2 from the left, with the first computer node in a first extended position and the second computer node removed; Fig. 6 is a perspective view of the housing structure of Fig. 5 from the front left, with the first computer node in a second, extended position and the fourth electronic components in a stored position; Fig. 7 is a plan view of the housing structure of Fig. 2 from above showing different sections of the fluid flow during operation; Fig. 8 is a perspective view of the housing structure of Fig. 2 from the back right; Fig. 9 is a circuit diagram of a motherboard of the second computer node of Fig. 2; and Fig. 10 shows a subsystem of the main board from Fig. 9, which is implemented in accordance with some embodiments of the present technology. DETAILED DESCRIPTION

[0013] The examples and optional language provided herein are intended primarily to facilitate the reader's understanding of the principles of the present technology, and not to limit its scope to the specifically cited examples and conditions. It is recognized that those skilled in the art may devise various arrangements that, while not expressly described or shown herein, nevertheless embody the principles of the present technology and are included within its spirit and scope.

[0014] Furthermore, to aid understanding, the following description may describe relatively simplified embodiments of the present technology. As those skilled in the art will understand, various embodiments of the present technology may be of greater complexity.

[0015] In some cases, examples of modifications to the present technology that are considered helpful may also be provided. This is done solely as an aid to understanding and, as stated, not to define the scope or explain the limitations of the present technology. These modifications are not an exhaustive list, and one skilled in the art may make other modifications while remaining within the scope of the present technology. Furthermore, if no examples of modifications are listed, this should not be interpreted to mean that no modifications are possible and / or that what is described is the only way to implement that element of the present technology. Housing structure

[0016] In Fig. 1 illustrates a server rack 1200 that houses a chassis structure 100 from a plurality of chassis structures (unnumbered). Thus, the chassis structure 100 can be said to be configured to be housed within the server rack 1200. Roughly speaking, one or more chassis structures of the server rack 1200 are configured to process processable requests and / or tasks for an external client. For example, data indicative of a given processable request can be captured by one or more electronic components of the chassis structure 100 (and / or by electronic components of other chassis structures of the server rack 1200). This data can then be processed and / or stored by the one or more electronic components of the chassis structure 100.

[0017] As in Fig. 2, the chassis structure 100 includes a chassis 200 and two computer nodes, namely a first computer node 301 and a second computer node 302. The chassis structure 100 also includes fans 400 at its rear. It is contemplated that in alternative embodiments of the present technology, the fans 400 may be omitted. It is further contemplated that the fans 400 may alternatively be provided at a rear portion of the server rack 1200. It should be noted that in some embodiments of the present technology, the first computer node 301 may be identical to the second computer node 302. Housing

[0018] How the housing 200 of the housing structure 100 may be implemented in at least some embodiments of the present technology will now be described with reference to Fig. 3 described.

[0019] As in Fig. 3, the housing 200 includes a first bottom plate 202, a first side wall 204, a second side wall 206, a partition wall 208, and a rear wall 210. The first side wall 204 and the second side wall extend longitudinally within the housing 200 and are disposed on respective sides of the first bottom plate 202. The partition wall 208 also extends longitudinally within the housing 200 and is disposed between the first side wall 204 and the second side wall 206. The partition wall 208 is substantially parallel to the first side wall 204 and the second side wall 206. The rear wall 210 extends laterally between and connects to the first side wall 204 and the second side wall 206 at the rear of the housing 200.

[0020] The first side wall 204, the second side wall 206, the partition wall 208, and the rear wall 210 are attached to the first bottom plate 202 of the housing 200 using suitable fasteners, such as bolts and / or screws. Alternatively, the first side wall 204, the second side wall 206, the partition wall 208, and the rear wall 210 may be integrally formed with the first bottom plate 202 to provide the housing 200.

[0021] The backplane 210 is also configured to receive, among other things, a power connector 214, motherboard connector 216, and other (unnumbered) connectors discussed in more detail below. The backplane 210 is provided with openings 212 that, generally speaking, allow fluid communication between an interior of the housing 200 and the exterior of the housing 200 through the backplane 210.

[0022] It should be noted that in the Fig. 3, the fans 400 are removably attached to the rear wall 210 on the exterior of the enclosure 200. As illustrated, when removably attached to the rear wall 214, the fans 400 are longitudinally aligned with the respective openings 212. As described in more detail below, positioning the fans 400 with respect to the openings 212 allows the fans 400 to create a fluid flow(s) in accordance with direction 250—i.e., from the interior of the enclosure 200 through the rear wall 210 to the exterior of the enclosure 200.

[0023] It should be noted that the first side wall 204, the second side wall 206, the partition wall 208 and the rear wall 210 as well as the first bottom plate 202 define two storage spaces in the housing 200, namely a first storage space 270 and a second storage space 260.

[0024] The first storage space 270 is defined by the first floor panel 202, the first side wall 204 on the left side, the partition wall 208 on the right side, and the rear wall 210 on the back. Similarly, the second storage space 260 is defined by the first floor panel 202, the second side wall 206 on the right side, the partition wall 208 on the left side, and the rear wall 210 on the back. The two storage spaces 120 are arranged on the respective sides of the partition wall 208. In a particular non-limiting embodiment of the present technology, the two storage spaces 270 and 260 may be substantially identical to each other.

[0025] The housing handles 285 are provided on the first bottom plate 202 and extend forwardly away from the housing 200.

[0026] The first storage space 270 of the housing 200 is configured to accommodate the first computer node 301 (see Fig. 1), and the second storage space 260 of the housing 200 is configured to accommodate the second computer node 302 (see Fig. 1) or vice versa. One can say that a given one of the two storage spaces 270 and 260 accommodates a corresponding one of the computer nodes 301 and 302. Computer nodes

[0027] How the second computer node 302 is implemented will now be explained with reference to Fig. 4. However, it should be noted that the first computer node 301 may be implemented in a similar manner to the second computer node 302 without departing from the scope of the present technology.

[0028] In Fig. 4 shows an exploded view of the housing 200 and the second computer node 302. It should be noted that the first computer node 301 and the internal components of the housing structure 100 are shown in Fig. 4 have been omitted. Also, the illustration 300 of the housing 200 and the second computer node 302 is a simplified illustration of the housing 200 and the second computer node 302, for the sake of simplicity only.

[0029] As can be seen, the second computer node 302 includes a body 304, a compartment frame 320, and a slide assembly 325, which will now be described in turn.

[0030] The body 304 includes a second bottom plate 306, a third side wall 308, and a fourth side wall 310. The third side wall 308 and the fourth side wall 310 extend longitudinally within the body 304 and are disposed on respective sides of the second bottom plate 306. The computer node handle 280 is provided on the second bottom plate 306 and extends forwardly away from the body 304. The third side wall 308 and the fourth side wall 310 are attached to the second bottom plate 306, but may alternatively be formed integrally with the second bottom plate 306.

[0031] It should be noted that a particular computer node is configured to be removed from a corresponding storage space, which may be desirable for a variety of reasons. For example, the particular computer node may be removed from the respective storage space by an operator for maintenance and / or replacement purposes. Thus, it can be said that the body 304 is configured to be removably stored in the second storage space 260. Consequently, it can be said that the second computer node 302 can be removably stored in the second storage space 260.

[0032] The body 304 also has a front portion 312 and a rear portion 314. The front portion 312 of the body 304 and the rear portion 314 of the body 304 are arranged longitudinally sequentially in the body 304 from the front end thereof to the rear end thereof.

[0033] The front portion 312 of the body 304 is configured to receive the tray frame 320. The tray frame 320 has two sides (unnumbered) and includes a top access opening 322. The tray handle 290 is provided on one of the two sides of the tray frame 320 and extends forwardly from the tray frame 320. The tray frame 320 is slidably movable from a received position to at least one extended position such that when the tray frame 320 is in the received position, the tray frame 320 is located within the front portion 312 of the body 304.

[0034] It should be noted that the compartment frame 320 is configured to move slidably between the retrieved position and the at least one extended position due to the sliding assembly 325 of the second computer node 302. The sliding assembly 325 is disposed in the front portion of the body 304. The sliding assembly 325 includes a particular side of the compartment frame 320 and the corresponding fourth sidewall 310 of the body 304. However, the sliding assembly 325 may also include the other side of the compartment frame 320 and the corresponding third sidewall 308. However, in some embodiments, the second computer node 302 may have two sliding assemblies, one on each side of the compartment frame 320, and may be implemented similarly to the sliding assembly 325.

[0035] In one embodiment, the given side of the compartment frame 320 may be embedded into the corresponding sidewall of the body 304 to provide the sliding arrangement 325. In other words, the corresponding sidewall of the body may be configured to receive the particular side of the compartment frame 320 in an embedded manner to provide a sliding arrangement. In another embodiment, the corresponding sidewall of the body may be configured to nest the particular side of the compartment frame 320 within one another to provide a sliding arrangement. In another embodiment, the given side of the compartment frame 320 and the corresponding sidewall of the body 304 may include suitable barrier structures to provide the sliding arrangement 325.

[0036] It should be noted that the sliding assembly 325 may be implemented in different ways for a particular application of the present technology. However, the sliding assembly 325 is configured to longitudinally and slidably support a respective compartment frame of a particular computer node between (i) a received position (see Fig. 2), (ii) a first extracted position (see Fig. 5) and (iii) a second extended position (see Fig. 6). As will be apparent from the description below, the purpose of sliding the respective compartment frame is to provide access or additional access to at least some electronic components of the respective computer node without requiring removal of the respective computer node from the housing 200.

[0037] It should also be noted that the second computer node 302 also includes a chain structure 3020 (see Fig. 7). The chain structure 3020 is attached (i) to the tray frame 320 at a rear side of the tray frame 320 at one end thereof, and (ii) to the second bottom plate 306 of the body 304 at the other end thereof. Generally, the chain structure 3020 is provided to prevent the risk of the tray frame 320 being pulled out of the body 304 to the point where it detaches therefrom. It can be said that the chain structure 3020 can limit the position of the tray frame 320 and cooperates with the slide assembly 325 to prevent the tray frame 320 from accidentally falling out or detaching from the body 304.

[0038] It is contemplated that in at least some embodiments of the present technology, the chain structure 3020 may be pivotally attached to the tray frame 320 at the rear of the tray frame 320 at one end thereof and pivotally attached to the second bottom plate 306 of the body 304 at the other end thereof.

[0039] In addition to connecting the compartment frame 320 to the housing 304, the chain structure 3020 may define a hollow passageway (unnumbered) for receiving cables for electrically coupling at least some electronic components in the compartment frame 320 to at least some other electronic components in the body 304. Electronic components

[0040] As previously mentioned, the second computer node 302 is configured to accommodate electronic components for data processing and / or storage purposes. It should be noted that at least some of the electronic components are housed in the compartment frame 320, while other electronic components are housed in the body 304. Which of the electronic components of the second computer node 302 are housed in the compartment frame 302 (e.g., housed in the front portion 312 of the body 304) and which electronic components of the second computer node 302 are housed in the body 304 (e.g., housed in the rear portion 314 of the body 302) will now be explained with reference to the two Fig. 7 and Fig. 8 described.

[0041] The second computer node 302 accommodates first electronic components 1000 and fourth electronic components 2000 in the compartment frame 320. In general, the first electronic components 1000 and the fourth electronic components 2000 may be different types of storage media. For example, the first electronic component 1000 may be a hard disk drive (HDD). The fourth electronic component 2000 may be a solid-state drive (SSD) or a non-volatile memory storage medium (NVME). The first electronic component 1000 may be arranged at the front of the compartment frame 320, and the fourth electronic component 2000 may be arranged at the rear of the compartment frame 320 (longitudinally behind the first electronic component 1000).

[0042] The rear portion 314 of the second computer node 302 houses a motherboard 3000. The motherboard 3000 is electrically coupled to the first electronic components 1000 and the fourth electronic components 2000 via cabling (not shown), as is known in the art. The motherboard 3000 is also electrically connected to the power connector 214 via the motherboard connector 216. For example, the power connector 214 may be electrically connected to a power bus of the server rack 1200 (see Fig. 1) and in turn be connected to a power source and provide power to the motherboard 3000 and other electronic components of the second computer node 302. motherboard

[0043] With reference to Fig. 9, the motherboard 3000 is described in more detail. The motherboard 3000 includes two central processing units (CPUs), namely a first CPU 3014 and a second CPU 3016. The first CPU 3014 and the second CPU 3016 are connected to the motherboard 3000. It is contemplated that the first CPU 3014 and the second CPU 3016 may be communicatively coupled and / or electrically connected to one or more other electronic components via the motherboard 3000. In some embodiments of the present technology, each of the first and second CPUs 3014, 3016 is insertable into a corresponding socket on the motherboard 3000. In some embodiments, the sockets are identical, so that the first and second CPUs 3014, 3016 are interchangeable.In alternative embodiments, one socket is configured to receive the first CPU 3014 and the other socket is configured to receive the second CPU 3016, such that one socket is dedicated to the first CPU 3014 and the other socket is dedicated to the second CPU 3016. Although two CPUs 3014, 3016 are depicted, any number of CPUs may be connected to the motherboard 3000 without departing from the scope of the present technology.

[0044] The mainboard 3000 includes a platform control node 3018. The platform control node 3018 is connected to the mainboard 3000. It is contemplated that the platform control node 3018 may be communicatively coupled and / or electrically connected to one or more other electronic components via the mainboard 3000. The platform control node 3018 is further connected to the first CPU 3014 and the second CPU 3016.

[0045] It should be noted that a Platform Controller Hub (PCH) is a component in computer architectures that serves as a central hub for managing and controlling various functions of a computer's motherboard, such as the Motherboard 3000. It acts as a communication and management center, facilitating the flow of data between one or more CPUs, memory, storage devices, and / or peripherals. It is envisioned that the PCH 3018 could also be used for tasks such as connecting USB ports, SATA ports, Ethernet ports, audio components, and other input / output interfaces to the Motherboard 3000. The PCH 3018 can also handle power management, system configuration, and various low-level operations that enable interoperability between different hardware components.By consolidating one or more of these functions onto a single chip, the PCH 3018 helps streamline communication and coordination between different hardware components, thereby optimizing overall system performance and efficiency. The PCH 3018 is designed to support a variety of interfaces and connectivity options.

[0046] The motherboard 3000 further includes a Baseboard Management Controller (BMC) chip 3021 for remote management, monitoring, and control of the hardware. The BMC chip 3021 may include a Serial Peripheral Interface (SPI) flash device 3043. The BMC chip 3021 is integrated into the motherboard 3000 and connected via an SPI bus 3044. In some embodiments of the present technology, the BMC chip 3021 may be connected via an Inter-Integrated Circuit (I2C) 3040 and / or a System Management Bus (SMBus). The BMC chip 3021 contains firmware memory, which includes code for remote management and monitoring functions and is typically stored in a flash memory chip located on the motherboard 3000. As shown in Fig. 9, the BMC chip 3021 is connected to the platform control node 3018 via a first multiplexer 3024.

[0047] It is envisioned that a BMC can be implemented as a specialized microcontroller embedded in a computer's motherboard, such as the 3000 motherboard. As such, a BMC chip can be responsible for monitoring, managing, and controlling various aspects of a system, even when a CPU is powered off or unresponsive. The 3021 BMC chip can be used for remote management, system health monitoring, and maintenance of servers, network devices, and other enterprise-level hardware. For example, the 3021 BMC chip can be used for system security by enabling features such as remote BIOS updates, monitoring intrusion detection sensors, and providing a secure interface for managing encryption keys.

[0048] An SPI flash device 3022 for a Basic Input-Output System (BIOS) is connected to the motherboard 3000. The SPI flash device 3022 is connected to the motherboard 3000 via an SPI bus 3042. In some embodiments of the present technology, the SPI flash device 3022 may be connected via an I3C or an SMBus. The SPI flash device 3022 stores instructions for hardware initialization and the boot process in memory and facilitates communication between the operating system and hardware components during boot. As shown in Fig. 9, the SPI flash device 3022 is connected to the PCH 3018 via a second multiplexer 3024.

[0049] An SPI flash device is broadly a type of non-volatile memory used in electronic devices such as embedded systems, microcontrollers, and other hardware components. An SPI flash device can store data when the power supply is interrupted and is accessible via the SPI protocol. SPI flash memory comes in various capacities and is used for storing firmware, boot sequences, configuration data, and other information that must be retained across power cycles. The SPI protocol is a synchronous communication protocol commonly used for connecting microcontrollers, sensors, and other peripheral devices to the CPU or other microcontrollers. It incorporates a master-slave architecture in which one device (the master) controls communication with one or more peripheral devices (the slaves).SPI uses a clock signal and multiple data lines to transfer data between devices. The clock signal synchronizes the data transfer, and data can be exchanged in full-duplex mode, allowing simultaneous sending and receiving of data. The SPI protocol is widely used for tasks including reading and writing to storage devices (e.g., SPI Flash), controlling peripherals such as sensors and displays, and enabling communication between microcontrollers in various embedded systems. Compared to other communication protocols such as I2C, it may require more pins.

[0050] When the server boots up, validation of the software and / or hardware components should be performed to determine if they have been modified by hackers or fraudulent users who can modify the server(s) firmware to steal data and / or generate false traffic. Microchips incorporating security checks can be implemented that can verify the server's operating system and hardware components. Specifically, the present technology employs a microchip from the ASTxxxx 3021 chip series from AspeedTech™ for the BMC chip 3021. It is recognized that, in this context, the identifier of xxxx is an indication of a serial number associated with the ASTxxxx chip series. In embodiments of the present technology, an AST2xxx 3021 chip may be used, such as the AST2600. The present technology employs a microchip from the CECxxx 3023 chip series from Microchip™ for the BIOS chip 3023.It is acknowledged that, in this context, the identifier xxx indicates a serial number associated with the CECxxx chip series. In embodiments of the present technology, a CEC173x chip 3023 is employed.

[0051] The AST2xxx chip 3021 provides security features such as secure boot, encryption, and remote authentication to protect the server and its management functions. The AST2xxx chip 3021 uses a special memory area that writes instructions once, preventing any ability to overwrite the instructions.

[0052] The CEC173x chip 3023 serves as a root of trust, providing robust security features such as hardware-based cryptographic acceleration, secure boot, secure key storage, and encryption capabilities, making the CEC173x chip suitable for a high level of data security.

[0053] Both the AST2xxx chip 3021 and the CEC173x chip 3023 are integrated into the motherboard 3000. Having both the AST2xxx chip 3021 and the CEC173x chip 3023 on the same motherboard 3000 provides end users with flexibility and adaptability to optimize chip selection for their server / data center requirements. In other words, end users can choose whether to connect the AST2xxx chip 3021 or the CEC173x chip to best meet their needs.

[0054] The AST2xxx chip 3021 and the CEC173x chip 3023 can be connected to the motherboard 3000 via a jumper 3028 and 3029, respectively. A host RST line 3045 is used in combination with the jumper 3028, and a BMC RST line 3046 is used in combination with the jumper 3029. Generally, the host RST line 3045 and the BMC RST line 3046 correspond to wired (circuit) communication lines for reboot command transmission to reboot the host and the BMC, respectively.

[0055] Broadly speaking, a jumper connection, often simply referred to as a "jumper," is an electrical component used in electronics and computer hardware to set up and / or change the behavior of a device and / or circuit. In some designs, a jumper comprises a pair of conductive metal pins or "terminals" that can be connected and / or disconnected using a plastic cap or metal bridge. Jumper connections are used to specify specific settings and modes on printed circuit boards, such as motherboards. They allow operators to select options without the need for special software or programming. By placing or removing the jumper cap on the corresponding pins, certain functions or configurations can be selectively enabled or disabled.

[0056] In some cases, jumpers can be used to set hardware parameters such as master / slave drive settings, clock frequencies, voltage levels, and data transfer modes. For example, with hard drives, they can determine whether a drive is set as master or slave in a dual-drive configuration. In other cases, a particular motherboard may be equipped with a jumper that clears BIOS or CMOS settings, effectively resetting the hardware to its default values. In yet other cases, jumpers can enable or disable specific features or components on a circuit board, as explained here.

[0057] In some embodiments, one or more jumpers may be implemented as software jumpers, as opposed to physical / hardware jumpers. A software jumper can enable the same functionality as a hardware jumper using software commands, without necessarily requiring physical manipulation. It is envisioned that a software jumper may enable configuration settings to be changed via software interfaces or commands, which can be easily and remotely changed compared to hardware jumpers. This virtual approach to jumper functionality allows for dynamic reconfiguration and customization. They provide flexibility to adjust system behavior, settings, and / or operating modes without requiring operators to access the physical hardware. This simplifies maintenance, troubleshooting, and system upgrades.In some embodiments, a software jumper may be implemented via one or more built-in BIOS commands.

[0058] Note that the AST2xxx chip 3021 is connected to a first jumper 3024, and the CEC173x chip 3023 is connected to a second jumper 3026. In this embodiment, the first and second jumpers 3028, 3029 are physical connectors with a jumper cap used to close the circuit on the motherboard 3000. The end user can select whether the AST2xxx chip 3021 or the CEC173x chip is connected by connecting the respective jumper 3028, 3029. When the first jumper 3028 is connected, the AST2xxx chip 3021 is connected. Similarly, the CEC173x chip is connected when the second jumper 3029 is connected. In other embodiments of the present technology, it is conceivable that the first and second jumpers 3028, 3029 are other forms of connectors without departing from the scope of the present technology.

[0059] In some embodiments, a server node is provided. The server node may include a body that houses a motherboard. More specifically, the motherboard includes (i) a load module, such as a BIOS / BMC module, (ii) a first security chip, such as the AST2xxx chip, and (iii) a second security chip, such as the CEC173x chip. The first security chip is associated with a first connection and a first jumper on the motherboard, and the second security chip is associated with a second connection and a second jumper on the motherboard.

[0060] During operation, one or more components of the motherboard may be configured to deploy the first security chip and / or the second security chip by closing and / or opening the first jumper and / or the second jumper. In some embodiments, the one or more components of the motherboard may deploy the first jumper and the second jumper to selectively and interchangeably deploy the first security chip and the second security chip during operation of the server node.

[0061] In some embodiments, the functionality of one or more jumpers can be implemented by a switch that includes a programmable element. The switch can, for example, comprise field-programmable gate arrays (FPGAs), which are integrated circuits with reconfigurable hardware functionality. Unlike traditional application-specific integrated circuits (ASICs), FPGAs can be programmed and reprogrammed after manufacturing, allowing rapid adaptation to different computing tasks. FPGAs consist of a matrix of programmable logic blocks interconnected by configurable routing channels, allowing users to create custom digital circuits or even entire processors.

[0062] In some embodiments, the motherboard 3000 may be configured to implement one or more secure boot mechanisms. Note that both the first security chip and the second security chip may include respective Roots of Trust (RoTs) that may be used to verify firmware and / or generate reset signals for application processors. It is contemplated that a first RoT of the first security chip or a second RoT of the second security chip may be selectively used, depending on, among other things, the needs or configuration of a client system.

[0063] With reference to Fig.Figure 10 illustrates subsystem 1000, which includes a RoT device 1002, an application processor 1004, and a flash device 1006. Broadly speaking, the RoT device 1002 is a hardware component configured to store encryption keys used in a "Chain of Trust" (CoT), in which the code to be executed is first verified. In computer security, a CoT is established by validating each hardware and software component, from the end device to the root certificate. The intention is to ensure that only trusted software and hardware can be used, while still maintaining flexibility.

[0064] During the verification process, if the code to be executed at a particular time and / or in a particular server state is valid / legitimate, the cryptographic signature can be calculated and verified by the RoT device 1002 to be executed. This process utilizes the public / private key pair—the private key is used to generate the signature, and the public key is used to verify that the signature is correct (i.e., that the signed file has not been modified). On the one hand, access to the private key is controlled or kept "secret" from a signature-generating environment. On the other hand, the public key is written to the RoT device 1002 and used by the hardware to verify the firmware.

[0065] Additionally or alternatively, the RoT device 1002 may be configured to perform data encryption and / or decryption mechanisms (without key disclosure), key generation mechanisms, key revocation mechanisms, storage of at least some boot settings, and the like. Although the RoT device 1002 is considered "secure"—that is, retrieving cryptographic data from the device is complex—the developers of the present technology have recognized that it may be advantageous for security purposes to avoid storing private keys in RoT devices.

[0066] It is contemplated that a one-time programmable (OTP) storage device may further be used to store cryptographic data and hardware settings. Depending on the specific embodiment of a RoT device, hardware bootstrap and other settings may also be stored in a corresponding OTP storage device. In some embodiments, write operations may be performed to configurable areas of the OTP storage device to support key revocation mechanisms after the initial OTP provisioning.

[0067] In some embodiments, it is contemplated that the RoT device 1002 may be used to prevent the execution of untrusted / unverified code on one or more components of the motherboard 3000 and / or the subsystem 1000. To this end, the RoT device 1002 may generate a reset signal for the application processor 1004, such as a BMC or a host device, during the power-on phase, thereby disallowing the execution of a CPU of the application processor 1004. Furthermore, the RoT device 1002 may read data from the firmware of the application processor 1004, generate signatures, and perform verification using the keys in the OTP storage device. In cases where verification fails, the RoT device 1002 may, among other things, program a golden image (immutable firmware known to be secure) into the SPI image of the application processor 1004.Additionally or alternatively, the RoT device 1002 may further transmit signals for reporting the current verification status to external subsystems such as a BMC via an I2C interface.

[0068] Modifications and improvements to the above-described embodiments of the present technology may be apparent to those skilled in the art. The foregoing description is intended to be exemplary rather than restrictive. Therefore, the scope of the present technology should be limited solely by the scope of the appended claims.

Claims

[1] Server nodes, comprising: A chassis comprising a server node body for receiving a motherboard; the motherboard comprising: (i) a BIOS \ BMC load module, (ii) a first security chip of an ASTXXXX type, and (iii) a second security chip of a CECXXX type; wherein the first security chip and the second security chip are connected to the BIOS \ BMC load module via a switch; wherein the switch is configured to selectively activate operation of the first security chip and the second security chip. [2] The server node of claim 1, wherein the switch comprises a first jumper connected to the first security chip and a second jumper connected to the second security chip. [3] The server node of claim 1, wherein the switch comprises a programmable element. [4] The server node of claim 3, wherein the programmable element is a field programmable gate array (FPGA). [5] The server node of claim 2, wherein the first jumper is a first hardware jumper and the second jumper is a second hardware jumper. [6] The server node of claim 2, wherein the first jumper is a first software jumper and the second jumper is a second software jumper.

Images