Data storage device

Abstract

An interface device enables data transfer between a radio transceiver and a mass storage device via a storage bus, with two operation modes: a first mode wherein a receive chain of the transceiver is

Description

The present disclosure relates to an interface device, and a method for transferring data. In particular, the present disclosure relates to an interface device for transferring data between a radio transceiver and a mass storage device via a storage bus. In the field of telecommunications, and in particular during the operation of a radio transceiver, it may be necessary to stream data to or from a mass storage device. For example, a radio transceiver receives a message from another device and it may be desirable to store the data contained in the message onto a mass storage device for later reference. As another example, a radio transceiver may transmit a message to one or more other devices, where data contained in the message is predetermined and stored on a mass storage device. Conventionally, it may be possible to store (e.g. write) received data onto a mass storage device and / or retrieve (e.g. read) data to be transmitted from a mass storage device using a processor. For example, a radio transceiver may interface with a mass storage device via a processor. In such an example, the received data or the data to be transmitted is routed via the processor. This creates a significant amount of computational work for the processor. This can be problematic because the computational resources of the processor may be needed to perform other tasks simultaneously. In order to implement such a system practically, it may be necessary to increase the processing capabilities of the processor in order to handle the streaming of data. This is particularly apparent in examples that involve data streaming to or from a highspeed mass storage device, such as a non-volatile memory express solid state drive (NVMe SSD). In such examples, the processing capabilities of the processor would need to be increased considerably to match the high data transfer rates achievable by the mass storage device. Moreover, in many scenarios, it may be necessary to provide such data streaming capability in a deployable or portable system. For example, such a system may be used for spectral monitoring during scientific analysis of radio frequencies in a particular geographic region. An operator may be sent to the region with a deployable system to gather data, which is streamed to a mass storage device for subsequent analysis by an analyst, who may be located elsewhere. Such a system may also be used in entertainment, or other licensed events, to transmit a pre-recorded message (such as an announcement) stored on the mass storage device. In these and other scenarios, it may not be technically feasible to simply increase the processing capabilities of the processor in order to facilitate data streaming, since this would lead to an increase in the physical size or power requirements of the system. This is disadvantageous in many systems, but particularly in deployable or portable systems. The present invention seeks to provide a means for transferring data to and / or from a mass storage device (e.g. for high-speed data streaming) while reducing the computational burden on an external processor. According to a first aspect of the present disclosure, there is provided an interface device for enabling data transfer between a radio transceiver and a mass storage device, as defined in claim 1. The interface device comprises storage interface logic configured to operate according to two or more operation modes. In a first operation mode, the storage interface logic may be configured to couple a receive chain of the radio transceiver to the storage bus to enable data transfer from the receive chain to the mass storage device. In a second operation mode, the storage interface logic may be configured to couple a transmit chain of the radio transceiver to the storage bus to enable data transfer from the mass storage device to the transmit chain. Advantageously, the storage interface logic enables data to be transferred between the transmit / receive chains and the mass storage device without the data being routed through a processor. As such, the processing load and computational resources required at the processor for the data transfer are reduced, allowing the processor to perform other tasks as needed. In this regard, it may be considered that the storage interface logic is configured to directly couple the receive chain and / or the transmit chain to the storage bus. Similarly, it may be said that this enables direct data transfer from the receive chain or to the transmit chain. The term “couple” in this context therefore refers to any electrical connection that allows the storage interface logic to access (e.g. transfer data via) the storage bus directly, without needing to go through the processor. The interface device described herein has many practical benefits. Firstly, it allows a system that comprises the interface device to be equipped with a less-powerful processor, since the processor is not needed when streaming data to or from the mass storage device. This is particularly advantageous in portable or power-constrained equipment, such as radio equipment that is transported for use in an operational zone (e.g. a location for scientific research or remote communication). Secondly, it allows for streaming of data to or from the mass storage device at much higher speeds than otherwise possible, without increasing the processing capabilities of the processor. That is, the speed of the data transfer between the radio chains and the mass storage device is limited by the storage bus and any intervening components, but is not limited by the processing capabilities of the processor. As used herein, the term “streaming of data” refers to the transfer of data between a mass storage device and a radio chain. A receive chain and a transmit chain are both examples of radio chains in a radio transceiver. A radio transceiver comprises any radio device capable of transmitting and receiving data, regardless of whether this is via a single transceiver antenna (or antenna array) or via separate transmit and receive antennas (or antenna arrays). The receive chain and / or the transmit chain may comprise an antenna and one or more electronic components of the radio transceiver. The first operation mode may be referred to as a write operation mode, because the first operation mode involves the transfer of data from the receive chain to the mass storage device. Data is thus written to the mass storage device in the storage interface logic’s write operation mode. The second operation mode may be referred to as a read operation mode, because the second operation mode involves the transfer of data to the transmit chain from the mass storage device. Data is thus read from the mass storage device in the storage interface logic’s read operation mode. In the first operation mode, the storage interface logic may be configured to couple a data converter of the receive chain, such as an analogue-to-digital converter (ADC), to the mass storage device. In the second operation mode, the storage interface logic may be configured to couple a data converter of the transmit chain, such as a digital-to- analogue converter (DAC), to the mass storage device. As used herein, the term “data converter” refers to a device capable of converting data between the analogue and digital domains. The term “data converter” encompasses both analogue-to-digital converters and digital-to-analogue converters. The storage interface logic may be configured to couple a digital back end, such as a digital signal processor (DSP), of the receive chain and / or of the transmit chain to the mass storage device. The interface device may be for use in a software-defined radio (SDR) system. The transferred data may be any data that is received and / or to be transmitted by the radio transceiver. Such data may be referred to as samples. The samples may be in any suitable format, such as integer or floating point. The samples may be in any base, for example, the samples may be binary. The samples may represent complex or real numbers. The samples may be signed or unsigned. In a particular example, the data may comprise an in-phase component and a quadrature component. Such data be referred to as l / Q data. l / Q data is complex data. In l / Q data, the in-phase component, termed T, represents the real portion of the data and the quadrature component, termed ‘Q’, represents the complex portion of the data. The mass storage device may comprise a non-volatile storage device. For example, the mass storage device may comprise a hard disk drive (HDD) or a solid state drive (SSD). In the latter case, the SSD may use any form factor and storage interface known in the art, including those that may be developed in the future, and suitable for such a purpose. For example, the SSD may use a form factor such as 1.8”, 2.5”, 3.5”, M.2, U.2, or mSATA. The SSD may use a non-volatile memory express (NVMe) storage interface or may use a serial AT attachment (SATA) storage interface. The storage interface logic may comprise an NVMe logic block or a SATA logic block. In a particular example, the mass storage device comprises an NVMe SSD (e.g. an M.2 NVMe SSD) and the storage interface logic comprises an NVMe logic block. The storage bus may comprise a serial storage bus. For example, the storage bus may comprise a peripheral component interconnect express (PCI-express or PCIe) bus or a SATA bus. The storage bus may comprise any storage bus known in the art, including those that may be developed in the future, and suitable for such a purpose. In a particular example, the interface device may enable data transfer between a radio transceiver and a NVMe SSD (e.g. an M.2 NVMe SSD) via a PCIe bus. In such an example, the interface device may comprise an NVMe logic block configured to operate according to the two or more operation modes described herein. Optionally, the storage interface logic is configured to operate in a third operation mode, in which the storage interface logic is configured to couple a processor to the storage bus to enable data transfer between the mass storage device and the processor. Advantageously, the storage interface logic allows a processor (e.g. belonging to an external system) to transfer data to and from the mass storage device. In other words, the interface device allows standard system access, for example, to enable the processor to read and write files and manage a file system on the mass storage device, while still allowing the reduction of processing demand when streaming data from the radio transceiver. The data transfer between the mass storage device and the processor may be two-way data transfer. The processor may be understood to be an external processor that does not form a part of the interface device. The third operation mode may be referred to as a system-access operation mode, because the third operation mode allows the processor (e.g. belonging to an external system) to exchange data with the mass storage device. The storage interface logic may be configured to operate in any or all of the three operating modes at the same time. For example, the storage interface logic may operate according to both the first and second operating modes at the same time. In this example, data received via the receive chain is written to the mass storage device whilst data is simultaneously read from the mass storage device for transmission via the transmit chain. As another example, the storage interface logic may operate according to both the first and third operating modes at the same time. In this example, data received via the receive chain is written to the mass storage device whilst the processor reads data from and / or writes data to the mass storage device. As yet another example, the storage interface the storage interface logic may operate according to both the second and third operating modes at the same time. In this example, data is read from the mass storage device for transmission via the transmit chain whilst also allowing the processor to have read and / or write access to the mass storage device. In another example, the storage interface logic may operate according to both the first, second and third operating modes at the same time. Optionally, the storage interface logic is further configured to switch between the operation modes upon receipt of a control signal. Advantageously, monitoring for a control signal allows the interface device to switch between the operation modes on demand. This, in turn, allows the interface device to permit system access (e.g. via the processor) when required, and then switch to streaming data to and / or from the radio transceiver (i.e. without placing demand on the processor). The storage interface logic may be configured to receive the control signal from the processor. The storage interface logic may be configured to receive the control signal from one or more drivers executed by the processor. For example, the storage interface logic may be configured to receive a write-operation control signal. Upon receipt of the write-operation control signal, the storage interface logic operates according to the first operation mode. The storage interface logic may be configured to receive a read-operation control signal. Upon receipt of the readoperation control signal, the storage interface logic operates according to the second operation mode. The storage interface logic may be configured to receive a systemaccess control signal. Upon receipt of the system-access control signal, the storage interface logic operates according to the third operation mode. Alternatively or additionally, the storage interface logic may be configured to receive a stream-operation control signal. Upon receipt of the stream-operation control signal, the storage interface logic may be configured to operate according to the first and second operation modes, depending on the activity of the radio transceiver. That is, the storage interface logic may be configured to switch between the first and second operation modes based on the behaviour (e.g. transmission or reception) of the radio transceiver, without receiving an explicit control signal. Optionally, the interface device is a programmable logic block for embedding in a programmable logic device. The programmable logic block may otherwise be called a programmable logic element, a configurable logic block (CLB), or a configurable logic element (OLE). Alternatively or additionally, the interface device may be implemented in a plurality of discrete logic gates. According to a second aspect of the present disclosure, there is provided a programmable logic device, as defined in claim 5. The programmable logic device comprises the interface device as described herein. The programmable logic device may be a field-programmable logic device. The field-programmable logic device may be a field-programmable gate array (FPGA), such as those manufactured by Xilinx ®. At least a portion of the receive chain and / or at least a portion of the transmit chain may be implemented by one or more programmable logic blocks of the programmable logic device. Optionally, the programmable logic device may further comprise a storage bus. The storage bus may be for connecting to a mass storage device to enable data transfer between the mass storage device and the programmable logic device. The storage bus may comprise a serial storage bus. For example, the storage bus may comprise a PCIe bus or a SATA bus. The storage bus may comprise any storage bus known in the art, including those that may be developed in the future, and suitable for such a purpose. As described above, the storage bus enables data transfer between the mass storage device and the programmable logic device, and the storage interface logic is configured to facilitate onwards data transfer between the storage bus and the receive chain and / or the transmit chain. That is, in the first operation mode, the storage interface logic enables transfer of data from the receive chain to the storage bus and the storage bus enables transfer of the data from the programmable logic device to the mass storage device. In the second operation mode, the storage bus enables transfer of data from the mass storage device to the programmable logic device and the storage interface logic enables transfer of the data from the storage bus to the transmit chain. Optionally, the programmable logic device may further comprise bus interface logic. The bus interface logic may be configured to control the data transfer between the mass storage device and the programmable logic device via the storage bus. The data transfer via the storage bus may comprise data transfer via the bus interface logic. The bus interface logic may comprise a root complex. The bus interface logic may be implemented in a programmable logic block of the programmable logic device. In examples in which the storage bus comprises a PCIe bus, the bus interface logic may comprise a PCIe logic block, such as a PCIe root complex. By way of comparison between two of the programmable logic blocks discussed herein, it will be understood that the bus interface logic controls the data transfer between the mass storage device and the programmable logic device, and the storage interface logic controls the data transfer between the programmable logic device and the transmit chain and / or the receive chain. Optionally, the programmable logic device may further comprise a converter bus. The converter bus may be for connecting to a data converter of a radio transceiver to provide an interface between the radio transceiver and the programmable logic device. More specifically, the converter bus may be for connecting to the data converter to provide an interface between the radio transceiver and the storage interface logic. In this regard, it may be considered that, in the first operation mode, the storage interface logic is configured to couple the receive chain of the radio transceiver to the storage bus, via the converter bus, to enable data transfer from the receive chain to the mass storage device. Similarly, it may be considered that, in the second operation mode, the storage interface logic is configured to couple the transmit chain of the radio transceiver to the storage bus, via the converter bus, to enable data transfer from the mass storage device to the transmit chain. The converter bus may be for connecting to an ADC and / or a DAC of a radio transceiver. The converter bus may be for connecting the data converter to a DSP in the receive chain and / or in the transmit chain. The DSP may be implemented in a programmable logic block of the programmable logic device. The converter bus may be a JESD204B bus. Advantageously, a JESD204B bus provides high-speed data transfer suitable for the speed and latencies required of a radio transceiver. According to a third aspect of the present disclosure, there is provided a system, as defined in claim 9. The system may comprise the interface device as described herein. The system may further comprise a radio transceiver. The radio transceiver may further comprise one or more electronic components defining a receive chain and a transmit chain of the radio transceiver. The system may be referred to as a software-defined radio (SDR) system. The receive chain and / or the transmit chain may further comprise one or more programmable logic blocks of the programmable logic device. The radio transceiver may further comprise an antenna. The antenna may be capable of transmitting and receiving data. The antenna may therefore form part of the receive chain and part of the transmit chain. Alternatively, the radio transceiver may comprise a receive antenna forming part of the receive chain and a transmit antenna forming part of the transmit chain. Optionally, the receive chain comprises an analogue front-end and a digital back-end. The analogue front-end of the receive chain may be connected to the digital back-end of the receive chain via a data converter. Alternatively or additionally, the transmit chain comprises an analogue front-end and a digital back-end. The analogue front-end of the transmit chain may be connected to the digital back-end of the receive chain via a data converter. The receive chain may comprise an analogue front-end and a digital back-end, wherein the analogue front-end is connected to the digital back-end via an analogue-to-digital converter (ADC). The transmit chain may comprise an analogue front-end and a digital back-end, wherein the analogue front-end is connected to the digital back-end via a digital-to-analogue converter (DAC). The analogue front-end of the receive chain and / or of the transmit chain may comprise one or more analogue signal processing components. For example, the analogue frontend of the receive chain may comprise one or more amplifiers, one or more downconverters, one or more filters, and / or any other analogue signal processing components. The analogue front-end of the transmit chain may comprise one or more amplifiers, one or more up-converters, one or more filters, and / or any other analogue signal processing components. The digital back-end of the receive chain and / or of the transmit chain may comprise one or more programmable logic blocks. For example, the digital back-end of the receive chain and / or of the transmit chain may comprise one or more digital signal processors. Optionally, the digital back-end is implemented by one or more additional programmable logic blocks of the programmable logic device. Optionally, the system may further comprise a processor. The processor may be coupled to the programmable logic device. The processor may be configured to execute one or more drivers to communicate with the interface device. The processor may be a microprocessor or a microcontroller. The processor may execute an operating system. The processor may execute an application program using the operating system. The operating system may manage a file system on the mass storage device. The operating system may be a Unix-like operating system, such as Linux. In such an example, the file system may be the ext4 file system. In the third operation mode, the system may be configured to couple the processor to the storage bus using the one or more drivers. The system may be configured to provide a user with access to data stored on the mass storage device via the processor (e.g. via the operating system and / or via the application program). The system may further comprise a system memory coupled to the processor. The system may further comprise a display coupled to the processor. The system may further comprise one or more input devices to enable a user to provide an input to the processor. Optionally, the processor is configured to transmit a control signal to the interface device. The processor may be configured to transmit the control signal to the programmable logic block using a first driver executed by the processor. The control signal may cause the storage interface logic to switch between operation modes. The control signal may be the write-operation control signal, the read-operation control signal, and / or the system-access control signal described herein. Optionally, the processor is configured to, in the third operation mode of the storage interface logic, transmit and receive data from the mass storage device. The processor may be configured to transmit and receive the data from the mass storage device using a second driver executed by the processor. The second driver may be different from the first driver. Optionally, the first driver is a custom driver. The custom driver may be configured to transfer data between the processor and the interface device. Alternatively or additionally, the custom driver may be configured to transfer control signals between the processor and the interface device. A custom driver refers to a driver not typically supplied by the publisher of the operating system or by the designer or manufacturer of the programmable logic device. Instead, a custom driver is specifically made to communicate with the storage interface logic. The data transferred by the first driver (e.g. the custom driver) may comprise output data indicative of the data transfer from the receive chain to the mass storage device and / or of the data transfer from the mass storage device to the transmit chain. The control signals may comprise control signals for controlling the functionality of the programmable logic block, the storage interface logic, the bus interface logic, the transmit chain, the receive chain, and / or the mass storage device. For example, the control signals may comprise the control signal effective to cause the storage interface logic to switch between operation modes. Optionally, the second driver is a standards-compliant driver. The standards-compliant driver may be configured to transfer data between the processor and the mass storage device. Alternatively or additionally, the standards-compliant driver may be configured to transfer control signals between the processor and the mass storage device. A standards-compliant driver may refer to a driver that enables an application program to communicate with a particular (e.g. standardised) storage bus. The standards-compliant driver may be a component of the operating system. Alternatively, the standards-compliant driver may be supplied by the publisher of the operating system and / or by the designer or manufacturer of the bus interface logic. For example, the data transferred by the second driver (e.g. the standards-compliant driver) may comprise operating system data, application data, and / or user data stored by the mass storage device. For example the data transferred by the second driver may comprise: the operating system; applications for execution by the operating system; data for use by the operating system or the applications; samples for transmission by the transmit chain; and / or samples received by the receive chain. The control signals may comprise control signals for controlling the functionality of the programmable logic block, the storage interface logic, the bus interface logic, the transmit chain, the receive chain, and / or the mass storage device. In a particular example, the first driver (e.g. the custom driver) is configured to transfer control signals between the processor and the programmable logic block (for example, control signals for controlling the functionality of the programmable logic block, such as the control signal effective to cause the storage interface logic to switch between operation modes) and the second driver (e.g. the standards-compliant driver) is configured to transfer data between the processor and the mass storage device (for example, application data and / or user data stored by the mass storage device). Optionally, the first driver is configured to generate output data indicative of the data transfer from the receive chain to the mass storage device. Alternatively or additionally, the first driver may be configured to generate output data indicative of the data transfer from the mass storage device to the transmit chain. The first driver may be configured to transmit the output data to an application program executed by the processor. The processor (e.g. by means of the application executed thereon) may be configured to provide the output data as a displayed output to a user via a display coupled to the processor. Optionally, the output data indicative of the data transfer comprises a value indicating the amount of data transferred. That is, the value may indicate how much data has been written to and / or read from the mass storage device. The value may indicate the amount of data transferred within a given time period and / or as part of a single read / write operation. Alternatively or additionally, the output data may comprise one or more values indicating: the current data transfer rate (e.g., in megabits per second, Mbps); a maximum data transfer rate within a given time period and / or as part of a single read / write operation; and / or a minimum data transfer rate within a given time period and / or as part of a single read / write operation. A single read / write operation may comprise the transmission / reception of a single message via the radio transceiver. According to a fourth aspect of the present disclosure, there is provided a method for transferring data between a radio transceiver and a mass storage device via a storage bus, as defined in claim 19. The method may comprise, in a first operation mode, coupling a receive chain of the radio transceiver to the storage bus. The method may further comprise, in the first operation mode, transferring data from the receive chain to the mass storage device. The method may further comprise, in a second operation mode, coupling a transmit chain of the radio transceiver to the storage bus. The method may further comprise, in the second operation mode, transferring data from the mass storage device to the transmit chain. Optionally, the method further comprises, in a third operation mode, coupling a processor to the mass storage device. The method may further comprise, in the third operation mode, transferring data between the mass storage device and the processor. Optionally, the method further comprises receiving a control signal. The method may further comprise, responsive to receiving the control signal, switching between the operation modes. Optionally, the method further comprises generating output data indicative of the data transfer from the receive chain to the mass storage device. Alternatively or additionally, the method further comprises generating output data indicative of the data transfer from the mass storage device to the transmit chain. According to a fifth aspect of the present disclosure, there is provided a computer-readable storage medium, as defined in claim 23. The computer-readable storage medium may comprising a hardware description of the interface device as described herein. Alternatively or additionally, the computer-readable storage medium may comprise a hardware description of the programmable logic device as described herein. The hardware description of the interface device may be executed by a processor to program a programmable logic device to implement the interface device as a programmable logic block. In a particular example, there is provided a programmable logic block for enabling data transfer between a radio transceiver and a non-volatile memory express solid state drive (NVMe SSD) via a peripheral component interface express (PCIe bus). The programmable logic device comprises NVMe logic configured to operate according to two or more operation modes. In a first operation mode, the NVMe logic is configured to couple a receive chain of the radio transceiver to the PCIe bus to enable data transfer from the receive chain to the NVMe SSD. In the second operation mode, the NVMe logic is configured to couple a transmit chain of the radio transceiver to the PCIe bus to enable data transfer from the NVMe SSD to the transmit chain. There is further provided a field-programmable gate array (FPGA) comprising such a programmable logic block. There is further provided a corresponding method for transferring data between a radio transceiver and a NVMe SSD via a PCIe bus. Any features, characteristics, functionality, and / or advantages of each aspect may correspondingly apply to any other of the aspects described herein. In particular, functionality and advantages described in relation to the interface device may equivalently apply to the programmable logic device, the system, the method, and / or the computer-readable storage medium described herein. Brief Description of the Drawings Examples of the present disclosure will now be described with reference to the Figures in which: Figure 1A depicts a system for enabling data transfer between a radio transceiver and a mass storage device via a storage bus, the system operating according to a first operation mode; Figure 1B depicts a system for enabling data transfer between a radio transceiver and a mass storage device via a storage bus, the system operating according to a second operation mode; Figure 1C depicts a system for enabling data transfer between a radio transceiver and a mass storage device via a storage bus, the system operating according to a third operation mode; Figure 2A depicts an example of a receive chain of a radio transceiver; Figure 2B depicts an example of a transmit chain of a radio transceiver; and Figure 3 is a flowchart of an example method for transferring data between a radio transceiver and a mass storage device via a storage bus. Detailed Description Figures 1A-1C depict various operational modes of a system 10. The system 10 comprises a programmable logic device 100, a radio transceiver 200, a mass storage device 300, a processor 400, and a memory 500. The programmable logic device 100 comprises programmable logic 102, which may be implemented as one or more programmable logic blocks. The programmable logic device 100 comprises an interface device 110 for enabling data transfer between the radio transceiver 200 and the mass storage device 300. In the example of Figures 1A-1C, the interface device 110 is implemented as a programmable logic block in the programmable logic device 100. The interface device 110 comprises storage interface logic 112. The functionality of the storage interface logic 112 will be described in detail below. The programmable logic device 100 further comprises a storage bus 120 for connecting to the mass storage device 300 to enable data transfer between the mass storage device 300 and the programmable logic device 100. The programmable logic device 100 further comprises bus interface logic 122 configured to control the data transfer between the mass storage device 300 and the programmable logic device 100 via the storage bus 120. The radio transceiver 200 comprises a receive antenna 210a and a transmit antenna 210b. It will be appreciated that the receive antenna 210a and the transmit antenna 210b may be separate antennas, or may be implemented as a single transceiver antenna. The radio transceiver 200 further comprises one or more electronic components defining a receive chain 220 and a transmit chain 230. The details of the receive chain 220 and the transmit chain 230 are discussed in more detail below with reference to Figures 2A and 2B. The processor 400 executes an application program 410 and an operating system 420. The processor further executes a first driver 432, which may be a custom driver 432. The processor further executes a second driver 434, which may be a standards-compliant driver. The functionality of the first driver 432 and the second driver 434 will be discussed in detail below. The processor 400 is coupled to the memory 500. The memory 500 may be a volatile memory device, such as a random access memory (RAM) device. Various data connections between the components of the system 10 are shown as solid arrows in Figures 1A-1C. Such data connections do not suggest that data is always, or must be, exchanged between the components. The data connections merely illustrate which entities may exchange data during the operations described herein. As used herein, an exchange of data refers to the possibility of two-way data exchange between components, a transfer of data to a component refers to the transmission of data to the component, a transfer of data from a component refers to the reception of data at the component. Explicitly, Figures 1A-1C depict the following data connections between the components. The receive antenna 210a may transfer data to the receive chain 220. The receive chain 220 may transfer data to the interface device 110 (e.g. to the storage interface logic 112). The interface device 110 may exchange data with the processor 400. For example, the interface device 110 may exchange data with the processor 400 via the first driver 432 and / or via the second driver 434. The processor 400 may exchange data with the memory 500. The interface device 110 may exchange data with the storage bus 120 (e.g. with the bus interface logic 122). The storage bus 120 may exchange data with the mass storage device 300. The interface device 110 may transfer data to the transmit chain 230. The transmit chain 230 may transfer data to the transmit antenna 210b. The interface device 110 is configured to operate according to two or more (in this example, three) operation modes. Each of the operation modes will now be described with reference to Figures 1A-1C. Figure 1A depicts the interface device 110 (and thus the system 10) operating according to a first operation mode. In the first operation mode, the storage interface logic 112 is configured to couple the receive chain 220 of the radio transceiver 200 to the storage bus 120 to enable data transfer from the receive chain 220 to the mass storage device 300. This functionality is depicted in the form of dotted arrows that span from the receive antenna 210a, through the receive chain 220, through the interface device 110, through the storage bus 120 and to the mass storage device 300. In other words, data is received via the receive antenna 210a and is transferred to the receive chain 220. The data is processed by the receive chain 220 and then transferred to the interface device 110. The data is then transferred, by the storage interface logic 112, from the interface device 100 to the mass storage device 300 via the storage bus 120. Advantageously, the storage interface logic 112 of the interface device 110 couples the receive chain 220 to the storage bus 120 such that the data from the receive chain 220 is transferred to the mass storage device 300, without any involvement (e.g. processing) by the processor 400. This reduces the computational burden on the processor 400 when streaming data to the mass storage device 300. This process may be controlled by one or more control signals transferred between the processor 400 and the interface device 110 (e.g. by the first driver 432). In particular, the one or more control signals may be transferred between the application program 410 and the interface device 110, via the first driver 432. This is depicted in Figure 1A by the dashed arrow spanning from the application program 410 to the interface device 110. The storage interface logic 112 may be configured to monitor for the one or more control signals. The control signals may control the functionality of the interface device 110, for example, during the first operational mode. Furthermore, the storage interface logic 112 may be configured to monitor for a control signal and, upon receipt of the control signal, switch between operation modes. Figure 1B depicts the interface device 110 (and thus the system 10) operating according to a second operation mode. In the second operation mode, the storage interface logic 112 is configured to couple the transmit chain 230 of the radio transceiver 200 to the storage bus 120 to enable data transfer from the mass storage device 300 to the transmit chain 230. This functionality is depicted in the form of dotted arrows that span from the mass storage device 300, through the storage bus 120, through the interface device 110, through the transmit chain 230, and to the transmit antenna 210b. In other words, data is retrieved from the mass storage device 300 and is transferred, by the storage interface logic 112, from the mass storage device 300 to the interface device 110 via the storage bus 120. The data is then transferred to the transmit chain 230 by the interface device 110. The data is processed by the transmit chain 230 and then transferred to the transmit antenna 210b for transmission. Advantageously, the storage interface logic 112 of the interface device 110 couples the transmit chain 230 to the storage bus 120 such that the data from the mass storage device 300 is transferred to the transmit chain 230, without any involvement (e.g. processing) by the processor 400. This reduces the computational burden on the processor 400 when streaming data from the mass storage device 300. This process may be controlled by one or more control signals transferred between the processor 400 and the interface device 110 (e.g. by the first driver 432). In particular, the one or more control signals may be transferred between the application program 410 and the interface device 110, via the first driver 432. This is depicted in Figure 1B by the dashed arrow spanning from the application program 410 to the interface device 110. The storage interface logic 112 may be configured to monitor for the one or more control signals. The control signals may control the functionality of the interface device 110, for example, during the second operational mode. Furthermore, the storage interface logic 112 may be configured to monitor for a control signal and, upon receipt of the control signal, switch between operation modes. Figure 1C depicts the interface device 110 (and thus the system 10) operating according to a third operation mode. In the third operation mode, the storage interface logic 112 is configured to couple the processor 400 to the storage bus 120 to enable data transfer between the mass storage device 300 and the processor 400. This functionality is depicted in the form of a dotted arrow that spans from the mass storage device 300, through the storage bus 120, through the interface device 110, into the processor 400 via the second driver 434, and through the operating system 420 and the application program 410. In other words, data is exchanged between the mass storage device 300 and the processor 400. The data may be exchanged in either direction (i.e. read from the mass storage device 300, or written to the mass storage device 300). The data is exchanged via the programmable logic device 100 by being transferred via the storage bus 120 and via the interface device 110. The second driver 434 allows data to be exchanged between the programmable logic device 100 and the processor 400. Advantageously, the storage interface logic 112 of the interface device 110 couples the processor 400 to the storage bus 120 such that data can be exchanged between the mass storage device 300 and the processor 400. This enables standard ‘system access’ by the processor 400, while still facilitating the first and second operation modes as required. In other words, a user may still access, manage, read, and / or write files in the mass storage device 300, via the processor 400 (such as via an application in the application program 410 or via the operating system 420), while still enabling a reduction of processing power when streaming data from the radio transceiver 200. In the example of Figures 1A-1C, the mass storage device 300 may be a solid state drive (SSD). In particular, the mass storage device 300 may be a non-volatile memory express SSD (NVMe SSD). In such an example, the storage bus 120 may be a peripheral component interface express (PCIe) bus. The bus interface logic 122 may be PCIe logic. The interface device 110 may be an NVMe logic block. The storage interface logic 112 may be NVMe logic. The programmable logic device 100 may be a field-programmable gate array (FPGA). Figures 2A and 2B depict examples of the receive chain 220 and the transmit chain 230, respectively. Figure 2A depicts an example of the receive chain 220 connected to the receive antenna 210a. The receive chain 220 comprises an analogue front-end 222 and a digital back-end 224. The analogue front-end 222 is connected to the digital back-end 224 via a data converter, which in this case is an analogue-to-digital converter (ADC) 226. The ADC 226 is, in the depicted example, connected to the digital back-end 224 via a converter bus 228. In a particular example, the converter bus 228 may be a JESD204B bus. The analogue front-end 222 comprises a receive amplifier 222a, a down-converter 222b, and a receive filter 222c. The receive amplifier 222a may comprise a low-noise amplifier (LNA). The down-converter 222b may comprise an l / Q down-converter. The receive filter 222c may comprise a low-pass filter, such as an anti-aliasing filter. It will be appreciated that the analogue front-end 222 may include any or all of these components, or other signal processing components not discussed herein, either alone or in combination, depending on the specific processing requirements of the radio transceiver 200. The digital back-end 224 may comprise a digital signal processor (DSP) 225. The radio transceiver 200 may comprise the analogue front-end 222, the ADC 226, and / or the converter bus 228. The DSP 225 may be implemented in one or more programmable logic blocks of the programmable logic device 100. In this regard, it may be considered that the converter bus 228 connects the data converter (e.g. ADC 226) of the receive chain 220 to the DSP 225. Moreover, it may be considered that the converter bus 228 provides an interface between the radio transceiver 200 and the programmable logic device 100 (since the analogue front-end 222 is implemented in the radio transceiver 200 and some or all of the digital back-end 224 is implemented in the programmable logic device 100). Figure 2B depicts an example of the transmit chain 230 connected to the transmit antenna 210b. The transmit chain 230 comprises an analogue front-end 232 and a digital back-end 234. The analogue front-end 232 is connected to the digital back-end 234 via a data converter, which in this case is a digital-to-analogue converter (DAC) 236. The DAC 236 is, in the depicted example, connected to the digital back-end 234 via a converter bus 238. It will be appreciated that the converter bus 228 and the converter bus 238 may be different converter buses. For example, the converter bus 228 may be a receive converter bus 228 and the converter bus 238 may be a transmit converter bus 238. Similarly, the digital back-end 224 and the digital back-end 234 may be different digital back-ends. For example, the digital back-end 224 may be a receive digital back-end 224 and the digital back-end 234 may be a transmit digital back-end 234. The receive digital back-end 224 and the transmit digital back-end 234 may be implemented by separate programmable logic blocks of the programmable logic device 100 or may be implemented by separate programmable logic devices 100. Alternatively, the converter buses in each chain may be a single converter bus 228 that is capable of connecting both the ADC 226 and the DAC 236 to a single digital back-end 224. The single digital back-end 224 may comprise one or more programmable logic blocks the programmable logic device 100 that are capable of performing digital signal processing for both the receive chain 220 and the transmit chain 230. The analogue front-end 232 comprises a transmit amplifier 232a, an up-converter 232b, and a transmit filter 232c. The transmit amplifier 232a may comprise a power amplifier (PA). The up-converter 232b may comprise an l / Q up-converter. The transmit filter 232c may comprise a reconstruction filter (sometimes called an anti-imaging filter). It will be appreciated that the analogue front-end 232 may include any or all of these components, or other signal processing components not discussed herein, either alone or in combination, depending on the specific processing requirements of the radio transceiver 200. The digital back-end 234 may a digital signal processor (DSP) 235. The radio transceiver 200 may comprise the analogue front-end 232, the DAC 236, and / or the converter bus 238. The DSP 235 may be implemented in one or more programmable logic blocks of the programmable logic device 100. In this regard, it may be considered that the converter bus 238 connects the data converter (e.g. DAC 236) of the transmit chain 230 to the DSP 235. Moreover, it may be considered that the converter bus 238 provides an interface between the radio transceiver 200 and the programmable logic device 100 (since the analogue front-end 232 is implemented in the radio transceiver 200 and some or all of the digital back-end 234 is implemented in the programmable logic device 100). Figure 3 depicts an example method 600 for transferring data between a radio transceiver 200 and a mass storage device 300 via a storage bus 120. The method 600 comprises a first operation mode 610a and a second operation mode 610b, and optionally further comprises a third operation mode 610c. In Figure 3, the operation modes are denoted by dotted lines and optional processes are denoted by dashed lines. The method 600 comprises, in the first operation mode 610a, coupling 612a a receive chain 220 of the radio transceiver 200 to the storage bus 120. The method 600 further comprises, in the first operation mode 610a, transferring 614a data from the receive chain 220 to the mass storage device 300. The method 600 further comprises, in the second operation mode 610b, coupling 612b a transmit chain 230 of the radio transceiver 200 to the storage bus 120. The method 600 further comprises, in the second operation mode 610b, transferring 614b data from the mass storage device 300 to the transmit chain 230. The method 600 may further comprise, in the third operation mode 610c, coupling 612c a processor 400 to the mass storage device 300. The method 600 may further comprise, in the third operation mode 610c, transferring data between the mass storage device 300 and the processor 400. Optionally, the method 600 may further comprise receiving 602 a control signal. The method 600 may further comprise, responsive to receiving the control signal, switching 604 between the operation modes. The arrows in Figure 3 depict the various switches between the operation modes. This includes: switching from the first operation mode 5 610a to the second operation mode 610b, and vice versa; switching from the first operation mode 610a to the third operation mode 610c, and vice versa; and switching from the second operation mode 610b to the third operation mode 610c, and vice versa.

Claims

1. An interface device for enabling data transfer between a radio transceiver and a mass storage device via a storage bus, the interface device comprising storage interface logic configured to operate according to two or more operation modes, wherein:i) in a first operation mode, the storage interface logic is configured to couple a receive chain of the radio transceiver to the storage bus to enable data transfer from the receive chain to the mass storage device; andii) in a second operation mode, the storage interface logic is configured to couple a transmit chain of the radio transceiver to the storage bus to enable data transfer from the mass storage device to the transmit chain.

2. The interface device of claim 1, wherein the storage interface logic is further configured to operate in a third operation mode in which the storage interface logic is configured to couple a processor to the storage bus to enable data transfer between the mass storage device and the processor.

3. The interface device of claim 1 or claim 2, wherein the storage interface logic is further configured to switch between the operation modes upon receipt of a control signal.

4. The interface device of any of the preceding claims, wherein the interface device is a programmable logic block for embedding in a programmable logic device.

5. A programmable logic device comprising the interface device of any of the preceding claims.

6. The programmable logic device of claim 5, further comprising a storage bus for connecting to a mass storage device to enable data transfer between the mass storage device and the programmable logic device.

7. The programmable logic device of claim 6, further comprising bus interface logic configured to control the data transfer between the mass storage device and the programmable logic device via the storage bus.

8. The programmable logic device of any of claims 5 to 7, further comprising a converter bus for connecting to a data converter of a radio transceiver to provide an interface between the radio transceiver and the programmable logic device.

9. A system comprising:the programmable logic device of any of claims 5 to 8; anda radio transceiver comprising one or more electronic components defining a receive chain and a transmit chain of the radio transceiver.

10. The system of claim 9, wherein the receive chain and / or the transmit chain comprises an analogue front-end and a digital back-end, and wherein each analogue front-end is connected to each digital back-end via a data converter.

11. The system of claim 10, wherein the digital back-end is implemented by one or more additional programmable logic blocks of the programmable logic device.

12. The system of any of claims 9 to 11, further comprising a processor coupled to the programmable logic device and configured to execute one or more drivers to communicate with the interface device.

13. The system of claim 12, wherein the processor is configured to transmit, using a first driver executed by the processor, a control signal to the interface device to cause the storage interface logic to switch between operation modes.

14. The system of claim 13 when dependent on claim 2, wherein the processor is configured to, in the third operation mode of the storage interface logic, transmit and receive data from the mass storage device using a second driver executed by the processor.

15. The system of claim 14, wherein the first driver is a custom driver configured to transfer data and / or control signals between the processor and the interface device.

16. The system of claim 14 or claim 15, wherein the second driver is a standards-compliant driver configured to transfer data and / or control signals between the processor and the mass storage device.

17. The system of any of claims 13 to 16, wherein the first driver is configured to generate output data indicative of the data transfer from the receive chain to the mass storage device and / or of the data transfer from the mass storage device to the transmit chain.

18. The system of claim 17, wherein the output data indicative of the data transfer comprises a value indicating the amount of data transferred.

19. A method of transferring data between a radio transceiver and a mass storage device via a storage bus, the method comprising:i) in a first operation mode,coupling a receive chain of the radio transceiver to the storage bus, and transferring data from the receive chain to the mass storage device; and ii) in a second operation mode,coupling a transmit chain of the radio transceiver to the storage bus, and transferring data from the mass storage device to the transmit chain.

20. The method of claim 19, further comprising:iii) in a third operation mode, coupling a processor to the mass storage device, and transferring data between the mass storage device and the processor.

21. The method of claim 19 or claim 20, further comprising:receiving a control signal; andresponsive to receiving the control signal, switching between the operation modes.

22. The method of any of claims 19 to 21, further comprising:generating output data indicative of the data transfer from the receive chain to the mass storage device and / or of the data transfer from the mass storage device to the transmit chain.

23. A computer-readable storage medium comprising a hardware description of the interface device of any of claims 1 to 4 and / or a hardware description of the programmable logic device of any of claims 5 to 8.

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