Apparatus and methods for biasing of power amplifiers

Abstract

Apparatuses and methods for biasing a power amplifier are provided herein. In certain embodiments, a power amplifier includes a bipolar transistor having a base biased by a bias network having a reactance that controls the impedance at the base of the transistor to achieve a substantially flat phase response over a large dynamic power level. For example, the bias network can have a frequency response, such as a high pass or band pass response, that reduces the effect of power level on phase distortion (AM / PM).

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to electronic systems, and more particularly to power amplifiers for radio frequency (RF) electronics. BACKGROUND

[0002] Power amplifiers are used in radio frequency (RF) communication systems to amplify RF signals for transmission through an antenna. It can be important to manage the power of RF signal transmission to extend battery life and / or to provide a suitable transmission power level.

[0003] Examples of RF communication systems having one or more power amplifiers include, but are not limited to, mobile phones, tablets, base stations, network access points, laptops, and wearable electronic devices. Power amplifiers provide amplification for RF signals, which can have frequencies in the range of about 30 kHz to 300 GHz, e.g., in the range of about 450 MHz to about 90 GHz for certain communication standards. SUMMARY

[0004] In certain embodiments, the present application relates to a mobile device. The mobile device includes a transceiver configured to produce a radio frequency input signal, a front-end system including a power amplifier configured to receive the radio frequency input signal and output a radio frequency output signal, and an antenna configured to wirelessly transmit the radio frequency output signal. The power amplifier includes a power amplifier transistor configured to amplify the radio frequency input signal, and a bias network configured to bias an input of the power amplifier transistor with a direct current bias voltage. The bias network has a reactance operable to flatten a phase response of the power amplifier.

[0005] In some embodiments, the reactance is operable to track an intrinsic input capacitance of the power amplifier transistor.

[0006] In various embodiments, the bias network includes a bias impedance electrically connected between the direct current bias voltage and the input of the power amplifier transistor, and a shunt impedance electrically connected between the input of the power amplifier transistor and a reference voltage. According to some embodiments, the bias impedance includes a first resistor, and the shunt impedance includes a second resistor and a capacitor in series. According to several embodiments, the shunt impedance further includes an inductor in series with the second resistor and the capacitor. According to some embodiments, the reference voltage is ground.

[0007] In some embodiments, the power amplifier transistor is a bipolar transistor having a base corresponding to the input.

[0008] In various embodiments, the power amplifier transistor is a field effect transistor having a gate corresponding to the input.

[0009] In some embodiments, the bias network includes a resistor and a capacitor connected in parallel between the input of the power amplifier transistor and the direct current bias voltage.

[0010] In several embodiments, the power amplifier transistor is implemented as a plurality of transistor elements operating in parallel with each other. According to some embodiments, the bias network includes a plurality of resistors and a plurality of capacitors, each of the plurality of resistors connected in parallel between the direct current bias voltage and an input of a corresponding one of the plurality of transistor elements.

[0011] In various embodiments, the bias network includes a series combination of a capacitor and an inductor connected electrically between the direct current bias voltage and the input of the power amplifier transistor, and a resistor connected in parallel with the series combination of the capacitor and the inductor.

[0012] In some embodiments, the power amplifier includes an input stage and an output stage, the power amplifier transistor incorporated into the output stage of the power amplifier.

[0013] In certain embodiments, the present application relates to a power amplifier system. The power amplifier system includes a bias control circuit configured to generate a direct current bias voltage, and a power amplifier configured to receive a radio frequency input signal and output a radio frequency output signal. The power amplifier includes a power amplifier transistor configured to amplify the radio frequency input signal, and a bias network configured to bias an input of the power amplifier transistor with the direct current bias voltage. The bias network has a reactance operable to flatten a phase response of the power amplifier.

[0014] In various embodiments, the reactance is operable to track an intrinsic input capacitance of the power amplifier transistor.

[0015] In several embodiments, the bias network includes a bias impedance connected electrically between the direct current bias voltage and the input of the power amplifier transistor, and a shunt impedance connected electrically between the input of the power amplifier transistor and a reference voltage. According to some embodiments, the bias impedance includes a first resistor, and the shunt impedance includes a second resistor and a capacitor in series. According to various embodiments, the shunt impedance further includes an inductor in series with the second resistor and the capacitor. According to some embodiments, the reference voltage is ground.

[0016] In some embodiments, the power amplifier transistor is a bipolar transistor having a base corresponding to the input.

[0017] In various embodiments, the power amplifier transistor is a field effect transistor having a gate corresponding to the input.

[0018] In some embodiments, the bias network includes a resistor and a capacitor connected in parallel electrically between the input of the power amplifier transistor and the direct current bias voltage.

[0019] In several embodiments, the power amplifier transistor is implemented as a plurality of transistor elements operating in parallel with each other. According to various embodiments, the bias network includes a plurality of resistors and a plurality of capacitors, each of the plurality of resistors connected in parallel between the direct current bias voltage and an input of a corresponding one of the plurality of transistor elements with a corresponding one of the plurality of capacitors.

[0020] In some embodiments, the bias network includes a series combination of a capacitor and an inductor electrically connected between the direct current bias voltage and the input of the power amplifier transistor, and a resistor in parallel with the series combination of the capacitor and the inductor.

[0021] In various embodiments, the power amplifier includes an input stage and an output stage, the power amplifier transistor incorporated into the output stage of the power amplifier.

[0022] In certain embodiments, the present application relates to a method of biasing a power amplifier. The method includes generating a direct current bias voltage using a bias control circuit, receiving a radio frequency input signal as an input to the power amplifier, amplifying the radio frequency input signal using a power amplifier transistor of the power amplifier, and biasing an input of the power amplifier transistor with the direct current bias voltage using a bias network of the power amplifier, including flattening a phase response of the power amplifier with a reactance of the bias network.

[0023] In some embodiments, the method further includes tracking an intrinsic input capacitance of the power amplifier transistor with the reactance of the bias network.

[0024] In several embodiments, the bias network includes a bias impedance electrically connected between the direct current bias voltage and the input of the power amplifier transistor, and a shunt impedance electrically connected between the input of the power amplifier transistor and a reference voltage. According to some embodiments, the bias impedance includes a first resistor, and the shunt impedance includes a second resistor and a capacitor in series. According to various embodiments, the shunt impedance further includes an inductor in series with the second resistor and the capacitor. According to several embodiments, the reference voltage is ground.

[0025] In various embodiments, the power amplifier transistor is a bipolar transistor having a base corresponding to the input.

[0026] In multiple embodiments, the power amplifier transistor is a field effect transistor having a gate corresponding to the input.

[0027] In several embodiments, the bias network includes a resistor and a capacitor connected in parallel electrically between the input of the power amplifier transistor and the direct current bias voltage.

[0028] In some embodiments, the power amplifier transistor is implemented as a plurality of transistor elements operating in parallel with each other. According to several embodiments, the bias network includes a plurality of resistors and a plurality of capacitors, each of the plurality of resistors connected in parallel with a corresponding one of the plurality of capacitors between the direct current bias voltage and an input of a corresponding one of the plurality of transistor elements. According to various embodiments, the bias network includes a series combination of a capacitor and an inductor electrically connected between the direct current bias voltage and the input of the power amplifier transistor, and a resistor in parallel with the series combination of the capacitor and the inductor. According to several embodiments, the power amplifier includes an input stage and an output stage, and the power amplifier transistor is incorporated into the output stage of the power amplifier. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a schematic diagram of one example of a communication network.

[0030] Figure 2 is a schematic diagram of one embodiment of a power amplifier system.

[0031] Figure 3 is a schematic diagram of another embodiment of a power amplifier system.

[0032] Figure 4 is a schematic diagram of a power amplifier according to one embodiment.

[0033] Figure 5 is a schematic diagram of a power amplifier according to another embodiment.

[0034] Figure 6 is a schematic diagram of a power amplifier according to another embodiment.

[0035] Figure 7 is a schematic diagram of a power amplifier according to another embodiment.

[0036] Figure 8 is a schematic diagram of a power amplifier according to another embodiment.

[0037] Figure 9 is a schematic diagram of a power amplifier according to another embodiment.

[0038] Figure 10 is a schematic diagram of a power amplifier according to another embodiment.

[0039] Figure 11A is one example of an amplitude distortion versus output power plot.

[0040] Figure 11B is an example of a plot of phase distortion versus output power.

[0041] Figure 12A is another example of a plot of amplitude distortion versus output power.

[0042] Figure 12B is another example of a plot of phase distortion versus output power.

[0043] Figure 13A is another example of a plot of amplitude distortion versus output power.

[0044] Figure 13B is another example of a plot of phase distortion versus output power.

[0045] Figure 14A is a schematic diagram of one embodiment of a packaged module.

[0046] Figure 14B is a schematic diagram of a cross-section of the packaged module taken along line 14B-14B of Figure 14A

[0047] Figure 15 is a schematic diagram of one embodiment of a mobile device. DETAILED DESCRIPTION

[0048] The following detailed description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein can be embodied in a multitude of different ways. For example, the innovations can be implemented using various programming or engineering techniques, with results specified and captured more or less precisely as desired. In this specification, reference can be made to aspects of the innovations described in terms such as specifying circumstances and events or specifying situations, environments, operations, conditions, or results. These terms are recognized by those of ordinary skill to describe certain embodiments and are not to be taken as a reduction over the ordinary acuity of one of ordinary skill. The following detailed description is, therefore, not to be taken in a literal or limiting sense, and the scope of the inventive embodiments is defined only by the claims.

[0049] The International Telecommunication Union (ITU) is a specialized agency of the United Nations (UN) that is responsible for global matters related to information and communication technologies, including shared global use of the radio spectrum.

[0050] The Third Generation Partnership Project (3GPP) is a collaboration between world-wide telecommunication standard groups such as the Association of Radio Industries and Businesses (ARIB), the Telecommunication Technology Committee (TTC), the China Communications Standards Association (CCSA), the Alliance for Telecommunications Industry Solutions (ATIS), the Telecommunication Technology Association (TTA), the European Telecommunications Standards Institute (ETSI), and the Indian Telegraphen Standard Development Society (TSDSI).

[0051] ​Working within the scope of ITU, 3GPP develops and maintains technical specifications for various mobile communication technologies, including, for example, second generation (2G) technologies (e.g., Global System for Mobile Communications (GSM) and Enhanced Data Rates for GSM Evolution (EDGE)), third generation (3G) technologies (e.g., Universal Mobile Telecommunications System (UMTS) and High Speed Packet Access (HSPA)), and fourth generation (4G) technologies (e.g., Long Term Evolution (LTE) and LTE-Advanced).

[0052] Technical specifications controlled by 3GPP can be extended and revised through specification releases, which can span multiple years and specify a breadth of new features and evolutions.

[0053] In one example, 3GPP introduced Carrier Aggregation (CA) for LTE in Release 10. While initially introducing two downlink carriers, 3GPP extended carrier aggregation in Release 14 to include up to five downlink carriers and up to three uplink carriers. Other examples of new features and evolutions provided by 3GPP releases include, but are not limited to, Licensed-Assisted Access (LAA), Enhanced LAA (eLAA), Narrow Band Internet of Things (NB-IOT), Vehicle-to-Everything (V2X), and High-Power User Equipment (HPUE).

[0054] 3GPP introduced the first phase of Fifth Generation (5G) technology in Release 15 and plans to introduce the second phase of 5G technology in Release 16 (targeting 2019). Subsequent 3GPP releases will further evolve and extend 5G technology. 5G technology is also referred to herein as 5G New Radio (NR).

[0055] 5G NR supports or is planned to support various features such as communications over millimeter wave spectrum, beamforming capabilities, high spectral efficiency waveforms, low latency communications, multiple radio parameter configurations, and / or Non-Orthogonal Multiple Access (NOMA). While such RF capabilities provide flexibility to the network and improve user data rates, supporting such features can present a number of technical challenges.

[0056] The teachings herein are applicable to a variety of communication systems, including but not limited to communication systems using advanced cellular technologies such as LTE-A, LTE-A Pro, and / or 5G NR.

[0057] Figure 1 is a schematic diagram of one example of a communication network 10. The communication network 10 includes various examples of macrocell base stations 1, small cell base stations 3, and user equipment (UE), including a first mobile device 2a, a wirelessly connected car 2b, a portable computer 2c, a fixed wireless device 2d, a wirelessly connected train 2e, a second mobile device 2f, and a third mobile device 2g.

[0058] Although specific examples of base stations and user equipment are shown in Figure 1 the communication network can include various types and / or numbers of base stations and user equipment.

[0059] For example, in the illustrated example, the communication network 10 includes a macrocell base station 1 and a small cell base station 3. The small cell base station 3 can operate at a relatively lower power, shorter range, and / or fewer concurrent users relative to the macrocell base station. The small cell base station 3 can also be referred to as a femtocell, a pico cell, or a micro cell. Although the communication network 10 is shown as including two base stations, the communication network 10 can be implemented to include more or fewer base stations and / or other types of base stations.

[0060] Although various examples of user equipment are shown, the teachings herein are applicable to a wide variety of user equipment including, but not limited to, mobile phones, tablets, portable computers, IoT devices, wearable electronic devices, customer premises equipment (CPE), wirelessly connected vehicles, wireless repeaters, and / or a variety of other communication devices. Moreover, the user equipment includes not only currently available communication devices that operate in cellular networks, but also communication devices that are subsequently developed that will readily be implemented with the inventive systems, processes, methods, and apparatus as described and claimed herein.

[0061] Figure 1 The illustrated communication network 10 supports communications using a variety of cellular technologies including, for example, 4G LTE and 5G NR. In certain embodiments, the communication network 10 is also adapted to provide a wireless local area network (WLAN) such as WiFi. Although various examples of communication technologies have been provided, the communication network 10 can be adapted to support a variety of communication technologies.

[0062] Various communication links of the communication network 10 have been described in Figure 1 The communication links can be duplexed in a variety of ways including, for example, using frequency division duplexing (FDD) and / or time division duplexing (TDD). FDD is a radio frequency communication that uses different frequencies to transmit and receive signals. FDD can provide a number of advantages such as high data rates and low latency. In contrast, TDD is a radio frequency communication that uses about the same frequency to transmit and receive signals and where the transmitting and receiving communications are switched in time. TDD can provide a number of advantages such as efficient use of spectrum and variable allocation of throughput between the transmit and receive directions.

[0063] In certain embodiments, user equipment can communicate with base stations using one or more of 4G LTE, 5G NR, and WiFi technology. In certain embodiments, enhanced licensed assisted access (eLAA) is used to aggregate one or more licensed frequency carriers (e.g., licensed 4G LTE and / or 5G NR frequencies) with one or more unlicensed carriers (e.g., unlicensed WiFi frequencies).

[0064] As shown in Figure 1 communication links include not only communication links between UEs and base stations, but also communication from UE to UE and base station to base station communications. For example, the communication network 10 can be implemented to support self-front-haul and / or self-backhaul (e.g., as between mobile device 2g and mobile device 2f).

[0065] The communication links can operate at various frequencies. In certain embodiments, 5G NR technology is used to support communications over one or more frequency bands of less than 6 gigahertz (GHz) and / or one or more frequency bands of more than 6 GHz. For example, the communication links can operate at a frequency range 1 (FR1), a frequency range 2 (FR2), or a combination thereof. In one embodiment, one or more mobile devices support a HPUE power class specification.

[0066] In certain embodiments, base stations and / or user equipment communicate using beamforming. For example, beamforming can be used to focus signal strength to overcome path loss, such as that associated with communicating at high signal frequencies. In certain embodiments, user equipment, such as one or more mobile phones, communicate using beamforming at millimeter wave bands ranging between 30 GHz and 300 GHz and / or at higher centimeter wave frequencies ranging between 6 GHz and 30 GHz (or more specifically, 24 GHz to 30 GHz).

[0067] Different users of the communication network 10 can share available network resources, such as available frequency spectrum, in a variety of ways.

[0068] In one example, frequency division multiple access (FDMA) is used to divide a frequency band into multiple frequency carriers. Additionally, one or more carriers are assigned to particular users. Examples of FDMA include, but are not limited to, single-carrier FDMA (SC-FDMA) and orthogonal FDMA (OFDMA). OFDMA is a multi-carrier technology that sub-divides the available bandwidth into multiple narrowband sub-carriers that are mutually orthogonal, which can be separately assigned to different users.

[0069] Other examples of shared access include, but are not limited to, time division multiple access (TDMA), where users are allocated specific time slots to use a frequency resource; code division multiple access (CDMA), where a frequency resource is shared among different users by allocating a unique code to each user; spatial division multiple access (SDMA), where beamforming is used to provide shared access through spatial division; and non-orthogonal multiple access (NOMA), where a power domain is used for multiple access. For example, NOMA can be used to serve multiple users with the same frequency, time, and / or code, but with different power levels.

[0070] Enhanced mobile broadband (eMBB) refers to techniques for increasing the system capacity of LTE networks. For example, eMBB can refer to communications with a peak data rate of at least 10 Gbps per user and a minimum of 100 Mbps. Ultra-reliable low-latency communications (uRLLC) refers to techniques for communicating with very low latency, e.g., less than 2 milliseconds. uRLLC can be used for mission-critical communications, such as for autonomous driving and / or remote surgery applications. Massive machine type communications (mMTC) refers to low-cost and low-data rate communications associated with wireless connectivity of everyday objects, such as those associated with Internet of Things (IoT) applications.

[0071] Figure 1 The communication network 10 can be used to support a variety of advanced communication features, including but not limited to eMBB, uRLLC, and / or mMTC.

[0072] Figure 2 is a schematic diagram of one embodiment of a power amplifier system 20. The illustrated power amplifier system 20 includes an antenna access circuit 21, an antenna 22, a directional coupler 24, a power management circuit 30, a bias control circuit 31, a power amplifier 32, a transceiver 33, and a baseband processor 34.

[0073] Although Figure 2 One embodiment of a power amplifier system is illustrated, the teachings herein are applicable to power amplifier systems implemented in a variety of ways. For example, a power amplifier system can include more or fewer components, different arrangements of components, and / or components implemented in different ways.

[0074] In the illustrated embodiment, the transceiver 33 includes a power amplifier control circuit 36, an I / Q modulator 37, a mixer 38, and an analog-to-digital converter (ADC) 39. Although not illustrated for the sake of clarity, the transceiver 33 can include other components, such as a digital-to-analog converter (DAC), a low noise amplifier (LNA), and / or a power management integrated circuit (PMIC). Figure 2As shown in FIG. 1, the transceiver 33 can also process signals received from one or more antennas (e.g., antenna 22 and / or other antennas) through one or more receive paths. Moreover, the transceiver 33 can be implemented in other ways, including but not limited to using different implementations of transmit paths, observation paths, and / or power amplifier control circuits.

[0075] The baseband signal processor 34 can be used to generate in-phase (I) and quadrature-phase (Q) signals, which can be used to represent a sine wave or signal of a desired amplitude, frequency, and phase. For example, the I signal can be used to represent the in-phase component of a sine wave, and the Q signal can be used to represent the quadrature-phase component of a sine wave, which can be an equivalent representation of the sine wave. In certain embodiments, the I and Q signals can be provided to the I / Q modulator 37 in digital format. The baseband processor 34 can be any suitable processor configured to process baseband signals. For example, the baseband processor 34 can include a digital signal processor, a microprocessor, a programmable core, or any combination thereof. Moreover, in some embodiments, two or more baseband processors 34 can be included in the power amplifier system 20.

[0076] The I / Q modulator 37 can be configured to receive the I and Q signals from the baseband processor 34 and process the I and Q signals to generate an RF signal. For example, the I / Q modulator 37 can include a digital-to-analog converter (DAC) configured to convert the I and Q signals to analog format, a mixer for upconverting the I and Q signals to radio frequencies, and a signal combiner for combining the upconverted I and Q signals into an RF signal suitable for amplification by the power amplifier 32. In certain embodiments, the I / Q modulator 37 can include one or more filters configured to filter frequency components of signals processed therein.

[0077] The power amplifier 32 can receive the radio frequency signal from the I / Q modulator 37 and, when enabled, can provide the amplified radio frequency signal to the antenna 22 through the antenna access circuit 21. The antenna access circuit 21 can be implemented in a variety of ways and can include, for example, one or more switches, filters, duplexers, triplexers, quadplexers, circulators, and / or other components suitable for providing access to the antenna 22. The directional coupler 24 can be disposed between the output of the power amplifier 32 and the input of the antenna access circuit 21, thereby allowing the output power measurement of the power amplifier 32 to not include the insertion loss of the antenna access circuit 21. However, other configurations of power measurement are possible.

[0078] In the illustrated configuration, the sensed output signal from directional coupler 24 is provided to a mixer 38, which multiplies the sensed output signal with a reference signal at a controlled frequency. Mixer 38 operates to generate a down-shifted signal by down-shifting frequency components of the sensed output signal. The down-shifted signal can be provided to an ADC 39, which can convert the down-shifted signal to a digital format suitable for processing by baseband processor 34. By including a feedback path between the output of power amplifier 32 and baseband processor 34, baseband processor 34 can be configured to dynamically adjust the I and Q signals to optimize operation of power amplifier system 20. For example, configuring power amplifier system 20 in this manner can facilitate controlling the PAE and / or linearity of power amplifier 32.

[0079] In the illustrated embodiment, power management circuit 30 receives a power control signal from transceiver 33 and controls the supply voltage of power amplifier 32. In certain implementations, transceiver 33 is electrically connected to power management circuit 30 through a serial interface, and power management circuit 30 receives the power control signal through the serial interface.

[0080] As Figure 2 illustrated, power management circuit 30 generates a first supply voltage V CC1 for powering the input stage of power amplifier 32 and a second supply voltage V CC2 for powering the output stage of power amplifier 32. Power management circuit 30 can control the voltage level of first supply voltage V CC1 and / or second supply voltage V CC2 to enhance the PAE of the power amplifier system. Although an embodiment with two controllable supply voltages is illustrated, power management circuit can control the voltage level of more or fewer supply voltages. In certain implementations, the power amplifier operates with one or more controllable supply voltages and / or one or more substantially fixed supply voltages.

[0081] In the illustrated embodiment, the power control signal instructs power management circuit 30 to operate in a particular supply control mode, such as an average power tracking mode, an envelope tracking mode, a fixed supply mode, or other suitable power management mode. Thus, in this embodiment, power amplifier control circuit 36 of transceiver 33 controls the selected supply control mode.

[0082] As Figure 2As shown, the bias control circuit 31 receives a bias control signal from the transceiver 33 and generates a bias control signal for the power amplifier 32. Further, the bias control circuit 31 generates a bias control signal (e.g., a bias voltage) based on the bias control signal. In certain embodiments, the transceiver 33 is electrically connected to the bias control circuit 31 through a serial interface, and the bias control signal corresponds to a control word received through the serial interface.

[0083] Figure 3 is a schematic diagram of another embodiment of a power amplifier system 100. The power amplifier system 100 includes a power amplifier 70, a power management circuit 71, and a bias control circuit 72.

[0084] Although Figure 3 One embodiment of a power amplifier system is shown, but the teachings herein are applicable to power amplifier systems implemented in a variety of ways.

[0085] The power amplifier 70 includes a first supply inductor 73 and a second supply inductor 74, an input stage bias network 75, an output stage bias network 76, an input stage bipolar transistor 81, an output stage bipolar transistor 82, an input matching circuit 83, an interstage matching circuit 84, and an output matching circuit 85.

[0086] Although the illustrated power amplifier 70 includes two stages, other configurations are possible, including for example, a power amplifier that includes one stage or a power amplifier that includes three or more stages. Although the illustrated power amplifier 70 is implemented using bipolar transistors, the teachings herein are also applicable to field effect transistor configurations.

[0087] As Figure 3 shown, the power amplifier 70 receives an RF input signal RF in , which is amplified using the input stage bipolar transistor 81. The collector of the input stage bipolar transistor 81 produces an amplified RF signal, which is provided to the base of the output stage bipolar transistor 82. The output stage bipolar transistor 82 further amplifies the amplified RF signal to produce an RF output signal RF out . As Figure 3 shown, the emitters of the input stage bipolar transistor 81 and the output stage bipolar transistor 82 are electrically connected to a first voltage VI, which can for example be a ground voltage.

[0088] As will be appreciated by those of ordinary skill in the art, the input matching circuit 83, the interstage matching circuit 84, and the output matching circuit 85 provide impedance matching, thereby enhancing radio frequency performance. In certain embodiments, the input matching circuit 83, the interstage matching circuit 84, and the output matching circuit 85 perform one or more additional functions, such as direct current blocking (DC blocking).

[0089] Figure 3 The power amplifier 70 uses the first supply voltage V CC1 Second supply voltage V CC2 Power supply. The first power supply inductor 73 is electrically connected to the first power supply voltage V. CC1 The second power supply inductor 74 is electrically connected to the second power supply voltage V between the collector of the input stage bipolar transistor 81 and the collector. CC2 Between the collector of the output stage bipolar transistor 82 and the first power supply inductor 73 and the second power supply inductor 74, the power amplifier 70 can be supplied with additional power while providing sufficient impedance to isolate the radio frequency signals generated by the power amplifier 70, preventing them from reaching the first supply voltage V. CC1 Second supply voltage V CC2 .

[0090] In some implementations, the power management circuit 71 can operate in a selected power supply control mode, such as Average Power Tracking (APT) mode, Envelope Tracking (ET) mode, Fixed Power Supply mode, or other suitable power management modes. Additionally, the power management circuit 71 receives a power control signal that instructs it to operate in the selected power supply control mode. In one embodiment, the power control signal is received via a serial interface, such as a Mobile Industrial Processor Interface (MIPI) Radio Frequency Front-End (RFFE) bus.

[0091] like Figure 3 As shown, the power management circuit 71 generates a first supply voltage V for powering the input stage bipolar transistor 81 of the power amplifier 70. CC1 and the second supply voltage V used to power the output stage bipolar transistor 82 of the power amplifier 70 CC2 .

[0092] The power management circuit 71 controls the first supply voltage V based on the selected power control mode. CC1 and / or second supply voltage V CC2 The voltage level. In one example, when the selected power supply control mode is envelope tracking mode, the power management circuit 71 controls the first supply voltage V. CC1 and / or second supply voltage V CC2 The voltage level is used to track the signal RF amplified by power amplifier 70. in The signal envelope. In another example, when the selected power supply control mode is average power point tracking mode, the power management circuit 71 controls the first supply voltage V based on the average output power of the power amplifier 70. CC1 and / or second supply voltage V CC2 The voltage level.

[0093] The input stage bias network 75 is used to provide an input stage bias voltage from the bias control circuit 72 to the base of the input stage bipolar transistor 81. Further, the output stage bias network 76 is used to provide an output stage bias voltage from the bias control circuit 72 to the base of the output stage bipolar transistor 82. In the illustrated embodiment, the bias control circuit 72 controls the voltage level of the input stage bias voltage and the voltage level of the output stage bias voltage. Further, the bias control circuit 72 receives a bias control signal that includes information indicative of a selected bias voltage level. In one embodiment, the bias control signal is received over a serial interface such as a MIPI RFFE bus.

[0094] The power amplifier 70 includes an input stage bias network 75 for biasing the input stage bipolar transistor 81 and an output stage bias network 76 for biasing the output stage bipolar transistor 82. The input stage bias network 75 and / or the output stage bias network 76 can be implemented in accordance with any of the embodiments herein.

[0095] Apparatuses and methods for biasing a power amplifier are provided herein. In certain embodiments, the power amplifier includes a bipolar transistor having a base that is biased by a bias network having a reactance that controls the impedance at the transistor base to achieve a substantially flat phase response over a large dynamic power level. For example, the bias network can have a frequency response such as a high pass or band pass response to reduce the impact of power level on phase distortion (AM / PM).

[0096] In a first example, the bias network is implemented to provide a low impedance path at radio frequency frequencies, thereby maintaining a flat phase response over a large dynamic power level. In a second example, the bias network is used to reduce the impact of the nonlinear portion of the bipolar transistor's active intrinsic capacitance (e.g., base junction capacitance) by tracking or shadowing it with a lower impedance at radio frequency frequencies. Thus, the impact of large transistor capacitance variations at high current bias is suppressed and a substantially flat phase response and a substantially flat amplitude response are achieved at the same time. In a third example, the bias network is used to decouple radio frequency performance from the direct current bias point and allows the use of a high ballast resistor for direct current bias. By using a high resistance ballast, the large signal ruggedness of the power amplifier is improved and / or the stability of the power amplifier is enhanced.

[0097] Accordingly, the bias networks herein can be used to control the phase response of a power amplifier, such as a wideband linear power amplifier that operates over a large dynamic power range. For example, using the bias networks herein enables support for wideband 5G modulations, such as a 100 MHz CP-OFDM waveform that requires a substantially flat phase response over a large peak-to-average power (PAPR) ratio. Moreover, the enhanced phase response is achieved without compromising ruggedness and / or stability.

[0098] In contrast, certain conventional power amplifiers maintain a flat amplitude response to achieve good linearity. However, the flat amplitude response achieved by transistor biasing with high quiescent current comes at the expense of a non-monotonic increasing phase response. This tradeoff impacts the performance of wideband phase-sensitive modulations, such as those used in certain 4G LTE carrier aggregation scenarios. Moreover, 5G modulations that support 100 MHz signal bandwidths have a more sensitive phase response.

[0099] The teachings herein also provide wideband characteristics in a power amplifier with a relatively flat phase response substantially independent of the amplitude response. Accordingly, such techniques facilitate support for 5G waveforms with good linearity and efficiency at relatively low cost and complexity.

[0100] Figure 4 is a schematic diagram of a power amplifier 110 according to an embodiment. The power amplifier 110 includes a first supply inductor 73, a second supply inductor 74, a first bipolar transistor 81, a second bipolar transistor 82, an output matching circuit 85, an input capacitor 87, an inter-stage capacitor 88, and a bias network 101.

[0101] Although one embodiment of a power amplifier is described, the teachings herein are applicable to power amplifiers implemented in a variety of ways. For example, the power amplifier can include more or fewer stages, different implementations of impedance matching, and / or different implementations of DC isolation. Moreover, although the power amplifier 110 is implemented using bipolar transistors, the teachings herein are also applicable to power amplifiers implemented using FETs. For example, any of the bias networks disclosed herein can be used to provide a bias voltage to the gate of an FET. Accordingly, other implementations are possible. Figure 4 The power amplifier 110 of uses bipolar transistors to implement, but the teachings herein are also applicable to power amplifiers implemented using FETs. For example, any of the bias networks disclosed herein can be used to provide a bias voltage to the gate of an FET. Accordingly, other implementations are possible.

[0102] In the illustrated embodiment, the bias network 101 includes a bias impedance 103 and a shunt impedance 104. At least one of the bias impedance 103 or the shunt impedance 104 includes a reactance to assist in flattening the phase response of the power amplifier 110. Accordingly, the bias networks here are not simply resistive bias networks (e.g., a standalone ballast resistor), but rather have a reactance that is operable to flatten the phase response of the power amplifier, thereby improving performance.

[0103] Bias impedance 103 is connected between the base of output stage bipolar transistor 82 and a DC bias voltage from a bias control circuit, such as bias control circuit 72. Figure 3 In addition, shunt impedance 104 is connected between the base of output stage bipolar transistor 82 and a DC voltage, such as ground. In certain embodiments, the DC voltage corresponds to the DC bias voltage, such that bias impedance 103 and shunt impedance 104 are electrically connected in parallel to each other.

[0104] For clarity of the drawings, biasing of input stage bipolar transistor 81 is not depicted in Figure 4 However, input stage bipolar transistor 81 can be biased in a variety of ways, including but not limited to using a ballast resistor connected between the base of input stage bipolar transistor 81 and an input bias voltage (e.g., provided by bias control circuit 72). In certain embodiments, the input stage bipolar transistor is biased with a bias network that includes a bias impedance and a shunt impedance implemented in accordance with the teachings herein. For example, a replica or copy of bias network 101 (with suitable impedance values selected for bias impedance 103 and shunt impedance 104) can be included for biasing input stage bipolar transistor 81. Figure 3

[0105] Implementing bias network 101 with bias impedance 103 and shunt impedance 104 provides a number of advantages. For example, bias impedance 103 and shunt impedance 104 control the impedance at the base of output stage transistor 82 to achieve a substantially flat phase response over large dynamic power levels. For example, the impedance values can be selected to reduce AM / PM.

[0106] In certain embodiments, shunt impedance 104 is used to provide a low impedance path at RF frequencies, thereby maintaining a flat phase response over large dynamic power levels. Additionally or alternatively, shunt impedance 104 can reduce the effect of the non-linear portion of the base capacitance of output stage bipolar transistor 82 by shunting the capacitance at RF frequencies with a lower impedance. Thus, the effects of large transistor capacitance variations at high current bias are suppressed, while at the same time achieving a substantially flat phase response and a substantially flat amplitude response.

[0107] Figure 5 is a schematic diagram of a power amplifier 120 according to another embodiment. Power amplifier 120 includes first supply inductor 73, second supply inductor 74, first bipolar transistor 81, second bipolar transistor 82, output matching circuit 85, input capacitor 87, interstage capacitor 88, and bias network 111.

[0108] Although one embodiment of a power amplifier is described, the teachings herein are applicable to power amplifiers implemented in a variety of ways. ​

[0109] In the illustrated embodiment, the bias network includes ballast resistor 113 (R Ballast ) and ballast capacitor 114 (C Ballast ) electrically connected in parallel with each other between the DC bias voltage and the base of output stage bipolar transistor 82.

[0110] Ballast resistor 113 serves to enhance the ruggedness of power amplifier 120. However, without compensation, ballast resistor 113 can cause a degradation in phase distortion performance. In the illustrated embodiment, ballast capacitor 114 has been included in parallel with ballast resistor 113 to provide a low impedance path at radio frequency frequencies to maintain a flat phase response over large dynamic power levels.

[0111] Accordingly, bias network 111 can be used to decouple radio frequency performance from the DC bias point, thereby allowing ballast resistor 113 to have a high resistance without causing a corresponding degradation in AM / PM. Conversely, flat phase performance characteristics can be achieved over a large dynamic power range while also achieving large signal ruggedness and stable operation.

[0112] Figure 6 is a schematic diagram of a power amplifier 130 according to another embodiment. Power amplifier 130 includes first supply inductor 73, second supply inductor 74, first bipolar transistor 81, second bipolar transistor 82, output matching circuit 85, input capacitor 87, interstage capacitor 88, and bias network 121.

[0113] Although one embodiment of a power amplifier is depicted, the teachings herein are applicable to power amplifiers implemented in a variety of ways.

[0114] Figure 6 Power amplifier 130 of Figure 5 is similar to power amplifier 120 of , except that power amplifier 130 illustrates an implementation in which the output stage bipolar transistor and the bias network have been segmented (into an integer number N of segments, in this example, where N is 2 or more).

[0115] Figure 6 For example, as shown, the output stage bipolar transistor is implemented as transistor elements 82a, 82b,... 82n electrically connected in parallel with each other. In addition, bias network 121 includes ballast resistors 113a, 113b,... 113n connected in parallel with corresponding ballast capacitors 114a, 114b,... 114n between the DC bias voltage and transistor elements 82a, 82b,... 82n, respectively. In this example, ballast resistors 113a, 113b,... 113n each have a resistance R UNIT , while ballast capacitors 114a, 114b,... 114n each have a capacitance CUNIT .

[0116] By segmenting the power amplifier in this way, superior bypassing of the ballast resistor at high frequencies is provided, thereby providing stronger phase control. Any bias network / power amplifier disclosed herein can be implemented with segmentation.

[0117] Figure 7 is a schematic diagram of a power amplifier 140 according to another embodiment. The power amplifier 140 includes a first supply inductor 73, a second supply inductor 74, a first bipolar transistor 81, a second bipolar transistor 82, an output matching circuit 85, an input capacitor 87, an interstage capacitor 88, and a bias network 131.

[0118] Although one embodiment of a power amplifier is described, the teachings herein are applicable to power amplifiers implemented in a variety of ways.

[0119] Figure 7 The power amplifier 140 of Figure 4 is similar to the power amplifier 110 of Figure 7 except that the bias network 131 of Figure 4 includes specific implementations of the bias impedance 103 and the shunt impedance 104.

[0120] For example, as shown in Figure 7 the bias network 181 includes a ballast resistor 113 electrically connected between the base of the output stage bipolar transistor 82 and a DC bias voltage, and a shunt impedance 134 electrically connected between the base of the output stage bipolar transistor 82 and a reference voltage, such as ground. In the illustrated embodiment, the shunt impedance 134 includes a shunt resistor 135 and a shunt capacitor 136 electrically connected in series.

[0121] The shunt capacitor 136 helps to provide a low impedance at RF frequencies, thereby maintaining a flat phase response over large dynamic power levels. In addition, the shunt capacitor 136 reduces the impact of the non-linear portion of the base capacitance of the output stage bipolar transistor 82 by shunting the capacitance at RF frequencies with a lower impedance. In addition, the shunt resistor 135 helps to control how much AC current passes through the shunt impedance 134.

[0122] Figure 8 is a schematic diagram of a power amplifier 150 according to another embodiment. The power amplifier 150 includes a first supply inductor 73, a second supply inductor 74, a first bipolar transistor 81, a second bipolar transistor 82, an output matching circuit 85, an input capacitor 87, an interstage capacitor 88, and a bias network 141.

[0123] Although one embodiment of a power amplifier is described, the teachings herein apply to power amplifiers implemented in a variety of ways.

[0124] Figure 8 The power amplifier 150 is similar to Figure 5 The power amplifier 120, except Figure 8 The bias network 141 also includes a ballast inductor (L) connected in series with the ballast capacitor 114. Ballast 115.

[0125] Implementing the bias network 141 in this way helps to provide low impedance at the resonant frequency of the ballast capacitor 114 and the ballast inductor 115, the component values ​​of which can be selected to attenuate or suppress noise at a specific frequency.

[0126] Furthermore, the ballast inductor 115 provides an additional degree of control over the frequency response of the bias network 141, thereby helping to achieve the desired frequency characteristics for a particular application and / or implementation. For example, a bandpass response can be provided at the base node, where R Ballast It was selected as the DC bias point, and C was chosen. Ballast and L Ballast Value pairs (e.g., the product of inductance and capacitance) are selected as the phase response at RF frequencies.

[0127] Figure 9 This is a schematic diagram of a power amplifier 160 according to another embodiment. The power amplifier 160 includes a first power supply inductor 73, a second power supply inductor 74, a first bipolar transistor 81, a second bipolar transistor 82, an output matching circuit 85, an input capacitor 87, an interstage capacitor 88, and a bias network 151.

[0128] Although one embodiment of a power amplifier is described, the teachings herein apply to power amplifiers implemented in a variety of ways.

[0129] Figure 9 The power amplifier 160 is similar to Figure 7 The power amplifier 140, except Figure 9 The bias network 151 includes a shunt resistor 154, which further includes a shunt inductor (L) connected in series with a shunt resistor 135 and a shunt capacitor 136. Shunt 137.

[0130] Implementing the bias network 141 in this manner provides an additional degree of control over the frequency response of the bias network 151, thereby helping to achieve the desired frequency characteristics for a particular application and / or implementation. For example, the shunt impedance 154 can provide a low-impedance bandpass response at a particular frequency (e.g., the RF fundamental or harmonic frequency).

[0131] Figure 10 is a schematic diagram of a power amplifier 170 according to another embodiment. The power amplifier 170 includes a first supply inductor 73, a second supply inductor 74, an input stage FET 91, an output stage FET 92, an output matching circuit 85, an input capacitor 87, an inter-stage capacitor 88, and a bias network 101.

[0132] Although one embodiment of a power amplifier is depicted, the teachings herein apply to power amplifiers implemented in a variety of ways.

[0133] Figure 10 The power amplifier 170 of Figure 4 is similar to the power amplifier 110 of Figure 10 except that the power amplifier 170 is implemented with an input stage FET 91 and an output stage FET 92 instead of an input stage bipolar transistor 81 and an output stage bipolar transistor 82, respectively. Although the power amplifier 170 of Figure 10 shows one embodiment of a power amplifier implemented with FETs, any of the power amplifiers herein can be implemented with FETs. For example, any of the power amplifiers can be implemented with FETs instead of bipolar transistors. In addition, a power amplifier can include a combination of bipolar and field effect transistors. Figures 3-9

[0134] Figure 11A is one example of an amplitude distortion versus output power plot. Figure 11A The measured output power of a power amplifier biased only by ballast resistors (line 301) is compared to the measured output power of a power amplifier biased by one embodiment of the biasing shown in Figure 6 . As shown in Figure 11A , the gain distortion (AM / AM) of line 301 and line 302 are similar.

[0135] Figure 11B is one example of a phase distortion versus output power plot. Figure 11A The measured phase response of a power amplifier biased only by ballast resistors (line 303) is compared to the measured phase response of a power amplifier biased by one embodiment of the biasing shown in Figure 6 . As shown in Figure 11B , the phase distortion (AM / PM) of line 304 is superior to that of line 303.

[0136] Figure 12A is another example of an amplitude distortion versus output power plot. This plot depicts the simulated amplitude distortion of a power amplifier biased only by ballast resistors (line 311) and Figure 5 ​The simulated amplitude distortion of the power amplifier biased by the two example implementations shown with different capacitance values biasing (lines 312 and 313) is shown. The simulated case is shown for frequency band 71.

[0137] Figure 12B is another example of a plot of phase distortion versus output power. This plot depicts the simulated phase distortion of a power amplifier biased by only the ballast resistor (line 321) and Figure 5 The simulated phase distortion of the power amplifier biased by the two example implementations shown with different capacitance values biasing (lines 322 and 323) is shown. The simulated case is shown for frequency band 71.

[0138] Figure 13A is another example of a plot of amplitude distortion versus output power. This plot is similar to Figure 12A the simulation of, except that the simulation is described for the case of frequency band 12. This plot includes lines 331, 332, and 333, which correspond to lines 311, 312, and 313, respectively.

[0139] Figure 13B is another example of a plot of phase distortion versus output power. This plot is similar to Figure 12B the simulation of , except that the simulation is described for the case of frequency band 12. This plot includes lines 341, 342, and 343, which correspond to lines 321, 322, and 323, respectively.

[0140] Figure 14A is a schematic diagram of one embodiment of a packaged module 700. Figure 14B is a schematic diagram of a cross-section of the packaged module 700 taken along line 14B-14B. Figure 14A

[0141] The packaged module 700 includes a power amplifier die 701, a bias control die 702, a surface mount component 703, wirebonds 708, a package substrate 720, and an encapsulation structure 740. The package substrate 720 includes pads 706 formed by conductors disposed therein. Additionally, the dies 701, 702 include pads 704, and the wirebonds 708 have been used to connect the pads 704 of the dies 701, 702 to the pads 706 of the package substrate 720.

[0142] The power amplifier chip 701 and bias control chip 702 are implemented according to one or more features of this application. In some embodiments, the package module 700 includes power pins or pads for receiving supply voltages from external power management circuitry. Furthermore, the bias chip 702 includes bias control circuitry that biases the power amplifier chip 701 with one or more DC bias voltages. The bias chip 702 may include a serial interface, such as a MIPI RFFE bus, for controlling the one or more DC bias voltages.

[0143] In some implementations, the power amplifier chip 701 and the bias control chip 702 are fabricated using different processing techniques. In one example, the power amplifier chip 701 is fabricated using a heterojunction bipolar transistor (HBT) process (e.g., a compound semiconductor process such as gallium arsenide), while the bias control chip 702 is fabricated using a complementary metal-oxide-semiconductor (CMOS) process.

[0144] The packaging substrate 720 may be configured to receive multiple components, such as wafers 701, 702 and surface mount components 703, which may include, for example, surface mount capacitors and / or inductors.

[0145] like Figure 14B As shown, the package module 700 is illustrated as including a plurality of contact pads 732 disposed on a side of the package module 700 opposite to the side used for mounting wafers 701, 702. This configuration of the package module 700 facilitates its connection to a circuit board, such as the telephone board of a wireless device. Exemplary contact pads 732 can be configured to provide radio frequency signals, bias signals, low-voltage power supply, and / or high-voltage power supply to the wafers 701, 702, and / or surface mount components 703. Figure 14B As shown, the electrical connection between the contact pad 732 and the wafer 701 can be facilitated by a connection 733 through the package substrate 720. The connection 733 can represent an electrical path formed through the package substrate 720, such as a connection associated with a via and conductor of a multilayer stacked package substrate.

[0146] In some embodiments, the packaging module 700 may further include one or more packaging structures to, for example, provide protection and / or facilitate the handling of the packaging module 700. Such packaging structures may include an overmold or encapsulation structure 740 formed over the packaging substrate 720 and components and wafers disposed thereon.

[0147] It should be understood that although package module 700 is described in the context of wire-bonded electrical connections, one or more features of this application may also be implemented in other package configurations, including, for example, flip-chip configurations.

[0148] Figure 15 is a schematic diagram of one embodiment of a mobile device 800. The mobile device 800 includes a baseband system 801, a transceiver 802, a front-end system 803, an antenna 804, a power management system 805, a memory 806, a user interface 807, and a battery 808.

[0149] Although the mobile device 800 illustrates one example of an RF system that can include one or more features of the present application, the teachings herein are applicable to electronic systems implemented in a wide variety of manners.

[0150] The mobile device 800 can communicate using a variety of communication techniques, including but not limited to 2G, 3G, 4G (including LTE, LTE-A, and LTE-A Pro), 5G, WLAN (e.g., Wi-Fi), WPAN (e.g., Bluetooth and ZigBee), WMAN (e.g., WiMax), and / or GPS techniques.

[0151] The transceiver 802 generates RF signals for transmission and processes input RF signals received from the antenna 804. It will be understood that various functions associated with the transmission and reception of RF signals can be implemented by one or more components collectively shown as the transceiver 802 in Figure 15 In one example, separate components (e.g., separate circuits or wafers) can be provided to handle certain types of RF signals.

[0152] As shown in Figure 15 The transceiver 802 is connected to the front-end system 803 and the power management circuit 805 using a serial interface 809. All or a portion of the illustrated RF components can be controlled by the serial interface 809 to configure the mobile device 800 during initialization and / or while fully operational. In another embodiment, the baseband processor 801 is additionally or alternatively connected to the serial interface 809 and operates to configure one or more RF components, such as components of the front-end system 803 and / or the power management system 805.

[0153] The front-end system 803 assists in conditioning signals transmitted to and / or received from the antenna 804. In the illustrated embodiment, the front-end system 803 includes one or more bias control circuits 810 for controlling power amplifier biasing, one or more power amplifiers (PAs) 811, one or more low noise amplifiers (LNAs) 812, one or more filters 813, one or more switches 814, and one or more duplexers 815. However, other implementations are possible.

[0154] For example, the front-end system 803 can provide a number of functions including, but not limited to, amplifying signals for transmission, amplifying received signals, filtering signals, switching between different frequency bands, switching between different power modes, switching between transmission and reception modes, signal duplexing, signal multiplexing (e.g., diplexing or triplexing), or some combination thereof.

[0155] In certain embodiments, the mobile device 800 supports carrier aggregation, providing flexibility to increase peak data rates. Carrier aggregation can be used for both frequency division duplex (FDD) and time division duplex (TDD), and can be used to aggregate multiple carriers or channels. Carrier aggregation includes contiguous aggregation, in which contiguous carriers within the same operating band are aggregated. Carrier aggregation can also be non-contiguous, and can include carriers separated in frequency within a common band or in different bands.

[0156] The antenna 804 can include antennas for multiple types of communication. For example, the antenna 804 can include antennas for transmitting and / or receiving signals associated with various frequencies and communication standards.

[0157] In certain embodiments, the antenna 804 supports MIMO communication and / or switched diversity communication. For example, MIMO communication uses multiple antennas to communicate multiple data streams over a single radio frequency channel. MIMO communication benefits from higher signal-to-noise ratios, improved coding, and / or reduced signal interference due to spatial multiplexing differences in the radio environment. Switched diversity refers to the selection of a particular antenna to operate at a particular time. For example, a switch can be used to select a particular antenna from a set of antennas based on various factors such as observed bit error rate and / or signal strength indicator.

[0158] In certain embodiments, the mobile device 800 can operate with beamforming. For example, the front-end system 803 can include phase shifters with variable phases controlled by the transceiver 802. Further, the phase shifters are controlled to provide beamforming and directivity for transmitting and / or receiving signals using the antenna 804. For example, in the case of signal transmission, the phases of the transmitted signals provided to the antenna 804 are controlled such that the radiated signals from the antenna 804 combine using constructive and destructive interference to generate an aggregated transmitted signal that exhibits a beam-like quality with more signal strength propagating in a given direction. In the case of signal reception, the phases are controlled such that more signal energy is received when signals arrive at the antenna 804 from a particular direction. In certain embodiments, the antenna 804 includes one or more arrays of antenna elements to enhance beamforming.

[0159] The baseband system 801 is coupled to a user interface 807 to facilitate the processing of various user inputs and outputs (I / O), such as voice and data. The baseband system 801 provides digital representations of transmit signals to the transceiver 802, which processes them to generate RF signals for transmission. The baseband system 801 also processes digital representations of received signals provided by the transceiver 802. As Figure 15 shown, the baseband system 801 is coupled to a memory 806 to facilitate the operation of the mobile device 800.

[0160] The memory 806 can be used for a variety of purposes, such as storing data and / or instructions to facilitate the operation of the mobile device 800 and / or providing storage of user information.

[0161] The power management system 805 provides many of the power management functions of the mobile device 800. In some embodiments, the power management system 805 includes power amplifier (PA) supply control circuitry that controls the supply voltage to the power amplifiers 811. For example, the power management system 805 can be configured to vary the supply voltage provided to one or more of the power amplifiers 811 to improve efficiency, such as power added efficiency (PAE).

[0162] The power management system 805 can operate in selectable supply control modes, such as an average power tracking mode, an envelope tracking mode, a fixed supply mode, or other suitable power management modes. In the illustrated embodiment, the selected supply control mode of the power management system 805 is controlled by the transceiver 802. In some embodiments, the transceiver 802 controls the selected supply control mode using the serial interface 809.

[0163] As Figure 15 shown, the power management system 805 receives a battery voltage from a battery 808. The battery 808 can be any suitable battery for the mobile device 800, including, for example, a lithium-ion battery. Although the power management system 805 is shown as being separate from the front-end system 803, in some embodiments, all or a portion of the power management system 805 (e.g., the PA supply control circuitry) is integrated into the front-end system 803.

[0164] Applications

[0165] Some of the embodiments described above have provided examples associated with a wireless device or mobile phone. However, the principles and advantages of the embodiments can be used in any other system or device that requires a power amplifier system.

[0166] Such power amplifier systems can be implemented in various electronic devices. Examples of electronic devices can include, but are not limited to, consumer electronic products, components of consumer electronic products, electronic test equipment, etc. Examples of electronic devices can also include, but are not limited to, memory chips, memory modules, circuitry of optical or other communication networks, and disk drive circuitry. Consumer electronic products can include, but are not limited to, mobile phones, telephones, televisions, computer monitors, computers, hand-held computers, personal digital assistants (PDAs), microwave ovens, refrigerators, vehicles, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, MP3 players, radios, camcorders, cameras, digital cameras, portable memory chips, washing machines, dryers, washer / dryers, copiers, facsimile machines, scanners, multi-functional peripherals (MFPs), watches, clocks, etc. Furthermore, electronic devices can include unfinished products.

[0167] CONCLUSION

[0168] Unless the context clearly dictates otherwise, throughout the description and the claims, the words "comprise," "comprising," and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense, that is, in the sense of "including, but not limited to." As generally used herein, the word "coupled" means two or more elements are either directly connected, or connected by way of one or more intermediate elements. Likewise, as generally used herein, the word "connection" means two or more elements are either directly connected, or connected by way of one or more intermediate elements. Additionally, the words "herein," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above using the singular or plural number can also include the plural or singular number respectively. The word "or" in reference to a list of two or more items that the word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0169] Further, conditional language used herein, such as, among others, "can," "could," "might," "may," "e.g.," "for instance," "like," "such as," and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is intended in most instances to identify a particular embodiment in which the feature, element, and / or state could be included, but does not necessarily constitute a limitation of every embodiment. Accordingly, a statement following such a conditional language that describes one feature, element, and / or state does not mean that every embodiment necessarily includes the feature, element, and / or state, to the contrary, many embodiments will include some features, elements, and / or states while excluding others in order to address a particular application or design. Thus, the use of such terms does not generally delimit the particular feature, element, and / or state unless specifically stated.

[0170] The foregoing detailed description of the embodiments of the application is not intended to be exhaustive or to limit the application to the precise form disclosed above. While specific embodiments of, and examples for, the application are described above, it will be understood that many modifications, equivalents, and alternatives to the above-described embodiments and examples for the application can be apparent to one of ordinary skill in the art. For example, although the flow or block diagrams show a particular order of execution, alternative embodiments can perform routines having a particular order, execution or blocks in different orders or employ systems having different block configurations. Furthermore, some steps or blocks can be deleted, moved about, combined, sub-divided, or modified in alternative embodiments. Each of these processes or blocks can be implemented in a variety of different ways. Additionally, while the processes or blocks are at times shown as being performed in series, these processes or blocks can instead be performed or implemented in parallel, or can be performed at different times.

[0171] The teachings of the application provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.

[0172] While certain embodiments of the application have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the application. Indeed, the novel methods and systems described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein can be made without departing from the spirit of the application. The enclosed claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the application.

Claims

1. A mobile device comprising: a transceiver configured to produce a radio frequency input signal; a front-end system comprising a power amplifier configured to receive the radio frequency input signal and output a radio frequency output signal, the power amplifier comprising a power amplifier transistor configured to amplify the radio frequency input signal and a bias network configured to bias an input of the power amplifier transistor with a direct current bias voltage, the bias network having a reactance operable to flatten a phase response of the power amplifier, the power amplifier transistor comprising a plurality of transistor elements operating in parallel with one another, and the bias network comprising a plurality of resistors and a plurality of capacitors, each of the plurality of resistors being connected in parallel between the direct current bias voltage and an input of a corresponding one of the plurality of transistor elements with a corresponding one of the plurality of capacitors; and an antenna configured to wirelessly transmit the radio frequency output signal.

2. The mobile device of claim 1, wherein, The reactance is operable to track an intrinsic input capacitance of the power amplifier transistor.

3. The mobile device of claim 1, wherein, The bias network comprises a bias impedance electrically connected between the direct current bias voltage and the input of the power amplifier transistor, and a shunt impedance electrically connected between the input of the power amplifier transistor and a reference voltage.

4. The mobile device of claim 3, wherein, The bias impedance comprises a first resistor, and the shunt impedance comprises a second resistor and a capacitor in series.

5. The mobile device of claim 4, wherein, The shunt impedance further comprises an inductor in series with the second resistor and capacitor.

6. The mobile device of claim 1, wherein, The bias network comprises a resistor and a capacitor electrically connected in parallel between the input of the power amplifier transistor and the direct current bias voltage.

7. The mobile device of claim 1, wherein, The bias network comprises a series combination of a capacitor and an inductor electrically connected between the direct current bias voltage and the input of the power amplifier transistor, and a resistor in parallel with the series combination of the capacitor and inductor.

8. The mobile device of claim 1, wherein, The power amplifier comprises an input stage and an output stage, the power amplifier transistor being incorporated into the output stage of the power amplifier.

9. A power amplifier system comprising: a bias control circuit configured to generate a direct current bias voltage; and a power amplifier configured to receive a radio frequency input signal and output a radio frequency output signal, the power amplifier comprising a power amplifier transistor configured to amplify the radio frequency input signal and a bias network configured to bias an input of the power amplifier transistor with a direct current bias voltage, the bias network having a reactance operable to flatten a phase response of the power amplifier, the power amplifier transistor comprising a plurality of transistor elements operating in parallel with one another, and the bias network comprising a plurality of resistors and a plurality of capacitors, each of the plurality of resistors being connected in parallel between the direct current bias voltage and an input of a corresponding one of the plurality of transistor elements with a corresponding one of the plurality of capacitors.

10. The power amplifier system of claim 9, wherein, The reactance is operable to track an intrinsic input capacitance of the power amplifier transistor.

11. The power amplifier system of claim 9, wherein, The bias network comprises a bias impedance electrically connected between the direct current bias voltage and the input of the power amplifier transistor, and a shunt impedance electrically connected between the input of the power amplifier transistor and a reference voltage.

12. The power amplifier system of claim 11, wherein, The bias impedance includes a first resistor and the shunt impedance includes a second resistor and a capacitor in series.

13. The power amplifier system of claim 12, wherein, The shunt impedance further includes an inductor in series with the second resistor and capacitor.

14. The power amplifier system of claim 9, wherein, The power amplifier transistor is a bipolar transistor having a base corresponding to the input.

15. The power amplifier system of claim 9, wherein, The bias network includes a resistor and a capacitor connected in parallel electrically between the input of the power amplifier transistor and the DC bias voltage.

16. The power amplifier system of claim 9, wherein, The bias network includes a series combination of a capacitor and an inductor connected electrically between the DC bias voltage and the input of the power amplifier transistor, and a resistor connected in parallel with the series combination of the capacitor and inductor.

17. A method of biasing a power amplifier, the method comprising: generating a DC bias voltage using a bias control circuit; receiving a radio frequency input signal as an input to the power amplifier; amplifying the radio frequency input signal using a power amplifier transistor of the power amplifier; and biasing an input of the power amplifier transistor with the DC bias voltage using a bias network of the power amplifier, including flattening a phase response of the power amplifier with a reactance of the bias network, the power amplifier transistor including a plurality of transistor elements operating in parallel with one another, and the bias network including a plurality of resistors and a plurality of capacitors, each of the plurality of resistors connected in parallel with a corresponding one of the plurality of capacitors between the DC bias voltage and an input of a corresponding one of the plurality of transistor elements.

18. The method of claim 17, further comprising tracking an intrinsic input capacitance of the power amplifier transistor with the reactance of the bias network.

19. The method of claim 17, wherein, The bias network includes a bias impedance connected electrically between the DC bias voltage and the input of the power amplifier transistor.

20. The method of claim 19, wherein, The bias network includes a shunt impedance connected electrically between the input of the power amplifier transistor and a reference voltage.

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