Systems and methods for noise reduction for multi-stage power amplifier chain

Abstract

Systems and methods for noise reduction in a multi-stage power amplifier are disclosed. In one aspect, a super source follower regulator provides a low noise power supply signal to a pre-driver stage of a multi-stage power amplifier chain. By providing such a low noise signal, noise amplified by the pre-driver stage is reduced, and thus noise at a subsequent stage is reduced. A second aspect of the present disclosure encompasses sensing noise provided to a first side of a complementary field effect transistor (FET) structure forming the pre-driver stage, and injecting the sensed noise into a second side of the complementary FET structure. Complementary properties of the FET structures allow for destructive summation of the noise, thereby reducing noise available for amplification by the pre-driver stage. These aspects may be used alone to achieve good effects, or together to achieve better effects.

Description

(19) State Intellectual Property Office (12) Invention Patent Application (10) Publication Number (43) Publication Date (21) Application Number 202480062179.5 (22) Application Date 2024.08.26 (30) Priority Data 63 / 589,707 2023.10.12 US 63 / 556,950 2024.02.23 US (85) PCT International Application Entering National Phase Date 2026.03.27 (86) PCT International Application Application Data PCT / US2024 / 043874 2024.08.26 (87) PCT International Application Publication Data WO2025 / 080347 EN 2025.04.17 (71) Applicant: QORVO, Inc., USA (72) Inventors: B. Scott, G. Maxim, S.J. Frank (74) Patent Agency: China Council for the Promotion of International Trade Patent & Trademark Office Co., Ltd., 11038 Patent Attorney: Wang Jingjing (51) Int.Cl. H03F 1 / 26 (2006.01) H03F 1 / 30 (2006.01) H03F 3 / 193 (2006.01) H03F 3 / 24 (2006.01) G05F 1 / 575 (2006.01) H03F 1 / 22 (2006.01) (54) Invention Title: System and Method for Noise Reduction in Multistage Power Amplifier Chains (57) Abstract: This invention discloses a system and method for noise reduction in multistage power amplifiers. In one aspect, a supersource follower regulator provides a low-noise power supply signal to the pre-driver stage of a multistage power amplifier chain. By providing such a low-noise signal, the noise amplified by the pre-driver stage is reduced, and therefore the noise at subsequent stages is reduced. A second aspect of this disclosure covers sensing noise provided to a first side of the complementary field-effect transistor (FET) structure forming the pre-driver stage, and injecting the sensed noise into a second side of the complementary FET structure. The complementary nature of the FET structure allows the noise to be destructively summed, thereby reducing the noise that can be amplified by the pre-driver stage. These aspects can be used individually for good results, or used together for better results.Claims 2 pages, Description 7 pages, Drawings 10 pages, Claims amended according to Article 19 of the Treaty 2 pages CN 121942131 A 2026.04.28 CN 1 21 94 21 31 A 1. A power amplifier chain comprising: a regulator configured to provide a power supply voltage; a pre-driver stage coupled to the regulator and receiving the power supply voltage, wherein the power supply voltage includes a noise component; a voltage sensor coupled to the pre-driver stage and configured to sense the noise component; and a re-injection circuit coupled to the pre-driver stage and configured to generate a reverse noise signal within the pre-driver stage, such that the pre-driver stage destructively sums the reverse noise signal to the noise component. 2. The power amplifier chain of claim 1, wherein the pre-driver stage includes a first P-type field-effect transistor (FET) connected to the regulator. 3. The power amplifier chain of claim 2, wherein the pre-driver stage further includes a first N-type FET (NFET) configured complementary to the first PFET. 4. The power amplifier chain of claim 3, further comprising a filter including a resistor and a capacitor coupled between the source and gate of the first PFET, wherein the noise component is present between the source and gate of the first PFET. 5. The power amplifier chain of claim 4, wherein the voltage sensor includes a sensing FET having a sensing source and a sensing gate, wherein the capacitor connects the sensing source and the sensing gate to mirror the noise component into the sensing FET. 6. The power amplifier chain of claim 3, wherein the re-injection circuitry includes a second NFET that mirrors the reverse noise signal into the first NFET. 7. The power amplifier chain of claim 6, wherein the second NFET is diode-connected such that the injected reverse signal flows through the gate of the second NFET to ground. 8. The power amplifier chain of claim 1, wherein the pre-driver stage further includes a cascode field-effect transistor (FET). 9. The power amplifier chain of claim 1, wherein the pre-driver stage further includes an output configured to be coupled to one or more downstream amplifier stages. 10. The power amplifier chain of claim 1, further comprising: a driver amplifier stage coupled to the pre-driver stage; and an output amplifier stage coupled to the driver amplifier stage. 11. The power amplifier chain of claim 1, wherein the regulator comprises a super-source follower regulator. 12. The power amplifier chain of claim 1, wherein the regulator comprises a diode transistor and a follower transistor that are mirror images of each other.13. The power amplifier chain of claim 12, further comprising a feedback path from the follower transistor to the gate of the series transistor. 14. The power amplifier chain of claim 1, wherein the regulator comprises a series transistor configured to be coupled to a battery voltage, a follower transistor series coupled to the series transistor, and a folded transistor coupled to the series transistor and the follower transistor. 15. The power amplifier chain of claim 14, wherein the gate of the folded transistor is coupled to ground. 16. A mobile communication device comprising: a transceiver chain including: a baseband processor; and a power amplifier chain including: a regulator configured to provide a power supply voltage; a pre-driver stage coupled to the regulator and receiving the power supply voltage, wherein the power supply voltage includes a noise component; a voltage sensor coupled to the pre-driver stage and configured to sense the noise component; and a re-injection circuit coupled to the pre-driver stage and configured to generate a reverse noise signal within the pre-driver stage, such that the pre-driver stage performs a destructive summation of the reverse noise signal and the noise component. 17. The mobile communication device of claim 16, wherein the pre-driver stage includes a first P-type field-effect transistor (FET) connected to the regulator; and a first N-type FET (NFET) configured complementary to the first PFET. 18. The mobile communication device of claim 16, wherein the regulator includes a supersource follower regulator. 19. A method for limiting noise in an amplifier chain, the method comprising: sensing a noise component in a power supply voltage signal of a pre-driver stage of the amplifier chain; and re-injecting an inverse noise signal into the pre-driver stage based on the noise component, such that the inverse noise signal is destructively summed with the noise component. 20. The method of claim 19, further comprising providing the power supply voltage signal using a supersource follower regulator.Claims 2 / 2 Page 3 CN 121942131 A System and Method for Noise Reduction of Multistage Power Amplifier Chain

[0001] Priority Application

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 589,707, filed October 12, 2023, entitled "Converged 2G / 3G / 4G / 5G POWER AMPLIFIER WITH DUAL-PATH SUPPLY NOICE CANCELLATION TO RELAX REGULATOR NOISE SPECIFICATIONS", the contents of which are incorporated herein by reference in their entirety.

[0003] This application also claims priority to U.S. Provisional Patent Application No. 63 / 556,950, filed February 23, 2024, entitled “Systems and methods for noise reduction for multi-stage power amplifier chains,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0004] The technology disclosed herein generally relates to multi-stage power amplifier chains and methods for reducing noise at the first stage of a multi-stage power amplifier chain. Background Art

[0005] Computing devices are ubiquitous in modern society, and more specifically, mobile communication devices have become increasingly prevalent. This prevalence is partly due to the many functions now available on such devices. The increased processing power in these devices means that mobile communication devices have evolved from simple communication tools into sophisticated mobile multimedia centers, thus enhancing the user experience. With the emergence of a variety of functions available for these devices, the pressure to find ways to increase the bandwidth of data transmission between mobile communication devices has increased. This pressure has led to the steady development of wireless communication standards. While new standards do offer improved bandwidth, there is still a desire to maintain backward compatibility with previous standards and to use some form of previous standard format in the form of carrier aggregation. The use of multiple generations of standards has resulted in the use of multi-stage power amplifier chains, which are used to boost the signal to the desired level. Making these multi-stage power amplifiers operate under the stringent requirements of next-generation wireless standards provides room for innovation. Summary of the Invention

[0006] The aspects disclosed in the embodiments include systems and methods for noise reduction in multi-stage power amplifier chains. Specifically, a first exemplary aspect of this disclosure covers providing a low-noise power supply signal to the pre-driver stage of a multi-stage power amplifier chain using a supersource follower regulator.By providing such a low-noise signal, the noise amplified by the pre-driver stage is reduced, and therefore the noise at subsequent stages is reduced. A second exemplary aspect of this disclosure covers sensing noise provided to a first side of a complementary field-effect transistor (FET) structure forming the pre-driver stage, and injecting the sensed noise into a second side of the complementary FET structure. The complementary nature of the FET structure allows the noise to be destructively summed, thereby reducing the noise that can be amplified by the pre-driver stage. These aspects can be used individually for good results, or used together for better results.

[0007] In this regard, in one aspect, a power amplifier chain is disclosed. The power amplifier chain includes: a regulator configured to provide a supply voltage; and a pre-driver stage coupled to the regulator and receiving the supply voltage, wherein the supply voltage includes a noise component. The power amplifier chain further includes: a voltage sensor coupled to a pre-driver stage and configured to sense noise components; and a re-injection circuit coupled to the pre-driver stage and configured to generate a reverse noise signal within the pre-driver stage, such that the pre-driver stage performs a destructive summation of the reverse noise signal and the noise components.

[0008] In another aspect, a mobile communication device is disclosed. The mobile communication device includes a transceiver chain, the transceiver chain including a baseband processor and a power amplifier chain. The power amplifier chain includes: a regulator configured to provide a power supply voltage; and a pre-driver stage coupled to the regulator and receiving the power supply voltage, wherein the power supply voltage includes a noise component. The power amplifier chain also includes: a voltage sensor coupled to the pre-driver stage and configured to sense noise components; and a re-injection circuit coupled to the pre-driver stage and configured to generate a reverse noise signal within the pre-driver stage, such that the pre-driver stage performs a destructive summation of the reverse noise signal and the noise components.

[0009] In another aspect, a method for limiting noise in an amplifier chain is disclosed. The method includes: sensing a noise component in the power supply voltage signal of the pre-driver stage of the amplifier chain; and re-injecting a reverse noise signal into the pre-driver stage based on the noise component, such that the reverse noise signal and the noise component are destructively summed.

[0010] FIG1A is a block diagram of a conventional multistage power amplifier chain;

[0011] FIG1B is a block diagram of the multistage power amplifier of FIG1A with prominent noise sources and noise effects in the pre-driver stage;

[0012] FIG2 is a circuit diagram of a super-source follower regulator that can be used with the pre-driver stage of a multistage power amplifier chain to have low noise;

[0013] FIG3 is a circuit diagram of an alternative super-source follower regulator that can be used with the pre-driver stage;

[0014] FIG4 is a block diagram of a second exemplary aspect in which noise from the regulator is sensed and injected into the pre-driver in a manner that eliminates noise from the regulator;

[0015] FIG5 is a circuit diagram of a first manner in which noise from the regulator is injected to perform a destructive summation with noise from the regulator;

[0016] FIG6 is a more detailed circuit diagram of the noise sensing and injection of FIG5;

[0017] FIG7 is a flowchart illustrating an exemplary procedure for reducing noise in a multistage power amplifier chain;

[0018] Figure 8 is a proof-of-concept circuit diagram showing a complete circuit layout for implementing aspects of this disclosure; and

[0019] Figure 9 is a block diagram of a mobile terminal that may include a multi-stage power amplifier chain of Figures 2-6 according to this disclosure. Detailed Description

[0020] The various embodiments set forth below represent the information required to enable those skilled in the art to practice the various embodiments and illustrate the best mode for practicing the various embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will appreciate the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0021] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited to these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and a second element may likewise be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Specification page 2 / 7 5 CN 121942131 A

[0022] It will be understood that when an element (e.g., layer, region, or substrate) is referred to as being "on" another element or extending "to" another element, the element may be directly on or directly extending to the other element, or there may be an intermediary element present. In contrast, when an element is referred to as being "directly on" or "directly" extending "to" another element, there is no intermediary element.Similarly, it should be understood that when an element (e.g., a layer, region, or substrate) is referred to as being "above" or extending "above" another element, the element may be directly above or extending directly above the other element, or an intermediate element may also be present. In contrast, when an element is referred to as being "directly on" or "directly" extending "above" another element, no intermediate element is present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or an intermediate element may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intermediate element is present.

[0023] As shown in the figures, relative terms (e.g., "below" or "above" or "up" or "down" or "horizontal" or "vertical") may be used herein to describe the relationship of an element, layer, or region to another element, layer, or region. It will be understood that, in addition to the orientations depicted in the figures, these terms and the terms discussed above are intended to cover different orientations of the device.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. Unless the context clearly indicates otherwise, the singular forms “a” and “described” as used herein are also intended to include the plural forms. It will be further understood that, when used herein, the terms “comprising” and / or “including” explicitly indicate the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0025] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and related prior art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0026] To comply with the foregoing warning regarding definitions, this disclosure uses the term transceiver in a broad manner. Current industry literature uses “transceiver” in two ways. The first approach broadly uses the term "transceiver" to refer to multiple circuits that transmit and receive signals. Exemplary circuitry may include a baseband processor, up-conversion / down-conversion circuitry, filters, amplifiers, couplers, and the like coupled to one or more antennas. A second approach, used by some industry literature authors, designates a circuit located between the baseband processor and the power amplifier circuitry as a transceiver. This intermediate circuitry may include up-conversion / down-conversion circuitry, mixers, oscillators, filters, and the like, but typically does not include a power amplifier. As used herein, the term transceiver is used in the first sense. Where necessary to distinguish between the two definitions, the terms "transceiver chain" and "transceiver circuitry" are used respectively.

[0027] The aspects disclosed in the embodiments include systems and methods for noise reduction in multi-stage power amplifier chains. Specifically, a first exemplary aspect of this disclosure covers providing a low-noise power supply signal to a pre-driver stage of a multi-stage power amplifier chain using a super-source follower regulator. By providing such a low-noise signal, noise amplified by the pre-driver stage is reduced, and therefore noise at subsequent stages is reduced. A second exemplary aspect of this disclosure covers sensing noise provided to a first side of a complementary field-effect transistor (FET) structure forming the pre-driver stage, and injecting the sensed noise into a second side of the complementary FET structure. The complementary nature of the FET structure allows the noise to be destructively summed, thereby reducing the noise that can be amplified by the pre-driver stage. These aspects can be used individually for good results, or used together for better results.

[0028] Before proceeding to the exemplary aspects of this disclosure, a brief overview of the power amplifier chain and noise sources is provided with reference to Figures 1A and 1B. The effects of pre-driver noise on subsequent stages are highlighted to better understand the benefits of this disclosure. A detailed description of the exemplary aspects of this disclosure begins below with reference to Figure 2.

[0029] In this regard, FIG1A is a block diagram of a multi-stage power amplifier chain 100 having a pre-driver stage 102, a driver stage 104, and an output stage 106 configured in series, such that an input signal is sequentially amplified by the stages and provided to an output 108 for transmission via an antenna (not shown). Not all signals require all three amplification stages, and therefore the signal to be transmitted can be provided to either a first input 110 or a second input 112. An input matching circuit 114 may be located between the first input 110 and the pre-driver stage 102. The pre-driver stage 102 may be coupled to a multiplexer 116, which selects between a signal from the pre-driver stage 102 and a signal at the second input 112. Regardless of the source, the signal from the multiplexer 116 is provided to the driver stage 104 via a matching circuit 117. Signals from driver stage 104 pass through interstage matching circuit 118, which converts single-ended signals into differential signals, and then reach output stage 106. Signals from output stage 106 pass through output matching circuit 120, which additionally converts the signals back to single-ended signals at output 108.

[0030] In many embodiments, each of stages 102, 104, and 106 receives a supply voltage from power management integrated circuit (PMIC) 122, which may be powered by battery voltage source 124. Additionally, bias circuit 126 may be coupled to battery voltage source 124. Other bias circuits 128 may also be present.Because all stages are actually biased from the same Vcc power supply, there is direct feedback from output 108 to Vcc, Vcc1, and the pre-driver stage. This feedback presents a stability challenge.

[0031] One solution to the stability challenge is to use a regulator 150 for the power supply voltage of the pre-driver stage 102, as preferably seen in Figure 1B. This regulator 150 helps provide isolation but introduces its own noise into the power amplifier chain 100'. Other noise can be introduced by the bias circuitry 152 used for the pre-driver stage 102. Noise from both sources will be up-converted to radio frequency (RF) and amplified, not only in the pre-driver stage 102 but also in the driver stage 104 and the output stage 106. Therefore, any noise present at the pre-driver stage 102 can have a significant, unbalanced effect on the signal at output 108. When there is too much noise at output 108, there may be crosstalk to the receive channel or other complications related to compliance with current wireless communication standards.

[0032] This disclosure proposes two solutions to the noise shown in FIG1B. Specifically, noise from the regulator is reduced by using a super-source follower regulator. This low-noise regulator still has some noise, but much less than a conventional regulator. Residual noise can be sensed and re-injected in a complementary manner to destructively sum with the original residual noise. It should be understood that it is possible to reduce noise by using either technique alone, but using both techniques together provides greater noise reduction and the commensurate benefit of being able to meet various wireless communication standards.

[0033] In this regard, FIG2 shows a first super-source follower regulator 200. The supply voltage is supplied from Vbat 204 to the power amplifier stage 202 via a first transistor 206. In an exemplary aspect, the first transistor 206 is a field-effect transistor (FET), and more specifically, a P-type FET (PFET). This first transistor 206 is sometimes (e.g., in FIG2) referred to as Mser (where M is a common name for transistors in the industry and ser is short for "series located between the source and the power amplifier").

[0034] Reference voltage 208 provides an additional input for second transistor 210, which is diode-connected and mirrored as third transistor 212. Third transistor 212 is coupled to first transistor 206 and generates a feedback loop 214 through amplifier 216 to the gate of first transistor 206. Essentially, second transistor 210 subtracts the voltage from Vref, but this voltage is added back by third transistor, thus providing a stable Vref voltage at node 218. This stable voltage is modulated by feedback loop 214.

[0035] Although not shown in the figure, noise from second transistor 210 can be reduced by using a resistor-capacitor (RC) filter. This method leaves only noise from third transistor 212, which can be relatively small.

[0036] Another source follower regulator 300 is shown in Figure 3. Some components are the same and remain in the same number, as shown in Figure 2. However, the follower transistor 302 is now coupled between the first transistor 206 and the current drain 304. Reference voltage generator circuit 306 includes a feedback path 308, which allows good tracking of the Vreg to Vref voltage, but still maintains the source follower nature of the regulator. In addition, an RC filter 309 helps reduce noise from the reference voltage generator circuit 306. A folded transistor 310 replaces the diode second transistor 210.

[0037] The source follower regulator 300 has relatively low baseband noise and relatively few noise contribution factors.

[0038] Other source follower regulators may also be possible and are used by aspects of this disclosure. Regardless of the type of supersource follower regulator used, the overall noise contribution of the pre-driver stage 102 depends on the regulator baseband noise value, the pre-driver baseband to RF up-conversion gain, and (if present) the rejection provided by the dual path disclosed below. The lower the regulator's baseline noise, the lower the noise of the pre-driver stage.

[0039] Another technique exists that can help reduce noise in the pre-driver stage. Specifically, as shown in FIG4, a power supply noise cancellation bias circuit 402 may be present in the amplifier chain 400. The power supply noise cancellation bias circuit 402 can sense noise in the power supply voltage supplied to the pre-driver stage 102 and generate an inverted or negative version of this noise, which can be added to the pre-driver stage 102 to destructively sum with the noise in the power supply voltage. The power supply noise cancellation bias circuit 402 may further include time matching such that an inverted version in phase with the noise is added for alignment-wise destructive summation.

[0040] Figure 5 illustrates one method in which sensing and injection can be easily implemented, wherein a pre-driver stage 500 is formed of a plurality of cascode FETs in a complementary configuration. Specifically, the pre-driver stage 500 includes PFETs 502(1)-502(N) and N-type FETs (NFETs) 504(1)-504(N). Regulators 200, 300 are coupled to the PFET 502(1) and inject noise therein, wherein the noise is represented by a current source 506 (Inoise regulator). Regulator noise appears at the source of the PFET 502(1). Since the gate of the PFET 502(1) is referenced to ground via the input signal source at the input, the regulator noise appears at the gate-source terminals of the PFET 502(1). A noise sensor 508 senses the noise injected by the regulators 200, 300 and generates a reverse noise signal by means of a noise re-injection circuit 510. This reverse signal is then injected at the gate of NFET 504(1), represented by current source 512 (Inoise cancellation).At node 514, the outputs of PFET 502(1)-502(N) and NFET 504(1)-504(N) are summed. By design, the inoise eliminates negative values ​​equal to the inoise regulator and performs a destructive summation at node 514, leaving a substantially noise-free output signal.

[0041] This injection and destructive summation is facilitated by the complementary nature of PFET 502(1)-502(N) and NFET 504(1)-504(N). It should be understood that another possibility is also possible to generate negative values ​​for re-injection or other modifications to the bias circuitry. Another advantage provided by the complementary structure is better efficiency. That is, PFET 502(1)-502(N) and NFET 504(1)-504(N) use the same DC bias current. Since the pre-driver stage is directly biased from Vbatt without any power supply modulation (i.e., no envelope or average power tracking), the current to the pre-driver stage directly affects the total power amplifier current and its overall efficiency.

[0042] Additional details regarding the noise sensor 508 and the re-injection circuit 510 are provided with reference to FIG6. Specifically, a capacitor 600 and a resistor 602 may be placed between the source and gate of the PFET 502(1). The capacitor 600 and the resistor 602 together form an RC filter for noise injected into the PFET 502(1). This RC filter rejects high-frequency noise.

[0043] Noise that appears at the gate and source of the PFET 502(1) and is not filtered out is sensed by the PFET device 604 of the bias current mirror 606 and converted into a noise current subsequently injected into the NFET bias reference device 608. The sizes of PFET 502(1)-502(N) and NFET 504(1)-504(N) are selected to match the transconductance so that this injection produces a comparable noise signal that is in phase.

[0044] It should be further noted that although a particular sensing mechanism has been described, it is possible to use other sensing mechanisms, such as capacitors.

[0045] FIG7 illustrates a procedure 700 for reducing noise in a multi-stage power amplifier chain. Specifically, procedure 700 begins on page 5 / 7 of the specification, CN 121942131 A, by using low-noise conditioners 200, 300 to limit the noise of the power supply reaching the pre-driver stage 102 (block 702). While this reduces some noise, some residual noise may still exist. Therefore, procedure 700 senses the noise in the power supply signal (block 704). An inverse noise signal is generated (block 706) and re-injected into the pre-driver stage 102 (block 708).

[0046] Figure 8 provides a circuit diagram 800 to demonstrate the author’s working circuit reflecting a complete implementation of a super-source follower regulator similar to that discussed above with respect to Figure 3.It should be understood that while complete details are provided herein, this disclosure is not limited to this circuit, and this diagram is provided more for enabling and written description requirements than for beliefs requiring specific configurations.

[0047] Systems and methods for noise reduction in multi-stage power amplifier chains, according to aspects disclosed herein, can be provided in or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular mobile phones, smartphones, session initiation protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), displays, computer screens, televisions, tuners, radios, satellite broadcasting, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi-rotor aircraft.

[0048] It should be further noted that while more suitable for use with multi-stage power amplifier chains, aspects of this disclosure can also help reduce noise even in single-stage amplifiers. That is, the more amplifier stages present, the greater the impact of the noise reduction provided herein, because each additional stage provides an opportunity for noise in earlier stages to be amplified and cause problems. Reducing the noise in earlier stages by using aspects of this disclosure helps to reduce the amount of noise available for amplification.

[0049] While the above discussion generally assumes that the presence of multiple amplification stages varies with a converged amplifier chain supporting transmissions within multiple wireless communication standards (e.g., 2G–5G), this disclosure is not limited thereto, and any multi-stage power amplifier chain can benefit from aspects of this disclosure.

[0050] Referring to FIG9, the noise reduction concept for power amplifier chains described above can be implemented in various types of user elements 900, such as mobile terminals, smartwatches, tablet computers, computers, navigation devices, access points, and similar wireless communication devices that support wireless communication, such as cellular, wireless local area networks (WLAN), Bluetooth, and near-field communication. User component 900 typically includes a control system 902, a baseband processor 904, a transmission circuitry system 906, a receiving circuitry system 908, an antenna switching circuitry system 910, multiple antennas 912, and a user interface circuitry system 914. In a non-limiting example, the control system 902 may be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In this respect, the control system 902 may include at least a microprocessor, embedded memory circuitry, and a communication bus interface.A receiving circuit system 908 receives radio frequency signals from one or more base stations via an antenna 912 and an antenna switching circuit system 910. A low-noise amplifier and filter in the receiving circuit system 908 cooperate to amplify and remove broadband interference from the received signal for processing. A down-conversion and digitization circuit system (not shown) then down-converts the filtered received signal into an intermediate frequency (IF) or baseband signal, which is then digitized into one or more digital streams using an analog-to-digital converter (ADC).

[0051] A baseband processor 904 processes the digitized received signal to extract the transmitted information or data bits from the received signal. This processing typically includes demodulation, decoding, and error correction operations. The baseband processor 904 is typically implemented in one or more digital signal processors (DSPs) and ASICs.

[0052] For transmission, the baseband processor 904 receives digitized data representing voice, data, or control information encoded by the control system 902 for transmission. Encoded data is output to transmission circuitry system 906, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at one or more desired transmission frequencies. For example, a power amplifier chain, as described herein with reference to Figures 2-8, amplifies the modulated carrier signal to a level suitable for transmission, and the modulated carrier signal is delivered to antenna 912 via antenna switching circuitry system 910. Multiple antennas 912 and replicated transmission and reception circuitry systems 906, 908 provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0053] It should also be noted that the operational steps described in any exemplary aspect herein are described to provide examples and discussion. The described operations may be performed in several different orders other than the order shown. Furthermore, the operations described in a single operational step may actually be performed in several different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that the operational steps shown in the flowchart can undergo many different modifications, as will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced in the above embodiments can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0054] The foregoing description of this disclosure is provided so that any person skilled in the art can make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations.Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be given the broadest scope that conforms to the principles and novel features disclosed herein. Instruction manual page 7 / 7, 10 CN 121942131 A, Figure 1A; Instruction manual figure 1 / 10, 11 CN 121942131 A, Figure 1B; Instruction manual figure 2 / 10, 12 CN 121942131 A, Figure 2; Instruction manual figure 3 / 10, 13 CN 121942131 A, Figure 3; Instruction manual figure 4 / 10, 14 CN 121942131 A, Figure 4; Instruction manual figure 5 / 10, 15 CN 121942131 A, Figure 5; Instruction manual figure 6 / 10, 16 CN 121942131 A, Figure 6; Instruction manual figure 7 / 10, 17 CN 121942131 A, Figure 7; Instruction manual figure 8 / 10, 18 CN 121942131 A, Figure 8; Instruction manual figure 9 / 10, 19 CN 121942131 A, Figure 9. Specification Figure 10 / 10 Page 20 CN 121942131 A 1. A power amplifier chain comprising: a regulator configured to provide a supply voltage; a pre-driver stage coupled to the regulator and receiving the supply voltage, wherein the supply voltage includes a noise component; a voltage sensor coupled to the pre-driver stage and configured to sense the noise component; and a re-injection circuit coupled to the pre-driver stage and configured to generate a reverse noise signal within the pre-driver stage, such that the pre-driver stage performs a destructive summation of the reverse noise signal and the noise component. 2. The power amplifier chain of claim 1, wherein the pre-driver stage includes a first P-type field-effect transistor (FET) connected to the regulator. 3. The power amplifier chain of claim 2, wherein the pre-driver stage further includes a first N-type FET (NFET) configured complementary to the first PFET. 4. The power amplifier chain of claim 3, further comprising a filter including a resistor and a capacitor coupled between the source and gate of the first PFET, wherein the noise component is present between the source and gate of the first PFET. 5. The power amplifier chain of claim 4, wherein the voltage sensor includes a sensing FET having a sensing source and a sensing gate, wherein the capacitor connects the sensing source and the sensing gate, thereby mirroring the noise component into the sensing FET.6. The power amplifier chain of claim 3, wherein the re-injection circuitry includes a second NFET that mirrors the reverse noise signal to the first NFET. 7. The power amplifier chain of claim 6, wherein the second NFET is diode-connected such that the injected reverse signal flows through the gate of the second NFET to ground. 8. The power amplifier chain of claim 1, wherein the pre-driver stage further includes a cascode field-effect transistor (FET). 9. The power amplifier chain of claim 1, wherein the pre-driver stage further includes an output configured to be coupled to one or more downstream amplifier stages. 10. The power amplifier chain of claim 1, further comprising: a driver amplifier stage coupled to the pre-driver stage; and an output amplifier stage coupled to the driver amplifier stage. 11. The power amplifier chain of claim 1, wherein the regulator includes a super-source follower regulator. 12. The power amplifier chain of claim 1, wherein the regulator includes a diode transistor and a follower transistor that are mirror images of each other. 13. The power amplifier chain of claim 12, further including a feedback path from the follower transistor to the gate of a series transistor. 14. The power amplifier chain of claim 1, wherein the regulator comprises a series transistor configured to be coupled to a battery voltage, a follower transistor series coupled to the series transistor, and a folded transistor coupled to the series transistor and the follower transistor. 15. The power amplifier chain of claim 14, wherein the gate of the folded transistor is coupled to ground. 16. A mobile communication device comprising: a transceiver chain including: a baseband processor; and a power amplifier chain comprising: a regulator configured to provide a power supply voltage; a pre-driver stage coupled to the regulator and receiving the power supply voltage, wherein the power supply voltage includes a noise component; a voltage sensor coupled to the pre-driver stage and configured to sense the noise component; and a re-injection circuit coupled to the pre-driver stage and configured to generate a reverse noise signal within the pre-driver stage, such that the pre-driver stage destructively sums the reverse noise signal to the noise component. 17. The mobile communication device of claim 16, wherein the pre-driver stage includes a first P-type field-effect transistor (FET) (PFET) connected to the regulator; and a first N-type FET (NFET) configured complementary to the first PFET. 18. The mobile communication device of claim 16, wherein the regulator includes a super-source follower regulator.19. A method for limiting noise in a power amplifier chain, the method comprising: providing a power supply voltage having a noise component; sensing the noise component in the power supply voltage signal of a pre-driver stage of the amplifier chain using a voltage sensor; and re-injecting a reverse noise signal into the pre-driver stage based on the noise component using a re-injection circuit, such that the reverse noise signal and the noise component are destructively summed in the pre-driver stage. 20. The method of claim 19, further comprising providing the power supply voltage signal using a supersource follower regulator. Claims amended under Article 19 of the Treaty, 2 / 2, page 22, CN 121942131 A.

Claims

1. A power amplifier chain, comprising: A regulator configured to provide a power supply voltage; A pre-driver stage, which is coupled to the regulator and receives the power supply voltage, wherein the power supply voltage includes a noise component; A voltage sensor, coupled to the pre-driver stage and configured to sense the noise component; The re-injection circuit is coupled to the pre-driver stage and configured to generate an inverse noise signal within the pre-driver stage, such that the pre-driver stage performs a destructive summation of the inverse noise signal and the noise component.

2. The power amplifier chain of claim 1, wherein the pre-driver stage includes a first P-type field-effect transistor (FET) connected to the regulator.

3. The power amplifier chain of claim 2, wherein the pre-driver stage further comprises a first N-type FET (NFET) configured in a complementary manner relative to the first PFET.

4. The power amplifier chain of claim 3, further comprising a filter including a resistor and a capacitor coupled between the source and gate of the first PFET, wherein the noise component is present between the source and gate of the first PFET.

5. The power amplifier chain of claim 4, wherein the voltage sensor comprises a sensing FET having a sensing source and a sensing gate, wherein the capacitor connects the sensing source and the sensing gate, thereby mirroring the noise component into the sensing FET.

6. The power amplifier chain of claim 3, wherein the re-injection circuitry includes a second NFET that mirrors the inverse noise signal onto the first NFET.

7. The power amplifier chain of claim 6, wherein the second NFET is diode-connected such that an injected reverse signal flows through the gate of the second NFET to ground.

8. The power amplifier chain of claim 1, wherein the pre-driver stage further comprises a cascode field-effect transistor (FET).

9. The power amplifier chain of claim 1, wherein the pre-driver stage further includes an output configured to be coupled to one or more downstream amplifier stages.

10. The power amplifier chain of claim 1, further comprising: A driver amplifier stage, which is coupled to the pre-driver stage; as well as The output amplifier stage is coupled to the driver amplifier stage.

11. The power amplifier chain of claim 1, wherein the regulator comprises a supersource follower regulator.

12. The power amplifier chain of claim 1, wherein the regulator comprises a diode transistor and a follower transistor that are mirror images of each other.

13. The power amplifier chain of claim 12, further comprising a feedback path from the follower transistor to the gate of the series transistor.

14. The power amplifier chain of claim 1, wherein the regulator comprises a series transistor configured to be coupled to a battery voltage, a follower transistor coupled in series to the series transistor, and a folded transistor coupled to the series transistor and the follower transistor.

15. The power amplifier chain of claim 14, wherein the gate of the folded transistor is coupled to ground.

16. A mobile communication device comprising: Transceiver chain, comprising: Baseband processor; and A power amplifier chain, comprising: A regulator configured to provide a power supply voltage; A pre-driver stage, which is coupled to the regulator and receives the power supply voltage, wherein the power supply voltage includes a noise component; A voltage sensor, coupled to the pre-driver stage and configured to sense the noise component; and The re-injection circuit is coupled to the pre-driver stage and configured to generate an inverse noise signal within the pre-driver stage, such that the pre-driver stage performs a destructive summation of the inverse noise signal and the noise component.

17. The mobile communication device of claim 16, wherein the pre-driver stage includes a first P-type field-effect transistor (FET) connected to the regulator; and A first N-type FET (NFET) configured in a complementary manner to the first PFET.

18. The mobile communication device of claim 16, wherein the regulator comprises a super-source follower regulator.

19. A method for limiting noise in an amplifier chain, the method comprising: Sensing the noise component in the power supply voltage signal of the pre-driver stage of the amplifier chain; as well as The inverse noise signal is then injected into the pre-driver stage based on the noise component, such that the inverse noise signal and the noise component are destructively summed.

20. The method of claim 19, further comprising providing the power supply voltage signal using a supersource follower regulator.

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