Module with built-in electronic component and manufacturing method of module with built-in electronic component

Abstract

To provide an electronic component embedded module and a manufacturing method of the electronic component embedded module that enable the diameter of connection holes to be made smaller.SOLUTION: An electronic component embedded module includes at least a hole diameter setting layer 14, an electronic component 161, and an insulating layer 22. The hole diameter setting layer has an inner wall 14Wi, an outer wall 14Wo, a surface 14Sf intersecting the inner wall and the outer wall, and a back surface 14Sr opposite the front surface. The electronic component includes a first terminal surface 161Sa facing the back surface, and a first terminal electrode 1611 provided on the first terminal surface. An insulating layer 151 is provided between the first terminal surface and the back surface, covers the outer wall, and has a step with the front surface around the front surface. The electronic component embedded module further includes a connection hole V21 that reaches the first terminal electrode from the inner wall through the insulating layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an electronic component built-in module and a method for manufacturing an electronic component built-in module. [Background technology]

[0002] In recent years, attention has been focused on electronic component built-in modules that have electronic components built in. The electronic component built-in module functions, for example, as an interposer that connects a semiconductor element and a mounting substrate (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2011-523773 Summary of the Invention [Problem to be solved by the invention]

[0004] In such an electronic component built-in module, it is desirable to make the diameter of the connection holes smaller.

[0005] The present invention has been made in consideration of the above circumstances, and has an object to provide an electronic component-embedded module and a manufacturing method thereof that enable a smaller diameter of connection holes. That is, an object of the present invention is to provide an electronic component-embedded module and a manufacturing method thereof that enable a smaller diameter of connection holes. [Means for solving the problem]

[0006] The above object can be achieved by the following means.

[0007] (1) An electronic component-embedded module comprising at least an aperture diameter defining layer, an electronic component, and an insulating layer, wherein the aperture diameter defining layer has an inner wall, an outer wall, a surface intersecting the inner wall and the outer wall, and a back surface opposite the surface, the electronic component has a first terminal surface opposite the back surface and a first terminal electrode provided on the first terminal surface, the insulating layer is provided between the first terminal surface and the back surface, covers the outer wall, and has a step with respect to the front surface around the periphery of the front surface, and the electronic component-embedded module further has a connection hole extending from the inner wall through the insulating layer to the first terminal electrode.

[0008] (2) The electronic component built-in module according to (1) above, wherein the insulating layer around the surface protrudes from the surface.

[0009] (3) An electronic component built-in module comprising at least a hole diameter defining layer, a metal film, an electronic component, and an insulating layer, wherein the hole diameter defining layer has an inner wall, an outer wall, a surface intersecting the inner wall and the outer wall, and a back surface opposite the front surface, the electronic component has a first terminal surface opposite the back surface and a first terminal electrode provided on the first terminal surface, the insulating layer is provided between the first terminal surface and the back surface and covers the outer wall, the metal film is provided on the front surface and has an opening, and the electronic component built-in module further has a connection hole extending from the opening through the inner wall and the insulating layer to the first terminal electrode.

[0010] (4) The electronic component built-in module according to (3) above, wherein the metal film contains at least one of copper (Cu), titanium (Ti) and chromium (Cr).

[0011] (5) The electronic component built-in module according to any one of the above (1) to (4), wherein the pore diameter setting layer contains at least copper.

[0012] (6) The electronic component built-in module according to any one of (1) to (5) above, further comprising a seed layer provided in the connection hole and a first conductor layer electrically connected to the first terminal electrode via the seed layer.

[0013] (7) The seed layer includes an adhesive film and a conductive film provided between the adhesive film and the first conductor layer, and the adhesive film and the conductive film include at least one of copper, aluminum (Al), titanium and chromium. The electronic component built-in module described in (6) above.

[0014] (8) The electronic component built-in module according to (6) or (7) above, further comprising a second conductor layer, the electronic component further comprising a second terminal surface facing the first terminal surface and a second terminal electrode provided on the second terminal surface, the second terminal electrode being electrically connected to the second conductor layer.

[0015] (9) The electronic component built-in module according to any one of (1) to (8) above, wherein the connection hole has a tapered shape.

[0016] (10) The electronic component built-in module according to any one of (1) to (9) above, wherein the hole diameter setting layer has a through hole penetrating from the front surface to the back surface, and the inner wall is provided in the through hole.

[0017] (11) The electronic component built-in module according to (10) above, wherein the through hole has a circular or elliptical planar shape.

[0018] (12) The electronic component built-in module according to (10) or (11) above, wherein the maximum hole diameter of the connection hole is larger than the maximum hole diameter of the through hole.

[0019] (13) The electronic component built-in module according to any one of the above (1) to (12), wherein the pore diameter defining layer includes a plating film.

[0020] (14) The electronic component built-in module according to any one of (1) to (13) above, comprising a plurality of the electronic components.

[0021] (15) The electronic component built-in module according to (14) above, wherein the plurality of electronic components include electronic components having thicknesses different from one another.

[0022] (16) The electronic component built-in module according to any one of (1) to (15) above, wherein the insulating layer contains an organic insulating material.

[0023] (17) A method for manufacturing an electronic component built-in module, comprising: a step (a) of forming a hole diameter defining layer having an inner wall on a support substrate; a step (b) of providing an adhesive layer on the support substrate to cover the hole diameter defining layer; a step (c) of bonding an electronic component having a terminal electrode on a terminal surface to the support substrate via the adhesive layer such that the terminal surface faces the support substrate; a step (d) of removing the support substrate after bonding the electronic component to the support substrate; a step (e) of forming a connection hole extending from the inner wall to the terminal electrode via the adhesive layer; a step (f) of forming a seed layer in the connection hole; and a step (g) of electrically connecting a conductor layer and the terminal electrode via the seed layer.

[0024] (18) The method for producing an electronic component built-in module according to (17) above, wherein in the step (f), the seed layer is formed in the connection hole by a sputtering method.

[0025] (19) The method for producing an electronic component built-in module according to (17) or (18) above, wherein in the step (a), the hole diameter defining layer is formed on the supporting substrate by electrolytic plating.

[0026] (20) The method for producing an electronic component built-in module according to any one of (17) to (19) above, wherein the support substrate contains glass. Effect of the Invention

[0027] In the electronic component built-in module and the manufacturing method of the electronic component built-in module according to the present invention, the inner wall of the hole diameter setting layer is utilized to form a connection hole in the insulating layer. This makes it possible to form a connection hole according to the shape of the inner wall of the hole diameter setting layer. This makes it possible to make the hole diameter of the connection hole smaller. [Brief description of the drawings]

[0028] [Figure 1] 1 is a cross-sectional view showing an example of a configuration of an electronic device including an electronic component built-in module according to an embodiment of the present invention. [Diagram 2] 2 is an enlarged cross-sectional view showing the vicinity of a pore diameter defining layer shown in FIG. 1. [Diagram 3] 3 is a diagram illustrating an example of a planar configuration of the pore diameter defining layer illustrated in FIG. 2. [Figure 4] 2 is a cross-sectional view illustrating a step in a method of manufacturing the electronic device illustrated in FIG. [Diagram 5] 5 is a cross-sectional view showing a process following FIG. 4. [Figure 6] FIG. 6 is a cross-sectional view showing a step following FIG. [Figure 7] FIG. 7 is a cross-sectional view showing a process following FIG. [Figure 8] FIG. 8 is a cross-sectional view showing a step following FIG. 7. [Figure 9] FIG. 9 is a cross-sectional view showing a step following FIG. 8. [Figure 10] FIG. 10 is a cross-sectional view showing a step following FIG. [Figure 11] FIG. 11 is a cross-sectional view showing a process following FIG. [Figure 12A] FIG. 12 is a cross-sectional view showing a step following FIG. [Figure 12B] 12B is an enlarged cross-sectional view showing the vicinity of the pore diameter setting layer shown in FIG. 12A. [Figure 13] FIG. 12B is a cross-sectional view showing a step following FIG. 12A. [Figure 14] FIG. 14 is a cross-sectional view showing a process following FIG. [Figure 15] 15 is a cross-sectional view showing a process following FIG. 14. [Figure 16]FIG. 16 is a cross-sectional view showing a process following FIG. [Figure 17] FIG. 17 is a cross-sectional view showing a step following FIG. 16. [Figure 18] 18 is a cross-sectional view showing a process following FIG. 17. [Figure 19] 19 is a cross-sectional view showing a step following FIG. 18. [Figure 20] 20 is a cross-sectional view showing a process following FIG. 19. [Figure 21] 11 is a cross-sectional view showing an example of a configuration of a main part of an electronic component built-in module according to a modified example. FIG. [Figure 22] FIG. 11 is a cross-sectional view showing an example of the configuration of an electronic component built-in module according to another modified example. [Diagram 23] FIG. 11 is a cross-sectional view showing an example of the configuration of an electronic component built-in module according to another modified example. [Figure 24] FIG. 11 is a cross-sectional view showing an example of the configuration of an electronic component built-in module according to another modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of description. Meanwhile, the embodiments described below are merely examples, and various modifications are possible from such embodiments.

[0030] In the following description, the terms "upper" and "above" may include not only something that is directly above in contact with something, but also something that is above without contacting something.

[0031] The singular expression includes the plural expression unless the context clearly indicates otherwise. In addition, when a part is described as "comprising" or "having" a certain element, it does not mean excluding other elements, but means that other elements may be further included, unless otherwise specified to the contrary.

[0032] Additionally, use of the terms "said" and similar referents refers to both the singular and the plural.

[0033] Unless the steps constituting the method are explicitly described in order or described to the contrary, the steps may be performed in any suitable order, and the order of the steps described is not necessarily limited to the order of the steps described. The use of any examples or exemplary terms (such as, for example, etc.) is merely for the purpose of illustrating the technical idea, and the scope of the invention is not limited by the examples or exemplary terms, except as limited by the scope of the claims.

[0034] <Embodiment> FIG. 1 shows an example of the configuration of an electronic device having an electronic component built-in module (electronic component built-in module 10) according to one embodiment of the present invention. This electronic device includes, for example, as main members, the electronic component built-in module 10, semiconductor elements 31 and 32, and a mounting substrate 40. The electronic component built-in module 10 functions as an interposer that connects the semiconductor elements 31 and 32 to the mounting substrate 40. In the electronic device, the mounting substrate 40, the electronic component built-in module 10, and the semiconductor elements 31 and 32 are stacked in this order. In the following description, the stacking direction of the mounting substrate 40, the electronic component built-in module 10, and the semiconductor elements 31 and 32 may be referred to as the Z direction, the direction perpendicular to the Z direction may be referred to as the X direction, and the direction perpendicular to the Z direction and the X direction may be referred to as the Y direction.

[0035] The semiconductor elements 31 and 32 are, for example, semiconductor chips each having a predetermined function. The semiconductor elements 31 and 32 are, for example, IC (Integrated Circuit) chips or memories. The semiconductor element 31 has, for example, a plurality of electrodes 311 on a predetermined surface (for example, the XY plane). The semiconductor element 32 has, for example, a plurality of electrodes 321 on a predetermined surface (for example, the XY plane). The electronic device further has, for example, a sealing layer 33, an underfill material 34, and a plurality of bumps 35 in the vicinity of the semiconductor elements 31 and 32.

[0036] The multiple bumps 35 electrically connect the electrodes 311, 321 to the electronic component built-in module 10. The bumps 35 contain, for example, a solder material. The underfill material 34 is provided between the semiconductor elements 31, 32 and the electronic component built-in module 10. For example, the spaces between adjacent bumps 35 are filled with the underfill material 34. The sealing layer 33 is laminated on the underfill material 34. The sealing layer 33 covers the periphery of the semiconductor elements 31, 32. The sealing layer 33 and the underfill material 34 contain, for example, a resin material.

[0037] The mounting substrate 40 is, for example, a semiconductor package substrate, a motherboard, etc. The mounting substrate 40 includes, for example, a base material 41, a wiring layer 42, electrodes 43, and a solder resist layer 44.

[0038] The mounting substrate 40 is electrically connected to the electronic component built-in module 10 via a plurality of bumps 45. The plurality of bumps 45 are provided on the electrodes 43. For example, the distance between adjacent bumps 45 is greater than the distance between adjacent bumps 35. The bumps 35 contain, for example, a solder material.

[0039] (Configuration of electronic component built-in module 10) The electronic component built-in module 10 includes, for example, a first substrate electrode 11, a relay conductor layer 12, a first conductor layer 13, a hole diameter defining layer 14, adhesive layers 151, 152, electronic components 161, 162, a second conductor layer 17, a second substrate electrode 18, a first solder resist layer 21, a first insulating layer 22, a second insulating layer 23, and a second solder resist layer 24. Here, the adhesive layers 151, 152 correspond to a specific example of an insulating layer of the present invention.

[0040] In the electronic component built-in module 10, a first solder resist layer 21, a first insulating layer 22, a second insulating layer 23, and a second solder resist layer 24 are laminated in this order along the Z direction. For example, the first solder resist layer 21, the first insulating layer 22, the second insulating layer 23, and the second solder resist layer 24 are arranged in this order from the position closest to the semiconductor elements 31, 32. The first solder resist layer 21 and the second solder resist layer 24 contain an organic insulating material such as an epoxy resin, a phenol resin, or an acrylic resin. The first solder resist layer 21 and the second solder resist layer 24 may contain a filler.

[0041] The first insulating layer 22 and the second insulating layer 23 include an organic insulating material such as an epoxy resin, a phenolic resin, an acrylic resin, a polyimide resin, or a liquid crystal polymer. The first insulating layer 22 and the second insulating layer 23 may include a filler. The first insulating layer 22 and the second insulating layer 23 may include an inorganic insulating material.

[0042] The first substrate electrode 11 is disposed on one end face in the Z direction of the electronic component built-in module 10 (for example, the XY plane). The second substrate electrode 18 is disposed on the other end face in the Z direction of the electronic component built-in module 10 (for example, the XY plane). The first substrate electrode 11 is provided, for example, in an opening of the first solder resist layer 21. The second substrate electrode 18 is provided, for example, in an opening of the second solder resist layer 24. The electronic component built-in module 10 has, for example, a plurality of first substrate electrodes 11 and a plurality of second substrate electrodes 18.

[0043] The first substrate electrode 11 is provided, for example, at a position corresponding to each of the electrodes 311 of the semiconductor element 31 and the electrodes 321 of the semiconductor element 32. The second substrate electrode 18 is provided, for example, at a position corresponding to each of the electrodes 43 of the mounting substrate 40. The first substrate electrode 11 is electrically connected to the electrodes 311 and 321 via the bumps 35. The second substrate electrode 18 is electrically connected to the electrode 43 via the bumps 45. The first substrate electrode 11 and the second substrate electrode 18 each contain, for example, a conductive metal material such as gold, copper, nickel, or tin. The constituent material of the first substrate electrode 11 may be different from the constituent material of the second substrate electrode 18. The first substrate electrode 11 and the second substrate electrode 18 each contain, for example, a plating film.

[0044] The relay conductor layer 12 is in contact with each of the multiple first substrate electrodes 11, for example. For example, the first substrate electrodes 11 are provided in selective regions on the surface of the relay conductor layer 12. The relay conductor layer 12 is arranged in a predetermined pattern on the upper surface of the first insulating layer 22, for example. For example, the surface and side surfaces of the relay conductor layer 12 are covered with a first solder resist layer 21. The relay conductor layer 12 includes a conductive metal material, for example, gold, platinum, palladium, silver, copper, aluminum, cobalt, titanium, chromium, nickel, tungsten, iron, tin, indium, or zinc. The relay conductor layer 12 includes, for example, copper. The relay conductor layer 12 includes, for example, a plating film.

[0045] The first conductor layer 13 serves to electrically connect the relay conductor layer 12 and the electronic components 161, 162 (more specifically, first terminal electrodes 1611, 1621 described later). The first conductor layer 13 contains a conductive metal material such as gold, platinum, palladium, silver, copper, aluminum, cobalt, titanium, chromium, nickel, tungsten, iron, tin, indium, or zinc. The first conductor layer 13 is arranged, for example, on the second insulating layer 23 in a predetermined pattern. The first conductor layer 13 is provided, for example, at a position overlapping each of the electronic components 161, 162 in a planar (XY) view. For example, the surface and side surfaces of the first conductor layer 13 are covered with the first insulating layer 22.

[0046] The first insulating layer 22 is provided with a connection hole V1 that reaches the surface of the first conductor layer 13. For example, a relay conductor layer 12 is provided in this connection hole V1. This electrically connects the first conductor layer 13 and the first substrate electrode 11. The relay conductor layer 12 may be connected to the first conductor layer 13 via a seed layer. The seed layer includes, for example, an adhesion film containing titanium and a conductive film containing copper.

[0047] The hole diameter setting layer 14 is disposed, for example, between the first conductor layer 13 and the electronic components 161 and 162. The hole diameter setting layer 14 will be described in detail later.

[0048] The adhesive layers 151, 152 are provided between the first insulating layer 22 and the electronic components 161, 162. The adhesive layer 151 is provided between the first insulating layer 22 and the electronic component 161, and the adhesive layer 152 is provided between the first insulating layer 22 and the electronic component 162. The adhesive layers 151, 152 serve to adhere the electronic components 161, 162 to the first insulating layer 22. The periphery of the adhesive layers 151, 152 is covered with the second insulating layer 23.

[0049] The adhesive layers 151, 152 contain an organic insulating material such as, for example, epoxy resin, phenol resin, acrylic resin, polyimide resin, and liquid crystal polymer. The adhesive layers 151, 152 may contain a filler. The linear expansion coefficient of the adhesive layers 151, 152 is preferably lower than that of the second insulating layer 23. This makes it possible to suppress warping of the electronic component built-in module 10. The thermal conductivity of the adhesive layers 151, 152 is preferably higher than that of the second insulating layer 23. This makes it possible to improve the heat dissipation of the electronic component built-in module 10.

[0050] The electronic components 161 and 162 are embedded in the second insulating layer 23. The electronic components 161 and 162 have predetermined functions, such as, for example, an IC, a bridge, a capacitor, an inductor, a coil, a thermistor, a resistor, and a fuse. The electronic components 161 and 162 are, for example, semiconductor chips. The electronic component built-in module 10 has the electronic components 161 and 162, so that the interposer that connects the semiconductor elements 31 and 32 and the mounting substrate 40 can be given a desired function. This makes it possible to realize miniaturization and high functionality of electronic devices. The constituent material of the electronic components 161 and 162 is different from the constituent material of the first insulating layer 22. The elastic modulus of the electronic components 161 and 162 is different from the elastic modulus of the first insulating layer 22. The thickness (size in the Z direction) of the electronic component 161 and the thickness of the electronic component 162 are, for example, different.

[0051] The electronic component 161 has, for example, a first terminal surface 161Sa and a second terminal surface 161Sb that face each other in the Z direction. The electronic component 162 has, for example, a first terminal surface 162Sa and a second terminal surface 162Sb that face each other in the Z direction. For example, the first terminal surfaces 161Sa, 162Sa and the second terminal surfaces 161Sb, 162Sb are arranged parallel to the XY plane. For example, the first terminal surfaces 161Sa, 162Sa face the first insulating layer 22, and the second terminal surfaces 161Sb, 162Sb face the second solder resist layer 24. An adhesive layer 151 is provided between the first terminal surface 161Sa and the first insulating layer 22. An adhesive layer 152 is provided between the first terminal surface 162Sa and the first insulating layer 22.

[0052] A first terminal electrode 1611 is provided on a first terminal surface 161Sa of the electronic component 161, and a second terminal electrode 1612 is provided on a second terminal surface 161Sb. The electronic component 161 has, for example, a plurality of first terminal electrodes 1611 and a plurality of second terminal electrodes 1612. A first terminal electrode 1621 is provided on a first terminal surface 162Sa of the electronic component 162, and a second terminal electrode 1622 is provided on a second terminal surface 162Sb. The electronic component 162 has, for example, a plurality of first terminal electrodes 1621 and a plurality of second terminal electrodes 1622.

[0053] The adhesive layer 151 is provided with a connection hole V21 that reaches the surface of the first terminal electrode 1611. The first conductor layer 13 and the connection hole V21 are connected. As a result, the first terminal electrode 1611 and the first substrate electrode 11 are electrically connected via the relay conductor layer 12 and the first conductor layer 13.

[0054] The adhesive layer 152 is provided with a connection hole V22 that reaches the surface of the first terminal electrode 1621. The first conductor layer 13 and the connection hole V22 are connected. As a result, the first terminal electrode 1621 and the first substrate electrode 11 are electrically connected via the relay conductor layer 12 and the first conductor layer 13.

[0055] The second conductor layer 17 is in contact with each of the multiple second board electrodes 18, for example. For example, the second board electrodes 18 are provided in selective regions on the surface of the second conductor layer 17. The second conductor layer 17 is arranged in a predetermined pattern on the lower surface of the second insulating layer 23, for example. For example, the surface and side surfaces of the second conductor layer 17 are covered with a second solder resist layer 24. The second conductor layer 17 includes a conductive metal material, such as gold, platinum, palladium, silver, copper, aluminum, cobalt, titanium, chromium, nickel, tungsten, iron, tin, indium, or zinc. The second conductor layer 17 includes copper, for example. The second conductor layer 17 includes a plating film, for example.

[0056] The second insulating layer 23 in which the electronic components 161 and 162 are embedded is provided with connection holes V31 and V32 that reach the second terminal electrodes 1612 and 1622. The second conductor layer 17 and the connection holes V31 and V32 are connected. As a result, the second terminal electrode 1622 and the second substrate electrode 18 are electrically connected via the second conductor layer 17. The second conductor layer 17 may be connected to the second terminal electrodes 1612 and 1622 via a seed layer (a seed layer 19A in FIG. 9 described later). In this way, the electronic component built-in module 10 has connection holes V31 and V32 that reach the second terminal surfaces 161Sb and 162Sb in addition to the connection holes V21 and V21 that reach the first terminal surfaces 161Sa and 162Sa. As a result, it is possible to improve the power supply to the electronic components 161 and 162, for example. Also, it is possible to more effectively dissipate heat generated by the electronic components 161 and 162.

[0057] It is preferable that the volumes of the connection holes V31 and V32 are larger than the volume of the connection hole V1. This can improve the signal integrity and power integrity. Furthermore, the heat dissipation of the electronic component built-in module 10 can be improved.

[0058] The second insulating layer 23 is provided with, for example, a connection hole V33 that penetrates the second insulating layer 23 in the Z direction and reaches the first conductor layer 13. The second conductor layer 17 and the connection hole V33 are connected. This electrically connects the first substrate electrode 11 and the second substrate electrode 18 via the first conductor layer 13 and the second conductor layer 17. The second insulating layer 23 may be provided with a pillar or the like instead of the connection hole V33. The second conductor layer 17 may be connected to the first conductor layer 13 via a seed layer (seed layer 19A in FIG. 9 described later).

[0059] (Configuration of pore diameter setting layer 14) Fig. 2 shows an enlarged view of the vicinity of the pore diameter setting layer 14 shown in Fig. 1. Fig. 3 shows an example of a planar (XY plane) configuration of the pore diameter setting layer 14 shown in Fig. 2. Fig. 2 shows an example of the pore diameter setting layer 14 arranged in the vicinity of an electronic component 161. For example, the pore diameter setting layer 14 arranged in the vicinity of an electronic component 162 also has a similar configuration.

[0060] The hole diameter setting layer 14 is disposed, for example, at a position facing the first terminal electrode 1611. The hole diameter setting layer 14 plays a role in setting the size of the hole diameter of the connection hole V21 formed in the adhesive layer 151. As will be described in detail later, in this embodiment, since the electronic component built-in module 10 has this hole diameter setting layer 14, it is possible to make the hole diameter of the connection hole V21 smaller.

[0061] The hole diameter setting layer 14 has, for example, a front surface 14Sf and a back surface 14Sr that face each other in the Z direction. The front surface 14Sf and the back surface 14Sr are arranged, for example, parallel to the XY plane. The front surface 14Sf faces the first insulating layer 22, and the back surface 14Sr faces the first terminal surface 161Sa. An adhesive layer 151 is provided between the back surface 14Sr and the first terminal surface 161Sa. The front surface 14Sf is not covered by the adhesive layer 151. In other words, the front surface 14Sf is exposed from the adhesive layer 151.

[0062] The hole diameter setting layer 14 has a circular or elliptical planar (XY plane) shape (FIG. 3). In the center of this hole diameter setting layer 14, for example, a through hole 14H is provided which penetrates from the front surface 14Sf to the back surface 14Sr. The through hole 14H has, for example, a circular or elliptical planar (XY plane) shape. The hole size (diameter) of the through hole 14H is, for example, 5 μm to 50 μm. By providing the through hole 14H of this size, a connection hole V21 which achieves both electrical characteristics and connection reliability can be formed.

[0063] The pore diameter setting layer 14 has an inner wall 14Wi along the through hole 14H and an outer wall 14Wo along the outer edge of the pore diameter setting layer 14. The inner wall 14Wi and the outer wall 14Wo are provided in a direction intersecting the front surface 14Sf and the back surface 14Sr. The outer wall 14Wo is covered with an adhesive layer 151. The adhesive layer 151 has a step s with the front surface 14Sf around the front surface 14Sf. For example, the adhesive layer 151 around the front surface 14Sf protrudes from the front surface 14Sf.

[0064] The connection hole V21 reaches the first terminal electrode 1611 from the inner wall 14Wi of the hole diameter setting layer 14 through the adhesive layer 151. In other words, the connection hole V21 is formed in the adhesive layer 151 according to the shape of the inner wall 14Wi of the hole diameter setting layer 14. Therefore, the hole diameter of the connection hole V21 can be made smaller by adjusting the hole diameter of the through hole 14H formed in the hole diameter setting layer 14. The hole diameter (diameter) of the connection hole V21 is, for example, 5 μm to 50 μm.

[0065] The diameter of the connection hole V21 gradually decreases, for example, from the back surface 14Sr toward the first terminal electrode 1611. That is, the connection hole 21V has a tapered shape. The maximum diameter of the connection hole V21 is, for example, larger than the maximum diameter of the hole diameter setting layer 14. The maximum diameter (outer diameter) of the connection hole V21 is, for example, approximately 1 μm to 20 μm larger than the maximum diameter of the through hole 14H. The diameter of the connection hole V21 is largest, for example, in the vicinity of the back surface 14Sr. The connection hole V21 having such a shape is formed, for example, by laser irradiation.

[0066] In the connection hole V21, for example, a seed layer 19 is provided together with the first conductor layer 13. The seed layer 19 is provided along the inner wall 14Wi and the wall surface of the connection hole V21. The first conductor layer 13 is electrically connected to the first terminal electrode 1611 via the seed layer 19.

[0067] The seed layer 19 includes, for example, an adhesive film 191 and a conductive film 192. The adhesive film 191 and the conductive film 192 each include, for example, a conductive metal material such as gold, platinum, palladium, silver, copper, aluminum, cobalt, titanium, chromium, nickel, tungsten, iron, tin, indium, or zinc. The adhesive film 191 and the conductive film 192 preferably include at least one of copper, aluminum, titanium, and chromium. The adhesive film 191 preferably includes titanium, and the conductive film 192 preferably includes copper. This allows the adhesion of the seed layer 19 to be maintained and the thickness to be suppressed. The surface 14Sf and the inner wall 14Wi of the hole diameter setting layer 14 are covered with, for example, the seed layer 19.

[0068] The thickness (size in the Z direction) of the hole diameter setting layer 14 is, for example, 2 μm to 10 μm. The hole diameter setting layer 14 contains, for example, a conductive metal such as copper. The hole diameter setting layer 14 is preferably formed using an electrolytic plating method. That is, the hole diameter setting layer 14 preferably contains a plating film. This makes it possible to easily control the hole diameter of the through hole 14H and easily form a connection hole V21 with a desired hole diameter.

[0069] (Electronic device manufacturing method) Next, an example of a method for manufacturing an electronic device will be described with reference to FIGS.

[0070] First, the support substrate 100 is prepared (FIG. 4). The support substrate 100 includes, for example, a support 101, a first adhesive layer 102, a second adhesive layer 103, a release layer 104, a first seed layer 105, and a second seed layer 106. The support 101 is formed of, for example, a plate-like member including at least one of glass, silicon (Si), SUS (Stainless Used Steel), ferrite, alumina, and prepreg. In terms of thermal expansion coefficient and surface smoothness, it is preferable that the support 101 includes glass. In the support substrate 100, the first adhesive layer 102, the second adhesive layer 103, the release layer 104, the first seed layer 105, and the second seed layer 106 are laminated on the support 101 in this order.

[0071] The first adhesive layer 102, the second adhesive layer 103, the first seed layer 105, and the second seed layer 106 contain a conductive metal such as gold, platinum, palladium, silver, copper, aluminum, cobalt, titanium, chromium, nickel, tungsten, iron, tin, indium, or zinc. In terms of adhesion between layers, the first adhesive layer 102 and the first seed layer 105 preferably contain titanium. In terms of conductivity and cost, the second adhesive layer 103 and the second seed layer 106 preferably contain copper. The release layer 104 contains, for example, an inorganic material and copper. The first adhesive layer 102, the second adhesive layer 103, the first seed layer 105, and the second seed layer 106 are formed, for example, by a metal foil pressing method, a plating method, a sputtering method, or the like. The support substrate 100 is, for example, made of HRDP (registered trademark, High Resolution De-bondable Panel).

[0072] Next, a resist film 107 is provided on the second seed layer 106, and an opening 107M is formed in this resist film 107 (FIG. 5). The opening 107M is formed, for example, in a ring shape (see FIG. 3). The opening 107M is formed, for example, by using a photolithography method.

[0073] After forming an opening 107M in the resist film 107, the pore diameter setting layer 14 is formed using this opening 107M (FIG. 6). The pore diameter setting layer 14 is formed, for example, by electrolytic plating to grow copper in the opening 107M. An electric charge is supplied to the first seed layer 105 and the second seed layer 106 through the opening 107M, and a metal such as copper is plated and grown. This forms the pore diameter setting layer 14 having through holes 14H. After the pore diameter setting layer 14 is formed, the resist film 107 is removed.

[0074] Next, the electronic components 161, 162 are mounted on the supporting substrate 100 so that the main surface of the supporting substrate 100 faces the first terminal surfaces 161Sa, 162Sa (FIG. 7). That is, the electronic components 161, 162 are mounted on the supporting substrate 100 by a face-down method. This makes it possible to easily mount a plurality of electronic components 161, 162 having different thicknesses. Also, it becomes possible to improve alignment accuracy.

[0075] In the mounting process of the electronic components 161, 162, the first terminal electrodes 1611, 1621 are disposed at positions facing the hole diameter defining layer 14. The electronic components 161, 162 are adhered onto the support substrate 100 using the adhesive layers 151, 152. The adhesive layers 151, 152 may be provided on the first terminal surfaces 161Sa, 162Sa of the electronic components 161, 162, or may be provided on the support substrate 100 (more specifically, on the second seed layer 106). The adhesive layers 151, 152 may be in any shape, such as a paste or a film, but it is preferable to use the adhesive layers 151, 152 in a paste form, for example.

[0076] After mounting the electronic components 161 and 162 on the support substrate 100, the second insulating layer 23 is formed on the support substrate 100 (FIG. 8). At this time, the second insulating layer 23 is formed with connection holes V31 and V32 that reach the second terminal electrodes 1612 and 1622 of the electronic components 161 and 162 from the surface of the second insulating layer 23 and a connection hole V33 that penetrates the second insulating layer 23 in the thickness direction. The second insulating layer 23 is formed by providing an organic insulating material on the support substrate 100 using, for example, a film lamination method or a spin coating method. By forming the second insulating layer 23 using the film lamination method, the second insulating layer 23 with high surface flatness can be formed. The connection holes V31, V32, and V33 are formed using laser processing, photolithography, or the like after the second insulating layer 23 is formed.

[0077] After the connection holes V31, V32, and V33 are formed in the second insulating layer 23, the second conductor layer 17 is formed on the second insulating layer 23 and in the connection holes V31, V32, and V33 (FIG. 9). The second conductor layer 17 is formed, for example, by using a semi-additive process.

[0078] The semi-additive process is performed, for example, as follows. First, a seed layer 19A is formed on the second insulating layer 23 and in the connection holes V31, V32, and V33. The seed layer 19A includes, for example, an adhesive film 193 and a conductive film 194. For example, after the adhesive film 193 is formed, the conductive film 194 is formed. The adhesive film 193 and the conductive film 194 include, for example, a conductive metal material such as titanium, aluminum, and copper. The adhesive film 193 preferably includes titanium, and the conductive film 194 preferably includes copper. The seed layer 19A is formed, for example, by using an electroless plating method, a sputtering method, a CVD (chemical vapor deposition) method, an ALD (atomic layer deposition) method, or the like. The seed layer 19A is preferably formed by using a sputtering method. After the seed layer 19A is formed, a resist film is formed, and an opening is formed in the resist film. A conductive metal material is plated and grown in the opening of the resist film. As a result, the second conductor layer 17 is formed in the opening of the resist film. Thereafter, the resist film is removed. The seed layer 19A exposed from the second conductor layer 17 is removed by, for example, an etching method.

[0079] After forming the second conductor layer 17, the second solder resist layer 24 and the second board electrode 18 are formed in this order (FIG. 10). For example, the second solder resist layer 24 is formed on the second insulating layer 23 so as to cover the second conductor layer 17, and then an opening is formed in the second solder resist layer 24. The opening in the second solder resist layer 24 is formed at a position corresponding to the second conductor layer 17. The second solder resist layer 24 is formed by using, for example, a photolithography method or a printing method. The second board electrode 18 is formed in the opening in the second solder resist layer 24. The second board electrode 18 is formed by using, for example, an electroless plating method or an electrolytic plating method.

[0080] After the second substrate electrode 18 is formed, the support 201 is bonded to the second solder resist layer 24 via the release layer 204 (FIG. 11). The support 201 is, for example, a plate-like member, and is made of the same material as the support 101. The support 201 includes, for example, glass. The release layer 204 includes, for example, epoxy resin or acrylic resin. A metal film including titanium, copper, nickel, or the like may be provided between the second solder resist layer 24 and the release layer 204. For example, after the support 201 is bonded to the second solder resist layer 24, the support 101 is removed. For example, the release layer 104 is irradiated with a laser or UV (ultraviolet) to peel off the release layer 104 and the support 101 from the first seed layer 105. For example, the support 101 may be peeled off by reducing the adhesive force between the release layer 104 and the first seed layer 105 using a chemical reaction with a chemical. Alternatively, a physical force may be applied to the support 101 to cause it to peel off.

[0081] After removing the support 101, the first seed layer 105 and the second seed layer 106 are removed (FIGS. 12A and 12B). The first seed layer 105 and the second seed layer 106 are removed, for example, by a chemical etching method using a chemical.

[0082] Fig. 12A shows a process after removing the first seed layer 105 and the second seed layer 106, and Fig. 12B shows an enlarged view of the vicinity of the pore diameter setting layer 14 shown in Fig. 12A. In the process of removing the first seed layer 105 and the second seed layer 106, a step is formed between the surface 14Sf and the adhesive layer 151 around the surface 14Sf of the pore diameter setting layer 14.

[0083] After removing the first seed layer 105 and the second seed layer 106, the connection holes V21, V22 are formed (FIG. 13). The connection holes V21, V22 are formed, for example, by removing the adhesive layers 151, 152 along the inner wall 14Wi of the hole diameter setting layer 14 until the first terminal electrodes 1611, 1621 are reached. Here, since the hole diameter setting layer 14 functions as a mask, the hole diameter of the connection holes V21, V22 is unlikely to widen. Therefore, the connection holes V21, V22 having a smaller hole diameter can be formed. The connection holes V21, V22 are formed, for example, by plasma irradiation or laser irradiation. The connection holes V21, V22 are formed by ionizing the material with carbon dioxide gas (CO 2 It is preferable that the thin film is formed by laser irradiation. After the laser irradiation, for example, a desmear process is performed.

[0084] Next, the first conductor layer 13 is formed on the second insulating layer 23 (FIG. 14). For example, the first conductor layer 13 is formed in the connection holes V21, V22, and also in a position corresponding to the connection hole V33. The first conductor layer 13 can be formed, for example, by a method similar to that of the second conductor layer 17. Specifically, after forming the seed layer 19 (FIG. 2), the first conductor layer 13 is formed by using an electrolytic plating method. The seed layer 19 is formed, for example, by using an electroless plating method, a sputtering method, a CVD method, an ALD method, or the like. It is desirable to form the seed layer 19 by using a sputtering method.

[0085] After forming the first conductor layer 13, the first insulating layer 22 is formed on the second insulating layer 23 so as to cover the first conductor layer 13 (FIG. 15). At this time, a connection hole V1 is formed in the first insulating layer 22, which extends from the surface of the first insulating layer 22 to the first conductor layer 13. The first insulating layer 22 and the connection hole V1 can be formed in the same manner as the second insulating layer 23 and the connection holes V31, V32, V33.

[0086] Next, the relay conductor layer 12 is formed on the first insulating layer 22 (FIG. 16). At this time, the relay conductor layer 12 and the inside of the connection hole V1 are connected. The relay conductor layer 12 can be formed, for example, by a method similar to that for the second conductor layer 17. Specifically, after forming a seed layer, the relay conductor layer 12 is formed by using an electrolytic plating method.

[0087] Next, the first solder resist layer 21 and the first substrate electrode 11 are formed in this order (FIG. 17). This forms the electronic component built-in module 10. The first solder resist layer 21 and the first substrate electrode 11 can be formed in the same manner as the second solder resist layer 24 and the second substrate electrode 18.

[0088] Next, the semiconductor elements 31, 32 are mounted on the electronic component built-in module 10 (FIG. 18). At this time, the electrodes 311, 321 of the semiconductor elements 31, 32 are electrically connected to the first substrate electrodes 11 of the electronic component built-in module 10 via bumps 35. An underfill material 34 is formed between the semiconductor elements 31, 32 and the electronic component built-in module 10.

[0089] Next, sealing layer 33 is formed so as to cover semiconductor elements 31 and 32 (FIG. 19). For example, the thickness of sealing layer 33 may be adjusted by polishing or the like.

[0090] Next, the support 201 is removed (FIG. 20). For example, the support 201 is removed by peeling it off from the electronic component built-in module 10. The support 201 can be removed using a method similar to that used for removing the support 101.

[0091] Thereafter, the mounting substrate 40 is connected to the electronic component built-in module 10. For example, the electrodes 43 of the mounting substrate 40 and the second substrate electrodes 18 of the electronic component built-in module 10 are electrically connected via bumps 45. For example, in this manner, an electronic device can be manufactured.

[0092] (Effects of the Electronic Component Built-in Module 10) The electronic component built-in module 10 of this embodiment is provided with a hole diameter setting layer 14 having an inner wall 14Wi. The inner wall 14Wi of this hole diameter setting layer 14 is used to form the connection holes V21, V22 in the adhesive layers 151, 152. This allows the connection holes V21, V22 to be formed according to the shape of the inner wall 14Wi of the hole diameter setting layer 14. For example, when the hole diameter of the through hole 14H of the hole diameter setting layer 14 is 5 μm, the connection holes V21, V22 having a hole diameter of about 5 μm can be formed. This allows the hole diameter of the connection holes V21, V22 to be made smaller.

[0093] Furthermore, in the electronic component built-in module 10, the hole diameter defining layer 14 is formed before forming the adhesive layers 151 and 152. This makes it possible to reduce the thickness of the electronic component built-in module 10. Furthermore, the surface flatness of the first insulating layer 22 can be maintained, and thin wires can be formed.

[0094] Moreover, in the electronic component built-in module 10, the hole diameter setting layer 14 is formed by electrolytic plating. This makes it easier to accurately control the hole diameter of the through hole 14H, that is, the shape of the inner wall 14Wi, and allows the connection holes V21, V22 of the desired hole diameter to be formed. For example, a method of forming a connection hole using copper foil formed on the entire surface of the insulating layer is also conceivable. At this time, for example, an etching method is used to form an opening in the copper foil. A connection hole is formed in the adhesive layer through this opening in the copper foil. However, in this method, since the opening is formed in the copper foil by etching, the opening tends to widen, and it is difficult to control the size of the opening. Therefore, the hole diameter of the connection hole is also large. In contrast, by forming the hole diameter setting layer 14 by electrolytic plating, the shape of the inner wall 14Wi can be accurately controlled. Therefore, it is possible to form the connection holes V21, V22 with a smaller hole diameter.

[0095] Furthermore, the copper foil is thick and has a large surface roughness. The thickness of the copper foil is, for example, 5 μm, and the surface roughness of the copper foil is, for example, Rz 1 μm or more. In an electronic component built-in module having such a copper foil, it is difficult to form thin wires. In contrast, in electronic component built-in module 10 of this embodiment, the formation of copper foil is not necessary. Therefore, it is possible to form thin wires with an L (line) / S (space) of about 2 / 2 μm.

[0096] As described above, in the electronic component built-in module 10 of this embodiment, the connection holes V21, V22 are formed in the adhesive layers 151, 152 by utilizing the inner wall 14Wi of the hole diameter setting layer 14. This makes it possible to form the connection holes V21, V22 according to the shape of the inner wall 14Wi of the hole diameter setting layer 14. This makes it possible to further reduce the hole diameters of the connection holes V21, V22.

[0097] The following describes a modified example of the electronic component built-in module 10 according to the above embodiment. In order to avoid duplication of explanation, detailed explanation of the same configuration as that of the electronic component built-in module 10 according to the above embodiment will be omitted.

[0098] <Modification> Fig. 21 shows an example of the configuration in the vicinity of the pore diameter setting layer 14 of an electronic component built-in module 10 according to a modified example. Fig. 21 corresponds to Fig. 2 showing the electronic component built-in module 10 of the above embodiment. This electronic component built-in module 10 has a first seed layer 105 and a second seed layer 106 in this order from the surface 14Sf side on the surface 14Sf of the pore diameter setting layer 14. Except for this, the electronic component built-in module 10 according to the modified example has the same configuration as the electronic component built-in module 10 described in the above embodiment. Here, the first seed layer 105 and the second seed layer 106 correspond to a specific example of a metal film of the present invention.

[0099] The first seed layer 105 has an opening 105M, and the second seed layer 106 has an opening 106M. The openings 105M and 106M are provided penetrating the first seed layer 105 and the second seed layer 106 in the thickness direction (Z direction). The openings 105M and 106M are provided at positions overlapping the through holes 14H of the hole diameter setting layer 14 in a planar (XY) view. The openings 105M and 106M have approximately the same diameter as the hole diameter (diameter) of the through holes 14H. The first seed layer 105 and the second seed layer 106 preferably contain at least one of copper, titanium, and chromium. The first seed layer 105 preferably contains titanium, and the second seed layer 106 preferably contains copper. The first seed layer 105 and the second seed layer 106 each have a thickness of, for example, 0.05 μm to 5 μm. The thicknesses of the first seed layer 105 and the second seed layer 106 are smaller than the thickness of the pore diameter setting layer 14 .

[0100] The first seed layer 105 and the second seed layer 106 are formed, for example, as follows. First, in the same manner as described in the above embodiment, the support 201 is attached to the second solder resist layer 24, and then the support 101 is removed (FIG. 11). Thereafter, the connection holes V21 and V22 are formed without removing the first seed layer 105 and the second seed layer 106. As a result, the openings 105M and 106M are formed in the first seed layer 105 and the second seed layer 106. In other words, the connection holes V21 and V22 are formed from the openings 105M and 106M to the first terminal electrodes 1611 and 1621 through the inner wall 14Wi of the hole diameter setting layer 14 and the adhesive layers 151 and 152. At this time, for example, a step (step s in FIG. 2) between the surface 14Sf and the adhesive layers 151 and 152 is not formed around the surface 14Sf of the hole diameter setting layer 14. The surface 14Sf is provided, for example, on approximately the same plane as the surfaces of the adhesive layers 151 and 152.

[0101] In the electronic component built-in module 10 according to the modified example, the connection holes V21, V22 are formed in the adhesive layers 151, 152 by utilizing the inner wall 14Wi of the hole diameter setting layer 14. This makes it possible to form the connection holes V21, V22 according to the shape of the inner wall 14Wi of the hole diameter setting layer 14. This makes it possible to further reduce the hole diameters of the connection holes V21, V22.

[0102] Furthermore, in this electronic component built-in module 10, the process of removing the first seed layer 105 and the second seed layer 106 is not necessary. This reduces the number of manufacturing processes, making it possible to improve yields. Furthermore, the first seed layer 105 and the second seed layer 106 contain a metal material such as copper, titanium, or chromium. This increases the thermal conductivity in the vicinity of the connection holes V21 and V22, thereby improving the heat dissipation of the electronic component built-in module 10.

[0103] <Other Modifications> 22 to 24 show examples of the configuration of the electronic component built-in module 10 according to other modified examples.

[0104] The electronic component built-in module 10 may have one built-in electronic component (electronic component 163) (FIGS. 22 and 23). This electronic component 163 may have only a first terminal surface 163Sa having a first terminal electrode 1631 (FIG. 22). The electronic component 163 may further have a second terminal surface 163Sb facing the first terminal surface 163Sa in the Z direction (FIG. 23). A second terminal electrode 1632 is provided on this second terminal surface 163Sb.

[0105] The electronic component built-in module 10 may have multiple built-in electronic components (electronic components 163, 164) (FIG. 24). The electronic components 163, 164 may have only first terminal surfaces 163Sa, 164Sa having first terminal electrodes 1631, 1641 (FIG. 24). Since the electronic components do not have second terminal surfaces (for example, second terminal surfaces 161Sb, 162Sb in FIG. 1), the manufacturing process of the electronic component built-in module 10 can be simplified. In addition, the yield of the electronic component built-in module 10 can be improved.

[0106] 1 and 24 show an example in which the electronic component built-in module 10 has two electronic components (electronic components 161 and 162 or electronic components 163 and 164). The electronic component built-in module 10 may have three or more electronic components.

[0107] 3 illustrates an example in which the pore diameter setting layer 14 and the through-hole 14H have a circular or elliptical planar shape. The pore diameter setting layer 14 and the through-hole 14H may have other planar shapes. For example, they may have a polygonal planar shape. The planar shape of the pore diameter setting layer 14 and the planar shape of the through-hole 14H may be different.

[0108] 1 and the like shows an example in which one connection hole V21, V22 is provided in one first terminal electrode 1611, 1621. A plurality of connection holes V21, V22 may be provided in one first terminal electrode 1611, 1621. The electronic component built-in module 10 may have a plurality of hole diameter defining layers 14 arranged along the Z direction, for example.

[0109] 4 to 20 show an example of a manufacturing process for the electronic component built-in module 10, but the electronic component built-in module 10 may be manufactured through processes different from the above. Other known methods may be used to form each member.

[0110] The above-described configuration of the electronic component built-in module 10 is a main configuration described in order to explain the features of the above-described embodiment, but is not limited to the above-described configuration and may be modified in various ways within the scope of the claims. Furthermore, configurations that are included in general electronic component built-in modules are not excluded. [Explanation of symbols]

[0111] 10 Modules with built-in electronic components, 11 first substrate electrode, 12 relay conductor layer, 13 first conductor layer, 14 Pore size defined layer, 14Sf surface, 14Sr back side, 14Wi inner wall, 14Wo exterior wall, 14H through hole, 151,152 adhesive layer, 161,162,163,164 Electronic components, 17 second conductor layer, 18 second substrate electrode, 19,19A seed layer, 21 first solder resist layer, 22 first insulating layer, 23 second insulating layer, 24 second solder resist layer, 31, 32 Semiconductor elements, 33 sealing layer, 34 Underfill material, 35,45 bump, 40 mounting board, 41 Base material, 42 wiring layer, 43 electrodes, 44 Solder resist layer.

Claims

1. A pore size defining layer; Electronic components, An electronic component built-in module comprising at least an insulating layer, the pore diameter defining layer has an inner wall, an outer wall, a surface intersecting the inner wall and the outer wall, and a back surface opposite to the surface; the electronic component has a first terminal surface facing the back surface and a first terminal electrode provided on the first terminal surface, the insulating layer is provided between the first terminal surface and the back surface, covers the outer wall, and has a step between the front surface and the outer wall around the front surface; The electronic component built-in module further includes a connection hole extending from the inner wall through the insulating layer to the first terminal electrode.

2. The electronic component built-in module according to claim 1 , wherein the insulating layer around the surface protrudes from the surface.

3. A pore size defining layer; A metal film; Electronic components, An electronic component built-in module comprising at least an insulating layer, the pore diameter defining layer has an inner wall, an outer wall, a surface intersecting the inner wall and the outer wall, and a back surface opposite to the surface; the electronic component has a first terminal surface facing the back surface and a first terminal electrode provided on the first terminal surface, the insulating layer is provided between the first terminal surface and the back surface and covers the outer wall; the metal film is provided on the surface and has an opening; The electronic component built-in module further includes a connection hole extending from the opening through the inner wall and the insulating layer to the first terminal electrode.

4. 4. The electronic component built-in module according to claim 3, wherein the metal film contains at least one of copper (Cu), titanium (Ti) and chromium (Cr).

5. 5. The electronic component built-in module according to claim 1, wherein the pore diameter defining layer contains at least copper.

6. a seed layer provided in the contact hole; a first conductor layer electrically connected to the first terminal electrode via the seed layer; 5. The electronic component built-in module according to claim 1, further comprising:

7. the seed layer includes an adhesive film and a conductive film provided between the adhesive film and the first conductor layer, 7. The electronic component built-in module according to claim 6, wherein the adhesive film and the conductive film contain at least one of copper, aluminum (Al), titanium, and chromium.

8. The electronic component built-in module further includes a second conductor layer, the electronic component further includes a second terminal surface facing the first terminal surface, and a second terminal electrode provided on the second terminal surface; The electronic component built-in module according to claim 6 , wherein the second terminal electrode is electrically connected to the second conductor layer.

9. 5. The electronic component built-in module according to claim 1, wherein the connection hole has a tapered shape.

10. the pore diameter defining layer has a through hole penetrating from the front surface to the back surface, 5. The electronic component built-in module according to claim 1, wherein the through hole is provided with the inner wall.

11. The electronic component built-in module according to claim 10 , wherein the through hole has a circular or elliptical planar shape.

12. The electronic component built-in module according to claim 10 , wherein the maximum hole diameter of the connection hole is larger than the maximum hole diameter of the through hole.

13. 5. The electronic component built-in module according to claim 1, wherein the hole diameter defining layer includes a plating film.

14. 5. The electronic component built-in module according to claim 1, comprising a plurality of said electronic components.

15. The electronic component built-in module according to claim 14 , wherein the plurality of electronic components include electronic components having thicknesses different from one another.

16. 5. The electronic component built-in module according to claim 1, wherein the insulating layer contains an organic insulating material.

17. (a) forming a pore size defining layer having an inner wall on a supporting substrate; (b) providing an adhesive layer covering the pore diameter defining layer on the supporting substrate; a step (c) of attaching an electronic component having a terminal electrode on a terminal surface to the supporting substrate via the adhesive layer such that the terminal surface faces the supporting substrate; a step (d) of removing the support substrate after the electronic component is bonded to the support substrate; a step (e) of forming a connection hole extending from the inner wall through the adhesive layer to the terminal electrode; (f) forming a seed layer in the contact hole; a step (g) of electrically connecting the conductor layer and the terminal electrode via the seed layer; A method for manufacturing an electronic component-embedded module comprising:

18. 18. The method for manufacturing an electronic component built-in module according to claim 17, wherein in the step (f), the seed layer is formed in the connection hole by using a sputtering method.

19. 18. The method for producing an electronic component built-in module according to claim 17, wherein in the step (a), the hole diameter defining layer is formed on the supporting substrate by using an electrolytic plating method.

20. The method for manufacturing an electronic component built-in module according to claim 17 , wherein the support substrate includes glass.

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