Memory system and memory device

Abstract

To provide a memory system and a memory device with high reliability.SOLUTION: A memory system of the embodiment includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to determine a first voltage based on information regarding a gradient of a distribution of threshold voltages of each of the plurality of memory cells, and to perform tracking operations. The memory controller causes the memory device to perform a plurality of read operations using a plurality of read levels for the plurality of memory cells in the tracking operation. The memory controller acquires the number of ON cells in each of the plurality of read operations. The memory controller sets a first potential difference of the plurality of read levels in a voltage range lower than the first voltage and a second potential difference of the plurality of read levels in a voltage range higher than the first voltage to be different from each other.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The embodiments relate to a memory system and a memory device. [Background technology]

[0002] 2. Description of the Related Art NAND flash memories capable of storing data in a non-volatile manner are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-168813 A [Patent Document 2] US Patent Application Publication No. 2022 / 0100413 [Patent Document 3] US Patent Application Publication No. 2022 / 0262450 Summary of the Invention [Problem to be solved by the invention]

[0004] At least one embodiment provides a reliable memory system and memory device. [Means for solving the problem]

[0005] A memory system according to an embodiment includes a memory device and a memory controller. The memory device includes a plurality of memory cells configured to non-volatilely store data including at least a first value and a second value according to a threshold voltage. The first value corresponds to a threshold voltage included in a first voltage range. The second value corresponds to a threshold voltage included in a second voltage range different from the first voltage range. The memory controller is configured to write data of the first value to each of a plurality of first memory cells among the plurality of memory cells, write data of the second value to each of a plurality of second memory cells among the plurality of memory cells, determine the first voltage based on information regarding a gradient of a distribution of the threshold voltages of each of the plurality of memory cells, and perform a tracking operation. The memory controller is configured to cause the memory device to perform a plurality of read operations using a plurality of read levels in a third voltage range including at least a portion of the first voltage range and at least a portion of the second voltage range, for the plurality of memory cells in the tracking operation, and obtain the number of on cells, which are memory cells that are in an on state among the plurality of memory cells, in each of the plurality of read operations. The memory controller is further configured to set, in the tracking operation, a first potential difference between two adjacent read levels of the plurality of read levels in a fourth voltage range lower than the first voltage of the third voltage range and a second potential difference between two adjacent read levels of the plurality of read levels in a fifth voltage range higher than the first voltage of the third voltage range to be different from each other. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of the configuration of a memory system according to a first embodiment. [Diagram 2] FIG. 2 is a block diagram showing an example of a hardware configuration of a memory controller included in the memory system according to the first embodiment. [Diagram 3] FIG. 2 is a block diagram showing an example of a hardware configuration of a memory device included in the memory system according to the first embodiment. [Figure 4]1 is a diagram showing an example of a circuit configuration of a memory cell array included in a memory system according to a first embodiment. [Diagram 5] 2 is a diagram showing an example of a circuit configuration of a row decoder module included in the memory system according to the first embodiment. [Figure 6] 2 is a diagram showing an example of a circuit configuration of a sense amplifier module and a data register included in the memory system according to the first embodiment. [Figure 7] 4A and 4B are diagrams showing an example of threshold voltage distributions and data allocations of memory cell transistors in the memory system according to the first embodiment. [Figure 8] 4 is a schematic diagram showing an example of fail bit counts occurring in adjacent states in the memory system according to the first embodiment. [Figure 9] 3 is a schematic diagram showing an example of symmetric threshold voltage distributions of adjacent states in the memory system according to the first embodiment. [Figure 10] 4 is a schematic diagram showing an example of asymmetric threshold voltage distributions of adjacent states in the memory system according to the first embodiment. [Figure 11] FIG. 4 is a schematic diagram showing an example of a more detailed threshold voltage distribution of a memory cell transistor according to the first embodiment. [Figure 12] 1 is a flowchart showing an example of a Vth tracking procedure executed in the memory system according to the first embodiment. [Figure 13] 5 is a schematic diagram showing an example of a method for setting a step value used in Vth tracking performed in the memory system according to the first embodiment. [Figure 14] 11 is a schematic diagram showing another example of the method for setting a step value used in Vth tracking executed in the memory system according to the first embodiment. FIG. [Figure 15] FIG. 11 is a block diagram showing an example of a functional configuration of a memory system according to a second embodiment. [Figure 16] FIG. 11 is a diagram showing an example of a start value table included in the memory system according to the second embodiment. [Figure 17] FIG. 11 is a diagram showing an example of a step value table included in the memory system according to the second embodiment. [Figure 18] 10 is a flowchart showing an example of a Vth tracking procedure executed in a memory system according to a second embodiment. [Figure 19] FIG. 11 is a schematic diagram showing a specific example of a part of Vth tracking processing executed in the memory system according to the second embodiment. [Figure 20] 10 is a table showing an example of a command sequence used in a memory system according to a second embodiment. [Figure 21] 10 is a flowchart showing an example of a procedure of a modified example of Vth tracking executed in a memory system according to the second embodiment. [Figure 22] FIG. 11 is a block diagram showing an example of the functional configuration of a memory system according to a third embodiment. [Figure 23] 13 is a flowchart showing an example of a procedure for setting initial parameters for Vth tracking executed in a memory system according to a third embodiment. [Figure 24] FIG. 13 is a block diagram showing an example of the functional configuration of a memory system according to a fourth embodiment. [Diagram 25] FIG. 13 is a diagram showing an example of a step value table included in the memory system according to the fourth embodiment. [Figure 26] 13 is a flowchart showing an example of a Vth tracking procedure executed in a memory system according to a fourth embodiment. [Figure 27] 13 is a flowchart showing an example of a detailed procedure of a part of a process of Vth tracking executed in a memory system according to a fourth embodiment. [Figure 28] 13 is a flowchart showing an example of a detailed procedure of another part of Vth tracking processing executed in the memory system according to the fourth embodiment. [Figure 29] 13 is a flowchart showing an example of detailed procedures of still another part of Vth tracking processing executed in the memory system according to the fourth embodiment. [Diagram 30] 13 is a table showing an example of a command sequence used in the memory system according to the fourth embodiment. [Diagram 31] 13 is a diagram showing a specific example of voltages applied to word lines in a search read in the memory system according to the fourth embodiment. [Diagram 32] 13 is a schematic diagram showing a specific example of a process for determining an optimum read level in a search read in a memory system according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Each embodiment will be described below with reference to the drawings. Each embodiment illustrates an apparatus or method for embodying the technical idea of ​​the invention. The drawings are schematic or conceptual. The illustration of the configuration is omitted as appropriate. The same reference numerals are attached to components having substantially the same functions and configurations. Numbers and the like added to the reference numerals are used to refer to the same reference numerals and to distinguish between similar elements.

[0008] <1> First embodiment The first embodiment relates to a memory system MS using a NAND type flash memory capable of storing data in a non-volatile manner. The memory system MS according to the first embodiment is configured to perform Vth tracking in which a plurality of different step sizes can be set. Details of the memory system MS according to the first embodiment will be described below.

[0009] <1-1> Configuration First, the configuration of the memory system MS according to the first embodiment will be described.

[0010] <1-1-1> Memory system MS configuration FIG. 1 is a block diagram showing an example of a configuration of a memory system MS according to the first embodiment. As shown in FIG. 1, the memory system MS can be connected to an external host device HD (also called a host). The host device HD is an electronic device such as a personal computer, a personal digital assistant, or a server. The memory system MS is a storage device such as a memory card or an SSD (solid state drive). The memory system MS includes, for example, a memory controller 1 and at least one memory device 2.

[0011] The memory controller 1 is a semiconductor integrated circuit configured as, for example, a SoC (System On a Chip), an ASIC (Application Specific Integrated Circuit), or an FPGA (Field-Programmable Gate Array). The memory controller 1 has a function of managing and controlling the memory device 2. The memory controller 1 is connected to a host device HD via a host bus HB. The memory controller 1 is connected to the memory device 2 via a memory bus MB. The memory controller 1 can control the memory device 2 based on an instruction received from the host device HD. For example, the memory controller 1 can control the memory device 2 to perform a read operation, a write operation, an erase operation, etc.

[0012] The memory device 2 is a semiconductor memory device configured to store data in a non-volatile manner. The memory device 2 is, for example, a NAND type flash memory. In the NAND type flash memory, a unit of data read operation and write operation is called a page. The memory device 2 includes a plurality of memory cell transistors MT, a plurality of bit lines BL, and a plurality of word lines WL. For example, each memory cell transistor MT is associated with one bit line BL and one word line WL. A column address is assigned to each bit line BL. A page address is assigned to each word line WL.

[0013] The memory controller 1 and at least one memory device 2 may be configured as one semiconductor device.

[0014] <1-1-2> Hardware configuration of memory controller 1 Fig. 2 is a block diagram showing an example of a hardware configuration of a memory controller 1 included in a memory system MS according to the first embodiment. As shown in Fig. 2, the memory controller 1 includes, for example, a host interface circuit (host I / F) 10, a memory interface circuit (memory I / F) 11, a CPU (Central Processing Unit) 12, an ECC (Error Correction Code) circuit 13, a ROM (Read Only Memory) 14, a RAM (Random Access Memory) 15, and a buffer memory 16. The host I / F 10, the memory I / F 11, the CPU 12, the ECC circuit 13, the ROM 14, the RAM 15, and the buffer memory 16 may be connected to an internal bus.

[0015] The host I / F 10 controls communication between the host device HD and the memory controller 1 in accordance with an interface standard. The host I / F 10 is connected to the host device HD via a host bus HB. The host I / F 10 supports, for example, SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), PCIe TM (PCI Express), NVMe TM (Non-Volatile Memory Express TM ) interface standards.

[0016] The memory I / F 11 controls communication between the memory controller 1 and the memory device 2 in accordance with an interface standard. The memory I / F 11 is connected to the memory device 2 via a memory bus MB. The memory I / F 11 supports interface standards such as Toggle DDR and ONFI (Open NAND Flash Interface).

[0017] The CPU 12 is a processor that controls the overall operation of the memory controller 1. The CPU 12 instructs the memory device 2 to perform a data write operation via the memory I / F 11 in accordance with a write request received via the host I / F 10. The CPU 12 instructs the memory device 2 to perform a data read operation via the memory I / F 11 in accordance with a read request received via the host I / F 10.

[0018] The ECC circuit 13 is a circuit that executes ECC processing. The ECC processing includes encoding and decoding of data. The ECC circuit 13 encodes data to be written to the memory device 2 and decodes data read from the memory device 2.

[0019] The ROM 14 is a non-volatile memory. The ROM 14 stores programs such as firmware. The ROM 14 is, for example, an EEPROM. TM (Electrically Erasable Programmable Read-Only Memory). The CPU 12 executes firmware stored in the ROM 14 or the like to perform various processes.

[0020] The RAM 15 is a volatile memory. The RAM 15 is used as a working area for the CPU 12. The RAM 15 is, for example, a static random access memory (SRAM) or a dynamic random access memory (DRAM).

[0021] The buffer memory 16 is, for example, a volatile memory. The buffer memory 16 temporarily stores data received via the host I / F 10, data received via the memory I / F 11, etc. The buffer memory 16 is, for example, a DRAM or an SRAM. The buffer memory 16 may be implemented outside the memory controller 1.

[0022] <1-1-3> Hardware configuration of memory device 2 Fig. 3 is a block diagram showing an example of a configuration of a memory device 2 included in a memory system MS according to the first embodiment. As shown in Fig. 3, the memory device 2 includes, for example, a memory cell array 20, an input / output circuit 21, a logic controller 22, a register circuit 23, a sequencer 24, a ready-busy controller 25, a driver circuit 26, a row decoder module 27, a data register 28, and a sense amplifier module 29. Signals transmitted and received via the memory bus MB include, for example, input / output signals I / O0 to I / O7, control signals CEn, CLE, ALE, WEn, REn, and WPn, and a ready-busy signal RBn.

[0023] The memory cell array 20 is a set of multiple memory cell transistors MT. The memory cell array 20 includes multiple blocks BLK0 to BLKn ("n" is an integer equal to or greater than 1). The block BLK is, for example, a unit of data erase operation. A block address is assigned to each block BLK. The memory cell array 20 is provided with multiple bit lines BL0 to BLm ("m" is an integer equal to or greater than 1) and multiple word lines WL (not shown).

[0024] The input / output circuit 21 controls transmission and reception (input / output) of input / output signals I / O0 to I / O7. The input / output signals I / O may include, for example, data DAT, status information, an address, and a command. The input / output circuit 21 may input and output data DAT between the data register 28 and the memory controller 1. The input / output circuit 21 may output status information transferred from the register circuit 23 to the memory controller 1. The input / output circuit 21 may output each of the addresses and commands transferred from the memory controller 1 to the register circuit 23.

[0025] The logic controller 22 controls each of the input / output circuit 21 and the sequencer 24 based on each control signal input from the memory controller 1. The logic controller 22 enables the memory device 2 based on the control signal CEn. The logic controller 22 notifies the input / output circuit 21 that the input / output signal I / O received by the memory device 2 is a command and an address based on the control signals CLE and ALE. The logic controller 22 instructs the input / output circuit 21 to receive the input / output signal I / O based on the control signal WEn, and instructs the input / output circuit 21 to transmit the input / output signal I / O based on the control signal REn. The logic controller 22 puts the memory device 2 into a protected state based on the control signal WPn.

[0026] The register circuit 23 temporarily stores a status, an address, a command, etc. The status is information indicating the operating state of the memory device 2. The status is updated based on the control of the sequencer 24, and is transferred to the memory controller 1 via the input / output circuit 21. The address may include a block address, a page address, a column address, etc. The command includes an instruction related to various operations of the memory device 2.

[0027] The sequencer 24 is a controller that controls the overall operation of the memory device 2. The sequencer 24 executes a read operation, a write operation, an erase operation, and the like, based on the commands and addresses stored in the register circuit 23.

[0028] The ready-busy controller 25 generates a ready-busy signal RBn under the control of the sequencer 24. The ready-busy signal RBn is a signal that notifies the memory controller 1 whether the memory device 2 is in a ready state or a busy state. The ready state is a state in which the memory device 2 can accept commands from the memory controller 1, and is notified by a ready-busy signal RBn at a high level. The busy state is a state in which the memory device 2 cannot accept commands from the memory controller 1, and is notified by a ready-busy signal RBn at a low level.

[0029] The driver circuit 26 generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 26 supplies the generated voltages to a row decoder module 27 and a sense amplifier module 29.

[0030] The row decoder module 27 is a circuit used for selecting a block BLK and supplying a voltage to wiring such as a word line WL. The row decoder module 27 includes a plurality of row decoders RD0 to RDn. The row decoders RD0 to RDn are associated with the blocks BLK0 to BLKn, respectively. Each row decoder RD can set the associated block BLK to selected or unselected based on a block address.

[0031] The data register 28 is a circuit that temporarily stores the data DAT. The data register 28 can be used to input and output the data DAT between the input / output circuit 21 and the sense amplifier module 29. The data register 28 is also called a data latch, a page register, or a cache memory.

[0032] The sense amplifier module 29 is a circuit used for supplying voltage to each bit line BL and reading data. The sense amplifier module 29 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are associated with a plurality of bit lines BL0 to BLm, respectively. Each sense amplifier unit SAU can determine data read from a selected memory cell transistor MT based on the voltage of the associated bit line BL.

[0033] A set of the memory cell array 20, the row decoder module 27, and the sense amplifier module 29 is also called, for example, a plane. The memory device 2 may include a plurality of planes. The sequencer 24 may be configured to be capable of controlling each of the plurality of planes.

[0034] An example of a detailed circuit configuration of the memory cell array 20, the row decoder module 27, the data register 28, and the sense amplifier module 29 will be described below.

[0035] (1: Circuit configuration of memory cell array 20) FIG. 4 is a diagram showing an example of a circuit configuration of the memory cell array 20 according to the first embodiment. FIG. 4 shows one of a plurality of blocks BLK included in the memory cell array 20. As shown in FIG. 4, the block BLK is provided with a plurality of bit lines BL0 to BLm, a plurality of word lines WL0 to WL7, select gate lines SGD0 to SGD4, a select gate line SGS, and a source line SL. The select gate lines SGD0 to SGD4 and SGS and the word lines WL0 to WL7 are provided for each block BLK. The bit lines BL0 to BLm are shared by a plurality of blocks BLK. The source line SL may be shared by a plurality of blocks BLK, or may be provided for each block BLK.

[0036] The block BLK includes, for example, five string units SU0 to SU4. Each string unit SU includes a plurality of NAND strings NS. The plurality of NAND strings NS are associated with bit lines BL0 to BLm, respectively. That is, each bit line BL is shared by NAND strings NS to which the same column address is assigned among the plurality of blocks BLK. Each NAND string NS is connected between the associated bit line BL and a source line SL.

[0037] Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and selection transistors STD and STS. Each memory cell transistor MT is a memory cell having a control gate and a charge storage layer, and holds (stores) data in a non-volatile manner. The threshold voltage of the memory cell transistor MT can be changed based on the amount of charge injected into the charge storage layer, etc. The memory cell transistor MT stores data according to the threshold voltage. Each of the selection transistors STD and STS is used to select a string unit SU.

[0038] In each NAND string NS, a selection transistor STD, memory cell transistors MT7 to MT0, and a selection transistor STS are connected in series in this order. Specifically, the drain of the selection transistor STD is connected to an associated bit line BL. The source of the selection transistor STD is connected to the drain of the memory cell transistor MT7. The drain of the selection transistor STS is connected to the source of the memory cell transistor MT0. The source of the selection transistor STS is connected to a source line SL. The memory cell transistors MT0 to MT7 are connected in series between the selection transistors STD and STS.

[0039] The select gate lines SGD0 to SGD4 are associated with the string units SU0 to SU4, respectively. Each select gate line SGD is connected to the gates of the select transistors STD included in the associated string unit SU. The select gate line SGS is connected to the gates of the select transistors STS included in the associated block BLK. The word lines WL0 to WL7 are connected to the control gates of the memory cell transistors MT0 to MT7 included in the associated block BLK, respectively.

[0040] In this specification, a set of multiple memory cell transistors MT commonly connected to a word line WL in one string unit SU is called a cell unit CU. In this specification, a set of 1-bit data stored in each of the multiple memory cell transistors MT included in the cell unit CU is called page data. The cell unit CU can store two or more pages of data depending on the number of bits of data stored in each memory cell transistor MT.

[0041] The memory cell array 20 may have a circuit configuration other than the above. For example, the number of string units SU included in each block BLK, and the number of memory cell transistors MT and select transistors STD and STS included in each NAND string NS may be designed to be any number.

[0042] (2: Circuit configuration of row decoder module 27) FIG. 5 is a diagram showing an example of a circuit configuration of the row decoder module 27 according to the first embodiment. FIG. 5 shows the connection relationship between the driver circuit 26 and the memory cell array 20 and the row decoder module 27, and a detailed circuit configuration of one row decoder RD0. The circuit configurations of the row decoders RD other than the row decoder RD0 are similar to that of the row decoder RD0. As shown in FIG. 5, each row decoder RD is connected to signal lines CG0 to CG7, SGDD0 to SGDD4, SGSD, USGD, and USGS connected to the driver circuit 26. In addition, each row decoder RD is connected to word lines WL0 to WL7 of the associated block BLK, and select gate lines SGD0 to SGD4 and SGS.

[0043] The row decoder RD0 includes, for example, transistors TR0 to TR19, transfer gate lines TG and bTG, and a block decoder BD. Each of the transistors TR0 to TR19 is an N-type high-voltage transistor. The transfer gate line TG is connected to the gates of the transistors TR0 to TR13. The transfer gate line bTG is connected to the gates of the transistors TR14 to TR19. The drains of the transistors TR0 to TR13 are connected to signal lines SGSD, CG0 to CG7, and SGDD0 to SGDD4, respectively. The sources of the transistors TR0 to TR13 are connected to the select gate line SGS of the block BLK0, the word lines WL0 to WL7, and the select gate lines SGD0 to SGD4, respectively. The drain and source of the transistor TR14 are connected to the signal line USGS and the select gate line SGS of the block BLK0, respectively. The drains of the transistors TR15 to TR19 are connected to the signal line USGD. The sources of the transistors TR15 to TR19 are connected to the select gate lines SGD0 to SGD4 of the block BLK0, respectively.

[0044] The block decoder BD is a circuit that decodes a block address. Based on the decoded result of the block address, the block decoder BD applies one of a high level and a low level voltage to the transfer gate line TG, and applies the other of a high level and a low level voltage to the transfer gate line bTG. Specifically, the block decoder BD of the selected block BLK applies a high level voltage to the transfer gate line TG, and a low level voltage to the transfer gate line bTG. The block decoder BD of the unselected block BLK applies a low level voltage to the transfer gate line TG, and a high level voltage to the transfer gate line bTG. As a result, the voltages of the signal lines CG0 to CG7 are applied to the word lines WL0 to WL7 of the selected block BLK, the voltages of the signal lines SGDD0 to SGDD4 and SGSD are applied to the select gate lines SGD0 to SGD4 and SGS of the selected block BLK, and the voltages of the signal lines USGD and USGS are applied to the select gate lines SGD and SGS of the unselected block BLK.

[0045] The row decoder module 27 may have a circuit configuration other than the above. For example, the number of transistors TR included in the row decoder module 27 may be appropriately changed according to the number of wirings in each block BLK. The signal line CG is also called a global word line because it is shared by multiple blocks BLK. The word line WL is also called a local word line because it is provided for each block. The signal lines SGDD and SGSD are also called global transfer gate lines because they are shared by multiple blocks BLK. The selection gate lines SGD and SGS are also called local transfer gate lines because they are provided for each block.

[0046] (3: Circuit configuration of the sense amplifier module 29 and the data register 28) 6 is a diagram showing an example of a circuit configuration of a sense amplifier module 29 and a data register 28 according to the first embodiment. As shown in FIG. 6, each sense amplifier unit SAU includes, for example, a bit line connection unit BLHU, a sense amplifier unit SA, buses DBUS and LBUS, latch circuits SDL, ADL, BDL and CDL, and a transistor T0. The data register 28 includes a plurality of latch circuits XDL0 to XDLm. The latch circuits XDL0 to XDLm are associated with the sense amplifier units SAU0 to SAUm, respectively. Each of the latch circuits XDL0 to XDLm is connected to the associated sense amplifier unit SAU via a bus DBUS.

[0047] The bit line connection unit BLHU is, for example, a protection circuit that prevents a high voltage applied to the channel of the NAND string NS during an erase operation from being applied to the sense amplifier unit SA. The bit line connection unit BLHU may be configured to be able to apply a predetermined voltage to unselected bit lines BL.

[0048] The sense amplifier unit SA is a circuit used to determine data based on the voltage of the bit line BL and to apply a voltage to the bit line BL. Each sense amplifier unit SA is connected to the associated bit line BL via a bit line connection unit BLHU. When a control signal STB is asserted during a read operation, the sense amplifier unit SA determines whether the data read from the selected memory cell transistor MT is “0” data or “1” data based on the voltage of the associated bit line BL. The control signal STB is generated by, for example, a sequencer 24.

[0049] Each of the latch circuits SDL, ADL, BDL, and CDL is capable of temporarily holding data. The latch circuits SDL, ADL, BDL, and CDL, and the sense amplifier unit SA are configured to be able to transmit and receive data via a bus LBUS.

[0050] The transistor T0 of each sense amplifier unit SAU controls the transfer of signals between the associated buses DBUS and LBUS. One end of the transistor T0 of each sense amplifier unit SAU is connected to the associated bus DBUS. The other end of the transistor T0 of each sense amplifier unit SAU is connected to the associated bus LBUS. A control signal DSW is input to the gate of the transistor T0 of each sense amplifier unit. The control signal DSW is generated by, for example, the sequencer 24.

[0051] Each latch circuit XDL can temporarily hold data. Each latch circuit XDL is configured to be able to transmit and receive data to and from an associated sense amplifier unit SAU via a bus DBUS. Each latch circuit XDL is used for inputting and outputting data DAT between the sense amplifier module 29 and the input / output circuit 21. Each latch circuit XDL may be shared by multiple sense amplifier units SAU.

[0052] The sense amplifier module 29 may have a circuit configuration other than that described above. For example, the number of latch circuits included in each sense amplifier unit SAU may be changed as appropriate. The sense amplifier unit SAU may have an arithmetic circuit capable of executing a logical operation.

[0053] <1-1-4> Threshold voltage distribution of memory cell transistor MT FIG. 7 is a diagram showing an example of the threshold voltage distribution and data allocation of the memory cell transistors MT in the memory system MS according to the first embodiment. The vertical axis "NMTs" indicates the number of memory cell transistors MT. The horizontal axis "Vth" indicates the threshold voltage of the memory cell transistors MT. As shown in FIG. 7, when each memory cell transistor MT stores 3-bit data, the threshold voltage distribution of the memory cell transistors MT forms eight states. In this specification, the eight states are called S0 state, S1 state, S2 state, S3 state, S4 state, S5 state, S6 state, and S7 state, in order from the lowest threshold voltage. The memory cell transistors MT belonging to each of the S0 state to S7 state are assigned different 3-bit data. Note that each memory cell transistor MT may store 1-bit, 2-bit, or 4-bit or more data, or may be assigned data different from the following description.

[0054] An example of data allocation to memory cell transistors MT belonging to each of the eight states is shown below. The 3-bit data stored in each memory cell transistor MT is also called upper bit data, middle bit data, and lower bit data. One page of data consisting of the upper bit data, middle bit data, and lower bit data stored in each of the memory cell transistors MT included in each cell unit CU is also called upper page data, middle page data, and lower page data, respectively.

[0055] S0 state: “111” data S1 state: “110” data S2 state: “100” data S3 state: “000” data S4 state: “010” data S5 state: “011” data S6 state: “001” data S7 state: “101” data

[0056] A read voltage and a verify voltage are set between adjacent states. Specifically, a read voltage R1 is set between the S0 state and the S1 state. Similarly, read voltages R2 to R7 are set between the S1 state to the S6 state and the S2 state to the S7 state, respectively. The read voltage is also called a read level. Verify voltages V1 to V7 are set in association with the S1 state to the S7 state, respectively. Also, a read pass voltage VREAD is set to a voltage higher than the state with the highest threshold voltage (S7 state).

[0057] A read voltage is applied to a word line WL selected as a target for a read operation. A memory cell transistor MT included in a cell unit CU targeted for a read operation in the selected word line WL is turned on if it has a threshold voltage lower than the applied read voltage. A read pass voltage VREAD is applied to unselected word lines WL. A memory cell transistor MT connected to a word line WL to which the read pass voltage VREAD is applied is turned on regardless of the data to be stored.

[0058] 7 is applied, the lower page data is determined by a read operation using read voltages R1 and R5. The middle page data is determined by a read operation using read voltages R2, R4, and R6. The upper page data is determined by a read operation using read voltages R3 and R7. In a page data read operation in which multiple read voltages are used, arithmetic processing is appropriately performed in the sense amplifier unit SAU.

[0059] <1-2> Operation Next, the operation of the memory system MS according to the first embodiment will be described.

[0060] <1-2-1>Vth tracking overview First, an overview of Vth tracking will be given. Vth tracking is an operation that searches for the valley position of the threshold voltage distribution of two adjacent states (hereinafter referred to as adjacent states) and estimates the optimum read level. The optimum read level is the read level value that minimizes the number of error bits (fail bits) when a read operation is performed. Vth tracking is also called a tracking operation.

[0061] For example, in Vth tracking, first, multiple shift reads are performed according to a preset read level setting. Each shift read is a read operation in which a voltage shift amount from a start read level is specified. The shift amount is specified, for example, by a DAC (Digital Analog Converter) value. In multiple shift reads in Vth tracking, multiple read levels set at equal intervals can be used. Then, the number of memory cell transistors MT that are turned on at each read level (also called the number of on cells) is counted, and the difference between the number of on cells at two adjacent read levels is calculated. Then, a point where the plot of the difference between the number of on cells is downwardly convex, that is, a point where the difference between the number of on cells is minimal, is extracted. Then, the ratio of the two differences adjacent to the minimal point is calculated. Also, the voltage difference (potential difference) between the two read levels adjacent to the minimal point is divided internally by the calculated ratio. The voltage obtained is estimated as the optimal read level.

[0062] In the following, among the multiple read levels used in multiple shift reads performed in Vth tracking, two adjacent read levels are also called adjacent read levels. The voltage difference (potential difference) between the adjacent read levels is also called step size. The value of the step size is also called step value. Like the shift amount, the step value can be specified by a DAC value.

[0063] 8 is a schematic diagram showing an example of a fail bit count (error bit count) occurring in adjacent states in the memory system MS according to the first embodiment. FIG. 8 shows the threshold voltage distribution of adjacent states. In this example, each memory cell transistor MT is configured to store 1-bit data. In this example, the adjacent states are associated with "1" data and "0" data, respectively, in ascending order of threshold voltage.

[0064] The threshold voltage of the memory cell transistor MT may vary due to factors such as disturbance. For example, the distribution width of the threshold voltage of each state may widen, or the most frequent value of the threshold voltage distribution of each state may change. As a result, as shown in FIG. 8, adjacent states may overlap. When adjacent states overlap, there are memory cell transistors MT in which "1" data is erroneously determined as "0" data, and memory cell transistors MT in which "0" data is erroneously determined as "1" data. In this example, the number of memory cell transistors MT in which "0" data is erroneously determined as "1" data is shown as the number of fail bits FBC1. Also, the number of memory cell transistors MT in which "1" data is erroneously determined as "0" data is shown as the number of fail bits FBC2.

[0065] 8, RTRK corresponds to the optimum read level estimated by Vth tracking, RBST corresponds to the actual optimum read level, and RBST corresponds to the intersection of adjacent states.

[0066] When "FBC1+FBC2" exceeds the number of error correctable bits, the ECC circuit 13 cannot correctly correct the data. Therefore, it is preferable to make "FBC1+FBC2" as small as possible. "FBC1+FBC2" is smallest when a read operation is performed using the actual optimum read level (RBST). On the other hand, the optimum read level (RTRK) estimated by Vth tracking may have a value different from RBST depending on the shape of the adjacent state. In FIG. 8, the difference between "FBC1+FBC2" generated in a read operation using RBST and "FBC1+FBC2" generated in a read operation using RTRK different from RBST is shown as the number of fail bits FBC3. In the threshold voltage distribution of the adjacent states, the number of fail bits FBC3 corresponds to the difference between the area corresponding to "FBC1+FBC2" generated in a read operation using RBST and the area corresponding to "FBC1+FBC2" generated in a read operation using RTRK. The number of fail bits FBC3 can be reduced by bringing RTRK closer to RBST.

[0067] 9 is a schematic diagram showing an example of symmetrical threshold voltage distribution of adjacent states. As shown in FIG. 9, when the S(L-1) state and the S(L) state (L is an integer of 1 or more) are substantially symmetrical, the optimum read level can be estimated by the minimum value of a quadratic function based on a plot of the difference in the number of ON cells of a plurality of adjacent read levels obtained by Vth tracking. In other words, when the adjacent states are symmetrical, the optimum read level (RTRK) estimated by Vth tracking and the actual optimum read level (RBST) are substantially the same.

[0068] Fig. 10 is a schematic diagram showing an example of an asymmetric threshold voltage distribution of adjacent states. As shown in Fig. 10, when the S(L-1) state and the S(L) state are asymmetric, the optimum lead level cannot be estimated with high accuracy by the minimum value of the quadratic function based on the plot of the difference in the number of ON cells of multiple adjacent lead levels obtained by Vth tracking. In other words, when the adjacent states are asymmetric, the optimum lead level (RTRK) estimated by Vth tracking shifts to the positive or negative side with respect to the actual optimum lead level (RBST).

[0069] 11 is a schematic diagram showing an example of a more detailed threshold voltage distribution of the memory cell transistor MT. As shown in FIG. 11, in this example, the S0 state and the S7 state located at both ends have a wider shape than the other states. Therefore, the asymmetry between the pair of adjacent S0 state and S1 state and the pair of adjacent S6 state and S7 state becomes prominent. In the following, the pair of adjacent S(L-1) state and S(L) state is called the S(L-1)-S(L) state.

[0070] FIG. 11(1) shows an enlarged view of the vicinity of the valley position of the S0-S1 state. Hereinafter, the ratio of the change in threshold voltage to the change in the number of memory cell transistors MT having that threshold voltage is also referred to as the gradient of the threshold voltage distribution or simply as the gradient. FIG. 11(1) shows a case where the gradient on the S0 state side is gentler than the gradient on the S1 state side. In this case, when Vth tracking is performed using multiple read levels set at equal intervals for the S0-S1 states, the optimum read level (RTRK) estimated by Vth tracking may deviate from the actual optimum read level (RBST).

[0071] Fig. 11(2) shows an enlarged view of the vicinity of the valley position of the S6-S7 state. Fig. 11(2) shows a case where the gradient on the S7 state side is gentler than that on the S6 state side. In this case, when Vth tracking is performed using multiple read levels set at equal intervals for the S6-S7 state, the optimum read level (RTRK) estimated by Vth tracking may deviate from the actual optimum read level (RBST).

[0072] The optimum read level (RTRK) estimated by Vth tracking may shift to the state with a gentler gradient (higher voltage in the case of S6-S7 state). Also, depending on the estimation method, the optimum read level (RTRK) estimated may shift to the state with a steeper gradient (lower voltage in the case of S6-S7 state).

[0073] In this example, the other adjacent states are formed substantially symmetrically. In this case, the optimum read level (RTRK) estimated by Vth tracking can substantially match the actual optimum read level (RBST) in each of the S1-S2 state, the S2-S3 state, the S3-S4 state, and the S5-S6 state.

[0074] The asymmetry between adjacent states may be greater in states located at both ends of the threshold voltage distribution. For this reason, in the S1-S2 state, S5-S6 state, etc., the optimum read level (RTRK) estimated by Vth tracking may deviate from the actual optimum read level (RBST). In this way, the adjacent states in which asymmetry occurs are not limited to the adjacent states at both ends of the threshold voltage distribution. The tendency for asymmetry between adjacent states to occur is similar even when each memory cell transistor MT stores 2-bit data or 4-bit or more data.

[0075] In Vth tracking, it is preferable to estimate the optimum read level with high accuracy while taking into account the asymmetry of adjacent states described above. Therefore, the Vth tracking executed in the memory system MS according to the first embodiment has a function of estimating the optimum read level with high accuracy while taking into account the gradient of the threshold voltage distribution, as shown below.

[0076] <1-2-2> Vth tracking considering the asymmetry of adjacent states FIG. 12 is a flowchart showing an example of a procedure of Vth tracking executed in the memory system MS according to the first embodiment.

[0077] The memory system MS starts (starts) a series of processes shown in FIG. 12, for example, when an error correction of data read from the memory device 2 in a read operation fails, or based on a predetermined schedule.

[0078] First, the memory controller 1 selects a Vth tracking parameter based on information related to the gradient of the threshold voltage distribution of the memory cell transistor MT (ST101). The information related to the gradient of the threshold voltage distribution of the memory cell transistor MT is, for example, information related to the type of the adjacent state, the address of the cell unit CU, and the optimal read level of the adjacent state obtained by Vth tracking performed in advance. The tendency of the gradient of the threshold voltage distribution of the memory cell transistor MT may also change depending on the address of the cell unit CU (i.e., the position of the memory cell transistor MT in the block BLK).

[0079] The Vth tracking parameters (also called search read parameters) include settings related to the read levels (start read level and step value) used in multiple shift reads performed in Vth tracking, and the number of shift reads (also called search count) performed in Vth tracking. The start read level is the read level used in the first shift read of multiple shift reads. In the Vth tracking of the first embodiment, multiple step values ​​different from each other can be used.

[0080] Next, the memory controller 1 executes multiple shift reads according to the selected parameters (ST102). In the process of step ST102, for example, the memory controller 1 transmits to the memory device 2 a parameter setting instruction for the read operation and an instruction to execute the read operation for each of the multiple shift reads. The parameter setting instruction includes information regarding the read level used in the shift read. Then, the memory controller 1 obtains the read result from the memory device 2 for each shift read.

[0081] Next, the memory controller 1 calculates the number of ON cells for each of the multiple shift reads (ST103). For example, the memory controller 1 counts the number of memory cell transistors MT that are in the ON state from the read result. If the memory device 2 includes a counter, the memory device 2 may count the number of ON cells based on the shift read result and transmit the count result to the memory controller 1.

[0082] Next, the memory controller 1 calculates the difference in the number of ON cells for each set of two shift reads using adjacent read levels, based on the results of the multiple shift reads (ST104).

[0083] Next, the memory controller 1 estimates the optimum read level based on the calculated data (plot) of the difference in the number of ON cells (ST105). For example, the method described in “<1-2-1> Overview of Vth Tracking” is used to estimate the optimum read level.

[0084] When the process of step ST105 is completed, the memory controller 1 ends (ends) the series of processes shown in Fig. 12. After Vth tracking, the memory controller 1 may execute a read operation using the estimated optimum read level.

[0085] <1-2-3> Specific examples of step values ​​set for asymmetric adjacent states A specific example of the step value used in Vth tracking of asymmetric adjacent states will be described below. Note that the following describes a case where five shift reads are performed in Vth tracking.

[0086] (1: When targeting S0-S1 state) 13 is a schematic diagram showing an example of a method for setting step values ​​used in Vth tracking for the S0-S1 states, which is executed in the memory system MS according to the first embodiment. As shown in FIG. 13, in Vth tracking for the S0-S1 states, for example, step values ​​SS1, SS2, and SS3 are used. The step value SS1 is greater than the step value SS2. The step value SS2 is greater than the step value SS3. In Vth tracking for the S0-S1 states, SS1, SS2, SS2, and SS3 are applied in order from the lowest read level as step values ​​for four sets of adjacent read levels.

[0087] When the gradient on the S0 state side is gentler than that on the S1 state side, in Vth tracking targeting the S0-S1 states, it is sufficient that the step value set on the S0 state side is set to be greater than the step value set on the S1 state side, so that the change in the number of ON cells can be detected with low resolution in the voltage range on the S0 state side with a gentle gradient, and the change in the number of ON cells can be detected with high resolution in the voltage range on the S1 state side with a steep gradient.

[0088] As a result, the memory system MS according to the first embodiment can improve the estimation accuracy of the optimum read level based on a plot of the difference in the number of on-cells at a plurality of adjacent read levels obtained by Vth tracking (for example, by a quadratic function). That is, the memory system MS can make the optimum read level RTRK estimated by Vth tracking targeting the S0-S1 state closer to the actual optimum read level RBST than the optimum read level RTRK(ref) estimated by Vth tracking using one type of step value.

[0089] (2: When targeting S6-S7 states) 14 is a schematic diagram showing an example of a method for setting step values ​​used in Vth tracking for the S6-S7 states in the memory system MS according to the first embodiment. As shown in FIG. 14, in Vth tracking for the S6-S7 states, for example, step values ​​SS1, SS2, and SS3 similar to those in Vth tracking for the S0-S1 states are used. In Vth tracking for the S6-S7 states, SS3, SS2, SS2, and SS1 are applied in order from the lowest read level as step values ​​for four sets of adjacent read levels.

[0090] When the gradient on the S7 state side is gentler than that on the S6 state side, in Vth tracking targeting the S6-S7 states, it is sufficient that the step value set on the S7 state side is set to be greater than the step value set on the S6 state side, so that the change in the number of ON cells can be detected with low resolution in the voltage range on the S7 state side with a gentle gradient, and the change in the number of ON cells can be detected with high resolution in the voltage range on the S6 state side with a steep gradient.

[0091] As a result, the memory system MS according to the first embodiment can improve the estimation accuracy of the optimum read level based on a plot of the difference in the number of on-cells at a plurality of adjacent read levels obtained by Vth tracking (for example, by a quadratic function). That is, the memory system MS can make the optimum read level RTRK estimated by Vth tracking targeting the S6-S7 states closer to the actual optimum read level RBST than the optimum read level RTRK(ref) estimated by Vth tracking using one type of step value.

[0092] <1-3> Effects of the first embodiment As described above, the memory system MS according to the first embodiment can set the step values ​​of the read levels used in multiple shift reads in Vth tracking to be non-uniform. In other words, the memory system MS uses at least two or more different step values ​​associated with asymmetric adjacent states for Vth tracking. The memory system MS uses an algorithm that searches for a voltage range in which the gradient of the threshold voltage distribution changes sharply with high resolution (i.e., a relatively small step value) and searches for a voltage range in which the gradient of the threshold voltage distribution changes gently with low resolution (i.e., a relatively large step value).

[0093] In this way, the memory system MS according to the first embodiment can shift the axis of the quadratic curve that is the approximation curve by setting a step value according to the gradient of the threshold voltage distribution in Vth tracking. As a result, the memory system MS according to the first embodiment can suppress a shift (displacement) of the optimum read level estimated by Vth tracking from the actual optimum read level to the positive or negative side. That is, the memory system MS according to the first embodiment can bring the estimated optimum read level closer to the actual optimum read level.

[0094] The memory system MS according to the first embodiment can reduce the number of error bits (number of fail bits) by using the optimal read level estimated by Vth tracking using unequal step values ​​for the read operation targeting the asymmetric adjacent states. Therefore, the memory system MS according to the first embodiment can obtain high reliability.

[0095] The number of shift reads performed in the Vth tracking described in the first embodiment is the same whether a plurality of different step values ​​are used or a single type of step value is used. In other words, the memory system MS of the first embodiment can improve the accuracy of Vth tracking without increasing the processing time of Vth tracking.

[0096] <2> Second embodiment The memory system MS according to the second embodiment is configured to perform Vth tracking similar to that of the first embodiment, and further has a function of estimating the gradient of the threshold voltage distribution of the memory cell transistor MT. Details of the memory system MS according to the second embodiment will be described below, focusing on the differences from the first embodiment.

[0097] <2-1> Configuration First, the configuration of the memory system MS according to the second embodiment will be described. The hardware configuration of the memory system MS according to the second embodiment is the same as that of the first embodiment. The functional configuration of the memory system MS according to the second embodiment will be described below. Note that, in the following, the memory device 2 will be described as including a core circuit 210 and a peripheral circuit 220. The core circuit 210 corresponds to the memory cell array 20, the row decoder module 27, the data register 28, and the sense amplifier module 29. The peripheral circuit 220 corresponds to the input / output circuit 21, the logic controller 22, the register circuit 23, the sequencer 24, the ready-busy controller 25, and the driver circuit 26.

[0098] Fig. 15 is a block diagram showing an example of a functional configuration of a memory system MS according to the second embodiment. As shown in Fig. 15, the memory controller 1 according to the second embodiment has a Vth tracking processing unit 110 and a parameter storage unit 120. The peripheral circuit 220 of the memory device 2 according to the second embodiment has a shift read processing unit 221.

[0099] The Vth tracking processing unit 110 has a function of performing the Vth tracking described in the first embodiment. The parameter storage unit 120 has a function of storing Vth tracking parameters. The Vth tracking processing unit 110 determines a start read level and a step value used in Vth tracking by referring to the Vth tracking parameters stored in the parameter storage unit 120. Furthermore, the Vth tracking processing unit 110 estimates the gradient of the threshold voltage distribution of the memory cell transistor MT based on the results of multiple shift reads. Then, the Vth tracking processing unit 110 has a function of selecting a more appropriate Vth tracking parameter by referring to the parameter storage unit 120 based on the estimation result of the gradient of the threshold voltage distribution.

[0100] The parameter storage unit 120 stores a plurality of types of Vth tracking parameters. Specifically, the parameter storage unit 120 stores a start value table 121 and a step value table 122. The start value table 121 stores information on the initial value (i.e., start read level) of the read level used in multiple shift reads performed in Vth tracking for each adjacent state that can be a target of Vth tracking. The step value table 122 stores information on the step value of the read level used in multiple shift reads performed in Vth tracking for each adjacent state that can be a target of Vth tracking. The Vth tracking parameters are preset in a plurality of combinations according to, for example, information related to the gradient of the adjacent states.

[0101] The shift read processing unit 221 executes a shift read using a read level based on an instruction from the Vth tracking processing unit 110. Then, the shift read processing unit 221 outputs a result of the shift read to the Vth tracking processing unit 110. In addition, the shift read processing unit 221 can change the setting of the read level used in the shift read based on an instruction from the Vth tracking processing unit 110.

[0102] (1: A concrete example of the start value table 121) FIG. 16 is a diagram showing an example of a start value table 121 stored in the parameter storage unit 120 of the memory controller 1 included in the memory system MS according to the second embodiment. As shown in FIG. 16, the start value table 121 stores, for example, a start read level used in Vth tracking of each of the S0-S1 state, the S1-S2 state, ..., the S6-S7 state for each index value (for example, #0 to #4). The start read level is expressed, for example, by a voltage value (V). The start read level may be specified by a DAC value instead of a voltage value (V). In this case, a value obtained by multiplying the DAC value stored in the start value table 121 by the voltage value per DAC value corresponds to the start read level.

[0103] In the start value table 121, in the row of index value #k ("k" is an integer equal to or greater than 0), start read levels RL1_k, RL2_k, ..., RL6_k, and RL7_k are stored in multiple fields associated with the columns of S0-S1 state, S1-S2 state, ..., S5-S6 state, and S6-S7 state, respectively.

[0104] More specifically, in the row with index value #0, the start read levels RL1_0, RL2_0, ..., RL6_0, and RL7_0 are stored in a plurality of fields associated with the columns of the S0-S1 state, the S1-S2 state, ..., the S5-S6 state, and the S6-S7 state, respectively. In the row with index value #1, the start read levels RL1_1, RL2_1, ..., RL6_1, and RL7_1 are stored in a plurality of fields associated with the columns of the S0-S1 state, the S1-S2 state, ..., the S5-S6 state, and the S6-S7 state, respectively. The same applies to the index values ​​#2 and onward.

[0105] In the start value table 121, the start read levels for the same adjacent state may be the same or different in multiple rows.

[0106] (2: Specific example of step value table 122) FIG. 17 is a diagram showing an example of a step value table 122 stored in the parameter storage unit 120 of the memory controller 1 included in the memory system MS according to the second embodiment. As shown in FIG. 17, the step value table 122 stores step values ​​used in Vth tracking of each of the S0-S1 state, the S1-S2 state, ..., and the S6-S7 state for each index value (for example, #0 to #4). The step value is expressed by, for example, a DAC value, but may be specified by a voltage value (V) similar to the start read level. In this example, it is assumed that five shift reads are performed in Vth tracking, and four types of step values ​​are stored for each adjacent state. The four types of step values ​​are respectively associated with four adjacent read levels included in the five shift reads. Each step value indicates the difference in the associated DAC values ​​or the difference in the voltage values ​​of the adjacent read levels. In the following, the four types of step values ​​set for each adjacent state will be described by adding "a", "b", "c", and "d" in order from the lowest associated adjacent read level to the reference symbols indicating the four types of step values.

[0107] Specifically, in step value table 122, in a row with index value #k ("k" is an integer equal to or greater than 0), step values ​​SS1a_k, SS1b_k, SS1c_k, and SS1d_k are stored in the field associated with the column of the S0-S1 state, step values ​​SS2a_k, SS2b_k, SS2c_k, and SS2d_k are stored in the field associated with the column of the S1-S2 state, ..., step values ​​SS7a_k, SS7b_k, SS7c_k, and SS7d_k are stored in the field associated with the column of the S6-S7 state.

[0108] More specifically, in the row with index value #0, step values ​​SS1a_0, SS1b_0, SS1c_0, and SS1d_0 are stored in the fields associated with the columns of the S0-S1 states, step values ​​SS2a_0, SS2b_0, SS2c_0, and SS2d_0 are stored in the fields associated with the columns of the S1-S2 states, ..., step values ​​SS7a_0, SS7b_0, SS7c_0, and SS7d_0 are stored in the fields associated with the columns of the S6-S7 states. In the row with index value #1, step values ​​SS1a_1, SS1b_1, SS1c_1, and SS1d_1 are stored in the fields associated with the columns of the S0-S1 states, step values ​​SS2a_1, SS2b_1, SS2c_1, and SS2d_1 are stored in the fields associated with the columns of the S1-S2 states, ..., step values ​​SS7a_1, SS7b_1, SS7c_1, and SS7d_1 are stored in the fields associated with the columns of the S6-S7 states.

[0109] Here, the details of the read voltage when the parameter of index value #1 is referred to in Vth tracking of the S0-S1 state will be described. In this example, in five shift reads, read operations using read levels RL1(1) to RL1(5) are executed. The read level RL1(1) used in the first shift read corresponds to the start read level and is set based on the start value table 121. The read level RL1(2) used in the second shift read is set based on "RL1(1)+SS1a_1". The read level RL1(3) used in the third shift read is set based on "RL1(2)+SS1b_1". The read level RL1(4) used in the fourth shift read is set based on "RL1(3)+SS1c_1". The read level RL1(5) used in the fifth shift read is set based on "RL1(4)+SS1d_1". For step values ​​in other adjacent states and other index values, multiple read levels are set to be used in multiple shift reads, just as when the parameters of index value #1 are referenced in Vth tracking of the S0-S1 states.

[0110] In the step value table 122, multiple step values ​​for the same adjacent state may be the same or different in multiple rows.

[0111] <2-2> Operation Next, the operation of the memory system MS according to the second embodiment will be described.

[0112] FIG. 18 is a flowchart showing an example of a procedure of Vth tracking executed in the memory system MS according to the second embodiment.

[0113] The memory system MS starts (starts) a series of processes shown in FIG. 18, for example, when an error correction of data read from the memory device 2 in a read operation fails, or based on a predetermined schedule.

[0114] First, the Vth tracking processing unit 110 loads initial parameters for Vth tracking from each of the start value table 121 and the step value table 122 (ST201). The initial parameters to be loaded can be selected based on, for example, the type of adjacent state, the address of the cell unit CU, information on the optimal read level of the adjacent state obtained by Vth tracking previously performed, the operation log of the memory system MS, etc.

[0115] Next, the Vth tracking processing unit 110 executes a plurality of shift reads according to the loaded parameters (ST202). In the plurality of shift reads in the process of step ST202, the Vth tracking processing unit 110 may use one type of step value, or may use two or more different types of step values.

[0116] Next, the Vth tracking processing unit 110 calculates the number of ON cells in each of the multiple shift reads (ST203).

[0117] Next, the Vth tracking processing unit 110 calculates the difference in the number of ON cells for each set of two shift reads using adjacent read levels, based on the results of the multiple shift reads (ST204).

[0118] Next, the Vth tracking processing unit 110 checks whether the difference plot shows a V-shape (ST205). The difference plot corresponds to a plot of the difference in the number of ON cells obtained by the processing of step ST204. For example, when the range of the read level in which the shift read is performed multiple times in the processing of step ST202 includes a voltage range in which the difference in the number of ON cells decreases with an increase in the read level and a voltage range in which the difference in the number of ON cells increases with an increase in the read level, the difference plot shows a V-shape. For example, when the difference plot is approximated by a quadratic function, the V-shape can be determined by whether the plot includes a minimum point of the quadratic function.

[0119] If it is confirmed in the process of step ST205 that the difference plot does not show a V-shape (ST205: NO), the Vth tracking processing unit 110 changes the Vth tracking parameters (ST206). In the process of step ST206, the Vth tracking processing unit 110 changes, for example, at least one of the start read level and the step value. Then, the Vth tracking processing unit 110 proceeds to the process of step ST202. That is, the Vth tracking processing unit 110 executes the processes of steps ST202 to ST205 using the changed Vth tracking parameters.

[0120] If it is confirmed in the process of step ST205 that the difference plot shows a V-shape (ST205: YES), the Vth tracking processing unit 110 calculates a difference DN1 between the minimum value of the obtained differences and the difference immediately before it, and a difference DN2 between the minimum value and the difference immediately after it, and compares the magnitudes of the difference DN1 and the difference DN2 (ST207). The process of step ST207 will be described in detail later. Then, based on the comparison result of step ST207, the Vth tracking processing unit 110 checks whether the absolute value of the difference between DN1 and DN2 is equal to or smaller than a predetermined threshold value (ST208). Note that multiple threshold values ​​may be set for the absolute value of this difference.

[0121] If it is confirmed in the process of step ST208 that the absolute value of the difference between DN1 and DN2 is equal to or less than the predetermined threshold value (ST208: YES), that is, if the asymmetry of the threshold voltage distribution of the adjacent states is within the expected range, the Vth tracking processing unit 110 proceeds to the process of step ST211. The fact that the absolute value of the difference between DN1 and DN2 is equal to or less than the predetermined threshold value indicates that a preferable Vth tracking parameter has been set in the multiple shift reads executed in step ST202.

[0122] When it is confirmed in the process of step ST208 that the absolute value of the difference between DN1 and DN2 is greater than the predetermined threshold value (ST208: NO), that is, when the asymmetry of the threshold voltage distribution of the adjacent states is unexpected, the Vth tracking processing unit 110 changes the Vth tracking parameter (ST209). In the process of step ST209, the Vth tracking processing unit 110 changes, for example, the row (i.e., index value) of the step value table 122 to be referred to in the next Vth tracking. Then, the Vth tracking processing unit 110 executes Vth tracking using the changed Vth tracking parameter (ST210). When the process of step ST210 is completed, the Vth tracking processing unit 110 proceeds to the process of step ST211.

[0123] In the process of step ST211, the Vth tracking processing unit 110 estimates the optimum read level. In the process of ST211, if the Vth tracking processing unit 110 goes through the process of "ST208: NO", it estimates the optimum read level based on the results of the multiple shift reads executed in step ST202. In addition, if the Vth tracking processing unit 110 goes through the process of "ST208: YES", it estimates the optimum read level based on the results of the multiple shift reads executed in the Vth tracking of step ST210. When the process of step ST211 is completed, the Vth tracking processing unit 110 ends the series of processes shown in FIG. 18 (end).

[0124] When the process moves from step ST206 to step ST202, the multiple shift reads in step ST202 may be replaced with one additional shift read. In this case, the processes of steps ST203 and ST204 are executed again based on the results of the additional one shift read according to the changed Vth parameter and the multiple shift reads executed before the change of the Vth parameter. Then, the process of step ST205 determines again whether the difference plot of the ON cell count shows a V-shape. This allows the memory system MS to reduce the number of shift reads executed in Vth tracking.

[0125] Note that a process similar to step ST205 may be executed between steps ST210 and ST211. If it is confirmed in the process similar to step ST205 that the difference plot shows a V-shape, the Vth tracking processing unit 110 proceeds to the process of step ST211. If it is not confirmed in the process similar to step ST205 that the difference plot shows a V-shape, the Vth tracking processing unit 110 proceeds to the process of step ST206, for example.

[0126] In addition, the difference between the difference DN1 and the difference DN2 may be used for the comparison with the predetermined threshold in step ST208. In this case, the difference between the difference DN1 and the difference DN2 is calculated by "DN1-DN2" or "DN2-DN1".

[0127] (1: Specific example of the process of steps ST207 to ST209) FIG. 19 is a schematic diagram showing a specific example of the processes of steps ST207 to ST209 described with reference to FIG. 18. FIG. 19 shows difference plots corresponding to the (j - 1)-th (where j is an integer of 2 or more), j-th, (j + 1)-th, and (j + 2)-th shift reads executed while increasing the read level. As shown in FIG. 19, in the (j - 1)-th, j-th, (j + 1)-th, and (j + 2)-th shift reads, read levels RL(j - 1), RL(j), RL(j + 1), and RL(j + 2) are used respectively. The relationship of the heights of the read levels is RL(j - 1) < RL(j) < RL(j + 1) < RL(j + 2). The difference in the number of on-cells corresponding to each of the (j - 1)-th and j-th shift reads is N3 (difference plot D(j - 1)). The difference in the number of on-cells corresponding to each of the j-th and (j + 1)-th shift reads is N1 (difference plot D(j)). The difference in the number of on-cells corresponding to each of the (j + 1)-th and (j + 2)-th shift reads is N2 (difference plot D(j + 1)). The relationship of the magnitudes of the differences in the number of on-cells is N1 < N2 < N3.

[0128] The Vth tracking processing unit 110 detects, for example, that the valley position of the difference plot corresponds to the difference plot D(j) based on the fact that N1 - N3 is negative and N2 - N1 is positive. In this case, the difference DN1 corresponds to N3 - N1. The difference DN2 corresponds to N2 - N1. In this example, since the difference DN1 is larger than the difference DN2, the Vth tracking processing unit 110 detects that the gradient of the threshold voltage distribution is steeper for the difference plots D(j - 1) to D(j) than for the difference plots D(j) to D(j + 1). Thereafter, when the absolute value of the difference between DN1 and DN2 is larger than a predetermined threshold (ST208: NO), the Vth tracking processing unit 110 changes the Vth tracking parameter by the same algorithm as in the first embodiment (ST209).

[0129] (2: Specific Example of Command Sequence) Fig. 20 is a table showing an example of a command sequence used in the memory system MS according to the second embodiment. As shown in Fig. 20, the memory system MS uses, for example, command sets CS1 to CS3. The command sets CS1 to CS3 are command sets used in the shift read executed in the process of step ST202 described with reference to Fig. 18.

[0130] The command set CS1 includes, for example, “aah”, “ADD(LUN)”, “ADD(AAh)”, and “DAT1”. “aah” is a command that instructs the specification of a read level used in a shift read. “ADD(LUN)” is a logical unit number (LUN) for which a read level is specified. When the memory system MS includes a plurality of memory devices 2, the logical unit number is assigned to each of the plurality of memory devices 2. “ADD(AAh)” is an address of a register that stores the setting of the read level. “DAT1” is information indicating the shift amount of the read level. “DAT1” includes, for example, a DAC value corresponding to the shift amount. When the memory device 2 receives “aah”, “ADD(LUN)”, “ADD(AAh)”, and “DAT1” from the memory controller 1 in this order, it transitions to a busy state and sets the parameter “DAT1” in the register specified by “ADD(LUN)” and “ADD(AAh)”. When the setting of the parameters is completed, the memory device 2 transitions to the ready state. The time tFEAT is the time for the memory device 2 to execute the process based on the command set CS1.

[0131] The command set CS2 includes, for example, "01h / 02h / 03h", "00h", "ADD(CUsel)", and "30h". "01h / 02h / 03h" is a command that specifies the page data to be read. For example, "01h", "02h", and "03h" correspond to lower page data, middle page data, and upper page data, respectively. "00h" is a command that instructs a read operation. "ADD(CUsel)" is the address of the cell unit CU to be read. "30h" is a command that instructs the start of a read operation. When the memory device 2 receives "01h / 02h / 03h", "00h", "ADD(CUsel)", and "30h" in this order from the memory controller 1, it transitions to a busy state and executes a read operation of the page data specified by "01h / 02h / 03h" from the cell unit CU specified by "ADD(CUsel)". When the read operation is completed, the memory device 2 transitions to a ready state. Time tR is the time for the memory device 2 to execute processing based on command set CS2.

[0132] The command set CS3 includes, for example, "bbh", "ADD(CUsel)", and "E0h". "bbh" is a command that specifies the transfer of data stored in the data register 28 by a read operation such as a shift read. "E0h" is a command that specifies the start of data transfer. When the memory device 2 receives "bbh", "ADD(CUsel)", and "E0h" in this order from the memory controller 1, it outputs the data stored in the data register 28 to the memory controller 1 (Data-out).

[0133] In the process of step ST202, the command set CS1 used for setting parameters for the shift read may be issued for each state when a read operation is executed for a plurality of states.

[0134] <2-3> Effects of the second embodiment As described above, the memory system MS according to the second embodiment can detect the gradient near the valley position of the threshold voltage distribution of adjacent states. In the second embodiment, a combination of Vth tracking parameters is selected from at least two or more pairs using the start value table 121 and the step value table 122.

[0135] As a result, the memory system MS according to the second embodiment can change the step value in Vth tracking according to the gradient of the threshold voltage distribution before and after the valley position, similar to the first embodiment. That is, the memory system MS according to the second embodiment can bring the optimum read level estimated by Vth tracking closer to the actual optimum read level, similar to the first embodiment. Therefore, the memory system MS according to the second embodiment can reduce the number of error bits and obtain high reliability, similar to the first embodiment.

[0136] In the second embodiment, the Vth tracking parameters may be changed depending on the comparison result of the magnitude of the gradient near the valley position of the threshold voltage distribution, and the Vth tracking may be retried. This allows the memory system MS according to the second embodiment to estimate the optimal read level with higher accuracy than the first embodiment.

[0137] <2-4> Modification of the second embodiment Fig. 21 is a flowchart showing an example of a procedure of a modified example of Vth tracking executed in the memory system according to the second embodiment. The procedure shown in the flowchart of Fig. 21 has a configuration in which the processes of steps ST207 and ST208 in the procedure shown in the flowchart of Fig. 18 are replaced with processes of steps ST220 and ST221, respectively.

[0138] In the process of step ST220, the Vth tracking processing unit 110 calculates a difference DN1 between the minimum value of the obtained differences and the difference immediately before it, and a difference DN2 between the minimum value and the difference immediately after it, and calculates a ratio between the difference DN1 and the difference DN2 (ST220). Then, the Vth tracking processing unit 110 checks whether the absolute value of the ratio between the difference DN1 and the difference DN2 (|DN1 / DN2|) is within a predetermined range (ST221). Specifically, in the process of step S221, it is checked whether the absolute value of the ratio between the difference DN1 and the difference DN2 (|DN1 / DN2|) is between a first threshold value TH1 and a second threshold value TH2. The first threshold value TH1 is, for example, 0.75. The second threshold value TH2 is, for example, 1.33. The closer the absolute value of this ratio is to 1, the more preferable the Vth tracking parameters have been set in the multiple shift reads executed in step ST202. A plurality of threshold ranges may be set for the absolute value of this ratio. If it is confirmed in the process of step ST221 that the absolute value of the ratio between the difference DN1 and the difference DN2 is within a predetermined range (ST221: YES), the Vth tracking processing unit 110 proceeds to the process of step ST211. If it is confirmed in the process of step ST221 that the absolute value of the ratio between the difference DN1 and the difference DN2 is outside the predetermined range (ST221: NO), the Vth tracking processing unit 110 proceeds to the process of step ST209.

[0139] Other processes of the modified Vth tracking shown in Fig. 21 are similar to those shown in Fig. 18. The modified Vth tracking performed in the second embodiment can estimate the optimum read level with high accuracy, like the Vth tracking performed in the second embodiment.

[0140] <3> Third embodiment The memory system MS according to the third embodiment is configured to perform Vth tracking similar to that of the second embodiment, and further has a function of selecting a Vth tracking parameter based on an operation log. Details of the memory system MS according to the third embodiment will be described below, focusing on differences from the first and second embodiments.

[0141] <3-1> Configuration First, the configuration of the memory system MS according to the third embodiment will be described. The hardware configuration of the memory system MS according to the third embodiment is the same as that of the first embodiment. Below, the functional configuration of the memory system MS according to the third embodiment will be described.

[0142] Fig. 22 is a block diagram showing an example of a functional configuration of a memory system MS according to the third embodiment. As shown in Fig. 22, the memory controller 1 according to the third embodiment has a Vth tracking processing unit 110a, a parameter storage unit 120a, and an operation log storage unit 130. The peripheral circuit 220 of the memory device 2 according to the third embodiment has a shift read processing unit 221 similar to that of the second embodiment.

[0143] The Vth tracking processing unit 110a has the same function as the Vth tracking processing unit 110 described in the second embodiment. Furthermore, the Vth tracking processing unit 110a refers to the Vth tracking parameters stored in the parameter storage unit 120 based on the operation log of the memory device 2 recorded in the operation log storage unit 130. From the operation log of the memory device 2, a change in the gradient of the threshold voltage distribution can be estimated. Then, the Vth tracking processing unit 110a determines the start read level and the step value to be used in Vth tracking based on the start value table 121 and the step value table 122 associated with the operation log, respectively.

[0144] The parameter storage unit 120a stores a start value table set 140 and a step value table set 150. The start value table set 140 includes a plurality of start value tables 121. Each of the plurality of start value tables 121 is associated with a numerical value that may be indicated by the operation log. The plurality of start value tables 121 includes information on a start read level suitable for a gradient of a threshold voltage distribution estimated from a numerical value of the associated operation log. The step value table set 150 includes a plurality of step value tables 122. Each of the plurality of step value tables 122 is associated with a numerical value that may be indicated by the operation log. The plurality of step value tables 122 includes information on a step value suitable for a gradient of a threshold voltage distribution estimated from a numerical value of the associated operation log. The configurations of the start value table 121 and the step value table 122 are, for example, similar to those of the second embodiment.

[0145] The operation log storage unit 130 stores an operation log of the memory system MS. The operation log storage unit 130 records, for example, the number of write / erase operations, the data retention period, and the number of read operations according to the operation of the memory system MS. The number of write / erase operations corresponds to the number of times a set of a write operation and an erase operation has been executed. The number of write / erase operations may be managed in units of blocks BLK, or in units of chips, pages, or cell units CU. The data retention period corresponds to the elapsed time since data has been written to a cell unit CU in an erased state. The number of read operations corresponds to the number of times a read operation has been executed since data was written.

[0146] When the number of write / erase operations, the number of read operations, or the data retention period increases, the gradient of the threshold voltage distribution may change. For example, as the data retention period of the cell unit CU progresses, the threshold voltage distribution in each state becomes wider toward the low voltage side. Conversely, as the number of write / erase operations and read operations increases, the threshold voltage distribution in each state becomes wider toward the high voltage side. Therefore, due to stress on the cell unit CU, adjacent threshold voltage distributions may become asymmetrical distributions having different gradients.

[0147] The operation log of the memory system MS may include other information, such as the number of times Vth tracking has been performed, the operating temperature of the memory system MS, or the operating time of the memory system MS.

[0148] Each of the multiple start value tables 121 and multiple step value tables 122 stored in the parameter storage unit 120a may be provided according to, for example, the number of writes / erases, the data retention period, or the number of reads. That is, the parameter storage unit 120a may store multiple tables for changing the Vth tracking parameter using the number of writes / erases as a trigger, may store multiple tables for changing the Vth tracking parameter using the data retention period as a trigger, or may store multiple tables for changing the Vth tracking parameter using the number of reads as a trigger. In each step value table 122, multiple different step values ​​may be set, as in the first embodiment. It is preferable that the multiple step values ​​are set so as to correspond to the shape of the threshold voltage distribution. Each of the start value table 121 and the step value table 122 may be a table including a read level for the operation log of the memory system MS.

[0149] Here, as a more specific example, a case where the Vth tracking parameter is changed using the number of write / erase operations as a trigger, that is, a case where the Vth tracking parameter is changed before and after the number of write / erase operations reaches a threshold will be described. When the number of write / erase operations increases, the threshold voltage distribution may be distributed widely on the high potential side in each state as described above. In this case, the threshold voltage distribution of the adjacent states may be a distribution in which one side (the high potential side) is steep and the other side (the low potential side) is gentle, with the valley position of the adjacent state as a boundary. When the number of write / erase operations for the cell unit CU increases, for example, the distribution of the S0 state, which is the state on the low potential side of the threshold voltage distribution, may be distributed widely on the high potential side. At this time, compared to the distribution on the low potential side of the S1 state, which is the adjacent state, the distribution on the high potential side of the S0 state has a relatively gentle gradient. For this reason, the threshold voltage distribution composed of the S0 state and the S1 state becomes an asymmetric distribution, and the optimum read level (RTRK) estimated by Vth tracking deviates from the actual optimum read level (RBST). In contrast, the memory system MS according to the present embodiment sets a set of step values ​​such that the step value on the S1 state side, where the gradient of the threshold voltage distribution is relatively steep, is relatively small, and the step value on the S0 state side, where the gradient of the threshold voltage distribution is relatively gentle, is relatively large. This improves the estimation accuracy of the optimum read level (RTRK) estimated by Vth tracking. In this way, the memory system MS according to the present embodiment, like the second embodiment, can search for the threshold voltage distribution with high accuracy by reducing the step value on the low potential side in the state adjacent to the high potential side and increasing the step value on the high potential side in the state adjacent to the low potential side.

[0150] Next, a case where the Vth tracking parameter is changed by using the data retention period as a trigger, that is, a case where the Vth tracking parameter is changed before and after the data retention period reaches a threshold will be described. When the data retention period increases, for example, the threshold voltage distribution on the high potential side (for example, S6-S7 state) may become a shape that is widely distributed on the low potential side. The influence of the data retention period may be noticeable, for example, in the S6 state and the S7 state. Specifically, when the data retention period for the cell unit CU increases, the distribution of the S7 state, which is the state on the high potential side of the threshold voltage distribution, becomes widely distributed on the low potential side. At this time, compared with the distribution on the high potential side of the S6 state, which is the adjacent state, the distribution on the low potential side of the S7 state has a relatively gentle gradient. For this reason, the threshold voltage distribution composed of the S6 state and the S7 state becomes an asymmetric distribution, and the optimum read level (RTRK) estimated by Vth tracking deviates from the actual optimum read level (RBST). In contrast, the memory system MS according to the present embodiment can improve the estimation accuracy of the optimum read level (RTRK) estimated by Vth tracking by setting a set of step values ​​such that the step value on the S6 state side, where the gradient of the threshold voltage distribution is relatively steep, is relatively small, and the step value on the S7 state side, where the gradient of the threshold voltage distribution is relatively gentle, is relatively large. That is, the memory system MS according to the present embodiment can search for the threshold voltage distribution with high accuracy by decreasing the step value on the high potential side in the adjacent state on the low potential side, and increasing the step value on the low potential side in the adjacent state on the high potential side.

[0151] Next, a case where the Vth tracking parameter is changed by using the number of reads as a trigger, that is, a case where the Vth tracking parameter is changed before and after the number of reads reaches a threshold value, will be described. When the number of reads increases, for example, the threshold voltage distribution may be a shape that is widely distributed on the high potential side in each state. In this case, the threshold voltage distribution of the adjacent states may be a distribution in which the gradient on one side (high potential side) is steep and the gradient on the other side (low potential side) is gentle, with the valley position of the adjacent state as a boundary. When the number of reads for the cell unit CU increases, for example, the distribution of the S0 state, which is the state on the low potential side of the threshold voltage distribution, is widely distributed on the high potential side. At this time, compared with the distribution on the low potential side of the S1 state, which is the adjacent state, the distribution on the high potential side of the S0 state has a relatively gentle gradient. For this reason, the threshold voltage distribution composed of the S0 state and the S1 state becomes an asymmetric distribution, and the optimum read level (RTRK) estimated by Vth tracking deviates from the actual optimum read level (RBST). In contrast, the memory system MS according to this embodiment can improve the estimation accuracy of the optimum read level (RTRK) estimated by Vth tracking by setting a set of step values ​​such that the step value on the S1 state side, where the gradient of the threshold voltage distribution is relatively steep, is relatively small, and the step value on the S0 state side, where the gradient of the threshold voltage distribution is relatively gentle, is relatively large. In this way, the memory system MS according to this embodiment can search for the threshold voltage distribution with high accuracy by reducing the step value on the low potential side in the state adjacent to the high potential side and increasing the step value on the high potential side in the state adjacent to the low potential side.

[0152] The start value table set 140 and the step value table set 150 may be set for each stress condition such as the number of write / erase operations, the data retention time, and the number of read operations. This allows a different start value table 121 and step value table 122 to be selected for each stress condition. The memory system MS may use a combination of different start value table sets 140 and step value table sets 150 for each stress condition.

[0153] It is desirable that index numbers are assigned according to, for example, the range of the number of write / erase operations in the start value table 121 and the step value table 122. By assigning a range of stress conditions to which the same Vth tracking parameter is applied to one index number, the memory system MS can select an optimal Vth tracking parameter for each stress condition.

[0154] <3-2> Operation Next, the operation of the memory system MS according to the third embodiment will be described.

[0155] FIG. 23 is a flowchart showing an example of a procedure for setting initial parameters for Vth tracking executed in the memory system MS according to the third embodiment.

[0156] 18 starts (START), the Vth tracking processing unit 110a checks the stress state by referring to the operation log stored in the operation log storage unit 130 (ST301). The operation log referred to in the process of step ST301 includes information on, for example, the number of writes / erases, the data retention period, or the number of reads.

[0157] Next, the Vth tracking processing unit 110a selects the start value table 121 according to the current stress state from the start value table set 140 (ST302). Also, the Vth tracking processing unit 110a selects the step value table 122 according to the current stress state from the step value table set 150 (ST303). For example, the first start value table 121 and the first step value table 122 are selected when the number of write / erase operations is less than the first threshold, and the second start value table 121 and the second step value table 122 are selected when the number of write / erase operations is equal to or greater than the first threshold. Similarly, the third start value table 121 and the third step value table 122 may be selected when the data retention period is less than the second threshold, and the fourth start value table 121 and the fourth step value table 122 may be selected when the data retention period is equal to or greater than the second threshold. Similarly, the fifth start value table 121 and the fifth step value table 122 may be selected when the number of reads is less than the third threshold, and the sixth start value table 121 and the sixth step value table 122 may be selected when the data retention period is greater than or equal to the third threshold.

[0158] When the process of step ST303 is completed, the series of processes included in step ST201 ends (END), and the Vth tracking processing unit 110a proceeds to the process of step ST202 described with reference to Fig. 18. Other operations of the memory system MS according to the third embodiment are similar to those of the second embodiment.

[0159] The order of the process of step ST302 and the process of step ST303 may be interchanged. The process of step ST302 and the process of step ST303 may be executed in parallel. The threshold value of the operation log used to select the start value table 121 and the threshold value of the operation log used to select the step value table 122 may be different from each other. Furthermore, each of the start value table set 140 and the step value table set 150 may be managed in units of a single or multiple chips or in units of a single or multiple blocks.

[0160] <3-3> Effects of the third embodiment The threshold voltage distribution of the memory cell transistor MT has a tendency according to the stress state. Therefore, the memory system MS according to the third embodiment monitors the stress state of the memory device 2 by referring to the operation log. Then, the memory system MS according to the third embodiment changes the initial value of the Vth tracking parameter (at least one of the starting read level and the step value) based on the operation log. As a result, the memory system MS according to the third embodiment can improve the accuracy of estimating the optimum read level in the first Vth tracking. Therefore, the memory system MS according to the third embodiment can reduce the number of error bits and obtain high reliability.

[0161] Moreover, the memory system MS according to the third embodiment can reduce the possibility of performing the processes of steps ST209 and ST210 described with reference to the respective flowcharts of Figures 18 and 21 by applying a Vth tracking parameter based on an operation log. That is, the memory system MS according to the third embodiment can suppress an increase in the time required for estimating the optimum read level, and can improve the performance of the memory system MS.

[0162] <4> Fourth embodiment In the memory system MS according to the fourth embodiment, the memory device 2 is configured to execute a part of the Vth tracking process similar to that of the first embodiment based on an instruction from the memory controller 1. Details of the memory system MS according to the fourth embodiment will be described below, focusing on the differences from the first to third embodiments.

[0163] <4-1> Configuration First, the configuration of the memory system MS according to the fourth embodiment will be described. The hardware configuration of the memory system MS according to the fourth embodiment is the same as that of the first embodiment. Below, the functional configuration of the memory system MS according to the fourth embodiment will be described.

[0164] Fig. 24 is a block diagram showing an example of a functional configuration of a memory system MS according to the fourth embodiment. As shown in Fig. 24, the memory controller 1 according to the fourth embodiment has a Vth tracking processing unit 110b and a parameter storage unit 120b. The peripheral circuit 220 of the memory device 2 according to the fourth embodiment has a shift read processing unit 221 and an on-chip Vth tracking processing unit 222. The configuration of the shift read processing unit 221 of the fourth embodiment is similar to that of the second embodiment.

[0165] The on-chip Vth tracking processing unit 222 is a functional block that executes processing related to Vth tracking including at least a search read. The search read is a read operation using multiple read levels that the memory device 2 executes based on a predetermined command set. The on-chip Vth tracking processing unit 222 can execute processing corresponding to multiple shift reads of the Vth tracking described in the first to third embodiments at once. Then, the on-chip Vth tracking processing unit 222 can calculate a detected search number and an adjustment coefficient based on the read result using multiple read levels. The detected search number is information on a read level corresponding to the minimum value of the difference between the number of on-cells obtained by the read result using multiple read levels. The adjustment coefficient is information corresponding to, for example, the difference between the read level corresponding to the detected search number and the optimal read level. The on-chip Vth tracking processing unit 222 can change the setting of the read level used in the search read based on an instruction from the Vth tracking processing unit 110b.

[0166] The Vth tracking processing unit 110b has a function of estimating an optimal read level taking into consideration the asymmetry of the threshold voltage distribution of the memory cell transistor MT. For example, the Vth tracking processing unit 110b first transmits an optimal read level estimation request using a step value corresponding to the symmetrical threshold voltage distribution of the adjacent states to the on-chip Vth tracking processing unit 222. Then, the Vth tracking processing unit 110b changes the start read level of the Vth tracking based on the estimation result of the optimal read level executed by the on-chip Vth tracking processing unit 222. Then, the Vth tracking processing unit 110b transmits an optimal read level estimation request using a step value corresponding to the asymmetrical threshold voltage distribution of the adjacent states to the on-chip Vth tracking processing unit 222.

[0167] The Vth tracking processing unit 110b includes an ECC processing unit 111. The ECC processing unit 111 includes an ECC circuit 13. The ECC processing unit 111 executes a decoding process on the page data received from the shift read processing unit 221. When the decoding process by the ECC processing unit 111 is successful, the Vth tracking processing unit 110b outputs the corrected page data to the host device HD. On the other hand, even when the decoding process by the ECC processing unit 111 fails, the Vth tracking processing unit 110b changes the start read level and step value of the Vth tracking and transmits an optimal read level estimation request to the on-chip Vth tracking processing unit 222.

[0168] The parameter storage unit 120b stores a start value table 121 and a step value table 123. The configuration of the start value table 121 is the same as that of the second embodiment described with reference to FIG. 16, for example, and is used to set the start read level of the search read. The step value table 123 stores information on multiple step values ​​used in the search read for each adjacent state that can be the target of the search read. The step values ​​stored in the step value table 123 are preset according to, for example, information related to the gradient of the adjacent states.

[0169] (Specific example of step value table 123) FIG. 25 is a diagram showing an example of a step value table 123 stored in the parameter storage unit 120b of the memory controller 1 included in the memory system MS according to the fourth embodiment. As shown in FIG. 25, the step value table 123 stores, for example, two step values ​​SSa and SSb used in search reads in the S0-S1 state, the S1-S2 state, ..., and the S6-S7 state for each index value (for example, #0 to #4). The step value is expressed, for example, as a DAC value. The step value SSa is a step value used to set a read level in the first half (for example, on the low voltage side) of a plurality of read levels used in the search read. The step value SSb is a step value used to set a read level in the second half (for example, on the high voltage side) of a plurality of read levels used in the search read. The switching points of the step values ​​SSa and SSb are specified, for example, by a command set from the memory controller 1. The median value of the number of searches specified by the command set from the memory controller 1 may be set as the switching point.

[0170] The index value #0 in the step value table 123 corresponds to a symmetrical threshold voltage distribution of adjacent states. The index values ​​#1 and on in the step value table 123 correspond to asymmetrical threshold voltage distribution of adjacent states.

[0171] Specifically, in the row with index value #0, SSa=8 and SSb=8 are associated with each of a plurality of fields associated with the S0-S1 state, the S1-S2 state, the S5-S6 state, and the S6-S7 state. In the row with index value #1, the step value SSb of the S0-S1 state and the step value SSa of the S6-S7 state are each changed to 4 for the row with index value #0. In the row with index value #2, the step value SSb of the S1-S2 state and the step value SSa of the S5-S6 state are each changed to 4 for the row with index value #1. In the row with index value #3, the step value SSa of the S0-S1 state and the step value SSb of the S5-S6 state are each changed to 16 for the row with index value #2. In the row with index value #4, the step value SSa of the S1-S2 states and the step value SSb of the S6-S7 states are changed to 16, respectively, with respect to the row with index value #3.

[0172] In this way, in the step value table 123, symmetrical step values ​​SSa and SSb are set in the row of index value #0 in all adjacent states, and asymmetrical step values ​​SSa and SSb are set in at least some adjacent states in the row of index value #1 and after. In addition, in the step value table 123, the step values ​​SSa and SSb in the S2-S3 state, the S3-S4 state, and the S4-S5 state are set to "n / a" in the row of all index values. Here, "n / a" means that a search read using one type of step value is executed. However, in each of the S2-S3 state, the S3-S4 state, and the S4-S5 state, a search read using multiple step values ​​different from each other may be executed. The adjacent states to which a search read using multiple step values ​​different from each other is applied and the adjacent states to which a search read using one type of step value is applied can be appropriately changed according to the gradient of the expected threshold voltage distribution.

[0173] <4-2>Operation Next, the operation of the memory system MS according to the fourth embodiment will be described.

[0174] FIG. 26 is a flowchart showing an example of a procedure of Vth tracking executed in the memory system according to the fourth embodiment.

[0175] The memory system MS starts (starts) the series of processes in FIG. 26, for example, when an error correction of data read from the memory device 2 in a read operation fails, or based on a predetermined schedule.

[0176] First, the Vth tracking processing unit 110b sets the index value to a value #0 corresponding to the symmetrical threshold voltage distribution of adjacent states (ST401).

[0177] Next, the Vth tracking processing unit 110b estimates the optimum read level assuming symmetry (ST402). In the process of step ST402, the Vth tracking processing unit 110b causes the memory device 2 to execute a search read using parameters corresponding to the index value #0 in the start value table 121 and the step value table 123, and causes the memory device 2 to estimate the optimum read level without considering asymmetry.

[0178] Next, the Vth tracking processing unit 110b increments the index value in the step value table 123 (ST403).

[0179] Next, the Vth tracking processing unit 110b estimates an optimum read level taking into consideration the asymmetry of the threshold voltage distribution (ST404). In the process of step ST404, the Vth tracking processing unit 110b causes the memory device 2 to execute a search read using, for example, a step value corresponding to the index value #1 in the step value table 123 and a start read level at which the optimum read level estimated by the process of step ST402 and the switching point of this step value coincide with each other.

[0180] Next, the Vth tracking processing unit 110b executes a page read using the estimated optimum read level (ST405). In the process of step ST405, the Vth tracking processing unit 110b causes the memory device 2 to execute a page read using the optimum read level estimated by the process of step ST404.

[0181] Next, the Vth tracking processing unit 110b checks whether or not the error correction on the page data obtained by the page read in step ST405 has been successful (ST406).

[0182] If it cannot be confirmed that the error correction has been successful in the process of step ST406, that is, if the error correction has failed (ST406: NO), the Vth tracking processing unit 110b proceeds to the process of step ST403. That is, the Vth tracking processing unit 110b executes the processes of steps ST404 to ST406 again using the parameters corresponding to the incremented index value in the step value table 123.

[0183] If it is confirmed in the process of step ST406 that the error correction has been successful (ST406: YES), the Vth tracking processing unit 110b outputs the corrected page data to the host device HD (ST407).

[0184] (1: Specific example of the process of step ST402) FIG. 27 is a flowchart showing an example of a detailed procedure of the process in step ST402 described with reference to FIG.

[0185] When the process of step ST402 starts (START), the Vth tracking processing unit 110b of the memory controller 1 issues a setting request for search read parameters assuming symmetry associated with the current index value (#0) to the on-chip Vth tracking processing unit 222 (ST411). In the search read parameters included in the setting request for the process of step ST411, the step value SSa is equal to the step value SSb.

[0186] Next, the on-chip Vth tracking processing unit 222 of the memory device 2 sets the search read parameters based on the setting request (ST412). This allows a plurality of read levels based on one type of step value to be used in the search read.

[0187] Next, the Vth tracking processing unit 110b issues a search read request to the on-chip Vth tracking processing unit 222 (ST413). Then, the on-chip Vth tracking processing unit 222 executes a search read based on the search read request (ST414). In the search read in the process of step ST414, multiple read levels based on one type of step value are used. Also, the on-chip Vth tracking processing unit 222 acquires a detected search number and an adjustment coefficient based on the result of the search read.

[0188] Next, the on-chip Vth tracking processing unit 222 outputs the valley position information (detection search number and adjustment coefficient) acquired by the search read to the Vth tracking processing unit 110b (ST415).

[0189] Next, the Vth tracking processing unit 110b estimates the valley position (i.e., the optimum read level) of the threshold voltage distribution of the adjacent state based on the valley position information (ST416). When the process of step ST416 is completed, the series of processes included in step ST402 ends (END).

[0190] The estimation of the optimum read level in the process of step ST402 is not limited to the method using the search read by the on-chip Vth tracking processing unit 222 described above. As a method for estimating the optimum read level, multiple shift reads by the Vth tracking processing unit 110b may be used. In addition, the Vth tracking processing unit 110b may estimate the optimum read level using other means and proceed to the process of step ST403. In the process of step ST402, an index value may not be used. In this case, asymmetric step values ​​SSa and SSb may be set from the row of index value #0 in the step value table 123.

[0191] (2: Specific example of the process of step ST404) FIG. 28 is a flowchart showing an example of a detailed procedure of the process in step ST404 described with reference to FIG.

[0192] When the process of step ST404 starts (START), the Vth tracking processing unit 110b of the memory controller 1 issues a setting request for search read parameters that consider the asymmetry associated with the current index value to the on-chip Vth tracking processing unit 222 (ST421). In the search read parameters included in the setting request of the process of step ST421, the step value SSa and the step value SSb are different from each other. In addition, the Vth tracking processing unit 110b sets the start read level so that the switching point of the step values ​​SSa and SSb coincides with the optimal read level estimated by the process of step ST402 described with reference to FIG. 26. The setting of the start read level will be described later in detail.

[0193] Next, the on-chip Vth tracking processing unit 222 of the memory device 2 sets the search read parameters based on the setting request (ST422). This allows a plurality of read levels based on a plurality of different step values ​​to be used in the search read.

[0194] Next, the Vth tracking processing unit 110b issues a search read request to the on-chip Vth tracking processing unit 222 (ST423). Then, the on-chip Vth tracking processing unit 222 executes a search read based on the search read request (ST424). In the search read in the process of step ST424, a plurality of read levels based on a plurality of different step values ​​may be used. Also, the on-chip Vth tracking processing unit 222 acquires a detection search number and an adjustment coefficient based on the result of the search read.

[0195] Next, the on-chip Vth tracking processing unit 222 outputs the valley position information (detection search number and adjustment coefficient) acquired by the search read to the Vth tracking processing unit 110b (ST425).

[0196] Next, the Vth tracking processing section 110b estimates the optimum read level based on the valley position information (ST426). When the process of step ST426 is completed, the series of processes included in step ST404 ends (END).

[0197] (3: Specific example of the process of step ST405) FIG. 29 is a flowchart showing an example of a detailed procedure of the process in step ST405 described with reference to FIG.

[0198] When the process of step ST405 starts (START), the Vth tracking processing unit 110b of the memory controller 1 issues a setting request for the page read parameters to which the estimated optimum read level is applied to the shift read processing unit 221 (ST431). This optimum read level is based on the result of the process of step ST426 that was most recently executed. In the process of step ST431, for example, the command set CS1 shown in FIG. 20 is used.

[0199] Next, the shift read processing unit 221 of the memory device 2 sets parameters based on the setting request (ST432). As a result, the optimal read level based on the result of Vth tracking is used in the page read.

[0200] Next, the Vth tracking processing unit 110b issues a page read request to the shift read processing unit 221 (ST433). In the process of step ST433, for example, the command set CS2 shown in FIG. 20 is used. Then, the shift read processing unit 221 executes a page read based on the page read request (ST434). In the page read in the process of step ST434, an optimal read level based on the result of Vth tracking is used. The page data acquired by this page read is stored in, for example, the data register 28.

[0201] Next, the shift read processing unit 221 outputs the page data acquired by the page read to the Vth tracking processing unit 110b (ST435). In the process of step ST435, for example, the command set CS3 shown in FIG. 20 is used. Then, the ECC processing unit 111 of the Vth tracking processing unit 110b executes an error correction process on the page data read by the process of step ST435 (ST436). When the process of step ST436 is completed, the series of processes included in step ST405 ends (END).

[0202] (4: Example of command sequence) FIG. 30 is a table showing an example of a command sequence used in the memory system MS according to the fourth embodiment. As shown in FIG. 30, the memory system MS may use command sets CS4 to CS8 in addition to command sets CS1 to CS3 described with reference to FIG. 20. The command sets CS4 to CS6 are used in a search read parameter setting request in the process of ST411 in FIG. 27 or ST421 in FIG. 28. The command set CS7 is used in a search read request in the process of ST413 in FIG. 27 or ST423 in FIG. 28. The command set CS8 is used in a valley position information output request in the process of ST415 in FIG. 27 or ST425 in FIG. 28.

[0203] The command set CS4 includes, for example, "cch", "ADD(LUN)", "ADD(BBh)", and "DAT2". "cch" is a command requesting a change in search read parameters. "ADD(BBh)" is the address of a register that stores the setting of the start read level used in the search read. "DAT2" includes a parameter corresponding to the start read level of the search read to be newly set. When the memory device 2 receives "cch", "ADD(LUN)", "ADD(BBh)", and "DAT2" from the memory controller 1 in this order, it transitions to a busy state and sets the parameter "DAT1" in the register specified by "ADD(LUN)" and "ADD(BBh)". When the parameter setting is completed, the memory device 2 transitions to a ready state. The time tFEAT indicates the time for the memory device 2 to execute the process based on the command set CS4.

[0204] The command set CS5 has a configuration in which "ADD(BBh)" is replaced with "ADD(CCh)" and "DAT2" is replaced with "DAT3" compared to the command set CS4. "ADD(CCh)" is, for example, the address of a register that stores the step value SSa of the search read and the number of searches in the first half (for example, the number of shift reads to which the step value SSa is applied). "DAT3" includes, for example, parameters corresponding to the newly set step value SSa of the search read and the number of searches in the first half. When the memory device 2 receives "cch", "ADD(LUN)", "ADD(CCh)", and "DAT3" from the memory controller 1 in this order, it sets the parameter "DAT3" in the register specified by "ADD(LUN)" and "ADD(CCh)".

[0205] The command set CS6 has a configuration in which "ADD(BBh)" is replaced with "ADD(DDh)" and "DAT2" is replaced with "DAT4" compared to the command set CS4. "ADD(DDh)" is the address of a register that stores the search read step value SSb and the latter half of the search count (for example, the number of shift reads to which the step value SSb is applied). "DAT4" includes parameters corresponding to the newly set search read step value SSb and the latter half of the search count. When the memory device 2 receives "cch", "ADD(LUN)", "ADD(DDh)", and "DAT4" from the memory controller 1 in this order, it sets the parameter "DAT4" in the register specified by "ADD(LUN)" and "ADD(DDh)".

[0206] The command set CS7 includes, for example, “ddh”, “01h / 02h / 03h”, “00h”, “ADD(CUsel)”, and “30h”. “ddh” is a command requesting the execution of a search read. “ADD(CUsel)” is the address of the cell unit CU targeted for the search read. “30h” is a command instructing the start of a read operation. When the memory device 2 receives “ddh”, “01h / 02h / 03h”, “00h”, “ADD(CUsel)”, and “30h” in this order from the memory controller 1, it transitions to a busy state and executes a search read of the page data specified by “01h / 02h / 03h” to the address specified by “ADD(CUsel)”. When the search read is completed, the memory device 2 transitions to a ready state. Time tR indicates the time during which the memory device 2 executes a process based on the command set CS7.

[0207] The command set CS8 includes, for example, "eeh" and "ADD(EEh)". "eeh" is a command requesting output of data stored in a register. "ADD(EEh)" is the address of a register that stores the detection search number and adjustment coefficient obtained by the search read of ST414 in FIG. 27 or ST424 in FIG. 28. When the memory device 2 receives "eeh" and "ADD(EEh)" in this order from the memory controller 1, it outputs the detection search number and adjustment coefficient stored in the register specified by "ADD(EEh)" to the memory controller 1. Note that in ST414 in FIG. 27 and ST424 in FIG. 28, the detection search number and adjustment coefficient may be stored in the same register or in different registers.

[0208] Depending on the type of search read parameters to be set, only a part of the command sets CS4 to CS6 may be used in the process of ST411 in Fig. 27 or ST421 in Fig. 28. The command set CS used to set the search read parameters may be issued for each state when a read operation targeting a plurality of states is executed.

[0209] (5: Example of search lead operation) Fig. 31 is a diagram showing a specific example of a voltage applied to a word line WL selected as a target of a search read in a search read of the memory system MS according to the fourth embodiment. In the graph shown in Fig. 31, the horizontal axis indicates time, and the vertical axis indicates a voltage applied to the selected word line WL. This example shows a case where a search read is performed using seven types of read levels for each state. As shown in Fig. 31, in the search read in this example, a search read (S0-S1 state tracking) targeting the S0-S1 state and a search read (S4-S5 state tracking) targeting the S4-S5 state are performed consecutively.

[0210] In S0-S1 state tracking, read levels RL1(1) to RL7(7) are applied to the selected word line WL in this order. The read levels RL1(1) to RL1(7) correspond to the seven types of read levels associated with S0-S1 state tracking. The sequencer 24 asserts the control signal STB during each of the multiple periods during which the read levels RL1(1) to RL1(7) are applied, and causes the sense amplifier module 29 to determine the data. In S0-S1 state tracking, the interval between the read levels RL1(4) and RL1(5) is set as the switching point between the step values ​​SSa and SSb. Also, the step value set in S0-S1 state tracking is set to SSb>SSa.

[0211] In S4-S5 state tracking, read levels RL5(1) to RL5(7) are applied to the selected word line WL in this order. The read levels RL5(1) to RL5(7) correspond to seven types of read levels associated with S4-S5 state tracking. The sequencer 24 asserts the control signal STB during each of the multiple periods during which the read levels RL5(1) to RL5(7) are applied, and causes the sense amplifier module 29 to determine the data. The step value of S4-S5 state tracking is set to SSa=SSb based on the symmetry of the S4-S5 states. In other words, in S4-S5 state tracking, multiple different step values ​​are not applied, and one type of step value is used.

[0212] (6: Specific examples of processing search leads) Fig. 32 is a schematic diagram showing a specific example of a process of estimating an optimal read level in Vth tracking of the memory system MS according to the fourth embodiment. Fig. 32 shows the threshold voltage distribution of adjacent states (S(L-1) state and S(L) state) and the search read process. The search number (SN) indicates which shift read is being performed during the search read. The search number (0) corresponds to the start point of the search read. The start read level is used in the shift read at the start point of the search read.

[0213] As shown in FIG. 32, in this example, a search read is performed using eight kinds of read levels. The area between search numbers (4) and (5) is set as the switching point of step values ​​SSa and SSb. The parameters used in the search read are the start point offset SPO (Start Point Offset), step values ​​SSa and SSb, and the number of searches in the first half and second half. The information output by the memory device 2 based on the result of the search read is the detected search number and the adjustment coefficient. A specific example of the search read process is described below.

[0214] First, a read operation is started from a position (i.e., the start read level) specified by the start point offset SPO based on the default read level DRL. Next, a read operation with the read level shifted is executed the number of times corresponding to the number of searches. Specifically, in the first half of the number of searches, a read operation with the read level shifted by the step value SSa is executed. Then, in the second half of the number of searches, a read operation with the read level shifted by the step value SSb is executed. Here, the default read level DRL, the start point offset SPO, and the step values ​​SSa and SSb are specified by the DAC value.

[0215] Next, the difference BC between the number of ON cells in successive read operations is calculated. Next, the search number corresponding to the smallest difference BC(best) is obtained as the detection search number. For example, if the read operation at the start point offset SPO corresponds to search number (0) and the difference between search number (4) and search number (5) is BC(best), the detection search number is (4). Next, an internal division point calculation is performed using the differences BC(prev) and BC(next) before and after the difference BC(best), and is obtained as an adjustment coefficient. The adjustment coefficient is calculated, for example, by the following formula (1).

[0216]

number

[0217] The optimal read level (RTRK) obtained by the search read can be estimated based on the following formula (2) or (3). Note that when the step value corresponding to the difference BC(best) is SSa, formula (2) is used, and when it is SSb, formula (3) is used. Specifically, assuming that the step value between search numbers (3) and (4) is SSa, the step value between search numbers (4) and (5) is SSb, and the step value between search numbers (5) and (6) is SSb, formula (2) is used when the difference between search numbers (3) and (4) is BC(best), and formula (3) is used when the difference between search numbers (4) and (5) is BC(best).

[0218]

number

[0219]

number

[0220] For example, when DRL=30DAC, SPO=-20DAC, SSa=4DAC, Adjust Coefficient=1 / 2, Detected Search Number=2, and the step value corresponding to the difference BC(best) is SSa, RTRK is (30-20)+(2*4)+(1 / 2*4)=20DAC.

[0221] The start point offset SPO used in the search read (for example, the start read level used in the processing of step ST404 described with reference to FIG. 26) can be adjusted based on the following formula (4). Note that RTRK(#0) is the valley position obtained by the search read processing using search read parameters in which the step values ​​SSa and SSb are equal (for example, the optimal read level estimated in the processing of step ST402 described with reference to FIG. 26).

[0222]

number

[0223] For example, if RTRK(#0)=20DAC, SSa=4DAC, Searching Counts=10, and DRL=30DAC, SPO is 20-(4*10*1 / 2)-30=-30DAC.

[0224] <4-3> Effects of the fourth embodiment As described above, in the memory system MS according to the fourth embodiment, a plurality of combinations of the step values ​​SSa and SSb are prepared in advance. Then, in the memory system MS according to the fourth embodiment, when the error correction of the page data read using the optimum read level estimated based on the search read fails, the search read parameters are changed in the order of the index value and the shift read is retried. As a result, the memory system MS according to the fourth embodiment can improve the accuracy of the estimation of the optimum read level in Vth tracking. Therefore, the memory system MS according to the fourth embodiment can reduce the number of error bits and obtain high reliability.

[0225] Moreover, in the memory system MS according to the fourth embodiment, after estimating a valley position (i.e., an optimum read level) by a search read using one type of step value, the switching point of the search read step values ​​SSa and SSb is made to coincide with the valley position. This allows the memory system MS according to the fourth embodiment to improve the accuracy of estimation of the optimum read level based on Vth tracking, and thus improve reliability.

[0226] Furthermore, in the memory system MS according to the fourth embodiment, the memory device 2 can execute a read operation using a plurality of read levels based on a search read request received from the memory controller 1. Therefore, in the memory system MS according to the fourth embodiment, the exchange of commands and the like between the memory controller 1 and the memory device 2 required for Vth tracking can be reduced compared to the first to third embodiments. Therefore, the memory system MS according to the fourth embodiment can improve performance compared to the first to third embodiments.

[0227] In the fourth embodiment, the case where two step values ​​SSa and SSb are set is exemplified, but three or more step values ​​may be set for the search read. The switching point of the step values ​​SSa and SSb is not limited to the center of the number of searches, and may be switched at a point other than the center of the number of searches. The formulas described in the fourth embodiment are merely examples. A coefficient or offset may be added according to the characteristics of the memory cell transistor MT. The start point of the search read may be changed as appropriate based on specified information. A fixed value may be selected as the start point of the search read.

[0228] <5> others The functional configuration of the memory controller 1 described in the second to fourth embodiments may be realized by firmware executed by the CPU 12 in the hardware configuration of the memory controller 1 described in the first embodiment. The functional configuration of the memory device 2 described in the second to fourth embodiments may be realized by a function assigned to the sequencer 24 in the hardware configuration of the memory device 2 described in the first embodiment. An MPU (Micro Processing Unit) may be used instead of the CPU 12. Each of the processes described in the above embodiments may be executed by a dedicated hardware circuit, a processor that executes a program (firmware), or a combination of these.

[0229] The command sequence illustrated in the above embodiment is merely an example. The address information (ADD) transmitted from the memory controller 1 to the memory device 2 may be one cycle or multiple cycles.

[0230] The flowcharts used in the above embodiments are merely examples. The order of the processes described using the flowcharts may be changed as far as possible. Other processes may be added to the processes shown in the flowcharts, or some processes may be omitted.

[0231] In this specification, "connection" refers to being electrically connected, and does not exclude, for example, the presence of another element therebetween. "Electrically connected" may be via an insulator as long as it can operate in the same way as something electrically connected. Word lines WL, select gate lines SGD and SGS, etc. may be simply called "wiring".

[0232] A high-level voltage is a voltage at which an N-type transistor having a voltage of that level applied to its gate is turned on. A low-level voltage is a voltage at which an N-type transistor having a voltage of that level applied to its gate is turned off. In this specification, application of a voltage to a word line WL corresponds to the driver circuit 26 applying a voltage to the word line WL via the row decoder module 27. Application of a voltage to other wirings also corresponds to the driver circuit 26 applying a voltage via the row decoder module 27, similar to the word line WL. The voltage of each wiring may be estimated based on the voltage of a signal line connecting the driver circuit 26 and the row decoder module 27.

[0233] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0234] 1...memory controller, 2...memory device, 10...host interface circuit, 11...memory interface circuit, 12...CPU, 13...ECC circuit, 14...ROM, 15...RAM, 16...buffer memory, 20...memory cell array, 21...input / output circuit, 22...logic controller, 23...register circuit, 24...sequencer, 25...ready / busy controller, 26...driver circuit, 27...row decoder module, 28...data register, 29...sense amplifier module, 110...Vth tracking processing unit, 111...ECC processing unit, 120...parameter storage unit, 121...start value table, 122...step value table, 123...step value table, 130...operation log storage unit, 140...start value table set, 150...step value table set, 210...core circuit, 220...peripheral circuit, 221...shift read processing unit, 222...on-chip Vth tracking processing unit, BL...bit line, WL...word line, SGD, SGS...select gate line, BLK...block, SU...string unit, CU...cell unit, MT...memory cell transistor, CS...command set, DN1, DN2...difference, RD...row decoder, SAU...sense amplifier unit, T0...transistor, TR0 to TR19...transistor, SS...step value

Claims

1. a memory device including a plurality of memory cells each configured to non-volatilely store data including at least a first value and a second value responsive to a threshold voltage, the first value corresponding to the threshold voltage within a first voltage range and the second value corresponding to the threshold voltage within a second voltage range different from the first voltage range; writing data of the first value into each of a plurality of first memory cells among the plurality of memory cells; writing the second value of data into each of a plurality of second memory cells among the plurality of memory cells; determining a first voltage based on information regarding a slope of the distribution of threshold voltages for each of the plurality of memory cells; performing a tracking operation in which the memory device performs a plurality of read operations using a plurality of read levels in a third voltage range including at least a portion of the first voltage range and at least a portion of the second voltage range, targeting the plurality of memory cells, and acquiring a number of on-cells, which are memory cells that are turned on among the plurality of memory cells, in each of the plurality of read operations; and a memory controller configured to: The memory controller further includes, in the tracking operation: a first potential difference between two adjacent read levels among the plurality of read levels in a fourth voltage range lower than the first voltage in the third voltage range, and a second potential difference between two adjacent read levels among the plurality of read levels in a fifth voltage range higher than the first voltage in the third voltage range, are set to be different from each other. Memory system.

2. The memory controller further comprises: Detecting that a slope of the threshold voltage distribution in the fourth voltage range is steeper than a slope of the threshold voltage distribution in the fifth voltage range; and configuring the first potential difference to be smaller than the second potential difference in response to the detection.

2. The memory system of claim 1.

3. The memory controller further comprises: causing the memory device to perform a plurality of read operations using a plurality of read levels in a sixth voltage range including at least a portion of the first voltage range and at least a portion of the second voltage range, and acquiring a number of the ON cells in each of the plurality of read operations; obtaining a difference between the number of ON cells for each set of two reads using two adjacent read levels among the plurality of read levels in the sixth voltage range; a seventh voltage range in which the difference decreases as the read level increases, and an eighth voltage range in which the difference increases as the read level increases; and the first voltage is determined from a voltage range between the seventh voltage range and the eighth voltage range.

2. The memory system of claim 1.

4. The memory controller further comprises: Obtaining a plurality of the differences; obtaining a first difference between a minimum difference and a difference immediately preceding the minimum difference among the plurality of differences, and a second difference between the minimum difference and a difference immediately following the minimum difference; obtaining a comparison result of the magnitude of each of the first difference and the second difference; and determining the first potential difference and the second potential difference in response to the comparison result when the comparison result satisfies a first condition.

4. The memory system of claim 3.

5. The memory controller further comprises: Obtaining a plurality of the differences; calculating a first difference between a minimum difference and a difference immediately preceding the minimum difference among the plurality of differences, and a second difference between the minimum difference and a difference immediately following the minimum difference; obtaining a ratio between the first difference and the second difference; and determining the first potential difference and the second potential difference in response to the ratio when the ratio satisfies a first condition.

4. The memory system of claim 3.

6. the information being a value of a voltage belonging to the first voltage range and a value of a voltage belonging to the second voltage range; 2. The memory system of claim 1.

7. The information is any one of the positions of the memory cells in the memory device, the number of reads, the time elapsed since data was written, and the number of writes and erases.

2. The memory system of claim 1.

8. a memory device including a plurality of memory cells each configured to non-volatilely store data including at least a first value and a second value responsive to a threshold voltage, the first value corresponding to the threshold voltage within a first voltage range and the second value corresponding to the threshold voltage within a second voltage range different from the first voltage range; The first value of data is stored in each of a plurality of first memory cells among the plurality of memory cells. Write the data, The second value of data is stored in each of a plurality of second memory cells among the plurality of memory cells. Write the data, performing a tracking operation a plurality of times, the tracking operation being for performing a plurality of read operations using a plurality of read levels in a third voltage range including at least a portion of the first voltage range and at least a portion of the second voltage range, on the plurality of memory cells, and acquiring a number of ON cells, which are memory cells that are turned on in each of the plurality of read operations; estimating a gradient of the threshold voltage based on a number of the ON cells acquired in a first tracking operation of the plurality of tracking operations; determining a first voltage based on the estimated slope; and a memory controller configured to set, in a second tracking operation executed after the first tracking operation of the plurality of tracking operations, a first potential difference between two adjacent read levels of the plurality of read levels in a fourth voltage range lower than the first voltage of the third voltage range and a second potential difference between two adjacent read levels of the plurality of read levels in a fifth voltage range higher than the first voltage of the third voltage range to be different from each other. Memory system.

9. The memory controller further comprises: in the first tracking operation, potential differences between two adjacent read levels among the plurality of read levels in the third voltage range are set to be equal to each other.

9. The memory system of claim 8.

10. The memory controller further comprises: a potential difference between two adjacent read levels among the plurality of read levels in the third voltage range of the first tracking operation and a potential difference between two adjacent read levels among the plurality of read levels in the third voltage range of the second tracking operation are set to be different from each other.

9. The memory system of claim 8.

11. The memory controller further comprises: configured to manage a plurality of the first potential differences that can be used for the second tracking operation; 9. The memory system of claim 8.

12. The memory controller further comprises: and determining the first potential difference to be used in the second tracking operation from the plurality of managed first potential differences based on any one of the number of reads, the elapsed time after writing data, and the number of writes and erases.

12. The memory system of claim 11.

13. a plurality of memory cells each configured to non-volatilely store data including at least a first value and a second value as a function of a threshold voltage, the first value corresponding to the threshold voltage within a first voltage range and the second value corresponding to the threshold voltage within a second voltage range different from the first voltage range; The first value of data is stored in each of a plurality of first memory cells among the plurality of memory cells. Write the data, The second value of data is stored in each of a plurality of second memory cells among the plurality of memory cells. Write the data, performing a search read for performing a plurality of read operations using a plurality of read levels in a third voltage range including at least a portion of the first voltage range and at least a portion of the second voltage range, with the plurality of memory cells as a target, and acquiring a number of ON cells, which are memory cells that are turned on among the plurality of memory cells, in each of the plurality of read operations; and a peripheral circuit configured as described above, The peripheral circuit further includes, in the search lead, a first potential difference between two adjacent read levels among the plurality of read levels in a fourth voltage range lower than the first voltage in the third voltage range, and a second potential difference between two adjacent read levels among the plurality of read levels in a fifth voltage range higher than the first voltage in the third voltage range, are set to be different from each other. Memory device.

14. The peripheral circuit further comprises: obtaining a difference between the number of ON cells for each set of two reads using two adjacent read levels among the plurality of read levels in the third voltage range; and outputting the acquired difference to an external device. The memory device of claim 13.

15. The peripheral circuit further comprises: Obtaining a plurality of the differences; and outputting information about a read level corresponding to a minimum difference among the plurality of differences to an external device. The memory device of claim 14.

16. The peripheral circuit further comprises: performing an internal division point calculation using differences before and after the smallest difference among the plurality of differences, and outputting a result of the internal division point calculation to an outside; 16. The memory device of claim 15.

17. A memory device according to claim 13; a memory controller configured to request the memory device to change the setting of a parameter of the search read and to execute the search read. Memory system.

18. The peripheral circuit further comprises: outputting a result of the search read to the memory controller; The memory controller further comprises: calculating a first read voltage based on a result of the search read; instructing the memory device to perform a read operation using the first read voltage; performing error correction on the data read by the first read operation; and when the error correction fails, requesting the memory device to execute the search read again with at least one of the first potential difference and the second potential difference changed.

20. The memory system of claim 17.

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