Logic circuit

Abstract

To suppress fluctuations in an input voltage threshold due to temperature changes, and also suppress delays when the input voltage changes in a logic circuit.SOLUTION: A logic circuit 1 according to an embodiment includes an enhancement-type first FET 3 having a source 3s connected to a reference potential G, and a shift circuit 2 that level-shifts an input voltage to generate a voltage V1 to be applied to the first FET 3. The shift circuit 2 includes a first resistor 5 connected between an input terminal 12 of the logic circuit 1 and a gate 3g of the first FET 3, and a second resistor 6 and a potential difference generating element 40 connected in series between the gate 3g and the reference potential G, and the potential difference generating element 40 generates a potential difference Vd smaller than the threshold voltage of the first FET 3.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to logic circuits. [Background technology]

[0002] A common-source field effect transistor (FET) may be used in the input section of a logic circuit such as an inverter. In particular, a circuit including a common-source FET that uses a compound semiconductor such as GaAs and operates in DCFL (Direct Coupled FET Logic) is capable of high-speed operation and high efficiency, and is therefore suitable for use in devices with high operating frequencies and devices that require low power consumption. Enhancement-type n-channel MESFETs (Metal-Semiconductor Field Effect Transistors) and HEMTs (High Electron Mobility Transistors) are used as common-source FETs in the input stage circuits of such logic circuits. In the gate region of MESFETs and HEMTs made of compound semiconductors, a diode is formed between the gate electrode and the electron supply layer, etc., with the gate electrode side serving as the anode. Therefore, when a gate voltage higher than the forward voltage of this diode is applied, a current suddenly flows into the gate electrode. Therefore, in a MESFET or HEMT used in the input section of a logic circuit, the threshold voltage is set so that conduction occurs between the drain and source at a gate voltage of about 0.1 V to 0.4 V, which is lower than the forward voltage of about 0.6 V to 0.9 V of the diode configured in the gate region.

[0003] In contrast, a front-stage circuit that operates on logic other than DCFL, for example CMOS logic, which is arranged in front of a logic circuit and outputs an input voltage of the logic circuit, may have a voltage higher than the threshold voltage set in a MESFET or the like as a low-level voltage. Therefore, a level conversion circuit is provided to shift the voltage from the front-stage circuit so that the input circuit composed of a MESFET, HEMT, or the like does not recognize the low-level voltage output by the front-stage circuit as a high-level voltage. For example, Patent Document 1 shows a logic circuit with a level conversion function that includes a level conversion circuit using a diode.

[0004] FIG. 8 shows a conventional logic circuit 100 having a level conversion circuit 101 similar to the level conversion circuit disclosed in Patent Document 1 at its input stage. The logic circuit 100 is an inverter that outputs a low-level / high-level output voltage Vo from an output terminal 105 when an input voltage Vi applied to an input terminal 104 is high-level / low-level. The logic circuit 100 includes the level conversion circuit 101 and an enhancement type FET 102. A drain 102d of the FET 102 is connected to a power supply potential Vdd of the logic circuit 100 via a resistor RL. An output terminal 105 is connected to the drain 102d of the FET 102. The level conversion circuit 101 includes a diode D100, resistors Ri1 and Ri2, and an enhancement type FET 103, which are connected in series between the input terminal 104 and the ground. A drain 103d of the FET 103 is connected to a gate 103g, so that the FET 103 functions as a diode. The voltage V1 between the resistors Ri1 and Ri2 is input to the gate 102g of the FET 102.

[0005] In the logic circuit 100, the cathode voltage V3 of the diode D100 is V3=Vi-Vdio and the voltage V1 of the gate 102g of the FET 102 is V1 = V2 + (V3 - V2) R2 / (R1 + R2) Here, Vdio is the forward voltage of the diode D100, R1 and R2 are the resistance values ​​of the resistors Ri1 and Ri2, respectively, and V2 is the voltage of the drain 103d of the FET 103.

[0006] When the threshold voltage of the FET 103 is Vth, the voltage V2 of the drain 103d of the FET 103 is expressed as follows: V2=Vth The FET 102 and the FET 103, which are formed with the same structure, have the same threshold voltage Vth.

[0007] The logic circuit 100 outputs a low-level output voltage Vo when the resistance between the drain 102d and source 102s of the FET 102 becomes smaller than the resistance between the power supply potential Vdd and the output terminal 105. If the value of the gate voltage V1 at which the resistance between the drain 102d and source 102s becomes lower than the resistance between the power supply potential Vdd and the output terminal 105 is set to be slightly higher than the threshold voltage Vth of the FET 102 (Vth+α), then from the above equations, Vth+α=Vth+(Vi-Vdio-Vth)·R2 / (R1+R2) Therefore, the output voltage Vo of the logic circuit 100 is expressed as follows when the input voltage Vi is: Vi=Vth+Vdio+(R1 / R2+1)·α···(1) That is, when the input voltage Vi reaches the voltage value represented by the above formula (1) from a state lower than the voltage value represented by the above formula (1), the output voltage Vo switches from a high level to a low level.

[0008] On the other hand, if the level conversion circuit 101 is not provided and the input terminal 104 is directly connected to the gate 102g of the FET 102, the level of the output voltage Vo will switch when the input voltage Vi reaches Vth+α. That is, by providing the level conversion circuit 101, the magnitude of the input voltage Vi at which the level of the output voltage of the logic circuit 100 switches becomes larger by at least the forward voltage Vdio of the diode D100. Therefore, for example, when the logic circuit 100 receives an input voltage from a previous circuit that operates with CMOS logic, it is prevented from mistaking the low-level voltage input from the previous circuit for a high-level voltage and outputting a low-level voltage, and the logic circuit 100 operates normally. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] International Publication No. 2013 / 118521 Summary of the Invention [Problem to be solved by the invention]

[0010] In the logic circuit 100 shown in FIG. 8, the input voltage Vi that switches the output voltage Vo from a high level to a low level depends on the forward voltage Vdio of the diode D100 as shown in the above formula (1). That is, if the forward voltage Vdio is small (large), the output voltage Vo switches to a low level at a smaller (larger) input voltage Vi. In this regard, the forward voltage of a general diode having a PN junction has a negative temperature characteristic. For example, the forward voltage of a general PN junction diode may have a negative temperature coefficient of about -several mV / °C. Therefore, in a conventional logic circuit such as the logic circuit 100 shown in FIG. 8, there is a problem that the input voltage that switches the output voltage from a high level to a low level varies due to the influence of the temperature characteristic of the forward voltage of the diode such as Vdio in response to changes in the ambient temperature.

[0011] 9 shows the results of a simulation performed on the relationship between the input voltage Vi and the output voltage Vo of the logic circuit 100 of FIG. 8. In FIG. 9, the solid line L4 shows the simulation results under high temperature conditions (105° C.), and the dashed line L5 shows the simulation results under low temperature conditions (−40° C.). As shown in FIG. 9, under high temperature conditions, the output voltage Vo changes from a high level to a low level at an input voltage Vi of about 0.5 V, whereas under low temperature conditions, the output voltage Vo changes to a low level at an input voltage Vi of about 1.0 V. In this way, within a temperature range considered to be the operating temperature range of a general logic circuit, the value of the input voltage Vi that inverts the output voltage Vo (hereinafter, the “input voltage that inverts the output voltage in an inverter” is also referred to as the “inverting input voltage”) fluctuates by about 0.5 V.

[0012] Such a variation in the inverted input voltage is problematic because it may result in failure to achieve the required specifications regarding the input characteristics of the logic circuit. That is, the logic circuit is required to switch whether to recognize the input voltage as a high level or a low level between a predetermined high level input voltage VIH and a predetermined low level input voltage VIL over a predetermined operating temperature range. For example, when the logic circuit is an inverter, the inverted input voltage is required to be between the high level input voltage VIH and the low level input voltage VIL. However, if the inverted input voltage, i.e., the voltage value at the boundary between whether the input voltage is treated as a high level or a low level, varies greatly within the operating temperature range as described above, it becomes problematic because the requirements for the logic circuit regarding the input characteristics cannot be met.

[0013] Moreover, the above-mentioned predetermined high-level input voltage VIH (i.e., the lower limit of the input voltage value to be recognized as a high level) is influenced by the power supply voltage of the logic circuit, and the lower the power supply voltage, the lower the required high-level input voltage VIH. For example, in a logic circuit that operates on a power supply voltage of 3.3V and a logic circuit that operates on a power supply voltage of 1.8V, the logic circuit that operates on 1.8V is required to reliably recognize the input voltage as a high level even at a lower voltage value. In recent years, with the trend of reducing power consumption and making electrical devices in which logic circuits are used smaller and thinner, the demand for low-voltage operation of logic circuits has increased. As an example, a logic circuit may be required to operate on a power supply voltage of 1.2V, and in that case, a voltage of about 1.0V may be required as the high-level input voltage VIH. In this case, considering that the above-mentioned predetermined low-level input voltage VIL (i.e., the upper limit of the voltage value to be recognized as a low level) is generally required to be about 0.4V, for example, the allowable fluctuation width for the inverted input voltage in an inverter is about 0.6V.

[0014] In this regard, the variation in Vi due to element variations at a constant temperature, such as Vth, Vdio, R1, and R2, which make up the above formula (1), is expected to be about 0.3 V. If a variation of about 0.5 V due to temperature fluctuations within the operating temperature range, as shown in Figure 9, is added to this variation, the variation in the inverting input voltage becomes about 0.8 V. In other words, the variation in the inverting input voltage does not fall within the narrowing tolerance range as the power supply voltage is lowered, and there are cases where the required specifications cannot be met, which causes a problem.

[0015] Furthermore, in the logic circuit 100 shown in FIG. 8, when the input voltage Vi drops from a high level to a low level, for example, 0V, it takes a very long time for the gate voltage V1 of the FET 102 to drop to the same voltage as the input voltage Vi. That is, the diode D100 included in the level conversion circuit 101 prevents the gate capacitance of the FET 102 from discharging toward the input terminal 104, so that it takes a long time for the gate voltage V1 to drop. In this regard, FIGS. 10A and 10B show the simulation results of the transition of the gate voltage V1 with respect to the elapsed time from the change of the input voltage Vi from a high level (1.8V) to a low level (0V) for the logic circuit 100 of FIG. 8. FIG. 10A shows the transition up to 4 μs after the change of the input voltage Vi, and FIG. 10B shows the transition up to a longer time of 10 ms.

[0016] As shown in FIG. 10A, the gate voltage V1 drops relatively quickly in a few hundred ns to about 0.25 V, which is near the threshold voltage of the FET 103. This is because the FET 103 is turned on and discharged to the ground through the FET 103. However, after that, the discharge path through the FET 103 is cut off, so the gate voltage V1 drops very slowly. As shown in FIG. 10B, the gate voltage V1 is still larger than 0 V even after 10 ms has elapsed, that is, it takes longer than 10 ms for the gate voltage V1 to reach 0 V. Such a slow change in the gate voltage V1 causes a delay in the operation of a logic circuit such as an inverter. For example, the logic circuit 100 shown in FIG. 8 may not be applicable to an inverter that requires switching within a few hundred ns. Furthermore, while the gate voltage V1 is not sufficiently lower than the threshold voltage of the FET 102, there is a risk of malfunction due to the inclusion of high frequency waves or external noise.

[0017] In view of the above-mentioned problems, the present invention aims to suppress fluctuations in the voltage value (hereinafter also referred to as the "input voltage threshold") at the boundary between the range of input voltage values ​​recognized as a high level and the range of input voltage values ​​recognized as a low level due to temperature fluctuations in a logic circuit, and to suppress delays in operation when the input voltage changes to a low level. [Means for solving the problem]

[0018] A logic circuit according to one embodiment of the present invention includes a first enhancement-type FET having a source connected to a reference potential, and a shift circuit that level-shifts an input voltage to generate a voltage to be applied to the first FET, the shift circuit including a first resistor connected between an input terminal of the logic circuit and a gate of the first FET, and a second resistor and a potential difference generating element connected in series between the gate and the reference potential, and the potential difference generating element generates a potential difference smaller than a threshold voltage of the first FET. Effect of the Invention

[0019] According to the logic circuit of the present invention, it is possible to suppress the fluctuation of the input voltage threshold due to temperature fluctuation, and also to suppress the delay in operation when the input voltage changes to a low level. [Brief description of the drawings]

[0020] [Figure 1] FIG. 2 is a circuit diagram showing an example of a logic circuit according to an embodiment of the present invention. [Diagram 2] 2 is a diagram showing a simulation result of an output voltage versus an input voltage at high and low temperatures for the logic circuit of FIG. 1. [Diagram 3] 2 is a diagram showing simulation results of the transition of the gate voltage of a first FET after an input voltage drop in the logic circuit of FIG. 1, together with results for a conventional circuit. FIG. [Figure 4] 2 is a diagram showing simulation results of a change in output voltage after an input voltage drop for the logic circuit of FIG. 1, together with results for a conventional circuit. [Diagram 5] FIG. 2 is a diagram showing a schematic structure of a FET provided in an embodiment of the present invention. [Figure 6] FIG. 2 is a diagram showing an example of the arrangement of two FETs provided in the embodiment of the present invention. [Figure 7A] 2 is a schematic diagram showing an example of the relationship between the crystal planes on which two FETs in the embodiment of the present invention are formed and the orientations of the two FETs. FIG. [Figure 7B] 10 is a schematic diagram showing another example of the relationship between the crystal planes on which the two FETs in the embodiment of the present invention are formed and the orientations of the two FETs. FIG. [Figure 8] FIG. 1 is a circuit diagram showing an example of a conventional logic circuit. [Figure 9] 9 is a diagram showing a simulation result of an output voltage versus an input voltage at high and low temperatures in the conventional logic circuit of FIG. 8. [Figure 10A] 9 is a diagram showing a simulation result of the transition of the gate voltage of the FET 102 after a drop in the input voltage for the conventional logic circuit of FIG. 8. FIG. [Figure 10B] FIG. 10B shows the simulation results of FIG. 10A for a longer period of time. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] An embodiment of the logic circuit of the present invention will be described with reference to the drawings. However, the logic circuit of the present invention is not limited to the embodiment described below. For example, the positional relationship between circuit elements connected in series in the circuits shown in each drawing may not be as shown in each drawing. In addition, the circuits shown in each drawing may include circuit elements that are not shown, and conversely, may not include all of the circuit elements shown. Furthermore, each element shown in each drawing may have any characteristic or constant, and it should be understood that the characteristic or constant of each element is limited only by the description of the claims.

[0022] <Logic circuit configuration> FIG. 1 shows a logic circuit 1, which is an example of a logic circuit of the embodiment. The logic circuit 1 of FIG. 1 includes an input terminal 12 and an output terminal 13. The logic circuit 1 is an inverter (NOT gate) that outputs a voltage corresponding to a logical value opposite to a logical value corresponding to a voltage input to the input terminal 12 from an output terminal 13. However, the logic circuit of the embodiment is not limited to a NOT gate, and may be any logic circuit that performs any logical operation, such as an AND gate, an OR gate, a NAND gate, and a NOR gate. Therefore, the logic circuit of the embodiment may include any circuit element other than the circuit elements shown in FIG. 1, and the output terminal 13 may be connected to any circuit element not shown in FIG. 1. The logic circuit of the embodiment is formed on a semiconductor substrate or a semiconductor wafer made of a compound semiconductor, a silicon semiconductor, or the like, for example.

[0023] The logic circuit 1 includes a first FET 3 having a drain 3d, a gate 3g, and a source 3s, a shift circuit 2, and a resistor 11. The first FET 3 is an enhancement type n-channel FET. Therefore, when a voltage with a high potential on the gate 3g side exceeding a gate threshold voltage (hereinafter also simply referred to as "threshold voltage") of the first FET 3 is applied between the gate 3g and the source 3s, the electrical resistance between the drain 3d and the source 3s decreases, and the drain 3d and the source 3s are conductive. The first FET 3 is made of a compound semiconductor such as GaAs, GaN, InP, ZnSe, or SiC, as some examples. The first FET 3 made of a compound semiconductor is preferable in that high-speed operation and high-efficiency operation can be easily achieved. However, the material making up the first FET 3 is not limited to a compound semiconductor, and may be made of any semiconductor. The first FET 3 may be a general MOSFET or a junction type FET, but may also be a MESFET or a HEMT.

[0024] The drain 3d of the first FET 3 is connected to a reference potential VDD (first reference potential) of the logic circuit 1 via a resistor 11. In the logic circuit of FIG. 1, the reference potential VDD is a power supply potential of the logic circuit 1. One end of the resistor 11 is connected to the reference potential VDD, and the other end is connected to the drain 3d of the first FET. An output terminal 13 is connected to a connection node between the resistor 11 and the drain 3d of the first FET 3. On the other hand, the source 3s is connected to a reference potential G (second reference potential) of the logic circuit of the embodiment. In the logic circuit 1 of FIG. 1, the reference potential G is a GND potential of the logic circuit 1.

[0025] The reference potential VDD to which the drain 3d of the first FET 3 is connected via the resistor 11 is not limited to the power supply potential, and the reference potential G to which the source 3s is connected is not limited to the GND potential. The reference potential VDD and the reference potential G may each be any stable potential present in the logic circuit of the embodiment. The reference potential VDD has a predetermined potential difference with respect to the GND potential. The reference potential G may have a predetermined potential difference with respect to the GND potential. The reference potential VDD is a higher potential than the reference potential G, and is preferably higher than the reference potential G by 1 V or more. Examples of the potential difference between the reference potential VDD and the reference potential G include 1.2 V, 1.5 V, and 1.8 V, but the potential difference between the reference potential VDD and the reference potential G is not limited to these.

[0026] The shift circuit 2 shifts the level of the voltage (input voltage Vi) input to the input terminal 12 to generate a voltage V1 (gate voltage V1) to be applied between the gate 3g and source 3s of the first FET 3. That is, the shift circuit 2 generates a gate voltage V1 smaller than the input voltage Vi based on the input voltage Vi.

[0027] The shift circuit 2 includes a first resistor 5, a second resistor 6, and a potential difference generating element 40, which are connected in series between the input terminal 12 of the logic circuit 1 and a reference potential G. The first resistor 5 is connected between the input terminal 12 and the gate 3g of the first FET 3. One end of the first resistor 5 is connected to the input terminal 12, and the other end is connected to the gate 3g of the first FET 3. The second resistor 6 and the potential difference generating element 40 are connected in series between the gate 3g of the first FET 3 and the reference potential G.

[0028] In the logic circuit 1, one end of the second resistor 6 is connected to the other end of the first resistor 5 and the gate 3g of the first FET 3. Therefore, the gate 3g of the first FET 3 is connected to the connection node between the first resistor 5 and the second resistor 6. The other end of the second resistor 6 is connected to one end 40a of the potential difference generating element 40. The one end 40a of the potential difference generating element 40 is indirectly connected to the gate 3g of the first FET 3 via the second resistor 6. The other end 40b of the potential difference generating element 40, which is opposite to the one end 40a, is connected to a reference potential G. The potential difference generating element 40 generates a predetermined potential difference Vd smaller than the threshold voltage of the first FET 3 between the one end 40a and the other end 40b of the potential difference generating element 40.

[0029] In the logic circuit 1 of FIG. 1, the potential difference generating element 40 is configured by a second FET 4 having a drain 4d, a gate 4g, and a source 4s. The drain 4d and gate 4g of the second FET 4 are connected to each other and to the other end of the second resistor 6. The drain 4d and gate 4g of the second FET 4 are indirectly connected to the gate 3g of the first FET 3 via the second resistor 6. The source 4s of the second FET 4 is connected to a reference potential G. The connection node between the drain 4d and gate 4g of the second FET 4 constitutes one end 40a of the potential difference generating element 40, and the source 4s constitutes the other end 40b of the potential difference generating element 40.

[0030] In the logic circuit 1, the second FET 4 is an enhancement type n-channel FET. Therefore, the second FET 4, in which the drain 4d and the gate 4g are connected, constitutes a diode having the drain 4d as an anode and the source 4s as a cathode. Therefore, when a voltage higher than the threshold voltage of the second FET 4 is applied between the gate 3g (one end of the second resistor 6) of the first FET 3 and the reference potential G, a forward current flows from the drain 4d to the source 4s. In the second FET 4, which constitutes a diode by the drain-gate connection, when a forward current flows from the drain 4d to the source 4s, the threshold voltage of the second FET 4 is generated between the drain 4d and the source 3s. In this way, the second FET 4 generates a potential difference Vd consisting of the threshold voltage of the second FET 4 between the drain 4d and the source 4s. When the potential difference generating element 40 is configured by the second FET 4 as shown in FIG. 1, in the logic circuit of the embodiment, the threshold voltage of the second FET 4 is lower than the threshold voltage of the first FET.

[0031] In the logic circuit of the embodiment, the potential difference generating element does not have to be configured as an FET such as the second FET 4 of the logic circuit 1 of FIG. 1. The internal structure of the potential difference generating element is not particularly limited as long as it can generate an intended potential difference between two terminals of the potential difference generating element. For example, the potential difference generating element may be a diode originally having only two terminals (hereinafter also referred to as an "intrinsic diode"), instead of a three-terminal transistor having two terminals connected to each other such as the second FET 4. For example, the potential difference generating element 40 may be configured as a Schottky barrier diode having a small forward voltage. When the potential difference generating element 40 is an intrinsic diode, its forward voltage is generated as a potential difference Vd between one end 40a (anode) and the other end 40b (cathode).

[0032] In the series circuit of the second resistor 6 and the potential difference generating element 40 in the logic circuit 1 of FIG. 1, the second resistor 6 is disposed on the side of the first resistor 5 and the gate 3g of the first FET 3, and the potential difference generating element 40 is disposed on the side of the reference potential G, but this positional relationship may be reversed. That is, one end 40a of the potential difference generating element 40 may be connected to the other end of the first resistor 5 and the gate 3g of the first FET 3, and the other end 40b may be connected to one end of the second resistor 6. And the other end of the second resistor 6 may be connected to the reference potential G. That is, the one end 40a of the potential difference generating element 40 may be indirectly connected to the gate 3g of the first FET 3 via another circuit element such as the second resistor 6 as shown in FIG. 1, or may be directly connected to the gate 3g of the first FET 3. In other words, the drain 4d and the gate 4g of the second FET 4 may be indirectly connected to the gate 3g of the first FET 3 via another circuit element, or may be directly connected to the gate 3g of the first FET 3.

[0033] As shown in the logic circuit 1 of Fig. 1, the logic circuit of the embodiment does not include a diode such as the diode D100 included in the conventional logic circuit 100 of Fig. 8. Therefore, the input voltage threshold does not vary significantly with changes in the ambient temperature. Compared to the conventional logic circuit as shown in Fig. 8, the variation of the input voltage threshold due to temperature change is suppressed.

[0034] In addition, since the logic circuit does not include a diode such as the diode D100 in FIG. 8, when the input voltage Vi changes to a low level voltage, the charge stored in the gate capacitance of the first FET 3 is quickly discharged to the input terminal 12 via the first resistor 5. Therefore, the gate voltage V1 of the first FET 3 can quickly follow the input voltage Vi and drop to a voltage sufficiently lower than the threshold voltage. Therefore, in the logic circuit of the embodiment, it is possible to suppress delays in operation when the input voltage changes to a low level. Also, during the change process, it may be possible to prevent malfunctions due to the inclusion of high-frequency signals or noise.

[0035] On the other hand, in a logic circuit of an embodiment that does not include a diode such as the diode D100 in FIG. 8, the potential difference generating element 40 is configured to generate a potential difference smaller than the threshold voltage of the first FET 3, as described above, in order to replace the level shift function of the diode D100. As an example, in the logic circuit 1 of FIG. 1, the second FET 4 is configured to have a threshold voltage lower than the threshold voltage of the first FET 3. Therefore, even if the logic circuit of the embodiment does not include a diode such as the diode D100, it is possible to shift the input voltage by an appropriate amount and perform an appropriate logical operation according to the logic of the output voltage of the preceding circuit (not shown). This point will be described in detail below.

[0036] <Operation of the logic circuit according to the embodiment> The operation of the logic circuit of the embodiment will be described using the logic circuit 1 of Fig. 1 as an example. In particular, the operation of the logic circuit 1 will be described, focusing mainly on the theory of determining the input voltage Vi that switches the conductive state of the first FET 3, i.e., the above-mentioned "input voltage threshold." Note that, in the logic circuit 1 which is an inverter, the input voltage threshold corresponds to the input voltage Vi (inverted input voltage) that inverts the output voltage Vo.

[0037] In the logic circuit 1 of FIG. 1, the voltage V2 at one end 40a of the potential difference generating element 40, i.e., the voltage V2 at the drain 4d of the second FET 4, is V2 = Vd 1, when the potential difference generating element 40 is configured by the second FET 4 having the drain 4d and the gate 4g connected to each other, as described above, the potential difference generating element 40 generates the threshold voltage Vth2 of the second FET 4 as the potential difference Vd. V2=Vth2 On the other hand, the voltage V1 of the gate 3g of the first FET 3 is V1 = V2 + (Vi - V2) R2 / (R1 + R2) Here, R1 is the resistance value of the first resistor 5, and R2 is the resistance value of the second resistor 6.

[0038] The logic circuit 1 outputs a low-level output voltage Vo when the resistance between the drain 3d and source 3s of the first FET 3 becomes smaller than the resistance between the power supply potential VDD and the output terminal 13. Therefore, if the value of the gate voltage V1 of the first FET 3 at that time is (Vth1+α), then, from the above equations, Vth1+α=Vd+(Vi-Vd)·R2 / (R1+R2) is introduced, and if the potential difference generating element 40 is composed of the second FET 4 as shown in FIG. Vth1+α=Vth2+(Vi-Vth2)·R2 / (R1+R2) Here, Vth1 is the threshold voltage of the first FET 3.

[0039] In this embodiment, the potential difference generating element 40 generates a potential difference Vd smaller than the threshold voltage Vth1 of the first FET 3. When the potential difference generating element 40 is configured with the second FET 4 as shown in FIG. 1, the second FET 4 generates a threshold voltage Vth2, which is lower than the threshold voltage Vth1 of the first FET 3, as Vd between the drain 3d and the source 3s. Vd = Vth1 - δ (2) Or, Vth2=Vth1-δ (3) Then, the input voltage Vi (inverted input voltage or input voltage threshold) that inverts the output voltage Vo of the logic circuit 1 is Vi=Vth1+δ·R1 / R2+(R1 / R2+1)·α ···(4) It becomes.

[0040] Comparing the above formula (4) with formula (1) shown for the conventional logic circuit of FIG. 8, in formula (4), instead of the forward voltage Vdio of the diode D100 of FIG. 8 in formula (1), (δ·R1 / R2) contributes to the inverting input voltage. As shown in formulas (2) and (3) above, δ is the difference between the threshold voltage Vth1 of the first FET 3 and the potential difference Vd generated by the potential difference generation element 40 (or the second FET 4 constituting the potential difference generation element 40). Therefore, by configuring the potential difference generation element 40 to have a structure that generates a potential difference Vd having the same temperature characteristics as the threshold voltage Vth1 of the first FET 3, it is possible to extremely reduce the fluctuation of δ due to temperature fluctuation. Similarly, by configuring the first resistor 5 and the second resistor 6 with the same structure and material, it is possible to extremely reduce the fluctuation of (R1 / R2) due to temperature fluctuation. In other words, it is possible to extremely reduce the fluctuation of (δ·R1 / R2) due to temperature fluctuation. Therefore, in the logic circuit of the embodiment, the temperature variation of the input voltage threshold, i.e., the temperature variation of the inverted input voltage in the inverter, can be suppressed compared to conventional logic circuits in which the forward voltage of a diode having a large temperature characteristic is solely responsible for the shift amount of the input voltage Vi.

[0041] Furthermore, as shown in the above formulas (2) to (4), an input voltage threshold such as an inverted input voltage in an inverter can be adjusted by selecting the difference δ between the potential difference Vd (or the threshold voltage Vth2 of the second FET 4) generated by the potential difference generation element 40 and the threshold voltage Vth1 of the first FET 3, and the resistance ratio (R1 / R2). That is, by setting the difference δ between the threshold voltage Vth1 and the potential difference Vd to an appropriate value, it is possible to increase the degree of freedom in setting the amount of shift for the input voltage Vi, compared to, for example, a case in which the first FET 3 and the second FET 4 have the same threshold voltage.

[0042] Furthermore, as described above, in the logic circuit of the embodiment, it is possible to suppress operational delays when the input voltage changes to a low level, and to prevent malfunctions when the voltage changes.

[0043] In the logic circuit of the embodiment, in order to reduce the fluctuation of the input voltage threshold due to temperature fluctuation, it is preferable to configure the potential difference generating element 40 to generate a potential difference Vd having the same temperature characteristics as the threshold voltage Vth1 of the first FET 3, as described above. Therefore, for example, when the potential difference generating element 40 is configured with the second FET 4 as shown in FIG. 1, it is preferable that the second FET 4 is configured with the same material as the first FET 3 and has the same structure. Therefore, when the first FET 3 is configured with a compound semiconductor, it is preferable that the second FET 4 is also configured with the same compound semiconductor as the compound semiconductor configuring the first FET 3. Also, for example, if the first FET 3 is a MESFET, it is preferable that the second FET 4 is also a MESFET, and if the first FET 3 is a HEMT, it is preferable that the second FET 4 is also a HEMT. The first FET 3 and the second FET 4 are preferably formed close to each other on the same semiconductor substrate.

[0044] Even when the potential difference generating element 40 is an intrinsic diode, it is preferable that the potential difference generating element 40 is formed using the constituent material of the first FET 3. It is also preferable that the potential difference generating element 40 has a junction structure between one end 40a and the other end 40b that is the same as the junction structure that the first FET 3 has between the gate and source. For example, when the first FET 3 has a junction structure of a metal and a compound semiconductor in the gate region, such as a MESFET, the potential difference generating element 40 may also have a junction structure of the same kind of metal and a compound semiconductor. When the first FET 3 has a heterojunction structure of a compound semiconductor, such as a HEMT, the potential difference generating element 40 may also have a heterojunction structure made of the same kind of compound semiconductor.

[0045] In the logic circuit of the embodiment, the "threshold voltage" of each of the first FET 3 and the second FET 4 is the voltage between the gate and source of each of the first FET 3 and the second FET 4 when a current of 0.1 μA flows between the drain and source per 1 μm of gate width, that is, the pinch-off voltage. In addition, when the potential difference generating element 40 is configured as an intrinsic diode, the potential difference Vd compared with the threshold voltage of the first FET 3 is the potential difference when a predetermined current (e.g., 1 μA) flows when the current starts to flow.

[0046] <Examples of Effects of the Logic Circuit of the Embodiment> In Fig. 2, the results of a simulation performed on the relationship between the input voltage Vi and the output voltage Vo of the logic circuit 1 in Fig. 1 are shown in the same format as Fig. 9, which was previously referred to. In Fig. 2, the solid line L1 indicates the simulation results under high temperature conditions (105°C), and the dashed line L2 indicates the simulation results under low temperature conditions (-40°C). As shown in Fig. 2, under high temperature conditions, the output voltage Vo changes from high to low at an input voltage Vi of about 0.6V, and even under low temperature conditions, the output voltage Vo changes to low at an input voltage Vi of about 0.7V. Therefore, in an environment where the ambient temperature varies by 145°C, the input voltage threshold varies only by about 0.1V, and it can be seen that the variation in the input voltage threshold due to temperature variation is significantly suppressed compared to Fig. 9, which shows the characteristics of the conventional circuit. Therefore, even if the variation in the input voltage threshold due to element variations at a constant temperature of Vth1, δ, R1, R2, etc. constituting the above formula (4) is expected to be about 0.3 V, the fluctuation range including temperature fluctuation of the input voltage threshold is about 0.4 V in the temperature range shown in Figure 2. Therefore, even if the fluctuation range of the input voltage threshold (e.g., inverted input voltage) allowed for the logic circuit is about 0.6 V in the operating temperature range, it is possible to meet the required specifications.

[0047] FIG. 3 shows, in the same format as FIG. 10A, a simulation result of the transition of the gate voltage V1 of the first FET 3 with respect to the elapsed time after the input voltage Vi changes from a high-level voltage (1.8V) to a low-level voltage (0V) for the logic circuit 1 of FIG. 1. In FIG. 3, the solid line L11 shows the result for the logic circuit 1 of FIG. 1, and the dashed line L31 shows the result for the conventional logic circuit shown in FIG. 10A again for comparison. As is clear from FIG. 3, in the logic circuit 1 of FIG. 1, when the input voltage Vi changes to 0V, the gate voltage V1 transitions to 0V faster than the conventional logic circuit shown by the dashed line L31 because the gate capacitance of the first FET 3 is discharged quickly and sufficiently through the first resistor 5. The gate voltage V1 transitions to approximately 0V in about 1 μs. Therefore, it is considered that the operation delay when the input voltage Vi changes to a low level is improved and malfunction during the change of the gate voltage V1 is also suppressed.

[0048] Fig. 4 shows the simulation results of the change in output voltage Vo after the input voltage Vi drops to 0V for the logic circuit 1 of Fig. 1, together with the results for the conventional logic circuit of Fig. 8. In Fig. 4, the solid line L12 shows the results for the logic circuit 1 of Fig. 1, and the dashed line L32 shows the results for the conventional logic circuit of Fig. 8. As shown by the dashed line L32 in Fig. 4, in the conventional logic circuit, after the input voltage drops, it takes 0.2 μs for the output voltage Vo to turn to a high level. This can be easily understood from the fact that in Fig. 3, in the conventional logic circuit, it takes time for the gate voltage V1 to drop to the threshold voltage of about 0.25 V of the FET 102 (see Fig. 8).

[0049] On the other hand, in the logic circuit 1 of the embodiment of FIG. 1, as indicated by the solid line L12, the gate voltage V1 of the first FET 3 falls quickly below the threshold voltage of the first FET 3 and transitions to 0 V at high speed (see FIG. 3), and therefore the output voltage Vo rises to a high level at high speed. That is, it is understood that the logic circuit 1 of the embodiment has an improved operation delay compared to the conventional logic circuit. For example, the logic circuit 1 of the embodiment is considered to be applicable to an inverter that is required to switch the output voltage within several hundreds of nanoseconds.

[0050] <Means for Making the Potential Difference Generated by the Potential Difference Generating Element Smaller than the Threshold Voltage of the First FET> In the logic circuit of the embodiment, the potential difference generated by the potential difference generating element can be made smaller than the threshold voltage of the first FET by any method. For example, when the potential difference generating element is configured as an intrinsic diode, the potential difference generated by the potential difference generating element can be set to any value smaller than the threshold voltage of the first FET by using a general method for adjusting the forward voltage of a diode. On the other hand, when the potential difference generating element 40 is configured as the second FET 4 as shown in FIG. 1, several examples of methods for making the potential difference Vd generated by the potential difference generating element 40 smaller than the threshold voltage of the first FET 3 are shown below.

[0051] When the potential difference generating element 40 is configured with the second FET 4 as in the logic circuit 1 of FIG. 1, the potential difference Vd generated by the potential difference generating element 40, i.e., the threshold voltage of the second FET 4, can be made lower than the threshold voltage of the first FET 3, for example, by forming the gate 4g of the second FET 4 with an appropriate size. As an example, if the gate length of the second FET 4 is shorter than the gate length of the first FET 3, the threshold voltage of the second FET 4 may be lower than the threshold voltage of the first FET 3. That is, by utilizing the so-called short channel effect, the threshold voltage of the second FET 4 may be made lower than the threshold voltage of the first FET 3. Therefore, the threshold voltage of the second FET 4 may be made lower than the threshold voltage of the first FET 3 by making the gate length of the second FET 4 shorter than the gate length of the first FET 3. As an example, the threshold voltage of the second FET 4 having a gate length half that of the first FET 3 is approximately 35 mV lower than the threshold voltage of the first FET 3.

[0052] In another example, when the potential difference generating element 40 is configured with the second FET 4 as in the logic circuit 1 of FIG. 1, if the gate width of the second FET 4 is larger than that of the first FET 3, the threshold voltage of the second FET 4 may be lower than that of the first FET 3. That is, if the gate width is larger, a larger number of carriers can be supplied between the drain 4d and the source 4s at a lower gate voltage to transition the second FET 4 to the conductive state. Therefore, the threshold voltage of the second FET 4 may be lower than that of the first FET 3 by making the gate width of the second FET 4 larger than that of the first FET 3. As an example, the threshold voltage of the second FET 4 having a gate width four times that of the first FET 3 is approximately 5 mV lower than the threshold voltage of the first FET 3.

[0053] 5 shows an example of a structure that the first FET 3 and the second FET 4 in FIG. 1 may have when these FETs are formed on a semiconductor substrate, and is illustrated using the structure of the FET 34. As an example, a semiconductor deposition layer 72 is laminated on a semiconductor substrate 71 made of GaN or the like by a film formation method such as metal-organic vapor phase epitaxy. Although not shown, the semiconductor deposition layer 72 has a multi-layer structure and may include, for example, a carrier supply layer, a carrier travel layer, and an i-type semiconductor layer or a channel layer.

[0054] The drain electrode 34d, the source electrode 34s, and the gate electrode 34g of the FET 34 are formed on the semiconductor deposition layer 72. The FET 34 has a gate length L and a gate width W for the gate electrode 34g. The drain electrode 34d and the source electrode 34s face each other in the X direction shown in Fig. 5. A rectangle S can be imagined between the drain electrode 34d and the source electrode 34s, having four vertices, namely, two vertices of the drain electrode 34d facing the source electrode 34s in a plan view and two vertices of the source electrode 34s facing the drain electrode 34d.

[0055] As described above, if the gate length L of the second FET 4 constituting the potential difference generating element 40 in the logic circuit 1 of FIG. 1 is shorter than the gate length L of the first FET 3, the threshold voltage of the second FET 4 is likely to be lower than the threshold voltage of the first FET 3. Also, if the gate width W of the second FET 4 is larger than the gate width W of the first FET 3, the threshold voltage of the second FET 4 is likely to be lower than the threshold voltage of the first FET 3. In the example of FIG. 5, the gate length L is the length in the X direction of the region So where the gate electrode 34g overlaps with a rectangle S imaginary between the drain electrode 34d and the source electrode 34s. Also, in the example of FIG. 5, the gate width W is the length in the direction perpendicular to the X direction of the region So.

[0056] 6 shows an example in which the first FET 3 and the second FET 4 are formed on the surface SS of the semiconductor layer of the semiconductor wafer SW. As in the structural example of FIG. 5, in the example of FIG. 6, the first FET 3 includes a drain electrode 3dd, a source electrode 3ss, and a gate electrode 3gg, and the second FET 4 includes a drain electrode 4dd, a source electrode 4ss, and a gate electrode 4gg. The gate electrode 3gg extends in a direction perpendicular to the direction in which the drain electrode 3dd and the source electrode 3ss face each other, and thus has a longitudinal direction perpendicular to the direction in which the drain electrode 3dd and the source electrode 3ss face each other. The gate electrode 4gg extends in a direction perpendicular to the direction in which the drain electrode 4dd and the source electrode 4ss face each other, and thus has a longitudinal direction perpendicular to the direction in which the drain electrode 4dd and the source electrode 4ss face each other.

[0057] In the example of FIG. 6, the longitudinal direction of the gate electrode 3gg of the first FET 3 (hereinafter also simply referred to as the "longitudinal direction of the first FET 3") and the longitudinal direction of the gate electrode 4gg of the second FET 4 (hereinafter also simply referred to as the "longitudinal direction of the second FET 4") are substantially orthogonal. That is, the first FET 3 and the second FET 4 are formed in such an orientation that the longitudinal direction of the first FET 3 and the longitudinal direction of the second FET 4 form an angle of substantially 90°. Therefore, the orientation of the longitudinal direction of the first FET 3 and the orientation of the longitudinal direction of the second FET 4 differ from each other by an angle of substantially 90°. Note that "substantially orthogonal" means that the two directions form an angle of 80° or more and 100° or less.

[0058] For example, when the first FET 3 and the second FET 4 are formed of a compound semiconductor, the surface SS of the semiconductor layer on which the first FET 3 and the second FET 4 are formed may be configured with a specific crystal plane of the compound semiconductor so as to obtain desired characteristics, as shown in FIG. 6. As an example, the specific crystal plane that configures the surface SS may be a (100) crystal plane. In this case, the first FET 3 is preferably formed so that the longitudinal direction of the gate electrode 3gg of the first FET 3 is approximately parallel to the direction of the crystal orientation

[0011] and the direction of the crystal orientation [0-1-1]. The second FET 4 is preferably formed so that the longitudinal direction of the gate electrode 4gg of the second FET 4 is approximately parallel to the direction of the crystal orientation [01-1] and the direction of the crystal orientation [0-11], that is, so that the longitudinal direction of the gate electrode 3gg is approximately perpendicular to the longitudinal direction of the gate electrode 4gg. In addition, a direction having a negative component in the notation of the crystal orientation is expressed as "-1" without a bar on the "1".

[0059] When the gate electrode 3gg of the first FET 3 and the gate electrode 4gg of the second FET 4 are formed so that their longitudinal directions are substantially perpendicular to each other in this manner, the threshold voltage of the second FET 4 can be easily made lower than the threshold voltage of the first FET 3. That is, in two FETs whose longitudinal directions of the gate electrodes are substantially perpendicular to each other, the carrier concentration increases or decreases due to the piezoelectric effect caused by the stress of the insulating film (not shown) covering the gate electrodes, resulting in a difference in the carrier concentration between the two FETs. The increase or decrease in the carrier concentration due to the piezoelectric effect depends on whether compressive stress or tensile stress is applied to the gate electrode, and the gate electrode is subjected to compressive stress or tensile stress depending on the crystal orientation in which the longitudinal direction of the gate electrode faces. Therefore, the threshold voltage of the second FET 4 can be made lower than the threshold voltage of the first FET 3 by orienting the longitudinal direction of the gate electrode 4gg of the second FET 4 in a crystal orientation in which the carrier concentration increases (i.e., the threshold voltage decreases) and by orienting the longitudinal direction of the gate electrode 3gg of the first FET 3 in a crystal orientation in which the carrier concentration decreases (i.e., the threshold voltage increases).

[0060] 7A and 7B each show an example of a crystal plane that may constitute the surface SS of the semiconductor layer as shown in FIG. 6 using a simple cubic lattice, and a crystal orientation in which the longitudinal direction of each of the gate electrodes of the first FET 3 and the second FET 4 is oriented. As described above, when the first FET 3 and the second FET 4 are formed on a surface constituted by the (100) crystal plane S1 shown in FIG. 7A, the longitudinal direction of the first FET 3 is preferably oriented so as to be approximately parallel to the direction of the crystal orientation

[0011] (the direction in which the arrow A1 faces) and the direction of the crystal orientation [0-1-1]. The longitudinal direction of the second FET 4 is preferably oriented so as to be approximately parallel to the direction of the crystal orientation [01-1] (the direction in which the arrow A2 faces) and the direction of the crystal orientation [0-11].

[0061] The first FET 3 and the second FET 4 may be formed on a specific crystal plane other than the (100) crystal plane. In this case, the longitudinal direction of the first FET 3 is preferably approximately parallel to the direction of the crystal orientation

[0011] and the direction of the crystal orientation [0-1-1] on the surface when the specific crystal plane constituting the surface of the semiconductor layer on which the first and second FETs 3 and 4 are formed is a (100) crystal plane. The longitudinal direction of the second FET 4 is preferably approximately parallel to the direction of the crystal orientation [01-1] and the direction of the crystal orientation [0-11] on the surface when the specific crystal plane constituting the surface of the semiconductor layer on which the first and second FETs 3 and 4 are formed is a (100) crystal plane. In this way, by orienting the longitudinal direction of the first FET 3 and the longitudinal direction of the second FET 4, respectively, the threshold voltage of the second FET 4 may be easily made lower than the threshold voltage of the first FET 3.

[0062] For example, when the first FET 3 and the second FET 4 are formed on the surface S2 of the semiconductor layer composed of the (110) crystal plane shown in Fig. 7B, the first FET 3 is preferably formed so that the direction of the crystal orientation [-111] (the direction indicated by the arrow A3) and the direction of the crystal orientation [1-1-1] are approximately parallel to the longitudinal direction of the first FET 3. The second FET 4 is preferably formed so that the direction of the crystal orientation [-11-1] (the direction indicated by the arrow A4) and the direction of the crystal orientation [1-11] are approximately parallel to the longitudinal direction of the second FET 4.

[0063] Even when the first FET 3 and the second FET 4 are formed on a surface consisting of a crystal plane other than the (100) crystal plane and the (110) crystal plane, if the crystal plane is a (100) crystal plane, the threshold voltage of the second FET 4 may be easily made lower than the threshold voltage of the first FET 3 by orienting the longitudinal direction of the first FET 3 approximately parallel to the direction of the crystal orientation

[0011] and the direction of the crystal orientation [0-1-1], and by orienting the longitudinal direction of the second FET 4 approximately parallel to the direction of the crystal orientation [01-1] and the direction of the crystal orientation [0-11]. That is, the input voltage threshold (or the inverted input voltage) of the logic circuit of the embodiment may be easily adjusted to a desired voltage value. Therefore, it is considered that the logic circuit of the embodiment having an input voltage threshold with little temperature fluctuation and stable operation with little delay can be easily realized. [Explanation of symbols]

[0064] 1. Logic Circuits 2 Shift circuit 12 Input terminals 13 Output terminal 3. 1st FET 3d drain 3g gate 3s Source 4. Second FET 4d Drain 4g gate 4s Source 40 Potential difference generating element 40a one end 40b Other end 5 1st resistor 6 Second resistor 71 Semiconductor Substrate 72 Semiconductor Deposition Layer G Reference potential (ground potential, second reference potential) L Gate length S1 (100) crystal face S2 (110) crystal plane Vd Potential difference generated by the potential difference generating element VDD reference potential (power supply potential, first reference potential) Vi input voltage Vo output voltage W Gate width

Claims

1. a first enhancement-mode FET having a source connected to a reference potential; a shift circuit that level-shifts an input voltage to generate a voltage that is applied to the first FET; A logic circuit comprising: a first resistor connected between an input terminal of the logic circuit and a gate of the first FET; a second resistor and a potential difference generating element connected in series between the gate and the reference potential; The potential difference generating element generates a potential difference smaller than a threshold voltage of the first FET.

2. the potential difference generating element is constituted by a second FET that generates the potential difference between a drain and a source; the drain and gate of the second FET are connected together and directly or indirectly to the gate of the first FET; 2. The logic circuit of claim 1, wherein a threshold voltage of said second FET is lower than said threshold voltage of said first FET.

3. 3. The logic circuit of claim 2, wherein the gate length of said second FET is shorter than the gate length of said first FET.

4. 4. The logic circuit according to claim 3, wherein the gate width of said second FET is greater than the gate width of said first FET.

5. the first FET and the second FET are formed on a surface of a semiconductor layer made of a compound semiconductor, 5. The logic circuit according to claim 2, wherein a longitudinal direction of the gate electrode of said first FET and a longitudinal direction of the gate electrode of said second FET are substantially perpendicular to each other.

6. the first FET and the second FET are formed on a surface of a semiconductor layer formed of a specific crystal plane of a compound semiconductor, a longitudinal direction of a gate electrode of the first FET is approximately parallel to a direction of a crystal orientation [011] when the specific crystal plane is a (100) crystal plane on the surface; 5. The logic circuit according to claim 2, wherein a longitudinal direction of the gate electrode of the second FET is approximately parallel to a direction in which the specific crystal plane faces a [01-1] crystal orientation when the specific crystal plane is a (100) crystal plane on the surface.

7. the specific crystal plane is a (100) crystal plane, a longitudinal direction of the gate electrode of the first FET is substantially parallel to a direction along a [011] crystal orientation; 7. The logic circuit according to claim 6, wherein a longitudinal direction of the gate electrode of the second FET is substantially parallel to a direction facing a crystal orientation [01-1].

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